LXR linux/arch/xtensa/include/asm/processor.h

   1/*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Copyright (C) 2001 - 2008 Tensilica Inc.
   7 * Copyright (C) 2015 Cadence Design Systems Inc.
   8 */
   9
  10#ifndef _XTENSA_PROCESSOR_H
  11#define _XTENSA_PROCESSOR_H
  12
  13#include <variant/core.h>
  14#include <platform/hardware.h>
  15
  16#include <linux/compiler.h>
  17#include <asm/ptrace.h>
  18#include <asm/types.h>
  19#include <asm/regs.h>
  20
  21/* Assertions. */
  22
  23#if (XCHAL_HAVE_WINDOWED != 1)
  24# error Linux requires the Xtensa Windowed Registers Option.
  25#endif
  26
  27#define ARCH_SLAB_MINALIGN      XCHAL_DATA_WIDTH
  28
  29/*
  30 * User space process size: 1 GB.
  31 * Windowed call ABI requires caller and callee to be located within the same
  32 * 1 GB region. The C compiler places trampoline code on the stack for sources
  33 * that take the address of a nested C function (a feature used by glibc), so
  34 * the 1 GB requirement applies to the stack as well.
  35 */
  36
  37#ifdef CONFIG_MMU
  38#define TASK_SIZE       __XTENSA_UL_CONST(0x40000000)
  39#else
  40#define TASK_SIZE       __XTENSA_UL_CONST(0xffffffff)
  41#endif
  42
  43#define STACK_TOP       TASK_SIZE
  44#define STACK_TOP_MAX   STACK_TOP
  45
  46/*
  47 * General exception cause assigned to fake NMI. Fake NMI needs to be handled
  48 * differently from other interrupts, but it uses common kernel entry/exit
  49 * code.
  50 */
  51
  52#define EXCCAUSE_MAPPED_NMI     62
  53
  54/*
  55 * General exception cause assigned to debug exceptions. Debug exceptions go
  56 * to their own vector, rather than the general exception vectors (user,
  57 * kernel, double); and their specific causes are reported via DEBUGCAUSE
  58 * rather than EXCCAUSE.  However it is sometimes convenient to redirect debug
  59 * exceptions to the general exception mechanism.  To do this, an otherwise
  60 * unused EXCCAUSE value was assigned to debug exceptions for this purpose.
  61 */
  62
  63#define EXCCAUSE_MAPPED_DEBUG   63
  64
  65/*
  66 * We use DEPC also as a flag to distinguish between double and regular
  67 * exceptions. For performance reasons, DEPC might contain the value of
  68 * EXCCAUSE for regular exceptions, so we use this definition to mark a
  69 * valid double exception address.
  70 * (Note: We use it in bgeui, so it should be 64, 128, or 256)
  71 */
  72
  73#define VALID_DOUBLE_EXCEPTION_ADDRESS  64
  74
  75#define XTENSA_INT_LEVEL(intno) _XTENSA_INT_LEVEL(intno)
  76#define _XTENSA_INT_LEVEL(intno) XCHAL_INT##intno##_LEVEL
  77
  78#define XTENSA_INTLEVEL_MASK(level) _XTENSA_INTLEVEL_MASK(level)
  79#define _XTENSA_INTLEVEL_MASK(level) (XCHAL_INTLEVEL##level##_MASK)
  80
  81#define XTENSA_INTLEVEL_ANDBELOW_MASK(l) _XTENSA_INTLEVEL_ANDBELOW_MASK(l)
  82#define _XTENSA_INTLEVEL_ANDBELOW_MASK(l) (XCHAL_INTLEVEL##l##_ANDBELOW_MASK)
  83
  84#define PROFILING_INTLEVEL XTENSA_INT_LEVEL(XCHAL_PROFILING_INTERRUPT)
  85
  86/* LOCKLEVEL defines the interrupt level that masks all
  87 * general-purpose interrupts.
  88 */
  89#if defined(CONFIG_XTENSA_FAKE_NMI) && defined(XCHAL_PROFILING_INTERRUPT)
  90#define LOCKLEVEL (PROFILING_INTLEVEL - 1)
  91#else
  92#define LOCKLEVEL XCHAL_EXCM_LEVEL
  93#endif
  94
  95#define TOPLEVEL XCHAL_EXCM_LEVEL
  96#define XTENSA_FAKE_NMI (LOCKLEVEL < TOPLEVEL)
  97
  98/* WSBITS and WBBITS are the width of the WINDOWSTART and WINDOWBASE
  99 * registers
 100 */
 101#define WSBITS  (XCHAL_NUM_AREGS / 4)      /* width of WINDOWSTART in bits */
 102#define WBBITS  (XCHAL_NUM_AREGS_LOG2 - 2) /* width of WINDOWBASE in bits */
 103
 104#ifndef __ASSEMBLY__
 105
 106/* Build a valid return address for the specified call winsize.
 107 * winsize must be 1 (call4), 2 (call8), or 3 (call12)
 108 */
 109#define MAKE_RA_FOR_CALL(ra,ws)   (((ra) & 0x3fffffff) | (ws) << 30)
 110
 111/* Convert return address to a valid pc
 112 * Note: We assume that the stack pointer is in the same 1GB ranges as the ra
 113 */
 114#define MAKE_PC_FROM_RA(ra,sp)    (((ra) & 0x3fffffff) | ((sp) & 0xc0000000))
 115
 116/* Spill slot location for the register reg in the spill area under the stack
 117 * pointer sp. reg must be in the range [0..4).
 118 */
 119#define SPILL_SLOT(sp, reg) (*(((unsigned long *)(sp)) - 4 + (reg)))
 120
 121/* Spill slot location for the register reg in the spill area under the stack
 122 * pointer sp for the call8. reg must be in the range [4..8).
 123 */
 124#define SPILL_SLOT_CALL8(sp, reg) (*(((unsigned long *)(sp)) - 12 + (reg)))
 125
 126/* Spill slot location for the register reg in the spill area under the stack
 127 * pointer sp for the call12. reg must be in the range [4..12).
 128 */
 129#define SPILL_SLOT_CALL12(sp, reg) (*(((unsigned long *)(sp)) - 16 + (reg)))
 130
 131typedef struct {
 132        unsigned long seg;
 133} mm_segment_t;
 134
 135struct thread_struct {
 136
 137        /* kernel's return address and stack pointer for context switching */
 138        unsigned long ra; /* kernel's a0: return address and window call size */
 139        unsigned long sp; /* kernel's a1: stack pointer */
 140
 141        mm_segment_t current_ds;    /* see uaccess.h for example uses */
 142
 143        /* struct xtensa_cpuinfo info; */
 144
 145        unsigned long bad_vaddr; /* last user fault */
 146        unsigned long bad_uaddr; /* last kernel fault accessing user space */
 147        unsigned long error_code;
 148#ifdef CONFIG_HAVE_HW_BREAKPOINT
 149        struct perf_event *ptrace_bp[XCHAL_NUM_IBREAK];
 150        struct perf_event *ptrace_wp[XCHAL_NUM_DBREAK];
 151#endif
 152        /* Make structure 16 bytes aligned. */
 153        int align[0] __attribute__ ((aligned(16)));
 154};
 155
 156
 157/*
 158 * Default implementation of macro that returns current
 159 * instruction pointer ("program counter").
 160 */
 161#define current_text_addr()  ({ __label__ _l; _l: &&_l;})
 162
 163
 164/* This decides where the kernel will search for a free chunk of vm
 165 * space during mmap's.
 166 */
 167#define TASK_UNMAPPED_BASE      (TASK_SIZE / 2)
 168
 169#define INIT_THREAD  \
 170{                                                                       \
 171        ra:             0,                                              \
 172        sp:             sizeof(init_stack) + (long) &init_stack,        \
 173        current_ds:     {0},                                            \
 174        /*info:         {0}, */                                         \
 175        bad_vaddr:      0,                                              \
 176        bad_uaddr:      0,                                              \
 177        error_code:     0,                                              \
 178}
 179
 180
 181/*
 182 * Do necessary setup to start up a newly executed thread.
 183 * Note: We set-up ps as if we did a call4 to the new pc.
 184 *       set_thread_state in signal.c depends on it.
 185 */
 186#define USER_PS_VALUE ((1 << PS_WOE_BIT) |                              \
 187                       (1 << PS_CALLINC_SHIFT) |                        \
 188                       (USER_RING << PS_RING_SHIFT) |                   \
 189                       (1 << PS_UM_BIT) |                               \
 190                       (1 << PS_EXCM_BIT))
 191
 192/* Clearing a0 terminates the backtrace. */
 193#define start_thread(regs, new_pc, new_sp) \
 194        memset(regs, 0, sizeof(*regs)); \
 195        regs->pc = new_pc; \
 196        regs->ps = USER_PS_VALUE; \
 197        regs->areg[1] = new_sp; \
 198        regs->areg[0] = 0; \
 199        regs->wmask = 1; \
 200        regs->depc = 0; \
 201        regs->windowbase = 0; \
 202        regs->windowstart = 1;
 203
 204/* Forward declaration */
 205struct task_struct;
 206struct mm_struct;
 207
 208/* Free all resources held by a thread. */
 209#define release_thread(thread) do { } while(0)
 210
 211extern unsigned long get_wchan(struct task_struct *p);
 212
 213#define KSTK_EIP(tsk)           (task_pt_regs(tsk)->pc)
 214#define KSTK_ESP(tsk)           (task_pt_regs(tsk)->areg[1])
 215
 216#define cpu_relax()  barrier()
 217
 218/* Special register access. */
 219
 220#define WSR(v,sr) __asm__ __volatile__ ("wsr %0,"__stringify(sr) :: "a"(v));
 221#define RSR(v,sr) __asm__ __volatile__ ("rsr %0,"__stringify(sr) : "=a"(v));
 222
 223#define set_sr(x,sr) ({unsigned int v=(unsigned int)x; WSR(v,sr);})
 224#define get_sr(sr) ({unsigned int v; RSR(v,sr); v; })
 225
 226#ifndef XCHAL_HAVE_EXTERN_REGS
 227#define XCHAL_HAVE_EXTERN_REGS 0
 228#endif
 229
 230#if XCHAL_HAVE_EXTERN_REGS
 231
 232static inline void set_er(unsigned long value, unsigned long addr)
 233{
 234        asm volatile ("wer %0, %1" : : "a" (value), "a" (addr) : "memory");
 235}
 236
 237static inline unsigned long get_er(unsigned long addr)
 238{
 239        register unsigned long value;
 240        asm volatile ("rer %0, %1" : "=a" (value) : "a" (addr) : "memory");
 241        return value;
 242}
 243
 244#endif /* XCHAL_HAVE_EXTERN_REGS */
 245
 246#endif  /* __ASSEMBLY__ */
 247#endif  /* _XTENSA_PROCESSOR_H */
 248