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12#include <linux/bitops.h>
13#include <linux/delay.h>
14#include <linux/dmaengine.h>
15#include <linux/dma-mapping.h>
16#include <linux/dmapool.h>
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/slab.h>
21
22#include <linux/dma/idma64.h>
23
24#include "idma64.h"
25
26
27#define IDMA64_NR_CHAN 2
28
29
30
31static struct device *chan2dev(struct dma_chan *chan)
32{
33 return &chan->dev->device;
34}
35
36
37
38static void idma64_off(struct idma64 *idma64)
39{
40 unsigned short count = 100;
41
42 dma_writel(idma64, CFG, 0);
43
44 channel_clear_bit(idma64, MASK(XFER), idma64->all_chan_mask);
45 channel_clear_bit(idma64, MASK(BLOCK), idma64->all_chan_mask);
46 channel_clear_bit(idma64, MASK(SRC_TRAN), idma64->all_chan_mask);
47 channel_clear_bit(idma64, MASK(DST_TRAN), idma64->all_chan_mask);
48 channel_clear_bit(idma64, MASK(ERROR), idma64->all_chan_mask);
49
50 do {
51 cpu_relax();
52 } while (dma_readl(idma64, CFG) & IDMA64_CFG_DMA_EN && --count);
53}
54
55static void idma64_on(struct idma64 *idma64)
56{
57 dma_writel(idma64, CFG, IDMA64_CFG_DMA_EN);
58}
59
60
61
62static void idma64_chan_init(struct idma64 *idma64, struct idma64_chan *idma64c)
63{
64 u32 cfghi = IDMA64C_CFGH_SRC_PER(1) | IDMA64C_CFGH_DST_PER(0);
65 u32 cfglo = 0;
66
67
68 cfglo |= IDMA64C_CFGL_DST_BURST_ALIGN | IDMA64C_CFGL_SRC_BURST_ALIGN;
69
70 channel_writel(idma64c, CFG_LO, cfglo);
71 channel_writel(idma64c, CFG_HI, cfghi);
72
73
74 channel_set_bit(idma64, MASK(XFER), idma64c->mask);
75 channel_set_bit(idma64, MASK(ERROR), idma64c->mask);
76
77
78
79
80
81
82
83
84 idma64_on(idma64);
85}
86
87static void idma64_chan_stop(struct idma64 *idma64, struct idma64_chan *idma64c)
88{
89 channel_clear_bit(idma64, CH_EN, idma64c->mask);
90}
91
92static void idma64_chan_start(struct idma64 *idma64, struct idma64_chan *idma64c)
93{
94 struct idma64_desc *desc = idma64c->desc;
95 struct idma64_hw_desc *hw = &desc->hw[0];
96
97 channel_writeq(idma64c, SAR, 0);
98 channel_writeq(idma64c, DAR, 0);
99
100 channel_writel(idma64c, CTL_HI, IDMA64C_CTLH_BLOCK_TS(~0UL));
101 channel_writel(idma64c, CTL_LO, IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN);
102
103 channel_writeq(idma64c, LLP, hw->llp);
104
105 channel_set_bit(idma64, CH_EN, idma64c->mask);
106}
107
108static void idma64_stop_transfer(struct idma64_chan *idma64c)
109{
110 struct idma64 *idma64 = to_idma64(idma64c->vchan.chan.device);
111
112 idma64_chan_stop(idma64, idma64c);
113}
114
115static void idma64_start_transfer(struct idma64_chan *idma64c)
116{
117 struct idma64 *idma64 = to_idma64(idma64c->vchan.chan.device);
118 struct virt_dma_desc *vdesc;
119
120
121 vdesc = vchan_next_desc(&idma64c->vchan);
122 if (!vdesc) {
123 idma64c->desc = NULL;
124 return;
125 }
126
127 list_del(&vdesc->node);
128 idma64c->desc = to_idma64_desc(vdesc);
129
130
131 idma64_chan_init(idma64, idma64c);
132
133
134 idma64_chan_start(idma64, idma64c);
135}
136
137
138
139static void idma64_chan_irq(struct idma64 *idma64, unsigned short c,
140 u32 status_err, u32 status_xfer)
141{
142 struct idma64_chan *idma64c = &idma64->chan[c];
143 struct idma64_desc *desc;
144 unsigned long flags;
145
146 spin_lock_irqsave(&idma64c->vchan.lock, flags);
147 desc = idma64c->desc;
148 if (desc) {
149 if (status_err & (1 << c)) {
150 dma_writel(idma64, CLEAR(ERROR), idma64c->mask);
151 desc->status = DMA_ERROR;
152 } else if (status_xfer & (1 << c)) {
153 dma_writel(idma64, CLEAR(XFER), idma64c->mask);
154 desc->status = DMA_COMPLETE;
155 vchan_cookie_complete(&desc->vdesc);
156 idma64_start_transfer(idma64c);
157 }
158
159
160 if (idma64c->desc == NULL || desc->status == DMA_ERROR)
161 idma64_stop_transfer(idma64c);
162 }
163 spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
164}
165
166static irqreturn_t idma64_irq(int irq, void *dev)
167{
168 struct idma64 *idma64 = dev;
169 u32 status = dma_readl(idma64, STATUS_INT);
170 u32 status_xfer;
171 u32 status_err;
172 unsigned short i;
173
174 dev_vdbg(idma64->dma.dev, "%s: status=%#x\n", __func__, status);
175
176
177 if (!status)
178 return IRQ_NONE;
179
180 status_xfer = dma_readl(idma64, RAW(XFER));
181 status_err = dma_readl(idma64, RAW(ERROR));
182
183 for (i = 0; i < idma64->dma.chancnt; i++)
184 idma64_chan_irq(idma64, i, status_err, status_xfer);
185
186 return IRQ_HANDLED;
187}
188
189
190
191static struct idma64_desc *idma64_alloc_desc(unsigned int ndesc)
192{
193 struct idma64_desc *desc;
194
195 desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
196 if (!desc)
197 return NULL;
198
199 desc->hw = kcalloc(ndesc, sizeof(*desc->hw), GFP_NOWAIT);
200 if (!desc->hw) {
201 kfree(desc);
202 return NULL;
203 }
204
205 return desc;
206}
207
208static void idma64_desc_free(struct idma64_chan *idma64c,
209 struct idma64_desc *desc)
210{
211 struct idma64_hw_desc *hw;
212
213 if (desc->ndesc) {
214 unsigned int i = desc->ndesc;
215
216 do {
217 hw = &desc->hw[--i];
218 dma_pool_free(idma64c->pool, hw->lli, hw->llp);
219 } while (i);
220 }
221
222 kfree(desc->hw);
223 kfree(desc);
224}
225
226static void idma64_vdesc_free(struct virt_dma_desc *vdesc)
227{
228 struct idma64_chan *idma64c = to_idma64_chan(vdesc->tx.chan);
229
230 idma64_desc_free(idma64c, to_idma64_desc(vdesc));
231}
232
233static void idma64_hw_desc_fill(struct idma64_hw_desc *hw,
234 struct dma_slave_config *config,
235 enum dma_transfer_direction direction, u64 llp)
236{
237 struct idma64_lli *lli = hw->lli;
238 u64 sar, dar;
239 u32 ctlhi = IDMA64C_CTLH_BLOCK_TS(hw->len);
240 u32 ctllo = IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN;
241 u32 src_width, dst_width;
242
243 if (direction == DMA_MEM_TO_DEV) {
244 sar = hw->phys;
245 dar = config->dst_addr;
246 ctllo |= IDMA64C_CTLL_DST_FIX | IDMA64C_CTLL_SRC_INC |
247 IDMA64C_CTLL_FC_M2P;
248 src_width = __ffs(sar | hw->len | 4);
249 dst_width = __ffs(config->dst_addr_width);
250 } else {
251 sar = config->src_addr;
252 dar = hw->phys;
253 ctllo |= IDMA64C_CTLL_DST_INC | IDMA64C_CTLL_SRC_FIX |
254 IDMA64C_CTLL_FC_P2M;
255 src_width = __ffs(config->src_addr_width);
256 dst_width = __ffs(dar | hw->len | 4);
257 }
258
259 lli->sar = sar;
260 lli->dar = dar;
261
262 lli->ctlhi = ctlhi;
263 lli->ctllo = ctllo |
264 IDMA64C_CTLL_SRC_MSIZE(config->src_maxburst) |
265 IDMA64C_CTLL_DST_MSIZE(config->dst_maxburst) |
266 IDMA64C_CTLL_DST_WIDTH(dst_width) |
267 IDMA64C_CTLL_SRC_WIDTH(src_width);
268
269 lli->llp = llp;
270}
271
272static void idma64_desc_fill(struct idma64_chan *idma64c,
273 struct idma64_desc *desc)
274{
275 struct dma_slave_config *config = &idma64c->config;
276 unsigned int i = desc->ndesc;
277 struct idma64_hw_desc *hw = &desc->hw[i - 1];
278 struct idma64_lli *lli = hw->lli;
279 u64 llp = 0;
280
281
282 do {
283 hw = &desc->hw[--i];
284 idma64_hw_desc_fill(hw, config, desc->direction, llp);
285 llp = hw->llp;
286 desc->length += hw->len;
287 } while (i);
288
289
290 lli->ctllo |= IDMA64C_CTLL_INT_EN;
291
292
293 lli->ctllo &= ~(IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN);
294}
295
296static struct dma_async_tx_descriptor *idma64_prep_slave_sg(
297 struct dma_chan *chan, struct scatterlist *sgl,
298 unsigned int sg_len, enum dma_transfer_direction direction,
299 unsigned long flags, void *context)
300{
301 struct idma64_chan *idma64c = to_idma64_chan(chan);
302 struct idma64_desc *desc;
303 struct scatterlist *sg;
304 unsigned int i;
305
306 desc = idma64_alloc_desc(sg_len);
307 if (!desc)
308 return NULL;
309
310 for_each_sg(sgl, sg, sg_len, i) {
311 struct idma64_hw_desc *hw = &desc->hw[i];
312
313
314 hw->lli = dma_pool_alloc(idma64c->pool, GFP_NOWAIT, &hw->llp);
315 if (!hw->lli) {
316 desc->ndesc = i;
317 idma64_desc_free(idma64c, desc);
318 return NULL;
319 }
320
321 hw->phys = sg_dma_address(sg);
322 hw->len = sg_dma_len(sg);
323 }
324
325 desc->ndesc = sg_len;
326 desc->direction = direction;
327 desc->status = DMA_IN_PROGRESS;
328
329 idma64_desc_fill(idma64c, desc);
330 return vchan_tx_prep(&idma64c->vchan, &desc->vdesc, flags);
331}
332
333static void idma64_issue_pending(struct dma_chan *chan)
334{
335 struct idma64_chan *idma64c = to_idma64_chan(chan);
336 unsigned long flags;
337
338 spin_lock_irqsave(&idma64c->vchan.lock, flags);
339 if (vchan_issue_pending(&idma64c->vchan) && !idma64c->desc)
340 idma64_start_transfer(idma64c);
341 spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
342}
343
344static size_t idma64_active_desc_size(struct idma64_chan *idma64c)
345{
346 struct idma64_desc *desc = idma64c->desc;
347 struct idma64_hw_desc *hw;
348 size_t bytes = desc->length;
349 u64 llp = channel_readq(idma64c, LLP);
350 u32 ctlhi = channel_readl(idma64c, CTL_HI);
351 unsigned int i = 0;
352
353 do {
354 hw = &desc->hw[i];
355 if (hw->llp == llp)
356 break;
357 bytes -= hw->len;
358 } while (++i < desc->ndesc);
359
360 if (!i)
361 return bytes;
362
363
364 bytes += desc->hw[--i].len;
365
366 return bytes - IDMA64C_CTLH_BLOCK_TS(ctlhi);
367}
368
369static enum dma_status idma64_tx_status(struct dma_chan *chan,
370 dma_cookie_t cookie, struct dma_tx_state *state)
371{
372 struct idma64_chan *idma64c = to_idma64_chan(chan);
373 struct virt_dma_desc *vdesc;
374 enum dma_status status;
375 size_t bytes;
376 unsigned long flags;
377
378 status = dma_cookie_status(chan, cookie, state);
379 if (status == DMA_COMPLETE)
380 return status;
381
382 spin_lock_irqsave(&idma64c->vchan.lock, flags);
383 vdesc = vchan_find_desc(&idma64c->vchan, cookie);
384 if (idma64c->desc && cookie == idma64c->desc->vdesc.tx.cookie) {
385 bytes = idma64_active_desc_size(idma64c);
386 dma_set_residue(state, bytes);
387 status = idma64c->desc->status;
388 } else if (vdesc) {
389 bytes = to_idma64_desc(vdesc)->length;
390 dma_set_residue(state, bytes);
391 }
392 spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
393
394 return status;
395}
396
397static void convert_burst(u32 *maxburst)
398{
399 if (*maxburst)
400 *maxburst = __fls(*maxburst);
401 else
402 *maxburst = 0;
403}
404
405static int idma64_slave_config(struct dma_chan *chan,
406 struct dma_slave_config *config)
407{
408 struct idma64_chan *idma64c = to_idma64_chan(chan);
409
410
411 if (!is_slave_direction(config->direction))
412 return -EINVAL;
413
414 memcpy(&idma64c->config, config, sizeof(idma64c->config));
415
416 convert_burst(&idma64c->config.src_maxburst);
417 convert_burst(&idma64c->config.dst_maxburst);
418
419 return 0;
420}
421
422static void idma64_chan_deactivate(struct idma64_chan *idma64c, bool drain)
423{
424 unsigned short count = 100;
425 u32 cfglo;
426
427 cfglo = channel_readl(idma64c, CFG_LO);
428 if (drain)
429 cfglo |= IDMA64C_CFGL_CH_DRAIN;
430 else
431 cfglo &= ~IDMA64C_CFGL_CH_DRAIN;
432
433 channel_writel(idma64c, CFG_LO, cfglo | IDMA64C_CFGL_CH_SUSP);
434 do {
435 udelay(1);
436 cfglo = channel_readl(idma64c, CFG_LO);
437 } while (!(cfglo & IDMA64C_CFGL_FIFO_EMPTY) && --count);
438}
439
440static void idma64_chan_activate(struct idma64_chan *idma64c)
441{
442 u32 cfglo;
443
444 cfglo = channel_readl(idma64c, CFG_LO);
445 channel_writel(idma64c, CFG_LO, cfglo & ~IDMA64C_CFGL_CH_SUSP);
446}
447
448static int idma64_pause(struct dma_chan *chan)
449{
450 struct idma64_chan *idma64c = to_idma64_chan(chan);
451 unsigned long flags;
452
453 spin_lock_irqsave(&idma64c->vchan.lock, flags);
454 if (idma64c->desc && idma64c->desc->status == DMA_IN_PROGRESS) {
455 idma64_chan_deactivate(idma64c, false);
456 idma64c->desc->status = DMA_PAUSED;
457 }
458 spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
459
460 return 0;
461}
462
463static int idma64_resume(struct dma_chan *chan)
464{
465 struct idma64_chan *idma64c = to_idma64_chan(chan);
466 unsigned long flags;
467
468 spin_lock_irqsave(&idma64c->vchan.lock, flags);
469 if (idma64c->desc && idma64c->desc->status == DMA_PAUSED) {
470 idma64c->desc->status = DMA_IN_PROGRESS;
471 idma64_chan_activate(idma64c);
472 }
473 spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
474
475 return 0;
476}
477
478static int idma64_terminate_all(struct dma_chan *chan)
479{
480 struct idma64_chan *idma64c = to_idma64_chan(chan);
481 unsigned long flags;
482 LIST_HEAD(head);
483
484 spin_lock_irqsave(&idma64c->vchan.lock, flags);
485 idma64_chan_deactivate(idma64c, true);
486 idma64_stop_transfer(idma64c);
487 if (idma64c->desc) {
488 idma64_vdesc_free(&idma64c->desc->vdesc);
489 idma64c->desc = NULL;
490 }
491 vchan_get_all_descriptors(&idma64c->vchan, &head);
492 spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
493
494 vchan_dma_desc_free_list(&idma64c->vchan, &head);
495 return 0;
496}
497
498static int idma64_alloc_chan_resources(struct dma_chan *chan)
499{
500 struct idma64_chan *idma64c = to_idma64_chan(chan);
501
502
503 idma64c->pool = dma_pool_create(dev_name(chan2dev(chan)),
504 chan->device->dev,
505 sizeof(struct idma64_lli), 8, 0);
506 if (!idma64c->pool) {
507 dev_err(chan2dev(chan), "No memory for descriptors\n");
508 return -ENOMEM;
509 }
510
511 return 0;
512}
513
514static void idma64_free_chan_resources(struct dma_chan *chan)
515{
516 struct idma64_chan *idma64c = to_idma64_chan(chan);
517
518 vchan_free_chan_resources(to_virt_chan(chan));
519 dma_pool_destroy(idma64c->pool);
520 idma64c->pool = NULL;
521}
522
523
524
525#define IDMA64_BUSWIDTHS \
526 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
527 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
528 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
529
530static int idma64_probe(struct idma64_chip *chip)
531{
532 struct idma64 *idma64;
533 unsigned short nr_chan = IDMA64_NR_CHAN;
534 unsigned short i;
535 int ret;
536
537 idma64 = devm_kzalloc(chip->dev, sizeof(*idma64), GFP_KERNEL);
538 if (!idma64)
539 return -ENOMEM;
540
541 idma64->regs = chip->regs;
542 chip->idma64 = idma64;
543
544 idma64->chan = devm_kcalloc(chip->dev, nr_chan, sizeof(*idma64->chan),
545 GFP_KERNEL);
546 if (!idma64->chan)
547 return -ENOMEM;
548
549 idma64->all_chan_mask = (1 << nr_chan) - 1;
550
551
552 idma64_off(idma64);
553
554 ret = devm_request_irq(chip->dev, chip->irq, idma64_irq, IRQF_SHARED,
555 dev_name(chip->dev), idma64);
556 if (ret)
557 return ret;
558
559 INIT_LIST_HEAD(&idma64->dma.channels);
560 for (i = 0; i < nr_chan; i++) {
561 struct idma64_chan *idma64c = &idma64->chan[i];
562
563 idma64c->vchan.desc_free = idma64_vdesc_free;
564 vchan_init(&idma64c->vchan, &idma64->dma);
565
566 idma64c->regs = idma64->regs + i * IDMA64_CH_LENGTH;
567 idma64c->mask = BIT(i);
568 }
569
570 dma_cap_set(DMA_SLAVE, idma64->dma.cap_mask);
571 dma_cap_set(DMA_PRIVATE, idma64->dma.cap_mask);
572
573 idma64->dma.device_alloc_chan_resources = idma64_alloc_chan_resources;
574 idma64->dma.device_free_chan_resources = idma64_free_chan_resources;
575
576 idma64->dma.device_prep_slave_sg = idma64_prep_slave_sg;
577
578 idma64->dma.device_issue_pending = idma64_issue_pending;
579 idma64->dma.device_tx_status = idma64_tx_status;
580
581 idma64->dma.device_config = idma64_slave_config;
582 idma64->dma.device_pause = idma64_pause;
583 idma64->dma.device_resume = idma64_resume;
584 idma64->dma.device_terminate_all = idma64_terminate_all;
585
586 idma64->dma.src_addr_widths = IDMA64_BUSWIDTHS;
587 idma64->dma.dst_addr_widths = IDMA64_BUSWIDTHS;
588 idma64->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
589 idma64->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
590
591 idma64->dma.dev = chip->dev;
592
593 dma_set_max_seg_size(idma64->dma.dev, IDMA64C_CTLH_BLOCK_TS_MASK);
594
595 ret = dma_async_device_register(&idma64->dma);
596 if (ret)
597 return ret;
598
599 dev_info(chip->dev, "Found Intel integrated DMA 64-bit\n");
600 return 0;
601}
602
603static int idma64_remove(struct idma64_chip *chip)
604{
605 struct idma64 *idma64 = chip->idma64;
606 unsigned short i;
607
608 dma_async_device_unregister(&idma64->dma);
609
610
611
612
613
614 devm_free_irq(chip->dev, chip->irq, idma64);
615
616 for (i = 0; i < idma64->dma.chancnt; i++) {
617 struct idma64_chan *idma64c = &idma64->chan[i];
618
619 tasklet_kill(&idma64c->vchan.task);
620 }
621
622 return 0;
623}
624
625
626
627static int idma64_platform_probe(struct platform_device *pdev)
628{
629 struct idma64_chip *chip;
630 struct device *dev = &pdev->dev;
631 struct resource *mem;
632 int ret;
633
634 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
635 if (!chip)
636 return -ENOMEM;
637
638 chip->irq = platform_get_irq(pdev, 0);
639 if (chip->irq < 0)
640 return chip->irq;
641
642 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
643 chip->regs = devm_ioremap_resource(dev, mem);
644 if (IS_ERR(chip->regs))
645 return PTR_ERR(chip->regs);
646
647 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
648 if (ret)
649 return ret;
650
651 chip->dev = dev;
652
653 ret = idma64_probe(chip);
654 if (ret)
655 return ret;
656
657 platform_set_drvdata(pdev, chip);
658 return 0;
659}
660
661static int idma64_platform_remove(struct platform_device *pdev)
662{
663 struct idma64_chip *chip = platform_get_drvdata(pdev);
664
665 return idma64_remove(chip);
666}
667
668#ifdef CONFIG_PM_SLEEP
669
670static int idma64_pm_suspend(struct device *dev)
671{
672 struct idma64_chip *chip = dev_get_drvdata(dev);
673
674 idma64_off(chip->idma64);
675 return 0;
676}
677
678static int idma64_pm_resume(struct device *dev)
679{
680 struct idma64_chip *chip = dev_get_drvdata(dev);
681
682 idma64_on(chip->idma64);
683 return 0;
684}
685
686#endif
687
688static const struct dev_pm_ops idma64_dev_pm_ops = {
689 SET_SYSTEM_SLEEP_PM_OPS(idma64_pm_suspend, idma64_pm_resume)
690};
691
692static struct platform_driver idma64_platform_driver = {
693 .probe = idma64_platform_probe,
694 .remove = idma64_platform_remove,
695 .driver = {
696 .name = LPSS_IDMA64_DRIVER_NAME,
697 .pm = &idma64_dev_pm_ops,
698 },
699};
700
701module_platform_driver(idma64_platform_driver);
702
703MODULE_LICENSE("GPL v2");
704MODULE_DESCRIPTION("iDMA64 core driver");
705MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
706MODULE_ALIAS("platform:" LPSS_IDMA64_DRIVER_NAME);
707
