linux/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
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   1/*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Christian König
  23 */
  24#ifndef __AMDGPU_RING_H__
  25#define __AMDGPU_RING_H__
  26
  27#include <drm/amdgpu_drm.h>
  28#include <drm/gpu_scheduler.h>
  29#include <drm/drm_print.h>
  30
  31/* max number of rings */
  32#define AMDGPU_MAX_RINGS                28
  33#define AMDGPU_MAX_GFX_RINGS            2
  34#define AMDGPU_MAX_COMPUTE_RINGS        8
  35#define AMDGPU_MAX_VCE_RINGS            3
  36#define AMDGPU_MAX_UVD_ENC_RINGS        2
  37
  38/* some special values for the owner field */
  39#define AMDGPU_FENCE_OWNER_UNDEFINED    ((void *)0ul)
  40#define AMDGPU_FENCE_OWNER_VM           ((void *)1ul)
  41#define AMDGPU_FENCE_OWNER_KFD          ((void *)2ul)
  42
  43#define AMDGPU_FENCE_FLAG_64BIT         (1 << 0)
  44#define AMDGPU_FENCE_FLAG_INT           (1 << 1)
  45#define AMDGPU_FENCE_FLAG_TC_WB_ONLY    (1 << 2)
  46
  47#define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
  48
  49enum amdgpu_ring_type {
  50        AMDGPU_RING_TYPE_GFX,
  51        AMDGPU_RING_TYPE_COMPUTE,
  52        AMDGPU_RING_TYPE_SDMA,
  53        AMDGPU_RING_TYPE_UVD,
  54        AMDGPU_RING_TYPE_VCE,
  55        AMDGPU_RING_TYPE_KIQ,
  56        AMDGPU_RING_TYPE_UVD_ENC,
  57        AMDGPU_RING_TYPE_VCN_DEC,
  58        AMDGPU_RING_TYPE_VCN_ENC,
  59        AMDGPU_RING_TYPE_VCN_JPEG
  60};
  61
  62struct amdgpu_device;
  63struct amdgpu_ring;
  64struct amdgpu_ib;
  65struct amdgpu_cs_parser;
  66struct amdgpu_job;
  67
  68/*
  69 * Fences.
  70 */
  71struct amdgpu_fence_driver {
  72        uint64_t                        gpu_addr;
  73        volatile uint32_t               *cpu_addr;
  74        /* sync_seq is protected by ring emission lock */
  75        uint32_t                        sync_seq;
  76        atomic_t                        last_seq;
  77        bool                            initialized;
  78        struct amdgpu_irq_src           *irq_src;
  79        unsigned                        irq_type;
  80        struct timer_list               fallback_timer;
  81        unsigned                        num_fences_mask;
  82        spinlock_t                      lock;
  83        struct dma_fence                **fences;
  84};
  85
  86int amdgpu_fence_driver_init(struct amdgpu_device *adev);
  87void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
  88void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
  89
  90int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
  91                                  unsigned num_hw_submission);
  92int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
  93                                   struct amdgpu_irq_src *irq_src,
  94                                   unsigned irq_type);
  95void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
  96void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
  97int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence,
  98                      unsigned flags);
  99int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s);
 100bool amdgpu_fence_process(struct amdgpu_ring *ring);
 101int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
 102signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
 103                                      uint32_t wait_seq,
 104                                      signed long timeout);
 105unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
 106
 107/*
 108 * Rings.
 109 */
 110
 111/* provided by hw blocks that expose a ring buffer for commands */
 112struct amdgpu_ring_funcs {
 113        enum amdgpu_ring_type   type;
 114        uint32_t                align_mask;
 115        u32                     nop;
 116        bool                    support_64bit_ptrs;
 117        bool                    no_user_fence;
 118        unsigned                vmhub;
 119        unsigned                extra_dw;
 120
 121        /* ring read/write ptr handling */
 122        u64 (*get_rptr)(struct amdgpu_ring *ring);
 123        u64 (*get_wptr)(struct amdgpu_ring *ring);
 124        void (*set_wptr)(struct amdgpu_ring *ring);
 125        /* validating and patching of IBs */
 126        int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
 127        int (*patch_cs_in_place)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
 128        /* constants to calculate how many DW are needed for an emit */
 129        unsigned emit_frame_size;
 130        unsigned emit_ib_size;
 131        /* command emit functions */
 132        void (*emit_ib)(struct amdgpu_ring *ring,
 133                        struct amdgpu_job *job,
 134                        struct amdgpu_ib *ib,
 135                        uint32_t flags);
 136        void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
 137                           uint64_t seq, unsigned flags);
 138        void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
 139        void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,
 140                              uint64_t pd_addr);
 141        void (*emit_hdp_flush)(struct amdgpu_ring *ring);
 142        void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
 143                                uint32_t gds_base, uint32_t gds_size,
 144                                uint32_t gws_base, uint32_t gws_size,
 145                                uint32_t oa_base, uint32_t oa_size);
 146        /* testing functions */
 147        int (*test_ring)(struct amdgpu_ring *ring);
 148        int (*test_ib)(struct amdgpu_ring *ring, long timeout);
 149        /* insert NOP packets */
 150        void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
 151        void (*insert_start)(struct amdgpu_ring *ring);
 152        void (*insert_end)(struct amdgpu_ring *ring);
 153        /* pad the indirect buffer to the necessary number of dw */
 154        void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
 155        unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
 156        void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
 157        /* note usage for clock and power gating */
 158        void (*begin_use)(struct amdgpu_ring *ring);
 159        void (*end_use)(struct amdgpu_ring *ring);
 160        void (*emit_switch_buffer) (struct amdgpu_ring *ring);
 161        void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
 162        void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
 163        void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
 164        void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
 165                              uint32_t val, uint32_t mask);
 166        void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring,
 167                                        uint32_t reg0, uint32_t reg1,
 168                                        uint32_t ref, uint32_t mask);
 169        void (*emit_tmz)(struct amdgpu_ring *ring, bool start);
 170        /* priority functions */
 171        void (*set_priority) (struct amdgpu_ring *ring,
 172                              enum drm_sched_priority priority);
 173        /* Try to soft recover the ring to make the fence signal */
 174        void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid);
 175        int (*preempt_ib)(struct amdgpu_ring *ring);
 176};
 177
 178struct amdgpu_ring {
 179        struct amdgpu_device            *adev;
 180        const struct amdgpu_ring_funcs  *funcs;
 181        struct amdgpu_fence_driver      fence_drv;
 182        struct drm_gpu_scheduler        sched;
 183
 184        struct amdgpu_bo        *ring_obj;
 185        volatile uint32_t       *ring;
 186        unsigned                rptr_offs;
 187        u64                     wptr;
 188        u64                     wptr_old;
 189        unsigned                ring_size;
 190        unsigned                max_dw;
 191        int                     count_dw;
 192        uint64_t                gpu_addr;
 193        uint64_t                ptr_mask;
 194        uint32_t                buf_mask;
 195        u32                     idx;
 196        u32                     me;
 197        u32                     pipe;
 198        u32                     queue;
 199        struct amdgpu_bo        *mqd_obj;
 200        uint64_t                mqd_gpu_addr;
 201        void                    *mqd_ptr;
 202        uint64_t                eop_gpu_addr;
 203        u32                     doorbell_index;
 204        bool                    use_doorbell;
 205        bool                    use_pollmem;
 206        unsigned                wptr_offs;
 207        unsigned                fence_offs;
 208        uint64_t                current_ctx;
 209        char                    name[16];
 210        u32                     trail_seq;
 211        unsigned                trail_fence_offs;
 212        u64                     trail_fence_gpu_addr;
 213        volatile u32            *trail_fence_cpu_addr;
 214        unsigned                cond_exe_offs;
 215        u64                     cond_exe_gpu_addr;
 216        volatile u32            *cond_exe_cpu_addr;
 217        unsigned                vm_inv_eng;
 218        struct dma_fence        *vmid_wait;
 219        bool                    has_compute_vm_bug;
 220
 221        atomic_t                num_jobs[DRM_SCHED_PRIORITY_MAX];
 222        struct mutex            priority_mutex;
 223        /* protected by priority_mutex */
 224        int                     priority;
 225
 226#if defined(CONFIG_DEBUG_FS)
 227        struct dentry *ent;
 228#endif
 229};
 230
 231#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
 232#define amdgpu_ring_patch_cs_in_place(r, p, ib) ((r)->funcs->patch_cs_in_place((p), (ib)))
 233#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
 234#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
 235#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
 236#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
 237#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
 238#define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags)))
 239#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
 240#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
 241#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
 242#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
 243#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
 244#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
 245#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
 246#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
 247#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
 248#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
 249#define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
 250#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
 251#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
 252#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
 253#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
 254#define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r)
 255
 256int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
 257void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
 258void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
 259void amdgpu_ring_commit(struct amdgpu_ring *ring);
 260void amdgpu_ring_undo(struct amdgpu_ring *ring);
 261void amdgpu_ring_priority_get(struct amdgpu_ring *ring,
 262                              enum drm_sched_priority priority);
 263void amdgpu_ring_priority_put(struct amdgpu_ring *ring,
 264                              enum drm_sched_priority priority);
 265int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
 266                     unsigned ring_size, struct amdgpu_irq_src *irq_src,
 267                     unsigned irq_type);
 268void amdgpu_ring_fini(struct amdgpu_ring *ring);
 269void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
 270                                                uint32_t reg0, uint32_t val0,
 271                                                uint32_t reg1, uint32_t val1);
 272bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
 273                               struct dma_fence *fence);
 274
 275static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring,
 276                                                        bool cond_exec)
 277{
 278        *ring->cond_exe_cpu_addr = cond_exec;
 279}
 280
 281static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
 282{
 283        int i = 0;
 284        while (i <= ring->buf_mask)
 285                ring->ring[i++] = ring->funcs->nop;
 286
 287}
 288
 289static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
 290{
 291        if (ring->count_dw <= 0)
 292                DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
 293        ring->ring[ring->wptr++ & ring->buf_mask] = v;
 294        ring->wptr &= ring->ptr_mask;
 295        ring->count_dw--;
 296}
 297
 298static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring,
 299                                              void *src, int count_dw)
 300{
 301        unsigned occupied, chunk1, chunk2;
 302        void *dst;
 303
 304        if (unlikely(ring->count_dw < count_dw))
 305                DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
 306
 307        occupied = ring->wptr & ring->buf_mask;
 308        dst = (void *)&ring->ring[occupied];
 309        chunk1 = ring->buf_mask + 1 - occupied;
 310        chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
 311        chunk2 = count_dw - chunk1;
 312        chunk1 <<= 2;
 313        chunk2 <<= 2;
 314
 315        if (chunk1)
 316                memcpy(dst, src, chunk1);
 317
 318        if (chunk2) {
 319                src += chunk1;
 320                dst = (void *)ring->ring;
 321                memcpy(dst, src, chunk2);
 322        }
 323
 324        ring->wptr += count_dw;
 325        ring->wptr &= ring->ptr_mask;
 326        ring->count_dw -= count_dw;
 327}
 328
 329int amdgpu_ring_test_helper(struct amdgpu_ring *ring);
 330
 331#endif
 332
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