linux/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
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   1/*
   2 * Copyright 2012-15 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26
  27#include "reg_helper.h"
  28#include "dcn10_optc.h"
  29#include "dc.h"
  30
  31#define REG(reg)\
  32        optc1->tg_regs->reg
  33
  34#define CTX \
  35        optc1->base.ctx
  36
  37#undef FN
  38#define FN(reg_name, field_name) \
  39        optc1->tg_shift->field_name, optc1->tg_mask->field_name
  40
  41#define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100
  42
  43/**
  44* apply_front_porch_workaround  TODO FPGA still need?
  45*
  46* This is a workaround for a bug that has existed since R5xx and has not been
  47* fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
  48*/
  49static void apply_front_porch_workaround(struct dc_crtc_timing *timing)
  50{
  51        if (timing->flags.INTERLACE == 1) {
  52                if (timing->v_front_porch < 2)
  53                        timing->v_front_porch = 2;
  54        } else {
  55                if (timing->v_front_porch < 1)
  56                        timing->v_front_porch = 1;
  57        }
  58}
  59
  60void optc1_program_global_sync(
  61                struct timing_generator *optc,
  62                int vready_offset,
  63                int vstartup_start,
  64                int vupdate_offset,
  65                int vupdate_width)
  66{
  67        struct optc *optc1 = DCN10TG_FROM_TG(optc);
  68
  69        optc1->vready_offset = vready_offset;
  70        optc1->vstartup_start = vstartup_start;
  71        optc1->vupdate_offset = vupdate_offset;
  72        optc1->vupdate_width = vupdate_width;
  73
  74        if (optc1->vstartup_start == 0) {
  75                BREAK_TO_DEBUGGER();
  76                return;
  77        }
  78
  79        REG_SET(OTG_VSTARTUP_PARAM, 0,
  80                VSTARTUP_START, optc1->vstartup_start);
  81
  82        REG_SET_2(OTG_VUPDATE_PARAM, 0,
  83                        VUPDATE_OFFSET, optc1->vupdate_offset,
  84                        VUPDATE_WIDTH, optc1->vupdate_width);
  85
  86        REG_SET(OTG_VREADY_PARAM, 0,
  87                        VREADY_OFFSET, optc1->vready_offset);
  88}
  89
  90static void optc1_disable_stereo(struct timing_generator *optc)
  91{
  92        struct optc *optc1 = DCN10TG_FROM_TG(optc);
  93
  94        REG_SET(OTG_STEREO_CONTROL, 0,
  95                OTG_STEREO_EN, 0);
  96
  97        REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0,
  98                OTG_3D_STRUCTURE_EN, 0,
  99                OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0);
 100}
 101
 102void optc1_setup_vertical_interrupt0(
 103                struct timing_generator *optc,
 104                uint32_t start_line,
 105                uint32_t end_line)
 106{
 107        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 108
 109        REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0,
 110                        OTG_VERTICAL_INTERRUPT0_LINE_START, start_line,
 111                        OTG_VERTICAL_INTERRUPT0_LINE_END, end_line);
 112}
 113
 114void optc1_setup_vertical_interrupt1(
 115                struct timing_generator *optc,
 116                uint32_t start_line)
 117{
 118        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 119
 120        REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0,
 121                                OTG_VERTICAL_INTERRUPT1_LINE_START, start_line);
 122}
 123
 124void optc1_setup_vertical_interrupt2(
 125                struct timing_generator *optc,
 126                uint32_t start_line)
 127{
 128        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 129
 130        REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0,
 131                        OTG_VERTICAL_INTERRUPT2_LINE_START, start_line);
 132}
 133
 134/**
 135 * program_timing_generator   used by mode timing set
 136 * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition.
 137 * Including SYNC. Call BIOS command table to program Timings.
 138 */
 139void optc1_program_timing(
 140        struct timing_generator *optc,
 141        const struct dc_crtc_timing *dc_crtc_timing,
 142        int vready_offset,
 143        int vstartup_start,
 144        int vupdate_offset,
 145        int vupdate_width,
 146        const enum signal_type signal,
 147        bool use_vbios)
 148{
 149        struct dc_crtc_timing patched_crtc_timing;
 150        uint32_t asic_blank_end;
 151        uint32_t asic_blank_start;
 152        uint32_t v_total;
 153        uint32_t v_sync_end;
 154        uint32_t h_sync_polarity, v_sync_polarity;
 155        uint32_t start_point = 0;
 156        uint32_t field_num = 0;
 157        enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
 158
 159        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 160
 161        optc1->signal = signal;
 162        optc1->vready_offset = vready_offset;
 163        optc1->vstartup_start = vstartup_start;
 164        optc1->vupdate_offset = vupdate_offset;
 165        optc1->vupdate_width = vupdate_width;
 166        patched_crtc_timing = *dc_crtc_timing;
 167        apply_front_porch_workaround(&patched_crtc_timing);
 168
 169        /* Load horizontal timing */
 170
 171        /* CRTC_H_TOTAL = vesa.h_total - 1 */
 172        REG_SET(OTG_H_TOTAL, 0,
 173                        OTG_H_TOTAL,  patched_crtc_timing.h_total - 1);
 174
 175        /* h_sync_start = 0, h_sync_end = vesa.h_sync_width */
 176        REG_UPDATE_2(OTG_H_SYNC_A,
 177                        OTG_H_SYNC_A_START, 0,
 178                        OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width);
 179
 180        /* blank_start = line end - front porch */
 181        asic_blank_start = patched_crtc_timing.h_total -
 182                        patched_crtc_timing.h_front_porch;
 183
 184        /* blank_end = blank_start - active */
 185        asic_blank_end = asic_blank_start -
 186                        patched_crtc_timing.h_border_right -
 187                        patched_crtc_timing.h_addressable -
 188                        patched_crtc_timing.h_border_left;
 189
 190        REG_UPDATE_2(OTG_H_BLANK_START_END,
 191                        OTG_H_BLANK_START, asic_blank_start,
 192                        OTG_H_BLANK_END, asic_blank_end);
 193
 194        /* h_sync polarity */
 195        h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ?
 196                        0 : 1;
 197
 198        REG_UPDATE(OTG_H_SYNC_A_CNTL,
 199                        OTG_H_SYNC_A_POL, h_sync_polarity);
 200
 201        v_total = patched_crtc_timing.v_total - 1;
 202
 203        REG_SET(OTG_V_TOTAL, 0,
 204                        OTG_V_TOTAL, v_total);
 205
 206        /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and
 207         * OTG_V_TOTAL_MIN are equal to V_TOTAL.
 208         */
 209        REG_SET(OTG_V_TOTAL_MAX, 0,
 210                OTG_V_TOTAL_MAX, v_total);
 211        REG_SET(OTG_V_TOTAL_MIN, 0,
 212                OTG_V_TOTAL_MIN, v_total);
 213
 214        /* v_sync_start = 0, v_sync_end = v_sync_width */
 215        v_sync_end = patched_crtc_timing.v_sync_width;
 216
 217        REG_UPDATE_2(OTG_V_SYNC_A,
 218                        OTG_V_SYNC_A_START, 0,
 219                        OTG_V_SYNC_A_END, v_sync_end);
 220
 221        /* blank_start = frame end - front porch */
 222        asic_blank_start = patched_crtc_timing.v_total -
 223                        patched_crtc_timing.v_front_porch;
 224
 225        /* blank_end = blank_start - active */
 226        asic_blank_end = asic_blank_start -
 227                        patched_crtc_timing.v_border_bottom -
 228                        patched_crtc_timing.v_addressable -
 229                        patched_crtc_timing.v_border_top;
 230
 231        REG_UPDATE_2(OTG_V_BLANK_START_END,
 232                        OTG_V_BLANK_START, asic_blank_start,
 233                        OTG_V_BLANK_END, asic_blank_end);
 234
 235        /* v_sync polarity */
 236        v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ?
 237                        0 : 1;
 238
 239        REG_UPDATE(OTG_V_SYNC_A_CNTL,
 240                OTG_V_SYNC_A_POL, v_sync_polarity);
 241
 242        if (optc1->signal == SIGNAL_TYPE_DISPLAY_PORT ||
 243                        optc1->signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
 244                        optc1->signal == SIGNAL_TYPE_EDP) {
 245                start_point = 1;
 246                if (patched_crtc_timing.flags.INTERLACE == 1)
 247                        field_num = 1;
 248        }
 249
 250        /* Interlace */
 251        if (REG(OTG_INTERLACE_CONTROL)) {
 252                if (patched_crtc_timing.flags.INTERLACE == 1)
 253                        REG_UPDATE(OTG_INTERLACE_CONTROL,
 254                                        OTG_INTERLACE_ENABLE, 1);
 255                else
 256                        REG_UPDATE(OTG_INTERLACE_CONTROL,
 257                                        OTG_INTERLACE_ENABLE, 0);
 258        }
 259
 260        /* VTG enable set to 0 first VInit */
 261        REG_UPDATE(CONTROL,
 262                        VTG0_ENABLE, 0);
 263
 264        /* original code is using VTG offset to address OTG reg, seems wrong */
 265        REG_UPDATE_2(OTG_CONTROL,
 266                        OTG_START_POINT_CNTL, start_point,
 267                        OTG_FIELD_NUMBER_CNTL, field_num);
 268
 269        optc->funcs->program_global_sync(optc,
 270                        vready_offset,
 271                        vstartup_start,
 272                        vupdate_offset,
 273                        vupdate_width);
 274
 275        optc->funcs->set_vtg_params(optc, dc_crtc_timing);
 276
 277        /* TODO
 278         * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1
 279         * program_horz_count_by_2
 280         * for DVI 30bpp mode, 0 otherwise
 281         * program_horz_count_by_2(optc, &patched_crtc_timing);
 282         */
 283
 284        /* Enable stereo - only when we need to pack 3D frame. Other types
 285         * of stereo handled in explicit call
 286         */
 287
 288        if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2)
 289                h_div = H_TIMING_DIV_BY2;
 290
 291        REG_UPDATE(OTG_H_TIMING_CNTL,
 292                OTG_H_TIMING_DIV_BY2, h_div);
 293}
 294
 295void optc1_set_vtg_params(struct timing_generator *optc,
 296                const struct dc_crtc_timing *dc_crtc_timing)
 297{
 298        struct dc_crtc_timing patched_crtc_timing;
 299        uint32_t asic_blank_end;
 300        uint32_t v_init;
 301        uint32_t v_fp2 = 0;
 302        int32_t vertical_line_start;
 303
 304        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 305
 306        patched_crtc_timing = *dc_crtc_timing;
 307        apply_front_porch_workaround(&patched_crtc_timing);
 308
 309        /* VCOUNT_INIT is the start of blank */
 310        v_init = patched_crtc_timing.v_total - patched_crtc_timing.v_front_porch;
 311
 312        /* end of blank = v_init - active */
 313        asic_blank_end = v_init -
 314                        patched_crtc_timing.v_border_bottom -
 315                        patched_crtc_timing.v_addressable -
 316                        patched_crtc_timing.v_border_top;
 317
 318        /* if VSTARTUP is before VSYNC, FP2 is the offset, otherwise 0 */
 319        vertical_line_start = asic_blank_end - optc1->vstartup_start + 1;
 320        if (vertical_line_start < 0)
 321                v_fp2 = -vertical_line_start;
 322
 323        /* Interlace */
 324        if (REG(OTG_INTERLACE_CONTROL)) {
 325                if (patched_crtc_timing.flags.INTERLACE == 1) {
 326                        v_init = v_init / 2;
 327                        if ((optc1->vstartup_start/2)*2 > asic_blank_end)
 328                                v_fp2 = v_fp2 / 2;
 329                }
 330        }
 331
 332        REG_UPDATE_2(CONTROL,
 333                        VTG0_FP2, v_fp2,
 334                        VTG0_VCOUNT_INIT, v_init);
 335}
 336
 337void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable)
 338{
 339        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 340
 341        uint32_t blank_data_double_buffer_enable = enable ? 1 : 0;
 342
 343        REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
 344                        OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable);
 345}
 346
 347/**
 348 * unblank_crtc
 349 * Call ASIC Control Object to UnBlank CRTC.
 350 */
 351static void optc1_unblank_crtc(struct timing_generator *optc)
 352{
 353        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 354
 355        REG_UPDATE_2(OTG_BLANK_CONTROL,
 356                        OTG_BLANK_DATA_EN, 0,
 357                        OTG_BLANK_DE_MODE, 0);
 358
 359        /* W/A for automated testing
 360         * Automated testing will fail underflow test as there
 361         * sporadic underflows which occur during the optc blank
 362         * sequence.  As a w/a, clear underflow on unblank.
 363         * This prevents the failure, but will not mask actual
 364         * underflow that affect real use cases.
 365         */
 366        optc1_clear_optc_underflow(optc);
 367}
 368
 369/**
 370 * blank_crtc
 371 * Call ASIC Control Object to Blank CRTC.
 372 */
 373
 374static void optc1_blank_crtc(struct timing_generator *optc)
 375{
 376        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 377
 378        REG_UPDATE_2(OTG_BLANK_CONTROL,
 379                        OTG_BLANK_DATA_EN, 1,
 380                        OTG_BLANK_DE_MODE, 0);
 381
 382        optc1_set_blank_data_double_buffer(optc, false);
 383}
 384
 385void optc1_set_blank(struct timing_generator *optc,
 386                bool enable_blanking)
 387{
 388        if (enable_blanking)
 389                optc1_blank_crtc(optc);
 390        else
 391                optc1_unblank_crtc(optc);
 392}
 393
 394bool optc1_is_blanked(struct timing_generator *optc)
 395{
 396        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 397        uint32_t blank_en;
 398        uint32_t blank_state;
 399
 400        REG_GET_2(OTG_BLANK_CONTROL,
 401                        OTG_BLANK_DATA_EN, &blank_en,
 402                        OTG_CURRENT_BLANK_STATE, &blank_state);
 403
 404        return blank_en && blank_state;
 405}
 406
 407void optc1_enable_optc_clock(struct timing_generator *optc, bool enable)
 408{
 409        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 410
 411        if (enable) {
 412                REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
 413                                OPTC_INPUT_CLK_EN, 1,
 414                                OPTC_INPUT_CLK_GATE_DIS, 1);
 415
 416                REG_WAIT(OPTC_INPUT_CLOCK_CONTROL,
 417                                OPTC_INPUT_CLK_ON, 1,
 418                                1, 1000);
 419
 420                /* Enable clock */
 421                REG_UPDATE_2(OTG_CLOCK_CONTROL,
 422                                OTG_CLOCK_EN, 1,
 423                                OTG_CLOCK_GATE_DIS, 1);
 424                REG_WAIT(OTG_CLOCK_CONTROL,
 425                                OTG_CLOCK_ON, 1,
 426                                1, 1000);
 427        } else  {
 428                REG_UPDATE_2(OTG_CLOCK_CONTROL,
 429                                OTG_CLOCK_GATE_DIS, 0,
 430                                OTG_CLOCK_EN, 0);
 431
 432                REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
 433                                OPTC_INPUT_CLK_GATE_DIS, 0,
 434                                OPTC_INPUT_CLK_EN, 0);
 435        }
 436}
 437
 438/**
 439 * Enable CRTC
 440 * Enable CRTC - call ASIC Control Object to enable Timing generator.
 441 */
 442static bool optc1_enable_crtc(struct timing_generator *optc)
 443{
 444        /* TODO FPGA wait for answer
 445         * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE
 446         * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK
 447         */
 448        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 449
 450        /* opp instance for OTG. For DCN1.0, ODM is remoed.
 451         * OPP and OPTC should 1:1 mapping
 452         */
 453        REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
 454                        OPTC_SRC_SEL, optc->inst);
 455
 456        /* VTG enable first is for HW workaround */
 457        REG_UPDATE(CONTROL,
 458                        VTG0_ENABLE, 1);
 459
 460        REG_SEQ_START();
 461
 462        /* Enable CRTC */
 463        REG_UPDATE_2(OTG_CONTROL,
 464                        OTG_DISABLE_POINT_CNTL, 3,
 465                        OTG_MASTER_EN, 1);
 466
 467        REG_SEQ_SUBMIT();
 468        REG_SEQ_WAIT_DONE();
 469
 470        return true;
 471}
 472
 473/* disable_crtc - call ASIC Control Object to disable Timing generator. */
 474bool optc1_disable_crtc(struct timing_generator *optc)
 475{
 476        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 477
 478        /* disable otg request until end of the first line
 479         * in the vertical blank region
 480         */
 481        REG_UPDATE_2(OTG_CONTROL,
 482                        OTG_DISABLE_POINT_CNTL, 3,
 483                        OTG_MASTER_EN, 0);
 484
 485        REG_UPDATE(CONTROL,
 486                        VTG0_ENABLE, 0);
 487
 488        /* CRTC disabled, so disable  clock. */
 489        REG_WAIT(OTG_CLOCK_CONTROL,
 490                        OTG_BUSY, 0,
 491                        1, 100000);
 492
 493        return true;
 494}
 495
 496
 497void optc1_program_blank_color(
 498                struct timing_generator *optc,
 499                const struct tg_color *black_color)
 500{
 501        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 502
 503        REG_SET_3(OTG_BLACK_COLOR, 0,
 504                        OTG_BLACK_COLOR_B_CB, black_color->color_b_cb,
 505                        OTG_BLACK_COLOR_G_Y, black_color->color_g_y,
 506                        OTG_BLACK_COLOR_R_CR, black_color->color_r_cr);
 507}
 508
 509bool optc1_validate_timing(
 510        struct timing_generator *optc,
 511        const struct dc_crtc_timing *timing)
 512{
 513        uint32_t v_blank;
 514        uint32_t h_blank;
 515        uint32_t min_v_blank;
 516        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 517
 518        ASSERT(timing != NULL);
 519
 520        v_blank = (timing->v_total - timing->v_addressable -
 521                                        timing->v_border_top - timing->v_border_bottom);
 522
 523        h_blank = (timing->h_total - timing->h_addressable -
 524                timing->h_border_right -
 525                timing->h_border_left);
 526
 527        if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE &&
 528                timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING &&
 529                timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM &&
 530                timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE &&
 531                timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE &&
 532                timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA)
 533                return false;
 534
 535        /* Temporarily blocking interlacing mode until it's supported */
 536        if (timing->flags.INTERLACE == 1)
 537                return false;
 538
 539        /* Check maximum number of pixels supported by Timing Generator
 540         * (Currently will never fail, in order to fail needs display which
 541         * needs more than 8192 horizontal and
 542         * more than 8192 vertical total pixels)
 543         */
 544        if (timing->h_total > optc1->max_h_total ||
 545                timing->v_total > optc1->max_v_total)
 546                return false;
 547
 548
 549        if (h_blank < optc1->min_h_blank)
 550                return false;
 551
 552        if (timing->h_sync_width  < optc1->min_h_sync_width ||
 553                 timing->v_sync_width  < optc1->min_v_sync_width)
 554                return false;
 555
 556        min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank;
 557
 558        if (v_blank < min_v_blank)
 559                return false;
 560
 561        return true;
 562
 563}
 564
 565/*
 566 * get_vblank_counter
 567 *
 568 * @brief
 569 * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which
 570 * holds the counter of frames.
 571 *
 572 * @param
 573 * struct timing_generator *optc - [in] timing generator which controls the
 574 * desired CRTC
 575 *
 576 * @return
 577 * Counter of frames, which should equal to number of vblanks.
 578 */
 579uint32_t optc1_get_vblank_counter(struct timing_generator *optc)
 580{
 581        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 582        uint32_t frame_count;
 583
 584        REG_GET(OTG_STATUS_FRAME_COUNT,
 585                OTG_FRAME_COUNT, &frame_count);
 586
 587        return frame_count;
 588}
 589
 590void optc1_lock(struct timing_generator *optc)
 591{
 592        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 593        uint32_t regval = 0;
 594
 595        regval = REG_READ(OTG_CONTROL);
 596
 597        /* otg is not running, do not need to be locked */
 598        if ((regval & 0x1) == 0x0)
 599                return;
 600
 601        REG_SET(OTG_GLOBAL_CONTROL0, 0,
 602                        OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
 603        REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
 604                        OTG_MASTER_UPDATE_LOCK, 1);
 605
 606        /* Should be fast, status does not update on maximus */
 607        if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) {
 608
 609                REG_WAIT(OTG_MASTER_UPDATE_LOCK,
 610                                UPDATE_LOCK_STATUS, 1,
 611                                1, 10);
 612        }
 613}
 614
 615void optc1_unlock(struct timing_generator *optc)
 616{
 617        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 618
 619        REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
 620                        OTG_MASTER_UPDATE_LOCK, 0);
 621}
 622
 623void optc1_get_position(struct timing_generator *optc,
 624                struct crtc_position *position)
 625{
 626        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 627
 628        REG_GET_2(OTG_STATUS_POSITION,
 629                        OTG_HORZ_COUNT, &position->horizontal_count,
 630                        OTG_VERT_COUNT, &position->vertical_count);
 631
 632        REG_GET(OTG_NOM_VERT_POSITION,
 633                        OTG_VERT_COUNT_NOM, &position->nominal_vcount);
 634}
 635
 636bool optc1_is_counter_moving(struct timing_generator *optc)
 637{
 638        struct crtc_position position1, position2;
 639
 640        optc->funcs->get_position(optc, &position1);
 641        optc->funcs->get_position(optc, &position2);
 642
 643        if (position1.horizontal_count == position2.horizontal_count &&
 644                position1.vertical_count == position2.vertical_count)
 645                return false;
 646        else
 647                return true;
 648}
 649
 650bool optc1_did_triggered_reset_occur(
 651        struct timing_generator *optc)
 652{
 653        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 654        uint32_t occurred_force, occurred_vsync;
 655
 656        REG_GET(OTG_FORCE_COUNT_NOW_CNTL,
 657                OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force);
 658
 659        REG_GET(OTG_VERT_SYNC_CONTROL,
 660                OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync);
 661
 662        return occurred_vsync != 0 || occurred_force != 0;
 663}
 664
 665void optc1_disable_reset_trigger(struct timing_generator *optc)
 666{
 667        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 668
 669        REG_WRITE(OTG_TRIGA_CNTL, 0);
 670
 671        REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
 672                OTG_FORCE_COUNT_NOW_CLEAR, 1);
 673
 674        REG_SET(OTG_VERT_SYNC_CONTROL, 0,
 675                OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1);
 676}
 677
 678void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst)
 679{
 680        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 681        uint32_t falling_edge;
 682
 683        REG_GET(OTG_V_SYNC_A_CNTL,
 684                        OTG_V_SYNC_A_POL, &falling_edge);
 685
 686        if (falling_edge)
 687                REG_SET_3(OTG_TRIGA_CNTL, 0,
 688                                /* vsync signal from selected OTG pipe based
 689                                 * on OTG_TRIG_SOURCE_PIPE_SELECT setting
 690                                 */
 691                                OTG_TRIGA_SOURCE_SELECT, 20,
 692                                OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
 693                                /* always detect falling edge */
 694                                OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1);
 695        else
 696                REG_SET_3(OTG_TRIGA_CNTL, 0,
 697                                /* vsync signal from selected OTG pipe based
 698                                 * on OTG_TRIG_SOURCE_PIPE_SELECT setting
 699                                 */
 700                                OTG_TRIGA_SOURCE_SELECT, 20,
 701                                OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
 702                                /* always detect rising edge */
 703                                OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1);
 704
 705        REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
 706                        /* force H count to H_TOTAL and V count to V_TOTAL in
 707                         * progressive mode and V_TOTAL-1 in interlaced mode
 708                         */
 709                        OTG_FORCE_COUNT_NOW_MODE, 2);
 710}
 711
 712void optc1_enable_crtc_reset(
 713                struct timing_generator *optc,
 714                int source_tg_inst,
 715                struct crtc_trigger_info *crtc_tp)
 716{
 717        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 718        uint32_t falling_edge = 0;
 719        uint32_t rising_edge = 0;
 720
 721        switch (crtc_tp->event) {
 722
 723        case CRTC_EVENT_VSYNC_RISING:
 724                rising_edge = 1;
 725                break;
 726
 727        case CRTC_EVENT_VSYNC_FALLING:
 728                falling_edge = 1;
 729                break;
 730        }
 731
 732        REG_SET_4(OTG_TRIGA_CNTL, 0,
 733                 /* vsync signal from selected OTG pipe based
 734                  * on OTG_TRIG_SOURCE_PIPE_SELECT setting
 735                  */
 736                  OTG_TRIGA_SOURCE_SELECT, 20,
 737                  OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
 738                  /* always detect falling edge */
 739                  OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge,
 740                  OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge);
 741
 742        switch (crtc_tp->delay) {
 743        case TRIGGER_DELAY_NEXT_LINE:
 744                REG_SET(OTG_VERT_SYNC_CONTROL, 0,
 745                                OTG_AUTO_FORCE_VSYNC_MODE, 1);
 746                break;
 747        case TRIGGER_DELAY_NEXT_PIXEL:
 748                REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
 749                        /* force H count to H_TOTAL and V count to V_TOTAL in
 750                         * progressive mode and V_TOTAL-1 in interlaced mode
 751                         */
 752                        OTG_FORCE_COUNT_NOW_MODE, 2);
 753                break;
 754        }
 755}
 756
 757void optc1_wait_for_state(struct timing_generator *optc,
 758                enum crtc_state state)
 759{
 760        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 761
 762        switch (state) {
 763        case CRTC_STATE_VBLANK:
 764                REG_WAIT(OTG_STATUS,
 765                                OTG_V_BLANK, 1,
 766                                1, 100000); /* 1 vupdate at 10hz */
 767                break;
 768
 769        case CRTC_STATE_VACTIVE:
 770                REG_WAIT(OTG_STATUS,
 771                                OTG_V_ACTIVE_DISP, 1,
 772                                1, 100000); /* 1 vupdate at 10hz */
 773                break;
 774
 775        default:
 776                break;
 777        }
 778}
 779
 780void optc1_set_early_control(
 781        struct timing_generator *optc,
 782        uint32_t early_cntl)
 783{
 784        /* asic design change, do not need this control
 785         * empty for share caller logic
 786         */
 787}
 788
 789
 790void optc1_set_static_screen_control(
 791        struct timing_generator *optc,
 792        uint32_t event_triggers,
 793        uint32_t num_frames)
 794{
 795        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 796
 797        // By register spec, it only takes 8 bit value
 798        if (num_frames > 0xFF)
 799                num_frames = 0xFF;
 800
 801        /* Bit 8 is no longer applicable in RV for PSR case,
 802         * set bit 8 to 0 if given
 803         */
 804        if ((event_triggers & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN)
 805                        != 0)
 806                event_triggers = event_triggers &
 807                ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN;
 808
 809        REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0,
 810                        OTG_STATIC_SCREEN_EVENT_MASK, event_triggers,
 811                        OTG_STATIC_SCREEN_FRAME_COUNT, num_frames);
 812}
 813
 814void optc1_setup_manual_trigger(struct timing_generator *optc)
 815{
 816        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 817
 818        REG_SET(OTG_GLOBAL_CONTROL2, 0,
 819                        MANUAL_FLOW_CONTROL_SEL, optc->inst);
 820
 821        REG_SET_8(OTG_TRIGA_CNTL, 0,
 822                        OTG_TRIGA_SOURCE_SELECT, 22,
 823                        OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
 824                        OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
 825                        OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
 826                        OTG_TRIGA_POLARITY_SELECT, 0,
 827                        OTG_TRIGA_FREQUENCY_SELECT, 0,
 828                        OTG_TRIGA_DELAY, 0,
 829                        OTG_TRIGA_CLEAR, 1);
 830}
 831
 832void optc1_program_manual_trigger(struct timing_generator *optc)
 833{
 834        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 835
 836        REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
 837                        MANUAL_FLOW_CONTROL, 1);
 838
 839        REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
 840                        MANUAL_FLOW_CONTROL, 0);
 841}
 842
 843
 844/**
 845 *****************************************************************************
 846 *  Function: set_drr
 847 *
 848 *  @brief
 849 *     Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*.
 850 *
 851 *****************************************************************************
 852 */
 853void optc1_set_drr(
 854        struct timing_generator *optc,
 855        const struct drr_params *params)
 856{
 857        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 858
 859        if (params != NULL &&
 860                params->vertical_total_max > 0 &&
 861                params->vertical_total_min > 0) {
 862
 863                if (params->vertical_total_mid != 0) {
 864
 865                        REG_SET(OTG_V_TOTAL_MID, 0,
 866                                OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
 867
 868                        REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
 869                                        OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
 870                                        OTG_VTOTAL_MID_FRAME_NUM,
 871                                        (uint8_t)params->vertical_total_mid_frame_num);
 872
 873                }
 874
 875                REG_SET(OTG_V_TOTAL_MAX, 0,
 876                        OTG_V_TOTAL_MAX, params->vertical_total_max - 1);
 877
 878                REG_SET(OTG_V_TOTAL_MIN, 0,
 879                        OTG_V_TOTAL_MIN, params->vertical_total_min - 1);
 880
 881                REG_UPDATE_5(OTG_V_TOTAL_CONTROL,
 882                                OTG_V_TOTAL_MIN_SEL, 1,
 883                                OTG_V_TOTAL_MAX_SEL, 1,
 884                                OTG_FORCE_LOCK_ON_EVENT, 0,
 885                                OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
 886                                OTG_SET_V_TOTAL_MIN_MASK, 0);
 887
 888                // Setup manual flow control for EOF via TRIG_A
 889                optc->funcs->setup_manual_trigger(optc);
 890
 891        } else {
 892                REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
 893                                OTG_SET_V_TOTAL_MIN_MASK, 0,
 894                                OTG_V_TOTAL_MIN_SEL, 0,
 895                                OTG_V_TOTAL_MAX_SEL, 0,
 896                                OTG_FORCE_LOCK_ON_EVENT, 0);
 897
 898                REG_SET(OTG_V_TOTAL_MIN, 0,
 899                        OTG_V_TOTAL_MIN, 0);
 900
 901                REG_SET(OTG_V_TOTAL_MAX, 0,
 902                        OTG_V_TOTAL_MAX, 0);
 903        }
 904}
 905
 906static void optc1_set_test_pattern(
 907        struct timing_generator *optc,
 908        /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode'
 909         * because this is not DP-specific (which is probably somewhere in DP
 910         * encoder) */
 911        enum controller_dp_test_pattern test_pattern,
 912        enum dc_color_depth color_depth)
 913{
 914        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 915        enum test_pattern_color_format bit_depth;
 916        enum test_pattern_dyn_range dyn_range;
 917        enum test_pattern_mode mode;
 918        uint32_t pattern_mask;
 919        uint32_t pattern_data;
 920        /* color ramp generator mixes 16-bits color */
 921        uint32_t src_bpc = 16;
 922        /* requested bpc */
 923        uint32_t dst_bpc;
 924        uint32_t index;
 925        /* RGB values of the color bars.
 926         * Produce two RGB colors: RGB0 - white (all Fs)
 927         * and RGB1 - black (all 0s)
 928         * (three RGB components for two colors)
 929         */
 930        uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000,
 931                                                0x0000, 0x0000};
 932        /* dest color (converted to the specified color format) */
 933        uint16_t dst_color[6];
 934        uint32_t inc_base;
 935
 936        /* translate to bit depth */
 937        switch (color_depth) {
 938        case COLOR_DEPTH_666:
 939                bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6;
 940        break;
 941        case COLOR_DEPTH_888:
 942                bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
 943        break;
 944        case COLOR_DEPTH_101010:
 945                bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10;
 946        break;
 947        case COLOR_DEPTH_121212:
 948                bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12;
 949        break;
 950        default:
 951                bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
 952        break;
 953        }
 954
 955        switch (test_pattern) {
 956        case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES:
 957        case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA:
 958        {
 959                dyn_range = (test_pattern ==
 960                                CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ?
 961                                TEST_PATTERN_DYN_RANGE_CEA :
 962                                TEST_PATTERN_DYN_RANGE_VESA);
 963                mode = TEST_PATTERN_MODE_COLORSQUARES_RGB;
 964
 965                REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS,
 966                                OTG_TEST_PATTERN_VRES, 6,
 967                                OTG_TEST_PATTERN_HRES, 6);
 968
 969                REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
 970                                OTG_TEST_PATTERN_EN, 1,
 971                                OTG_TEST_PATTERN_MODE, mode,
 972                                OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range,
 973                                OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
 974        }
 975        break;
 976
 977        case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS:
 978        case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS:
 979        {
 980                mode = (test_pattern ==
 981                        CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ?
 982                        TEST_PATTERN_MODE_VERTICALBARS :
 983                        TEST_PATTERN_MODE_HORIZONTALBARS);
 984
 985                switch (bit_depth) {
 986                case TEST_PATTERN_COLOR_FORMAT_BPC_6:
 987                        dst_bpc = 6;
 988                break;
 989                case TEST_PATTERN_COLOR_FORMAT_BPC_8:
 990                        dst_bpc = 8;
 991                break;
 992                case TEST_PATTERN_COLOR_FORMAT_BPC_10:
 993                        dst_bpc = 10;
 994                break;
 995                default:
 996                        dst_bpc = 8;
 997                break;
 998                }
 999
1000                /* adjust color to the required colorFormat */
1001                for (index = 0; index < 6; index++) {
1002                        /* dst = 2^dstBpc * src / 2^srcBpc = src >>
1003                         * (srcBpc - dstBpc);
1004                         */
1005                        dst_color[index] =
1006                                src_color[index] >> (src_bpc - dst_bpc);
1007                /* CRTC_TEST_PATTERN_DATA has 16 bits,
1008                 * lowest 6 are hardwired to ZERO
1009                 * color bits should be left aligned aligned to MSB
1010                 * XXXXXXXXXX000000 for 10 bit,
1011                 * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6
1012                 */
1013                        dst_color[index] <<= (16 - dst_bpc);
1014                }
1015
1016                REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
1017
1018                /* We have to write the mask before data, similar to pipeline.
1019                 * For example, for 8 bpc, if we want RGB0 to be magenta,
1020                 * and RGB1 to be cyan,
1021                 * we need to make 7 writes:
1022                 * MASK   DATA
1023                 * 000001 00000000 00000000                     set mask to R0
1024                 * 000010 11111111 00000000     R0 255, 0xFF00, set mask to G0
1025                 * 000100 00000000 00000000     G0 0,   0x0000, set mask to B0
1026                 * 001000 11111111 00000000     B0 255, 0xFF00, set mask to R1
1027                 * 010000 00000000 00000000     R1 0,   0x0000, set mask to G1
1028                 * 100000 11111111 00000000     G1 255, 0xFF00, set mask to B1
1029                 * 100000 11111111 00000000     B1 255, 0xFF00
1030                 *
1031                 * we will make a loop of 6 in which we prepare the mask,
1032                 * then write, then prepare the color for next write.
1033                 * first iteration will write mask only,
1034                 * but each next iteration color prepared in
1035                 * previous iteration will be written within new mask,
1036                 * the last component will written separately,
1037                 * mask is not changing between 6th and 7th write
1038                 * and color will be prepared by last iteration
1039                 */
1040
1041                /* write color, color values mask in CRTC_TEST_PATTERN_MASK
1042                 * is B1, G1, R1, B0, G0, R0
1043                 */
1044                pattern_data = 0;
1045                for (index = 0; index < 6; index++) {
1046                        /* prepare color mask, first write PATTERN_DATA
1047                         * will have all zeros
1048                         */
1049                        pattern_mask = (1 << index);
1050
1051                        /* write color component */
1052                        REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
1053                                        OTG_TEST_PATTERN_MASK, pattern_mask,
1054                                        OTG_TEST_PATTERN_DATA, pattern_data);
1055
1056                        /* prepare next color component,
1057                         * will be written in the next iteration
1058                         */
1059                        pattern_data = dst_color[index];
1060                }
1061                /* write last color component,
1062                 * it's been already prepared in the loop
1063                 */
1064                REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
1065                                OTG_TEST_PATTERN_MASK, pattern_mask,
1066                                OTG_TEST_PATTERN_DATA, pattern_data);
1067
1068                /* enable test pattern */
1069                REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
1070                                OTG_TEST_PATTERN_EN, 1,
1071                                OTG_TEST_PATTERN_MODE, mode,
1072                                OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
1073                                OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
1074        }
1075        break;
1076
1077        case CONTROLLER_DP_TEST_PATTERN_COLORRAMP:
1078        {
1079                mode = (bit_depth ==
1080                        TEST_PATTERN_COLOR_FORMAT_BPC_10 ?
1081                        TEST_PATTERN_MODE_DUALRAMP_RGB :
1082                        TEST_PATTERN_MODE_SINGLERAMP_RGB);
1083
1084                switch (bit_depth) {
1085                case TEST_PATTERN_COLOR_FORMAT_BPC_6:
1086                        dst_bpc = 6;
1087                break;
1088                case TEST_PATTERN_COLOR_FORMAT_BPC_8:
1089                        dst_bpc = 8;
1090                break;
1091                case TEST_PATTERN_COLOR_FORMAT_BPC_10:
1092                        dst_bpc = 10;
1093                break;
1094                default:
1095                        dst_bpc = 8;
1096                break;
1097                }
1098
1099                /* increment for the first ramp for one color gradation
1100                 * 1 gradation for 6-bit color is 2^10
1101                 * gradations in 16-bit color
1102                 */
1103                inc_base = (src_bpc - dst_bpc);
1104
1105                switch (bit_depth) {
1106                case TEST_PATTERN_COLOR_FORMAT_BPC_6:
1107                {
1108                        REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1109                                        OTG_TEST_PATTERN_INC0, inc_base,
1110                                        OTG_TEST_PATTERN_INC1, 0,
1111                                        OTG_TEST_PATTERN_HRES, 6,
1112                                        OTG_TEST_PATTERN_VRES, 6,
1113                                        OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
1114                }
1115                break;
1116                case TEST_PATTERN_COLOR_FORMAT_BPC_8:
1117                {
1118                        REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1119                                        OTG_TEST_PATTERN_INC0, inc_base,
1120                                        OTG_TEST_PATTERN_INC1, 0,
1121                                        OTG_TEST_PATTERN_HRES, 8,
1122                                        OTG_TEST_PATTERN_VRES, 6,
1123                                        OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
1124                }
1125                break;
1126                case TEST_PATTERN_COLOR_FORMAT_BPC_10:
1127                {
1128                        REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1129                                        OTG_TEST_PATTERN_INC0, inc_base,
1130                                        OTG_TEST_PATTERN_INC1, inc_base + 2,
1131                                        OTG_TEST_PATTERN_HRES, 8,
1132                                        OTG_TEST_PATTERN_VRES, 5,
1133                                        OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6);
1134                }
1135                break;
1136                default:
1137                break;
1138                }
1139
1140                REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
1141
1142                /* enable test pattern */
1143                REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
1144
1145                REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0,
1146                                OTG_TEST_PATTERN_EN, 1,
1147                                OTG_TEST_PATTERN_MODE, mode,
1148                                OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
1149                                OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
1150        }
1151        break;
1152        case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE:
1153        {
1154                REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
1155                REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
1156                REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
1157        }
1158        break;
1159        default:
1160                break;
1161
1162        }
1163}
1164
1165void optc1_get_crtc_scanoutpos(
1166        struct timing_generator *optc,
1167        uint32_t *v_blank_start,
1168        uint32_t *v_blank_end,
1169        uint32_t *h_position,
1170        uint32_t *v_position)
1171{
1172        struct optc *optc1 = DCN10TG_FROM_TG(optc);
1173        struct crtc_position position;
1174
1175        REG_GET_2(OTG_V_BLANK_START_END,
1176                        OTG_V_BLANK_START, v_blank_start,
1177                        OTG_V_BLANK_END, v_blank_end);
1178
1179        optc1_get_position(optc, &position);
1180
1181        *h_position = position.horizontal_count;
1182        *v_position = position.vertical_count;
1183}
1184
1185static void optc1_enable_stereo(struct timing_generator *optc,
1186        const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
1187{
1188        struct optc *optc1 = DCN10TG_FROM_TG(optc);
1189
1190        if (flags) {
1191                uint32_t stereo_en;
1192                stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0;
1193
1194                if (flags->PROGRAM_STEREO)
1195                        REG_UPDATE_3(OTG_STEREO_CONTROL,
1196                                OTG_STEREO_EN, stereo_en,
1197                                OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0,
1198                                OTG_STEREO_SYNC_OUTPUT_POLARITY, 0);
1199
1200                if (flags->PROGRAM_POLARITY)
1201                        REG_UPDATE(OTG_STEREO_CONTROL,
1202                                OTG_STEREO_EYE_FLAG_POLARITY,
1203                                flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1);
1204
1205                if (flags->DISABLE_STEREO_DP_SYNC)
1206                        REG_UPDATE(OTG_STEREO_CONTROL,
1207                                OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1);
1208
1209                if (flags->PROGRAM_STEREO)
1210                        REG_UPDATE_2(OTG_3D_STRUCTURE_CONTROL,
1211                                OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED,
1212                                OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED);
1213
1214        }
1215}
1216
1217void optc1_program_stereo(struct timing_generator *optc,
1218        const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
1219{
1220        if (flags->PROGRAM_STEREO)
1221                optc1_enable_stereo(optc, timing, flags);
1222        else
1223                optc1_disable_stereo(optc);
1224}
1225
1226
1227bool optc1_is_stereo_left_eye(struct timing_generator *optc)
1228{
1229        bool ret = false;
1230        uint32_t left_eye = 0;
1231        struct optc *optc1 = DCN10TG_FROM_TG(optc);
1232
1233        REG_GET(OTG_STEREO_STATUS,
1234                OTG_STEREO_CURRENT_EYE, &left_eye);
1235        if (left_eye == 1)
1236                ret = true;
1237        else
1238                ret = false;
1239
1240        return ret;
1241}
1242
1243bool optc1_get_hw_timing(struct timing_generator *tg,
1244                struct dc_crtc_timing *hw_crtc_timing)
1245{
1246        struct dcn_otg_state s = {0};
1247
1248        if (tg == NULL || hw_crtc_timing == NULL)
1249                return false;
1250
1251        optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
1252
1253        hw_crtc_timing->h_total = s.h_total + 1;
1254        hw_crtc_timing->h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end);
1255        hw_crtc_timing->h_front_porch = s.h_total + 1 - s.h_blank_start;
1256        hw_crtc_timing->h_sync_width = s.h_sync_a_end - s.h_sync_a_start;
1257
1258        hw_crtc_timing->v_total = s.v_total + 1;
1259        hw_crtc_timing->v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end);
1260        hw_crtc_timing->v_front_porch = s.v_total + 1 - s.v_blank_start;
1261        hw_crtc_timing->v_sync_width = s.v_sync_a_end - s.v_sync_a_start;
1262
1263        return true;
1264}
1265
1266
1267void optc1_read_otg_state(struct optc *optc1,
1268                struct dcn_otg_state *s)
1269{
1270        REG_GET(OTG_CONTROL,
1271                        OTG_MASTER_EN, &s->otg_enabled);
1272
1273        REG_GET_2(OTG_V_BLANK_START_END,
1274                        OTG_V_BLANK_START, &s->v_blank_start,
1275                        OTG_V_BLANK_END, &s->v_blank_end);
1276
1277        REG_GET(OTG_V_SYNC_A_CNTL,
1278                        OTG_V_SYNC_A_POL, &s->v_sync_a_pol);
1279
1280        REG_GET(OTG_V_TOTAL,
1281                        OTG_V_TOTAL, &s->v_total);
1282
1283        REG_GET(OTG_V_TOTAL_MAX,
1284                        OTG_V_TOTAL_MAX, &s->v_total_max);
1285
1286        REG_GET(OTG_V_TOTAL_MIN,
1287                        OTG_V_TOTAL_MIN, &s->v_total_min);
1288
1289        REG_GET(OTG_V_TOTAL_CONTROL,
1290                        OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel);
1291
1292        REG_GET(OTG_V_TOTAL_CONTROL,
1293                        OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel);
1294
1295        REG_GET_2(OTG_V_SYNC_A,
1296                        OTG_V_SYNC_A_START, &s->v_sync_a_start,
1297                        OTG_V_SYNC_A_END, &s->v_sync_a_end);
1298
1299        REG_GET_2(OTG_H_BLANK_START_END,
1300                        OTG_H_BLANK_START, &s->h_blank_start,
1301                        OTG_H_BLANK_END, &s->h_blank_end);
1302
1303        REG_GET_2(OTG_H_SYNC_A,
1304                        OTG_H_SYNC_A_START, &s->h_sync_a_start,
1305                        OTG_H_SYNC_A_END, &s->h_sync_a_end);
1306
1307        REG_GET(OTG_H_SYNC_A_CNTL,
1308                        OTG_H_SYNC_A_POL, &s->h_sync_a_pol);
1309
1310        REG_GET(OTG_H_TOTAL,
1311                        OTG_H_TOTAL, &s->h_total);
1312
1313        REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
1314                        OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status);
1315}
1316
1317bool optc1_get_otg_active_size(struct timing_generator *optc,
1318                uint32_t *otg_active_width,
1319                uint32_t *otg_active_height)
1320{
1321        uint32_t otg_enabled;
1322        uint32_t v_blank_start;
1323        uint32_t v_blank_end;
1324        uint32_t h_blank_start;
1325        uint32_t h_blank_end;
1326        struct optc *optc1 = DCN10TG_FROM_TG(optc);
1327
1328
1329        REG_GET(OTG_CONTROL,
1330                        OTG_MASTER_EN, &otg_enabled);
1331
1332        if (otg_enabled == 0)
1333                return false;
1334
1335        REG_GET_2(OTG_V_BLANK_START_END,
1336                        OTG_V_BLANK_START, &v_blank_start,
1337                        OTG_V_BLANK_END, &v_blank_end);
1338
1339        REG_GET_2(OTG_H_BLANK_START_END,
1340                        OTG_H_BLANK_START, &h_blank_start,
1341                        OTG_H_BLANK_END, &h_blank_end);
1342
1343        *otg_active_width = v_blank_start - v_blank_end;
1344        *otg_active_height = h_blank_start - h_blank_end;
1345        return true;
1346}
1347
1348void optc1_clear_optc_underflow(struct timing_generator *optc)
1349{
1350        struct optc *optc1 = DCN10TG_FROM_TG(optc);
1351
1352        REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1);
1353}
1354
1355void optc1_tg_init(struct timing_generator *optc)
1356{
1357        optc1_set_blank_data_double_buffer(optc, true);
1358        optc1_clear_optc_underflow(optc);
1359}
1360
1361bool optc1_is_tg_enabled(struct timing_generator *optc)
1362{
1363        struct optc *optc1 = DCN10TG_FROM_TG(optc);
1364        uint32_t otg_enabled = 0;
1365
1366        REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled);
1367
1368        return (otg_enabled != 0);
1369
1370}
1371
1372bool optc1_is_optc_underflow_occurred(struct timing_generator *optc)
1373{
1374        struct optc *optc1 = DCN10TG_FROM_TG(optc);
1375        uint32_t underflow_occurred = 0;
1376
1377        REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
1378                        OPTC_UNDERFLOW_OCCURRED_STATUS,
1379                        &underflow_occurred);
1380
1381        return (underflow_occurred == 1);
1382}
1383
1384bool optc1_configure_crc(struct timing_generator *optc,
1385                          const struct crc_params *params)
1386{
1387        struct optc *optc1 = DCN10TG_FROM_TG(optc);
1388
1389        /* Cannot configure crc on a CRTC that is disabled */
1390        if (!optc1_is_tg_enabled(optc))
1391                return false;
1392
1393        REG_WRITE(OTG_CRC_CNTL, 0);
1394
1395        if (!params->enable)
1396                return true;
1397
1398        /* Program frame boundaries */
1399        /* Window A x axis start and end. */
1400        REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL,
1401                        OTG_CRC0_WINDOWA_X_START, params->windowa_x_start,
1402                        OTG_CRC0_WINDOWA_X_END, params->windowa_x_end);
1403
1404        /* Window A y axis start and end. */
1405        REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL,
1406                        OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start,
1407                        OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end);
1408
1409        /* Window B x axis start and end. */
1410        REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL,
1411                        OTG_CRC0_WINDOWB_X_START, params->windowb_x_start,
1412                        OTG_CRC0_WINDOWB_X_END, params->windowb_x_end);
1413
1414        /* Window B y axis start and end. */
1415        REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL,
1416                        OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start,
1417                        OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end);
1418
1419        /* Set crc mode and selection, and enable. Only using CRC0*/
1420        REG_UPDATE_3(OTG_CRC_CNTL,
1421                        OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
1422                        OTG_CRC0_SELECT, params->selection,
1423                        OTG_CRC_EN, 1);
1424
1425        return true;
1426}
1427
1428bool optc1_get_crc(struct timing_generator *optc,
1429                    uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
1430{
1431        uint32_t field = 0;
1432        struct optc *optc1 = DCN10TG_FROM_TG(optc);
1433
1434        REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field);
1435
1436        /* Early return if CRC is not enabled for this CRTC */
1437        if (!field)
1438                return false;
1439
1440        REG_GET_2(OTG_CRC0_DATA_RG,
1441                        CRC0_R_CR, r_cr,
1442                        CRC0_G_Y, g_y);
1443
1444        REG_GET(OTG_CRC0_DATA_B,
1445                        CRC0_B_CB, b_cb);
1446
1447        return true;
1448}
1449
1450static const struct timing_generator_funcs dcn10_tg_funcs = {
1451                .validate_timing = optc1_validate_timing,
1452                .program_timing = optc1_program_timing,
1453                .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
1454                .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
1455                .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
1456                .program_global_sync = optc1_program_global_sync,
1457                .enable_crtc = optc1_enable_crtc,
1458                .disable_crtc = optc1_disable_crtc,
1459                /* used by enable_timing_synchronization. Not need for FPGA */
1460                .is_counter_moving = optc1_is_counter_moving,
1461                .get_position = optc1_get_position,
1462                .get_frame_count = optc1_get_vblank_counter,
1463                .get_scanoutpos = optc1_get_crtc_scanoutpos,
1464                .get_otg_active_size = optc1_get_otg_active_size,
1465                .set_early_control = optc1_set_early_control,
1466                /* used by enable_timing_synchronization. Not need for FPGA */
1467                .wait_for_state = optc1_wait_for_state,
1468                .set_blank = optc1_set_blank,
1469                .is_blanked = optc1_is_blanked,
1470                .set_blank_color = optc1_program_blank_color,
1471                .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
1472                .enable_reset_trigger = optc1_enable_reset_trigger,
1473                .enable_crtc_reset = optc1_enable_crtc_reset,
1474                .disable_reset_trigger = optc1_disable_reset_trigger,
1475                .lock = optc1_lock,
1476                .unlock = optc1_unlock,
1477                .enable_optc_clock = optc1_enable_optc_clock,
1478                .set_drr = optc1_set_drr,
1479                .set_static_screen_control = optc1_set_static_screen_control,
1480                .set_test_pattern = optc1_set_test_pattern,
1481                .program_stereo = optc1_program_stereo,
1482                .is_stereo_left_eye = optc1_is_stereo_left_eye,
1483                .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,
1484                .tg_init = optc1_tg_init,
1485                .is_tg_enabled = optc1_is_tg_enabled,
1486                .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
1487                .clear_optc_underflow = optc1_clear_optc_underflow,
1488                .get_crc = optc1_get_crc,
1489                .configure_crc = optc1_configure_crc,
1490                .set_vtg_params = optc1_set_vtg_params,
1491                .program_manual_trigger = optc1_program_manual_trigger,
1492                .setup_manual_trigger = optc1_setup_manual_trigger,
1493                .get_hw_timing = optc1_get_hw_timing,
1494};
1495
1496void dcn10_timing_generator_init(struct optc *optc1)
1497{
1498        optc1->base.funcs = &dcn10_tg_funcs;
1499
1500        optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
1501        optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
1502
1503        optc1->min_h_blank = 32;
1504        optc1->min_v_blank = 3;
1505        optc1->min_v_blank_interlace = 5;
1506        optc1->min_h_sync_width = 8;
1507        optc1->min_v_sync_width = 1;
1508}
1509
1510/* "Containter" vs. "pixel" is a concept within HW blocks, mostly those closer to the back-end. It works like this:
1511 *
1512 * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as
1513 *   containter rate.
1514 *
1515 * - In 4:2:0 (DSC or uncompressed) there are two pixels per container, hence the target container rate has to be
1516 *   halved to maintain the correct pixel rate.
1517 *
1518 * - Unlike 4:2:2 uncompressed, DSC 4:2:2 Native also has two pixels per container (this happens when DSC is applied
1519 *   to it) and has to be treated the same as 4:2:0, i.e. target containter rate has to be halved in this case as well.
1520 *
1521 */
1522bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
1523{
1524        bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
1525
1526        two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
1527                        && !timing->dsc_cfg.ycbcr422_simple);
1528        return two_pix;
1529}
1530
1531