LXR linux/drivers/gpu/drm/amd/powerplay/inc/smu_v11

   1/*
   2 * Copyright 2019 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23#ifndef __SMU_V11_0_H__
  24#define __SMU_V11_0_H__
  25
  26#include "amdgpu_smu.h"
  27
  28#define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
  29#define SMU11_DRIVER_IF_VERSION_VG20 0x13
  30#define SMU11_DRIVER_IF_VERSION_ARCT 0x12
  31#define SMU11_DRIVER_IF_VERSION_NV10 0x33
  32#define SMU11_DRIVER_IF_VERSION_NV14 0x34
  33
  34/* MP Apertures */
  35#define MP0_Public                      0x03800000
  36#define MP0_SRAM                        0x03900000
  37#define MP1_Public                      0x03b00000
  38#define MP1_SRAM                        0x03c00004
  39#define MP1_SMC_SIZE            0x40000
  40
  41/* address block */
  42#define smnMP1_FIRMWARE_FLAGS           0x3010024
  43#define smnMP0_FW_INTF                  0x30101c0
  44#define smnMP1_PUB_CTRL                 0x3010b14
  45
  46#define TEMP_RANGE_MIN                  (0)
  47#define TEMP_RANGE_MAX                  (80 * 1000)
  48
  49#define SMU11_TOOL_SIZE                 0x19000
  50
  51#define MAX_PCIE_CONF 2
  52
  53#define CLK_MAP(clk, index) \
  54        [SMU_##clk] = {1, (index)}
  55
  56#define FEA_MAP(fea) \
  57        [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT}
  58
  59#define TAB_MAP(tab) \
  60        [SMU_TABLE_##tab] = {1, TABLE_##tab}
  61
  62#define PWR_MAP(tab) \
  63        [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab}
  64
  65#define WORKLOAD_MAP(profile, workload) \
  66        [profile] = {1, (workload)}
  67
  68static const struct smu_temperature_range smu11_thermal_policy[] =
  69{
  70        {-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
  71        { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
  72};
  73
  74struct smu_11_0_cmn2aisc_mapping {
  75        int     valid_mapping;
  76        int     map_to;
  77};
  78
  79struct smu_11_0_max_sustainable_clocks {
  80        uint32_t display_clock;
  81        uint32_t phy_clock;
  82        uint32_t pixel_clock;
  83        uint32_t uclock;
  84        uint32_t dcef_clock;
  85        uint32_t soc_clock;
  86};
  87
  88struct smu_11_0_dpm_table {
  89        uint32_t    min;        /* MHz */
  90        uint32_t    max;        /* MHz */
  91};
  92
  93struct smu_11_0_pcie_table {
  94        uint8_t  pcie_gen[MAX_PCIE_CONF];
  95        uint8_t  pcie_lane[MAX_PCIE_CONF];
  96};
  97
  98struct smu_11_0_dpm_tables {
  99        struct smu_11_0_dpm_table        soc_table;
 100        struct smu_11_0_dpm_table        gfx_table;
 101        struct smu_11_0_dpm_table        uclk_table;
 102        struct smu_11_0_dpm_table        eclk_table;
 103        struct smu_11_0_dpm_table        vclk_table;
 104        struct smu_11_0_dpm_table        dclk_table;
 105        struct smu_11_0_dpm_table        dcef_table;
 106        struct smu_11_0_dpm_table        pixel_table;
 107        struct smu_11_0_dpm_table        display_table;
 108        struct smu_11_0_dpm_table        phy_table;
 109        struct smu_11_0_dpm_table        fclk_table;
 110        struct smu_11_0_pcie_table       pcie_table;
 111};
 112
 113struct smu_11_0_dpm_context {
 114        struct smu_11_0_dpm_tables  dpm_tables;
 115        uint32_t                    workload_policy_mask;
 116        uint32_t                    dcef_min_ds_clk;
 117};
 118
 119enum smu_11_0_power_state {
 120        SMU_11_0_POWER_STATE__D0 = 0,
 121        SMU_11_0_POWER_STATE__D1,
 122        SMU_11_0_POWER_STATE__D3, /* Sleep*/
 123        SMU_11_0_POWER_STATE__D4, /* Hibernate*/
 124        SMU_11_0_POWER_STATE__D5, /* Power off*/
 125};
 126
 127struct smu_11_0_power_context {
 128        uint32_t        power_source;
 129        uint8_t         in_power_limit_boost_mode;
 130        enum smu_11_0_power_state power_state;
 131};
 132
 133enum smu_v11_0_baco_seq {
 134        BACO_SEQ_BACO = 0,
 135        BACO_SEQ_MSR,
 136        BACO_SEQ_BAMACO,
 137        BACO_SEQ_ULPS,
 138        BACO_SEQ_COUNT,
 139};
 140
 141int smu_v11_0_init_microcode(struct smu_context *smu);
 142
 143int smu_v11_0_load_microcode(struct smu_context *smu);
 144
 145int smu_v11_0_init_smc_tables(struct smu_context *smu);
 146
 147int smu_v11_0_fini_smc_tables(struct smu_context *smu);
 148
 149int smu_v11_0_init_power(struct smu_context *smu);
 150
 151int smu_v11_0_fini_power(struct smu_context *smu);
 152
 153int smu_v11_0_check_fw_status(struct smu_context *smu);
 154
 155int smu_v11_0_setup_pptable(struct smu_context *smu);
 156
 157int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu);
 158
 159int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu);
 160
 161int smu_v11_0_check_pptable(struct smu_context *smu);
 162
 163int smu_v11_0_parse_pptable(struct smu_context *smu);
 164
 165int smu_v11_0_populate_smc_pptable(struct smu_context *smu);
 166
 167int smu_v11_0_check_fw_version(struct smu_context *smu);
 168
 169int smu_v11_0_write_pptable(struct smu_context *smu);
 170
 171int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu);
 172
 173int smu_v11_0_set_driver_table_location(struct smu_context *smu);
 174
 175int smu_v11_0_set_tool_table_location(struct smu_context *smu);
 176
 177int smu_v11_0_notify_memory_pool_location(struct smu_context *smu);
 178
 179int smu_v11_0_system_features_control(struct smu_context *smu,
 180                                             bool en);
 181
 182int
 183smu_v11_0_send_msg_with_param(struct smu_context *smu,
 184                              enum smu_message_type msg,
 185                              uint32_t param);
 186
 187int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg);
 188
 189int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count);
 190
 191int smu_v11_0_set_allowed_mask(struct smu_context *smu);
 192
 193int smu_v11_0_get_enabled_mask(struct smu_context *smu,
 194                                      uint32_t *feature_mask, uint32_t num);
 195
 196int smu_v11_0_notify_display_change(struct smu_context *smu);
 197
 198int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n);
 199
 200int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
 201                                          enum smu_clk_type clk_id,
 202                                          uint32_t *value);
 203
 204int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu);
 205
 206int smu_v11_0_start_thermal_control(struct smu_context *smu);
 207
 208int smu_v11_0_stop_thermal_control(struct smu_context *smu);
 209
 210int smu_v11_0_read_sensor(struct smu_context *smu,
 211                                 enum amd_pp_sensors sensor,
 212                                 void *data, uint32_t *size);
 213
 214int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk);
 215
 216int
 217smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
 218                                        struct pp_display_clock_request
 219                                        *clock_req);
 220
 221uint32_t
 222smu_v11_0_get_fan_control_mode(struct smu_context *smu);
 223
 224int
 225smu_v11_0_set_fan_control_mode(struct smu_context *smu,
 226                               uint32_t mode);
 227
 228int
 229smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed);
 230
 231int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
 232                                       uint32_t speed);
 233
 234int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
 235                                     uint32_t pstate);
 236
 237int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable);
 238
 239int smu_v11_0_register_irq_handler(struct smu_context *smu);
 240
 241int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu);
 242
 243int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
 244                struct pp_smu_nv_clock_table *max_clocks);
 245
 246bool smu_v11_0_baco_is_support(struct smu_context *smu);
 247
 248enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu);
 249
 250int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);
 251
 252int smu_v11_0_baco_enter(struct smu_context *smu);
 253int smu_v11_0_baco_exit(struct smu_context *smu);
 254
 255int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
 256                                                 uint32_t *min, uint32_t *max);
 257
 258int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
 259                            uint32_t min, uint32_t max);
 260
 261int smu_v11_0_override_pcie_parameters(struct smu_context *smu);
 262
 263int smu_v11_0_set_default_od_settings(struct smu_context *smu, bool initialize, size_t overdrive_table_size);
 264
 265uint32_t smu_v11_0_get_max_power_limit(struct smu_context *smu);
 266
 267int smu_v11_0_set_performance_level(struct smu_context *smu,
 268                                    enum amd_dpm_forced_level level);
 269
 270#endif
 271