LXR linux/drivers/gpu/drm/ast/ast

   1/*
   2 * Copyright 2012 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the
   6 * "Software"), to deal in the Software without restriction, including
   7 * without limitation the rights to use, copy, modify, merge, publish,
   8 * distribute, sub license, and/or sell copies of the Software, and to
   9 * permit persons to whom the Software is furnished to do so, subject to
  10 * the following conditions:
  11 *
  12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
  19 *
  20 * The above copyright notice and this permission notice (including the
  21 * next paragraph) shall be included in all copies or substantial portions
  22 * of the Software.
  23 *
  24 */
  25/*
  26 * Authors: Dave Airlie <airlied@redhat.com>
  27 */
  28
  29#include <linux/pci.h>
  30
  31#include <drm/drm_atomic_helper.h>
  32#include <drm/drm_crtc_helper.h>
  33#include <drm/drm_fb_helper.h>
  34#include <drm/drm_gem.h>
  35#include <drm/drm_gem_framebuffer_helper.h>
  36#include <drm/drm_gem_vram_helper.h>
  37
  38#include "ast_drv.h"
  39
  40void ast_set_index_reg_mask(struct ast_private *ast,
  41                            uint32_t base, uint8_t index,
  42                            uint8_t mask, uint8_t val)
  43{
  44        u8 tmp;
  45        ast_io_write8(ast, base, index);
  46        tmp = (ast_io_read8(ast, base + 1) & mask) | val;
  47        ast_set_index_reg(ast, base, index, tmp);
  48}
  49
  50uint8_t ast_get_index_reg(struct ast_private *ast,
  51                          uint32_t base, uint8_t index)
  52{
  53        uint8_t ret;
  54        ast_io_write8(ast, base, index);
  55        ret = ast_io_read8(ast, base + 1);
  56        return ret;
  57}
  58
  59uint8_t ast_get_index_reg_mask(struct ast_private *ast,
  60                               uint32_t base, uint8_t index, uint8_t mask)
  61{
  62        uint8_t ret;
  63        ast_io_write8(ast, base, index);
  64        ret = ast_io_read8(ast, base + 1) & mask;
  65        return ret;
  66}
  67
  68static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev)
  69{
  70        struct device_node *np = dev->pdev->dev.of_node;
  71        struct ast_private *ast = dev->dev_private;
  72        uint32_t data, jregd0, jregd1;
  73
  74        /* Defaults */
  75        ast->config_mode = ast_use_defaults;
  76        *scu_rev = 0xffffffff;
  77
  78        /* Check if we have device-tree properties */
  79        if (np && !of_property_read_u32(np, "aspeed,scu-revision-id",
  80                                        scu_rev)) {
  81                /* We do, disable P2A access */
  82                ast->config_mode = ast_use_dt;
  83                DRM_INFO("Using device-tree for configuration\n");
  84                return;
  85        }
  86
  87        /* Not all families have a P2A bridge */
  88        if (dev->pdev->device != PCI_CHIP_AST2000)
  89                return;
  90
  91        /*
  92         * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge
  93         * is disabled. We force using P2A if VGA only mode bit
  94         * is set D[7]
  95         */
  96        jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
  97        jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
  98        if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) {
  99                /* Double check it's actually working */
 100                data = ast_read32(ast, 0xf004);
 101                if (data != 0xFFFFFFFF) {
 102                        /* P2A works, grab silicon revision */
 103                        ast->config_mode = ast_use_p2a;
 104
 105                        DRM_INFO("Using P2A bridge for configuration\n");
 106
 107                        /* Read SCU7c (silicon revision register) */
 108                        ast_write32(ast, 0xf004, 0x1e6e0000);
 109                        ast_write32(ast, 0xf000, 0x1);
 110                        *scu_rev = ast_read32(ast, 0x1207c);
 111                        return;
 112                }
 113        }
 114
 115        /* We have a P2A bridge but it's disabled */
 116        DRM_INFO("P2A bridge disabled, using default configuration\n");
 117}
 118
 119static int ast_detect_chip(struct drm_device *dev, bool *need_post)
 120{
 121        struct ast_private *ast = dev->dev_private;
 122        uint32_t jreg, scu_rev;
 123
 124        /*
 125         * If VGA isn't enabled, we need to enable now or subsequent
 126         * access to the scratch registers will fail. We also inform
 127         * our caller that it needs to POST the chip
 128         * (Assumption: VGA not enabled -> need to POST)
 129         */
 130        if (!ast_is_vga_enabled(dev)) {
 131                ast_enable_vga(dev);
 132                DRM_INFO("VGA not enabled on entry, requesting chip POST\n");
 133                *need_post = true;
 134        } else
 135                *need_post = false;
 136
 137
 138        /* Enable extended register access */
 139        ast_open_key(ast);
 140        ast_enable_mmio(dev);
 141
 142        /* Find out whether P2A works or whether to use device-tree */
 143        ast_detect_config_mode(dev, &scu_rev);
 144
 145        /* Identify chipset */
 146        if (dev->pdev->device == PCI_CHIP_AST1180) {
 147                ast->chip = AST1100;
 148                DRM_INFO("AST 1180 detected\n");
 149        } else {
 150                if (dev->pdev->revision >= 0x40) {
 151                        ast->chip = AST2500;
 152                        DRM_INFO("AST 2500 detected\n");
 153                } else if (dev->pdev->revision >= 0x30) {
 154                        ast->chip = AST2400;
 155                        DRM_INFO("AST 2400 detected\n");
 156                } else if (dev->pdev->revision >= 0x20) {
 157                        ast->chip = AST2300;
 158                        DRM_INFO("AST 2300 detected\n");
 159                } else if (dev->pdev->revision >= 0x10) {
 160                        switch (scu_rev & 0x0300) {
 161                        case 0x0200:
 162                                ast->chip = AST1100;
 163                                DRM_INFO("AST 1100 detected\n");
 164                                break;
 165                        case 0x0100:
 166                                ast->chip = AST2200;
 167                                DRM_INFO("AST 2200 detected\n");
 168                                break;
 169                        case 0x0000:
 170                                ast->chip = AST2150;
 171                                DRM_INFO("AST 2150 detected\n");
 172                                break;
 173                        default:
 174                                ast->chip = AST2100;
 175                                DRM_INFO("AST 2100 detected\n");
 176                                break;
 177                        }
 178                        ast->vga2_clone = false;
 179                } else {
 180                        ast->chip = AST2000;
 181                        DRM_INFO("AST 2000 detected\n");
 182                }
 183        }
 184
 185        /* Check if we support wide screen */
 186        switch (ast->chip) {
 187        case AST1180:
 188                ast->support_wide_screen = true;
 189                break;
 190        case AST2000:
 191                ast->support_wide_screen = false;
 192                break;
 193        default:
 194                jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
 195                if (!(jreg & 0x80))
 196                        ast->support_wide_screen = true;
 197                else if (jreg & 0x01)
 198                        ast->support_wide_screen = true;
 199                else {
 200                        ast->support_wide_screen = false;
 201                        if (ast->chip == AST2300 &&
 202                            (scu_rev & 0x300) == 0x0) /* ast1300 */
 203                                ast->support_wide_screen = true;
 204                        if (ast->chip == AST2400 &&
 205                            (scu_rev & 0x300) == 0x100) /* ast1400 */
 206                                ast->support_wide_screen = true;
 207                        if (ast->chip == AST2500 &&
 208                            scu_rev == 0x100)           /* ast2510 */
 209                                ast->support_wide_screen = true;
 210                }
 211                break;
 212        }
 213
 214        /* Check 3rd Tx option (digital output afaik) */
 215        ast->tx_chip_type = AST_TX_NONE;
 216
 217        /*
 218         * VGACRA3 Enhanced Color Mode Register, check if DVO is already
 219         * enabled, in that case, assume we have a SIL164 TMDS transmitter
 220         *
 221         * Don't make that assumption if we the chip wasn't enabled and
 222         * is at power-on reset, otherwise we'll incorrectly "detect" a
 223         * SIL164 when there is none.
 224         */
 225        if (!*need_post) {
 226                jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff);
 227                if (jreg & 0x80)
 228                        ast->tx_chip_type = AST_TX_SIL164;
 229        }
 230
 231        if ((ast->chip == AST2300) || (ast->chip == AST2400)) {
 232                /*
 233                 * On AST2300 and 2400, look the configuration set by the SoC in
 234                 * the SOC scratch register #1 bits 11:8 (interestingly marked
 235                 * as "reserved" in the spec)
 236                 */
 237                jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
 238                switch (jreg) {
 239                case 0x04:
 240                        ast->tx_chip_type = AST_TX_SIL164;
 241                        break;
 242                case 0x08:
 243                        ast->dp501_fw_addr = kzalloc(32*1024, GFP_KERNEL);
 244                        if (ast->dp501_fw_addr) {
 245                                /* backup firmware */
 246                                if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) {
 247                                        kfree(ast->dp501_fw_addr);
 248                                        ast->dp501_fw_addr = NULL;
 249                                }
 250                        }
 251                        /* fallthrough */
 252                case 0x0c:
 253                        ast->tx_chip_type = AST_TX_DP501;
 254                }
 255        }
 256
 257        /* Print stuff for diagnostic purposes */
 258        switch(ast->tx_chip_type) {
 259        case AST_TX_SIL164:
 260                DRM_INFO("Using Sil164 TMDS transmitter\n");
 261                break;
 262        case AST_TX_DP501:
 263                DRM_INFO("Using DP501 DisplayPort transmitter\n");
 264                break;
 265        default:
 266                DRM_INFO("Analog VGA only\n");
 267        }
 268        return 0;
 269}
 270
 271static int ast_get_dram_info(struct drm_device *dev)
 272{
 273        struct device_node *np = dev->pdev->dev.of_node;
 274        struct ast_private *ast = dev->dev_private;
 275        uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap;
 276        uint32_t denum, num, div, ref_pll, dsel;
 277
 278        switch (ast->config_mode) {
 279        case ast_use_dt:
 280                /*
 281                 * If some properties are missing, use reasonable
 282                 * defaults for AST2400
 283                 */
 284                if (of_property_read_u32(np, "aspeed,mcr-configuration",
 285                                         &mcr_cfg))
 286                        mcr_cfg = 0x00000577;
 287                if (of_property_read_u32(np, "aspeed,mcr-scu-mpll",
 288                                         &mcr_scu_mpll))
 289                        mcr_scu_mpll = 0x000050C0;
 290                if (of_property_read_u32(np, "aspeed,mcr-scu-strap",
 291                                         &mcr_scu_strap))
 292                        mcr_scu_strap = 0;
 293                break;
 294        case ast_use_p2a:
 295                ast_write32(ast, 0xf004, 0x1e6e0000);
 296                ast_write32(ast, 0xf000, 0x1);
 297                mcr_cfg = ast_read32(ast, 0x10004);
 298                mcr_scu_mpll = ast_read32(ast, 0x10120);
 299                mcr_scu_strap = ast_read32(ast, 0x10170);
 300                break;
 301        case ast_use_defaults:
 302        default:
 303                ast->dram_bus_width = 16;
 304                ast->dram_type = AST_DRAM_1Gx16;
 305                if (ast->chip == AST2500)
 306                        ast->mclk = 800;
 307                else
 308                        ast->mclk = 396;
 309                return 0;
 310        }
 311
 312        if (mcr_cfg & 0x40)
 313                ast->dram_bus_width = 16;
 314        else
 315                ast->dram_bus_width = 32;
 316
 317        if (ast->chip == AST2500) {
 318                switch (mcr_cfg & 0x03) {
 319                case 0:
 320                        ast->dram_type = AST_DRAM_1Gx16;
 321                        break;
 322                default:
 323                case 1:
 324                        ast->dram_type = AST_DRAM_2Gx16;
 325                        break;
 326                case 2:
 327                        ast->dram_type = AST_DRAM_4Gx16;
 328                        break;
 329                case 3:
 330                        ast->dram_type = AST_DRAM_8Gx16;
 331                        break;
 332                }
 333        } else if (ast->chip == AST2300 || ast->chip == AST2400) {
 334                switch (mcr_cfg & 0x03) {
 335                case 0:
 336                        ast->dram_type = AST_DRAM_512Mx16;
 337                        break;
 338                default:
 339                case 1:
 340                        ast->dram_type = AST_DRAM_1Gx16;
 341                        break;
 342                case 2:
 343                        ast->dram_type = AST_DRAM_2Gx16;
 344                        break;
 345                case 3:
 346                        ast->dram_type = AST_DRAM_4Gx16;
 347                        break;
 348                }
 349        } else {
 350                switch (mcr_cfg & 0x0c) {
 351                case 0:
 352                case 4:
 353                        ast->dram_type = AST_DRAM_512Mx16;
 354                        break;
 355                case 8:
 356                        if (mcr_cfg & 0x40)
 357                                ast->dram_type = AST_DRAM_1Gx16;
 358                        else
 359                                ast->dram_type = AST_DRAM_512Mx32;
 360                        break;
 361                case 0xc:
 362                        ast->dram_type = AST_DRAM_1Gx32;
 363                        break;
 364                }
 365        }
 366
 367        if (mcr_scu_strap & 0x2000)
 368                ref_pll = 14318;
 369        else
 370                ref_pll = 12000;
 371
 372        denum = mcr_scu_mpll & 0x1f;
 373        num = (mcr_scu_mpll & 0x3fe0) >> 5;
 374        dsel = (mcr_scu_mpll & 0xc000) >> 14;
 375        switch (dsel) {
 376        case 3:
 377                div = 0x4;
 378                break;
 379        case 2:
 380        case 1:
 381                div = 0x2;
 382                break;
 383        default:
 384                div = 0x1;
 385                break;
 386        }
 387        ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000));
 388        return 0;
 389}
 390
 391enum drm_mode_status ast_mode_config_mode_valid(struct drm_device *dev,
 392                                                const struct drm_display_mode *mode)
 393{
 394        static const unsigned long max_bpp = 4; /* DRM_FORMAT_XRGBA8888 */
 395
 396        struct ast_private *ast = dev->dev_private;
 397        unsigned long fbsize, fbpages, max_fbpages;
 398
 399        /* To support double buffering, a framebuffer may not
 400         * consume more than half of the available VRAM.
 401         */
 402        max_fbpages = (ast->vram_size / 2) >> PAGE_SHIFT;
 403
 404        fbsize = mode->hdisplay * mode->vdisplay * max_bpp;
 405        fbpages = DIV_ROUND_UP(fbsize, PAGE_SIZE);
 406
 407        if (fbpages > max_fbpages)
 408                return MODE_MEM;
 409
 410        return MODE_OK;
 411}
 412
 413static const struct drm_mode_config_funcs ast_mode_funcs = {
 414        .fb_create = drm_gem_fb_create,
 415        .mode_valid = ast_mode_config_mode_valid,
 416        .atomic_check = drm_atomic_helper_check,
 417        .atomic_commit = drm_atomic_helper_commit,
 418};
 419
 420static u32 ast_get_vram_info(struct drm_device *dev)
 421{
 422        struct ast_private *ast = dev->dev_private;
 423        u8 jreg;
 424        u32 vram_size;
 425        ast_open_key(ast);
 426
 427        vram_size = AST_VIDMEM_DEFAULT_SIZE;
 428        jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xaa, 0xff);
 429        switch (jreg & 3) {
 430        case 0: vram_size = AST_VIDMEM_SIZE_8M; break;
 431        case 1: vram_size = AST_VIDMEM_SIZE_16M; break;
 432        case 2: vram_size = AST_VIDMEM_SIZE_32M; break;
 433        case 3: vram_size = AST_VIDMEM_SIZE_64M; break;
 434        }
 435
 436        jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xff);
 437        switch (jreg & 0x03) {
 438        case 1:
 439                vram_size -= 0x100000;
 440                break;
 441        case 2:
 442                vram_size -= 0x200000;
 443                break;
 444        case 3:
 445                vram_size -= 0x400000;
 446                break;
 447        }
 448
 449        return vram_size;
 450}
 451
 452int ast_driver_load(struct drm_device *dev, unsigned long flags)
 453{
 454        struct ast_private *ast;
 455        bool need_post;
 456        int ret = 0;
 457
 458        ast = kzalloc(sizeof(struct ast_private), GFP_KERNEL);
 459        if (!ast)
 460                return -ENOMEM;
 461
 462        dev->dev_private = ast;
 463        ast->dev = dev;
 464
 465        ast->regs = pci_iomap(dev->pdev, 1, 0);
 466        if (!ast->regs) {
 467                ret = -EIO;
 468                goto out_free;
 469        }
 470
 471        /*
 472         * If we don't have IO space at all, use MMIO now and
 473         * assume the chip has MMIO enabled by default (rev 0x20
 474         * and higher).
 475         */
 476        if (!(pci_resource_flags(dev->pdev, 2) & IORESOURCE_IO)) {
 477                DRM_INFO("platform has no IO space, trying MMIO\n");
 478                ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
 479        }
 480
 481        /* "map" IO regs if the above hasn't done so already */
 482        if (!ast->ioregs) {
 483                ast->ioregs = pci_iomap(dev->pdev, 2, 0);
 484                if (!ast->ioregs) {
 485                        ret = -EIO;
 486                        goto out_free;
 487                }
 488        }
 489
 490        ast_detect_chip(dev, &need_post);
 491
 492        if (need_post)
 493                ast_post_gpu(dev);
 494
 495        if (ast->chip != AST1180) {
 496                ret = ast_get_dram_info(dev);
 497                if (ret)
 498                        goto out_free;
 499                ast->vram_size = ast_get_vram_info(dev);
 500                DRM_INFO("dram MCLK=%u Mhz type=%d bus_width=%d size=%08x\n",
 501                         ast->mclk, ast->dram_type,
 502                         ast->dram_bus_width, ast->vram_size);
 503        }
 504
 505        ret = ast_mm_init(ast);
 506        if (ret)
 507                goto out_free;
 508
 509        drm_mode_config_init(dev);
 510
 511        dev->mode_config.funcs = (void *)&ast_mode_funcs;
 512        dev->mode_config.min_width = 0;
 513        dev->mode_config.min_height = 0;
 514        dev->mode_config.preferred_depth = 24;
 515        dev->mode_config.prefer_shadow = 1;
 516        dev->mode_config.fb_base = pci_resource_start(ast->dev->pdev, 0);
 517
 518        if (ast->chip == AST2100 ||
 519            ast->chip == AST2200 ||
 520            ast->chip == AST2300 ||
 521            ast->chip == AST2400 ||
 522            ast->chip == AST2500 ||
 523            ast->chip == AST1180) {
 524                dev->mode_config.max_width = 1920;
 525                dev->mode_config.max_height = 2048;
 526        } else {
 527                dev->mode_config.max_width = 1600;
 528                dev->mode_config.max_height = 1200;
 529        }
 530
 531        ret = ast_mode_init(dev);
 532        if (ret)
 533                goto out_free;
 534
 535        drm_mode_config_reset(dev);
 536
 537        ret = drm_fbdev_generic_setup(dev, 32);
 538        if (ret)
 539                goto out_free;
 540
 541        return 0;
 542out_free:
 543        kfree(ast);
 544        dev->dev_private = NULL;
 545        return ret;
 546}
 547
 548void ast_driver_unload(struct drm_device *dev)
 549{
 550        struct ast_private *ast = dev->dev_private;
 551
 552        /* enable standard VGA decode */
 553        ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x04);
 554
 555        ast_release_firmware(dev);
 556        kfree(ast->dp501_fw_addr);
 557        ast_mode_fini(dev);
 558        drm_mode_config_cleanup(dev);
 559
 560        ast_mm_fini(ast);
 561        if (ast->ioregs != ast->regs + AST_IO_MM_OFFSET)
 562                pci_iounmap(dev->pdev, ast->ioregs);
 563        pci_iounmap(dev->pdev, ast->regs);
 564        kfree(ast);
 565}
 566