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31#include <linux/export.h>
32#include <linux/pci.h>
33
34#include <drm/drm_atomic.h>
35#include <drm/drm_atomic_helper.h>
36#include <drm/drm_atomic_state_helper.h>
37#include <drm/drm_crtc.h>
38#include <drm/drm_crtc_helper.h>
39#include <drm/drm_fourcc.h>
40#include <drm/drm_gem_vram_helper.h>
41#include <drm/drm_plane_helper.h>
42#include <drm/drm_probe_helper.h>
43
44#include "ast_drv.h"
45#include "ast_tables.h"
46
47static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev);
48static void ast_i2c_destroy(struct ast_i2c_chan *i2c);
49static int ast_cursor_move(struct drm_crtc *crtc,
50 int x, int y);
51
52
53static u32 copy_cursor_image(u8 *src, u8 *dst, int width, int height);
54static int ast_cursor_update(void *dst, void *src, unsigned int width,
55 unsigned int height);
56static void ast_cursor_set_base(struct ast_private *ast, u64 address);
57static int ast_cursor_move(struct drm_crtc *crtc,
58 int x, int y);
59
60static inline void ast_load_palette_index(struct ast_private *ast,
61 u8 index, u8 red, u8 green,
62 u8 blue)
63{
64 ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index);
65 ast_io_read8(ast, AST_IO_SEQ_PORT);
66 ast_io_write8(ast, AST_IO_DAC_DATA, red);
67 ast_io_read8(ast, AST_IO_SEQ_PORT);
68 ast_io_write8(ast, AST_IO_DAC_DATA, green);
69 ast_io_read8(ast, AST_IO_SEQ_PORT);
70 ast_io_write8(ast, AST_IO_DAC_DATA, blue);
71 ast_io_read8(ast, AST_IO_SEQ_PORT);
72}
73
74static void ast_crtc_load_lut(struct ast_private *ast, struct drm_crtc *crtc)
75{
76 u16 *r, *g, *b;
77 int i;
78
79 if (!crtc->enabled)
80 return;
81
82 r = crtc->gamma_store;
83 g = r + crtc->gamma_size;
84 b = g + crtc->gamma_size;
85
86 for (i = 0; i < 256; i++)
87 ast_load_palette_index(ast, i, *r++ >> 8, *g++ >> 8, *b++ >> 8);
88}
89
90static bool ast_get_vbios_mode_info(const struct drm_format_info *format,
91 const struct drm_display_mode *mode,
92 struct drm_display_mode *adjusted_mode,
93 struct ast_vbios_mode_info *vbios_mode)
94{
95 u32 refresh_rate_index = 0, refresh_rate;
96 const struct ast_vbios_enhtable *best = NULL;
97 u32 hborder, vborder;
98 bool check_sync;
99
100 switch (format->cpp[0] * 8) {
101 case 8:
102 vbios_mode->std_table = &vbios_stdtable[VGAModeIndex];
103 break;
104 case 16:
105 vbios_mode->std_table = &vbios_stdtable[HiCModeIndex];
106 break;
107 case 24:
108 case 32:
109 vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex];
110 break;
111 default:
112 return false;
113 }
114
115 switch (mode->crtc_hdisplay) {
116 case 640:
117 vbios_mode->enh_table = &res_640x480[refresh_rate_index];
118 break;
119 case 800:
120 vbios_mode->enh_table = &res_800x600[refresh_rate_index];
121 break;
122 case 1024:
123 vbios_mode->enh_table = &res_1024x768[refresh_rate_index];
124 break;
125 case 1280:
126 if (mode->crtc_vdisplay == 800)
127 vbios_mode->enh_table = &res_1280x800[refresh_rate_index];
128 else
129 vbios_mode->enh_table = &res_1280x1024[refresh_rate_index];
130 break;
131 case 1360:
132 vbios_mode->enh_table = &res_1360x768[refresh_rate_index];
133 break;
134 case 1440:
135 vbios_mode->enh_table = &res_1440x900[refresh_rate_index];
136 break;
137 case 1600:
138 if (mode->crtc_vdisplay == 900)
139 vbios_mode->enh_table = &res_1600x900[refresh_rate_index];
140 else
141 vbios_mode->enh_table = &res_1600x1200[refresh_rate_index];
142 break;
143 case 1680:
144 vbios_mode->enh_table = &res_1680x1050[refresh_rate_index];
145 break;
146 case 1920:
147 if (mode->crtc_vdisplay == 1080)
148 vbios_mode->enh_table = &res_1920x1080[refresh_rate_index];
149 else
150 vbios_mode->enh_table = &res_1920x1200[refresh_rate_index];
151 break;
152 default:
153 return false;
154 }
155
156 refresh_rate = drm_mode_vrefresh(mode);
157 check_sync = vbios_mode->enh_table->flags & WideScreenMode;
158
159 while (1) {
160 const struct ast_vbios_enhtable *loop = vbios_mode->enh_table;
161
162 while (loop->refresh_rate != 0xff) {
163 if ((check_sync) &&
164 (((mode->flags & DRM_MODE_FLAG_NVSYNC) &&
165 (loop->flags & PVSync)) ||
166 ((mode->flags & DRM_MODE_FLAG_PVSYNC) &&
167 (loop->flags & NVSync)) ||
168 ((mode->flags & DRM_MODE_FLAG_NHSYNC) &&
169 (loop->flags & PHSync)) ||
170 ((mode->flags & DRM_MODE_FLAG_PHSYNC) &&
171 (loop->flags & NHSync)))) {
172 loop++;
173 continue;
174 }
175 if (loop->refresh_rate <= refresh_rate
176 && (!best || loop->refresh_rate > best->refresh_rate))
177 best = loop;
178 loop++;
179 }
180 if (best || !check_sync)
181 break;
182 check_sync = 0;
183 }
184
185 if (best)
186 vbios_mode->enh_table = best;
187
188 hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0;
189 vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0;
190
191 adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht;
192 adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder;
193 adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder;
194 adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder +
195 vbios_mode->enh_table->hfp;
196 adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder +
197 vbios_mode->enh_table->hfp +
198 vbios_mode->enh_table->hsync);
199
200 adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt;
201 adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder;
202 adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder;
203 adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder +
204 vbios_mode->enh_table->vfp;
205 adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder +
206 vbios_mode->enh_table->vfp +
207 vbios_mode->enh_table->vsync);
208
209 return true;
210}
211
212static void ast_set_vbios_color_reg(struct ast_private *ast,
213 const struct drm_format_info *format,
214 const struct ast_vbios_mode_info *vbios_mode)
215{
216 u32 color_index;
217
218 switch (format->cpp[0]) {
219 case 1:
220 color_index = VGAModeIndex - 1;
221 break;
222 case 2:
223 color_index = HiCModeIndex;
224 break;
225 case 3:
226 case 4:
227 color_index = TrueCModeIndex;
228 break;
229 default:
230 return;
231 }
232
233 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0x0f) << 4));
234
235 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
236
237 if (vbios_mode->enh_table->flags & NewModeInfo) {
238 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
239 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, format->cpp[0] * 8);
240 }
241}
242
243static void ast_set_vbios_mode_reg(struct ast_private *ast,
244 const struct drm_display_mode *adjusted_mode,
245 const struct ast_vbios_mode_info *vbios_mode)
246{
247 u32 refresh_rate_index, mode_id;
248
249 refresh_rate_index = vbios_mode->enh_table->refresh_rate_index;
250 mode_id = vbios_mode->enh_table->mode_id;
251
252 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff);
253 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff);
254
255 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
256
257 if (vbios_mode->enh_table->flags & NewModeInfo) {
258 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
259 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000);
260 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay);
261 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8);
262 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay);
263 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8);
264 }
265}
266
267static void ast_set_std_reg(struct ast_private *ast,
268 struct drm_display_mode *mode,
269 struct ast_vbios_mode_info *vbios_mode)
270{
271 const struct ast_vbios_stdtable *stdtable;
272 u32 i;
273 u8 jreg;
274
275 stdtable = vbios_mode->std_table;
276
277 jreg = stdtable->misc;
278 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
279
280
281 ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03);
282 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x01, 0xdf, stdtable->seq[0]);
283 for (i = 1; i < 4; i++) {
284 jreg = stdtable->seq[i];
285 ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg);
286 }
287
288
289 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
290 for (i = 0; i < 12; i++)
291 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
292 for (i = 14; i < 19; i++)
293 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
294 for (i = 20; i < 25; i++)
295 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
296
297
298 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
299 for (i = 0; i < 20; i++) {
300 jreg = stdtable->ar[i];
301 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i);
302 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg);
303 }
304 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14);
305 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00);
306
307 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
308 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20);
309
310
311 for (i = 0; i < 9; i++)
312 ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]);
313}
314
315static void ast_set_crtc_reg(struct ast_private *ast,
316 struct drm_display_mode *mode,
317 struct ast_vbios_mode_info *vbios_mode)
318{
319 u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0;
320 u16 temp, precache = 0;
321
322 if ((ast->chip == AST2500) &&
323 (vbios_mode->enh_table->flags & AST2500PreCatchCRT))
324 precache = 40;
325
326 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
327
328 temp = (mode->crtc_htotal >> 3) - 5;
329 if (temp & 0x100)
330 jregAC |= 0x01;
331 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp);
332
333 temp = (mode->crtc_hdisplay >> 3) - 1;
334 if (temp & 0x100)
335 jregAC |= 0x04;
336 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp);
337
338 temp = (mode->crtc_hblank_start >> 3) - 1;
339 if (temp & 0x100)
340 jregAC |= 0x10;
341 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp);
342
343 temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f;
344 if (temp & 0x20)
345 jreg05 |= 0x80;
346 if (temp & 0x40)
347 jregAD |= 0x01;
348 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f));
349
350 temp = ((mode->crtc_hsync_start-precache) >> 3) - 1;
351 if (temp & 0x100)
352 jregAC |= 0x40;
353 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp);
354
355 temp = (((mode->crtc_hsync_end-precache) >> 3) - 1) & 0x3f;
356 if (temp & 0x20)
357 jregAD |= 0x04;
358 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05));
359
360 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC);
361 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD);
362
363
364 temp = (mode->crtc_vtotal) - 2;
365 if (temp & 0x100)
366 jreg07 |= 0x01;
367 if (temp & 0x200)
368 jreg07 |= 0x20;
369 if (temp & 0x400)
370 jregAE |= 0x01;
371 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp);
372
373 temp = (mode->crtc_vsync_start) - 1;
374 if (temp & 0x100)
375 jreg07 |= 0x04;
376 if (temp & 0x200)
377 jreg07 |= 0x80;
378 if (temp & 0x400)
379 jregAE |= 0x08;
380 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp);
381
382 temp = (mode->crtc_vsync_end - 1) & 0x3f;
383 if (temp & 0x10)
384 jregAE |= 0x20;
385 if (temp & 0x20)
386 jregAE |= 0x40;
387 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf);
388
389 temp = mode->crtc_vdisplay - 1;
390 if (temp & 0x100)
391 jreg07 |= 0x02;
392 if (temp & 0x200)
393 jreg07 |= 0x40;
394 if (temp & 0x400)
395 jregAE |= 0x02;
396 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp);
397
398 temp = mode->crtc_vblank_start - 1;
399 if (temp & 0x100)
400 jreg07 |= 0x08;
401 if (temp & 0x200)
402 jreg09 |= 0x20;
403 if (temp & 0x400)
404 jregAE |= 0x04;
405 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp);
406
407 temp = mode->crtc_vblank_end - 1;
408 if (temp & 0x100)
409 jregAE |= 0x10;
410 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp);
411
412 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07);
413 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09);
414 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80));
415
416 if (precache)
417 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80);
418 else
419 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00);
420
421 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80);
422}
423
424static void ast_set_offset_reg(struct ast_private *ast,
425 struct drm_framebuffer *fb)
426{
427 u16 offset;
428
429 offset = fb->pitches[0] >> 3;
430 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff));
431 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f);
432}
433
434static void ast_set_dclk_reg(struct ast_private *ast,
435 struct drm_display_mode *mode,
436 struct ast_vbios_mode_info *vbios_mode)
437{
438 const struct ast_vbios_dclk_info *clk_info;
439
440 if (ast->chip == AST2500)
441 clk_info = &dclk_table_ast2500[vbios_mode->enh_table->dclk_index];
442 else
443 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index];
444
445 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1);
446 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2);
447 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f,
448 (clk_info->param3 & 0xc0) |
449 ((clk_info->param3 & 0x3) << 4));
450}
451
452static void ast_set_color_reg(struct ast_private *ast,
453 const struct drm_format_info *format)
454{
455 u8 jregA0 = 0, jregA3 = 0, jregA8 = 0;
456
457 switch (format->cpp[0] * 8) {
458 case 8:
459 jregA0 = 0x70;
460 jregA3 = 0x01;
461 jregA8 = 0x00;
462 break;
463 case 15:
464 case 16:
465 jregA0 = 0x70;
466 jregA3 = 0x04;
467 jregA8 = 0x02;
468 break;
469 case 32:
470 jregA0 = 0x70;
471 jregA3 = 0x08;
472 jregA8 = 0x02;
473 break;
474 }
475
476 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0);
477 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3);
478 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8);
479}
480
481static void ast_set_crtthd_reg(struct ast_private *ast)
482{
483
484 if (ast->chip == AST2300 || ast->chip == AST2400 ||
485 ast->chip == AST2500) {
486 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78);
487 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60);
488 } else if (ast->chip == AST2100 ||
489 ast->chip == AST1100 ||
490 ast->chip == AST2200 ||
491 ast->chip == AST2150) {
492 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f);
493 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f);
494 } else {
495 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f);
496 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f);
497 }
498}
499
500static void ast_set_sync_reg(struct ast_private *ast,
501 struct drm_display_mode *mode,
502 struct ast_vbios_mode_info *vbios_mode)
503{
504 u8 jreg;
505
506 jreg = ast_io_read8(ast, AST_IO_MISC_PORT_READ);
507 jreg &= ~0xC0;
508 if (vbios_mode->enh_table->flags & NVSync) jreg |= 0x80;
509 if (vbios_mode->enh_table->flags & NHSync) jreg |= 0x40;
510 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
511}
512
513static void ast_set_start_address_crt1(struct ast_private *ast,
514 unsigned offset)
515{
516 u32 addr;
517
518 addr = offset >> 2;
519 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff));
520 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff));
521 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff));
522
523}
524
525
526
527
528
529static const uint32_t ast_primary_plane_formats[] = {
530 DRM_FORMAT_XRGB8888,
531 DRM_FORMAT_RGB565,
532 DRM_FORMAT_C8,
533};
534
535static int ast_primary_plane_helper_atomic_check(struct drm_plane *plane,
536 struct drm_plane_state *state)
537{
538 struct drm_crtc_state *crtc_state;
539 struct ast_crtc_state *ast_crtc_state;
540 int ret;
541
542 if (!state->crtc)
543 return 0;
544
545 crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc);
546
547 ret = drm_atomic_helper_check_plane_state(state, crtc_state,
548 DRM_PLANE_HELPER_NO_SCALING,
549 DRM_PLANE_HELPER_NO_SCALING,
550 false, true);
551 if (ret)
552 return ret;
553
554 if (!state->visible)
555 return 0;
556
557 ast_crtc_state = to_ast_crtc_state(crtc_state);
558
559 ast_crtc_state->format = state->fb->format;
560
561 return 0;
562}
563
564void ast_primary_plane_helper_atomic_update(struct drm_plane *plane,
565 struct drm_plane_state *old_state)
566{
567 struct ast_private *ast = plane->dev->dev_private;
568 struct drm_plane_state *state = plane->state;
569 struct drm_gem_vram_object *gbo;
570 s64 gpu_addr;
571
572 gbo = drm_gem_vram_of_gem(state->fb->obj[0]);
573 gpu_addr = drm_gem_vram_offset(gbo);
574 if (WARN_ON_ONCE(gpu_addr < 0))
575 return;
576
577 ast_set_offset_reg(ast, state->fb);
578 ast_set_start_address_crt1(ast, (u32)gpu_addr);
579
580 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x00);
581}
582
583static void
584ast_primary_plane_helper_atomic_disable(struct drm_plane *plane,
585 struct drm_plane_state *old_state)
586{
587 struct ast_private *ast = plane->dev->dev_private;
588
589 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20);
590}
591
592static const struct drm_plane_helper_funcs ast_primary_plane_helper_funcs = {
593 .prepare_fb = drm_gem_vram_plane_helper_prepare_fb,
594 .cleanup_fb = drm_gem_vram_plane_helper_cleanup_fb,
595 .atomic_check = ast_primary_plane_helper_atomic_check,
596 .atomic_update = ast_primary_plane_helper_atomic_update,
597 .atomic_disable = ast_primary_plane_helper_atomic_disable,
598};
599
600static const struct drm_plane_funcs ast_primary_plane_funcs = {
601 .update_plane = drm_atomic_helper_update_plane,
602 .disable_plane = drm_atomic_helper_disable_plane,
603 .destroy = drm_plane_cleanup,
604 .reset = drm_atomic_helper_plane_reset,
605 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
606 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
607};
608
609
610
611
612
613static const uint32_t ast_cursor_plane_formats[] = {
614 DRM_FORMAT_ARGB8888,
615};
616
617static int
618ast_cursor_plane_helper_prepare_fb(struct drm_plane *plane,
619 struct drm_plane_state *new_state)
620{
621 struct drm_framebuffer *fb = new_state->fb;
622 struct drm_crtc *crtc = new_state->crtc;
623 struct drm_gem_vram_object *gbo;
624 struct ast_private *ast;
625 int ret;
626 void *src, *dst;
627
628 if (!crtc || !fb)
629 return 0;
630
631 if (WARN_ON_ONCE(fb->width > AST_MAX_HWC_WIDTH) ||
632 WARN_ON_ONCE(fb->height > AST_MAX_HWC_HEIGHT))
633 return -EINVAL;
634
635 ast = crtc->dev->dev_private;
636
637 gbo = drm_gem_vram_of_gem(fb->obj[0]);
638 src = drm_gem_vram_vmap(gbo);
639 if (IS_ERR(src)) {
640 ret = PTR_ERR(src);
641 goto err_drm_gem_vram_unpin;
642 }
643
644 dst = drm_gem_vram_vmap(ast->cursor.gbo[ast->cursor.next_index]);
645 if (IS_ERR(dst)) {
646 ret = PTR_ERR(dst);
647 goto err_drm_gem_vram_vunmap_src;
648 }
649
650 ret = ast_cursor_update(dst, src, fb->width, fb->height);
651 if (ret)
652 goto err_drm_gem_vram_vunmap_dst;
653
654
655
656
657
658 drm_gem_vram_vunmap(ast->cursor.gbo[ast->cursor.next_index], dst);
659 drm_gem_vram_vunmap(gbo, src);
660
661 return 0;
662
663err_drm_gem_vram_vunmap_dst:
664 drm_gem_vram_vunmap(ast->cursor.gbo[ast->cursor.next_index], dst);
665err_drm_gem_vram_vunmap_src:
666 drm_gem_vram_vunmap(gbo, src);
667err_drm_gem_vram_unpin:
668 drm_gem_vram_unpin(gbo);
669 return ret;
670}
671
672static int ast_cursor_plane_helper_atomic_check(struct drm_plane *plane,
673 struct drm_plane_state *state)
674{
675 struct drm_framebuffer *fb = state->fb;
676 struct drm_crtc_state *crtc_state;
677 int ret;
678
679 if (!state->crtc)
680 return 0;
681
682 crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc);
683
684 ret = drm_atomic_helper_check_plane_state(state, crtc_state,
685 DRM_PLANE_HELPER_NO_SCALING,
686 DRM_PLANE_HELPER_NO_SCALING,
687 true, true);
688 if (ret)
689 return ret;
690
691 if (!state->visible)
692 return 0;
693
694 if (fb->width > AST_MAX_HWC_WIDTH || fb->height > AST_MAX_HWC_HEIGHT)
695 return -EINVAL;
696
697 return 0;
698}
699
700static void
701ast_cursor_plane_helper_atomic_update(struct drm_plane *plane,
702 struct drm_plane_state *old_state)
703{
704 struct drm_plane_state *state = plane->state;
705 struct drm_crtc *crtc = state->crtc;
706 struct drm_framebuffer *fb = state->fb;
707 struct ast_private *ast = plane->dev->dev_private;
708 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
709 struct drm_gem_vram_object *gbo;
710 s64 off;
711 u8 jreg;
712
713 ast_crtc->offset_x = AST_MAX_HWC_WIDTH - fb->width;
714 ast_crtc->offset_y = AST_MAX_HWC_WIDTH - fb->height;
715
716 if (state->fb != old_state->fb) {
717
718 gbo = ast->cursor.gbo[ast->cursor.next_index];
719 off = drm_gem_vram_offset(gbo);
720 if (WARN_ON_ONCE(off < 0))
721 return;
722 ast_cursor_set_base(ast, off);
723
724 ++ast->cursor.next_index;
725 ast->cursor.next_index %= ARRAY_SIZE(ast->cursor.gbo);
726 }
727
728 ast_cursor_move(crtc, state->crtc_x, state->crtc_y);
729
730 jreg = 0x2;
731
732 jreg |= 1;
733 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg);
734}
735
736static void
737ast_cursor_plane_helper_atomic_disable(struct drm_plane *plane,
738 struct drm_plane_state *old_state)
739{
740 struct ast_private *ast = plane->dev->dev_private;
741
742 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, 0x00);
743}
744
745static const struct drm_plane_helper_funcs ast_cursor_plane_helper_funcs = {
746 .prepare_fb = ast_cursor_plane_helper_prepare_fb,
747 .cleanup_fb = NULL,
748 .atomic_check = ast_cursor_plane_helper_atomic_check,
749 .atomic_update = ast_cursor_plane_helper_atomic_update,
750 .atomic_disable = ast_cursor_plane_helper_atomic_disable,
751};
752
753static const struct drm_plane_funcs ast_cursor_plane_funcs = {
754 .update_plane = drm_atomic_helper_update_plane,
755 .disable_plane = drm_atomic_helper_disable_plane,
756 .destroy = drm_plane_cleanup,
757 .reset = drm_atomic_helper_plane_reset,
758 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
759 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
760};
761
762
763
764
765
766static void ast_crtc_dpms(struct drm_crtc *crtc, int mode)
767{
768 struct ast_private *ast = crtc->dev->dev_private;
769
770 if (ast->chip == AST1180)
771 return;
772
773
774
775
776 switch (mode) {
777 case DRM_MODE_DPMS_ON:
778 case DRM_MODE_DPMS_STANDBY:
779 case DRM_MODE_DPMS_SUSPEND:
780 if (ast->tx_chip_type == AST_TX_DP501)
781 ast_set_dp501_video_output(crtc->dev, 1);
782 ast_crtc_load_lut(ast, crtc);
783 break;
784 case DRM_MODE_DPMS_OFF:
785 if (ast->tx_chip_type == AST_TX_DP501)
786 ast_set_dp501_video_output(crtc->dev, 0);
787 break;
788 }
789}
790
791static int ast_crtc_helper_atomic_check(struct drm_crtc *crtc,
792 struct drm_crtc_state *state)
793{
794 struct ast_private *ast = crtc->dev->dev_private;
795 struct ast_crtc_state *ast_state;
796 const struct drm_format_info *format;
797 bool succ;
798
799 if (ast->chip == AST1180) {
800 DRM_ERROR("AST 1180 modesetting not supported\n");
801 return -EINVAL;
802 }
803
804 if (!state->enable)
805 return 0;
806
807 ast_state = to_ast_crtc_state(state);
808
809 format = ast_state->format;
810 if (!format)
811 return 0;
812
813 succ = ast_get_vbios_mode_info(format, &state->mode,
814 &state->adjusted_mode,
815 &ast_state->vbios_mode_info);
816 if (!succ)
817 return -EINVAL;
818
819 return 0;
820}
821
822static void ast_crtc_helper_atomic_begin(struct drm_crtc *crtc,
823 struct drm_crtc_state *old_crtc_state)
824{
825 struct ast_private *ast = crtc->dev->dev_private;
826
827 ast_open_key(ast);
828}
829
830static void ast_crtc_helper_atomic_flush(struct drm_crtc *crtc,
831 struct drm_crtc_state *old_crtc_state)
832{
833 struct drm_device *dev = crtc->dev;
834 struct ast_private *ast = dev->dev_private;
835 struct ast_crtc_state *ast_state;
836 const struct drm_format_info *format;
837 struct ast_vbios_mode_info *vbios_mode_info;
838 struct drm_display_mode *adjusted_mode;
839
840 crtc->state->no_vblank = true;
841
842 ast_state = to_ast_crtc_state(crtc->state);
843
844 format = ast_state->format;
845 if (!format)
846 return;
847
848 vbios_mode_info = &ast_state->vbios_mode_info;
849
850 ast_set_color_reg(ast, format);
851 ast_set_vbios_color_reg(ast, format, vbios_mode_info);
852
853 if (!crtc->state->mode_changed)
854 return;
855
856 adjusted_mode = &crtc->state->adjusted_mode;
857
858 ast_set_vbios_mode_reg(ast, adjusted_mode, vbios_mode_info);
859 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06);
860 ast_set_std_reg(ast, adjusted_mode, vbios_mode_info);
861 ast_set_crtc_reg(ast, adjusted_mode, vbios_mode_info);
862 ast_set_dclk_reg(ast, adjusted_mode, vbios_mode_info);
863 ast_set_crtthd_reg(ast);
864 ast_set_sync_reg(ast, adjusted_mode, vbios_mode_info);
865}
866
867static void
868ast_crtc_helper_atomic_enable(struct drm_crtc *crtc,
869 struct drm_crtc_state *old_crtc_state)
870{
871 ast_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
872}
873
874static void
875ast_crtc_helper_atomic_disable(struct drm_crtc *crtc,
876 struct drm_crtc_state *old_crtc_state)
877{
878 ast_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
879}
880
881static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = {
882 .atomic_check = ast_crtc_helper_atomic_check,
883 .atomic_begin = ast_crtc_helper_atomic_begin,
884 .atomic_flush = ast_crtc_helper_atomic_flush,
885 .atomic_enable = ast_crtc_helper_atomic_enable,
886 .atomic_disable = ast_crtc_helper_atomic_disable,
887};
888
889static void ast_crtc_reset(struct drm_crtc *crtc)
890{
891 struct ast_crtc_state *ast_state =
892 kzalloc(sizeof(*ast_state), GFP_KERNEL);
893
894 if (crtc->state)
895 crtc->funcs->atomic_destroy_state(crtc, crtc->state);
896
897 __drm_atomic_helper_crtc_reset(crtc, &ast_state->base);
898}
899
900static void ast_crtc_destroy(struct drm_crtc *crtc)
901{
902 drm_crtc_cleanup(crtc);
903 kfree(crtc);
904}
905
906static struct drm_crtc_state *
907ast_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
908{
909 struct ast_crtc_state *new_ast_state, *ast_state;
910
911 if (WARN_ON(!crtc->state))
912 return NULL;
913
914 new_ast_state = kmalloc(sizeof(*new_ast_state), GFP_KERNEL);
915 if (!new_ast_state)
916 return NULL;
917 __drm_atomic_helper_crtc_duplicate_state(crtc, &new_ast_state->base);
918
919 ast_state = to_ast_crtc_state(crtc->state);
920
921 new_ast_state->format = ast_state->format;
922 memcpy(&new_ast_state->vbios_mode_info, &ast_state->vbios_mode_info,
923 sizeof(new_ast_state->vbios_mode_info));
924
925 return &new_ast_state->base;
926}
927
928static void ast_crtc_atomic_destroy_state(struct drm_crtc *crtc,
929 struct drm_crtc_state *state)
930{
931 struct ast_crtc_state *ast_state = to_ast_crtc_state(state);
932
933 __drm_atomic_helper_crtc_destroy_state(&ast_state->base);
934 kfree(ast_state);
935}
936
937static const struct drm_crtc_funcs ast_crtc_funcs = {
938 .reset = ast_crtc_reset,
939 .set_config = drm_crtc_helper_set_config,
940 .gamma_set = drm_atomic_helper_legacy_gamma_set,
941 .destroy = ast_crtc_destroy,
942 .set_config = drm_atomic_helper_set_config,
943 .page_flip = drm_atomic_helper_page_flip,
944 .atomic_duplicate_state = ast_crtc_atomic_duplicate_state,
945 .atomic_destroy_state = ast_crtc_atomic_destroy_state,
946};
947
948static int ast_crtc_init(struct drm_device *dev)
949{
950 struct ast_private *ast = dev->dev_private;
951 struct ast_crtc *crtc;
952 int ret;
953
954 crtc = kzalloc(sizeof(struct ast_crtc), GFP_KERNEL);
955 if (!crtc)
956 return -ENOMEM;
957
958 ret = drm_crtc_init_with_planes(dev, &crtc->base, &ast->primary_plane,
959 &ast->cursor_plane, &ast_crtc_funcs,
960 NULL);
961 if (ret)
962 goto err_kfree;
963
964 drm_mode_crtc_set_gamma_size(&crtc->base, 256);
965 drm_crtc_helper_add(&crtc->base, &ast_crtc_helper_funcs);
966 return 0;
967
968err_kfree:
969 kfree(crtc);
970 return ret;
971}
972
973
974
975
976
977static void ast_encoder_destroy(struct drm_encoder *encoder)
978{
979 drm_encoder_cleanup(encoder);
980 kfree(encoder);
981}
982
983static const struct drm_encoder_funcs ast_enc_funcs = {
984 .destroy = ast_encoder_destroy,
985};
986
987static int ast_encoder_init(struct drm_device *dev)
988{
989 struct ast_encoder *ast_encoder;
990
991 ast_encoder = kzalloc(sizeof(struct ast_encoder), GFP_KERNEL);
992 if (!ast_encoder)
993 return -ENOMEM;
994
995 drm_encoder_init(dev, &ast_encoder->base, &ast_enc_funcs,
996 DRM_MODE_ENCODER_DAC, NULL);
997
998 ast_encoder->base.possible_crtcs = 1;
999 return 0;
1000}
1001
1002
1003
1004
1005
1006static int ast_get_modes(struct drm_connector *connector)
1007{
1008 struct ast_connector *ast_connector = to_ast_connector(connector);
1009 struct ast_private *ast = connector->dev->dev_private;
1010 struct edid *edid;
1011 int ret;
1012 bool flags = false;
1013 if (ast->tx_chip_type == AST_TX_DP501) {
1014 ast->dp501_maxclk = 0xff;
1015 edid = kmalloc(128, GFP_KERNEL);
1016 if (!edid)
1017 return -ENOMEM;
1018
1019 flags = ast_dp501_read_edid(connector->dev, (u8 *)edid);
1020 if (flags)
1021 ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev);
1022 else
1023 kfree(edid);
1024 }
1025 if (!flags)
1026 edid = drm_get_edid(connector, &ast_connector->i2c->adapter);
1027 if (edid) {
1028 drm_connector_update_edid_property(&ast_connector->base, edid);
1029 ret = drm_add_edid_modes(connector, edid);
1030 kfree(edid);
1031 return ret;
1032 } else
1033 drm_connector_update_edid_property(&ast_connector->base, NULL);
1034 return 0;
1035}
1036
1037static enum drm_mode_status ast_mode_valid(struct drm_connector *connector,
1038 struct drm_display_mode *mode)
1039{
1040 struct ast_private *ast = connector->dev->dev_private;
1041 int flags = MODE_NOMODE;
1042 uint32_t jtemp;
1043
1044 if (ast->support_wide_screen) {
1045 if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050))
1046 return MODE_OK;
1047 if ((mode->hdisplay == 1280) && (mode->vdisplay == 800))
1048 return MODE_OK;
1049 if ((mode->hdisplay == 1440) && (mode->vdisplay == 900))
1050 return MODE_OK;
1051 if ((mode->hdisplay == 1360) && (mode->vdisplay == 768))
1052 return MODE_OK;
1053 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900))
1054 return MODE_OK;
1055
1056 if ((ast->chip == AST2100) || (ast->chip == AST2200) ||
1057 (ast->chip == AST2300) || (ast->chip == AST2400) ||
1058 (ast->chip == AST2500) || (ast->chip == AST1180)) {
1059 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080))
1060 return MODE_OK;
1061
1062 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) {
1063 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
1064 if (jtemp & 0x01)
1065 return MODE_NOMODE;
1066 else
1067 return MODE_OK;
1068 }
1069 }
1070 }
1071 switch (mode->hdisplay) {
1072 case 640:
1073 if (mode->vdisplay == 480) flags = MODE_OK;
1074 break;
1075 case 800:
1076 if (mode->vdisplay == 600) flags = MODE_OK;
1077 break;
1078 case 1024:
1079 if (mode->vdisplay == 768) flags = MODE_OK;
1080 break;
1081 case 1280:
1082 if (mode->vdisplay == 1024) flags = MODE_OK;
1083 break;
1084 case 1600:
1085 if (mode->vdisplay == 1200) flags = MODE_OK;
1086 break;
1087 default:
1088 return flags;
1089 }
1090
1091 return flags;
1092}
1093
1094static void ast_connector_destroy(struct drm_connector *connector)
1095{
1096 struct ast_connector *ast_connector = to_ast_connector(connector);
1097 ast_i2c_destroy(ast_connector->i2c);
1098 drm_connector_unregister(connector);
1099 drm_connector_cleanup(connector);
1100 kfree(connector);
1101}
1102
1103static const struct drm_connector_helper_funcs ast_connector_helper_funcs = {
1104 .get_modes = ast_get_modes,
1105 .mode_valid = ast_mode_valid,
1106};
1107
1108static const struct drm_connector_funcs ast_connector_funcs = {
1109 .reset = drm_atomic_helper_connector_reset,
1110 .fill_modes = drm_helper_probe_single_connector_modes,
1111 .destroy = ast_connector_destroy,
1112 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1113 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1114};
1115
1116static int ast_connector_init(struct drm_device *dev)
1117{
1118 struct ast_connector *ast_connector;
1119 struct drm_connector *connector;
1120 struct drm_encoder *encoder;
1121
1122 ast_connector = kzalloc(sizeof(struct ast_connector), GFP_KERNEL);
1123 if (!ast_connector)
1124 return -ENOMEM;
1125
1126 connector = &ast_connector->base;
1127 ast_connector->i2c = ast_i2c_create(dev);
1128 if (!ast_connector->i2c)
1129 DRM_ERROR("failed to add ddc bus for connector\n");
1130
1131 drm_connector_init_with_ddc(dev, connector,
1132 &ast_connector_funcs,
1133 DRM_MODE_CONNECTOR_VGA,
1134 &ast_connector->i2c->adapter);
1135
1136 drm_connector_helper_add(connector, &ast_connector_helper_funcs);
1137
1138 connector->interlace_allowed = 0;
1139 connector->doublescan_allowed = 0;
1140
1141 drm_connector_register(connector);
1142
1143 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1144
1145 encoder = list_first_entry(&dev->mode_config.encoder_list, struct drm_encoder, head);
1146 drm_connector_attach_encoder(connector, encoder);
1147
1148 return 0;
1149}
1150
1151
1152static int ast_cursor_init(struct drm_device *dev)
1153{
1154 struct ast_private *ast = dev->dev_private;
1155 size_t size, i;
1156 struct drm_gem_vram_object *gbo;
1157 int ret;
1158
1159 size = roundup(AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE, PAGE_SIZE);
1160
1161 for (i = 0; i < ARRAY_SIZE(ast->cursor.gbo); ++i) {
1162 gbo = drm_gem_vram_create(dev, size, 0);
1163 if (IS_ERR(gbo)) {
1164 ret = PTR_ERR(gbo);
1165 goto err_drm_gem_vram_put;
1166 }
1167 ret = drm_gem_vram_pin(gbo, DRM_GEM_VRAM_PL_FLAG_VRAM |
1168 DRM_GEM_VRAM_PL_FLAG_TOPDOWN);
1169 if (ret) {
1170 drm_gem_vram_put(gbo);
1171 goto err_drm_gem_vram_put;
1172 }
1173
1174 ast->cursor.gbo[i] = gbo;
1175 }
1176
1177 return 0;
1178
1179err_drm_gem_vram_put:
1180 while (i) {
1181 --i;
1182 gbo = ast->cursor.gbo[i];
1183 drm_gem_vram_unpin(gbo);
1184 drm_gem_vram_put(gbo);
1185 ast->cursor.gbo[i] = NULL;
1186 }
1187 return ret;
1188}
1189
1190static void ast_cursor_fini(struct drm_device *dev)
1191{
1192 struct ast_private *ast = dev->dev_private;
1193 size_t i;
1194 struct drm_gem_vram_object *gbo;
1195
1196 for (i = 0; i < ARRAY_SIZE(ast->cursor.gbo); ++i) {
1197 gbo = ast->cursor.gbo[i];
1198 drm_gem_vram_unpin(gbo);
1199 drm_gem_vram_put(gbo);
1200 }
1201}
1202
1203int ast_mode_init(struct drm_device *dev)
1204{
1205 struct ast_private *ast = dev->dev_private;
1206 int ret;
1207
1208 memset(&ast->primary_plane, 0, sizeof(ast->primary_plane));
1209 ret = drm_universal_plane_init(dev, &ast->primary_plane, 0x01,
1210 &ast_primary_plane_funcs,
1211 ast_primary_plane_formats,
1212 ARRAY_SIZE(ast_primary_plane_formats),
1213 NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
1214 if (ret) {
1215 DRM_ERROR("ast: drm_universal_plane_init() failed: %d\n", ret);
1216 return ret;
1217 }
1218 drm_plane_helper_add(&ast->primary_plane,
1219 &ast_primary_plane_helper_funcs);
1220
1221 ret = drm_universal_plane_init(dev, &ast->cursor_plane, 0x01,
1222 &ast_cursor_plane_funcs,
1223 ast_cursor_plane_formats,
1224 ARRAY_SIZE(ast_cursor_plane_formats),
1225 NULL, DRM_PLANE_TYPE_CURSOR, NULL);
1226 if (ret) {
1227 DRM_ERROR("drm_universal_plane_failed(): %d\n", ret);
1228 return ret;
1229 }
1230 drm_plane_helper_add(&ast->cursor_plane,
1231 &ast_cursor_plane_helper_funcs);
1232
1233 ast_cursor_init(dev);
1234 ast_crtc_init(dev);
1235 ast_encoder_init(dev);
1236 ast_connector_init(dev);
1237
1238 return 0;
1239}
1240
1241void ast_mode_fini(struct drm_device *dev)
1242{
1243 ast_cursor_fini(dev);
1244}
1245
1246static int get_clock(void *i2c_priv)
1247{
1248 struct ast_i2c_chan *i2c = i2c_priv;
1249 struct ast_private *ast = i2c->dev->dev_private;
1250 uint32_t val, val2, count, pass;
1251
1252 count = 0;
1253 pass = 0;
1254 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
1255 do {
1256 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
1257 if (val == val2) {
1258 pass++;
1259 } else {
1260 pass = 0;
1261 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
1262 }
1263 } while ((pass < 5) && (count++ < 0x10000));
1264
1265 return val & 1 ? 1 : 0;
1266}
1267
1268static int get_data(void *i2c_priv)
1269{
1270 struct ast_i2c_chan *i2c = i2c_priv;
1271 struct ast_private *ast = i2c->dev->dev_private;
1272 uint32_t val, val2, count, pass;
1273
1274 count = 0;
1275 pass = 0;
1276 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
1277 do {
1278 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
1279 if (val == val2) {
1280 pass++;
1281 } else {
1282 pass = 0;
1283 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
1284 }
1285 } while ((pass < 5) && (count++ < 0x10000));
1286
1287 return val & 1 ? 1 : 0;
1288}
1289
1290static void set_clock(void *i2c_priv, int clock)
1291{
1292 struct ast_i2c_chan *i2c = i2c_priv;
1293 struct ast_private *ast = i2c->dev->dev_private;
1294 int i;
1295 u8 ujcrb7, jtemp;
1296
1297 for (i = 0; i < 0x10000; i++) {
1298 ujcrb7 = ((clock & 0x01) ? 0 : 1);
1299 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf4, ujcrb7);
1300 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01);
1301 if (ujcrb7 == jtemp)
1302 break;
1303 }
1304}
1305
1306static void set_data(void *i2c_priv, int data)
1307{
1308 struct ast_i2c_chan *i2c = i2c_priv;
1309 struct ast_private *ast = i2c->dev->dev_private;
1310 int i;
1311 u8 ujcrb7, jtemp;
1312
1313 for (i = 0; i < 0x10000; i++) {
1314 ujcrb7 = ((data & 0x01) ? 0 : 1) << 2;
1315 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf1, ujcrb7);
1316 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04);
1317 if (ujcrb7 == jtemp)
1318 break;
1319 }
1320}
1321
1322static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev)
1323{
1324 struct ast_i2c_chan *i2c;
1325 int ret;
1326
1327 i2c = kzalloc(sizeof(struct ast_i2c_chan), GFP_KERNEL);
1328 if (!i2c)
1329 return NULL;
1330
1331 i2c->adapter.owner = THIS_MODULE;
1332 i2c->adapter.class = I2C_CLASS_DDC;
1333 i2c->adapter.dev.parent = &dev->pdev->dev;
1334 i2c->dev = dev;
1335 i2c_set_adapdata(&i2c->adapter, i2c);
1336 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
1337 "AST i2c bit bus");
1338 i2c->adapter.algo_data = &i2c->bit;
1339
1340 i2c->bit.udelay = 20;
1341 i2c->bit.timeout = 2;
1342 i2c->bit.data = i2c;
1343 i2c->bit.setsda = set_data;
1344 i2c->bit.setscl = set_clock;
1345 i2c->bit.getsda = get_data;
1346 i2c->bit.getscl = get_clock;
1347 ret = i2c_bit_add_bus(&i2c->adapter);
1348 if (ret) {
1349 DRM_ERROR("Failed to register bit i2c\n");
1350 goto out_free;
1351 }
1352
1353 return i2c;
1354out_free:
1355 kfree(i2c);
1356 return NULL;
1357}
1358
1359static void ast_i2c_destroy(struct ast_i2c_chan *i2c)
1360{
1361 if (!i2c)
1362 return;
1363 i2c_del_adapter(&i2c->adapter);
1364 kfree(i2c);
1365}
1366
1367static u32 copy_cursor_image(u8 *src, u8 *dst, int width, int height)
1368{
1369 union {
1370 u32 ul;
1371 u8 b[4];
1372 } srcdata32[2], data32;
1373 union {
1374 u16 us;
1375 u8 b[2];
1376 } data16;
1377 u32 csum = 0;
1378 s32 alpha_dst_delta, last_alpha_dst_delta;
1379 u8 *srcxor, *dstxor;
1380 int i, j;
1381 u32 per_pixel_copy, two_pixel_copy;
1382
1383 alpha_dst_delta = AST_MAX_HWC_WIDTH << 1;
1384 last_alpha_dst_delta = alpha_dst_delta - (width << 1);
1385
1386 srcxor = src;
1387 dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta;
1388 per_pixel_copy = width & 1;
1389 two_pixel_copy = width >> 1;
1390
1391 for (j = 0; j < height; j++) {
1392 for (i = 0; i < two_pixel_copy; i++) {
1393 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
1394 srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0;
1395 data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
1396 data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
1397 data32.b[2] = srcdata32[1].b[1] | (srcdata32[1].b[0] >> 4);
1398 data32.b[3] = srcdata32[1].b[3] | (srcdata32[1].b[2] >> 4);
1399
1400 writel(data32.ul, dstxor);
1401 csum += data32.ul;
1402
1403 dstxor += 4;
1404 srcxor += 8;
1405
1406 }
1407
1408 for (i = 0; i < per_pixel_copy; i++) {
1409 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
1410 data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
1411 data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
1412 writew(data16.us, dstxor);
1413 csum += (u32)data16.us;
1414
1415 dstxor += 2;
1416 srcxor += 4;
1417 }
1418 dstxor += last_alpha_dst_delta;
1419 }
1420 return csum;
1421}
1422
1423static int ast_cursor_update(void *dst, void *src, unsigned int width,
1424 unsigned int height)
1425{
1426 u32 csum;
1427
1428
1429 csum = copy_cursor_image(src, dst, width, height);
1430
1431
1432 dst += AST_HWC_SIZE;
1433 writel(csum, dst);
1434 writel(width, dst + AST_HWC_SIGNATURE_SizeX);
1435 writel(height, dst + AST_HWC_SIGNATURE_SizeY);
1436 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX);
1437 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY);
1438
1439 return 0;
1440}
1441
1442static void ast_cursor_set_base(struct ast_private *ast, u64 address)
1443{
1444 u8 addr0 = (address >> 3) & 0xff;
1445 u8 addr1 = (address >> 11) & 0xff;
1446 u8 addr2 = (address >> 19) & 0xff;
1447
1448 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, addr0);
1449 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, addr1);
1450 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, addr2);
1451}
1452
1453static int ast_cursor_move(struct drm_crtc *crtc,
1454 int x, int y)
1455{
1456 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
1457 struct ast_private *ast = crtc->dev->dev_private;
1458 struct drm_gem_vram_object *gbo;
1459 int x_offset, y_offset;
1460 u8 *dst, *sig;
1461 u8 jreg;
1462
1463 gbo = ast->cursor.gbo[ast->cursor.next_index];
1464 dst = drm_gem_vram_vmap(gbo);
1465 if (IS_ERR(dst))
1466 return PTR_ERR(dst);
1467
1468 sig = dst + AST_HWC_SIZE;
1469 writel(x, sig + AST_HWC_SIGNATURE_X);
1470 writel(y, sig + AST_HWC_SIGNATURE_Y);
1471
1472 x_offset = ast_crtc->offset_x;
1473 y_offset = ast_crtc->offset_y;
1474 if (x < 0) {
1475 x_offset = (-x) + ast_crtc->offset_x;
1476 x = 0;
1477 }
1478
1479 if (y < 0) {
1480 y_offset = (-y) + ast_crtc->offset_y;
1481 y = 0;
1482 }
1483 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset);
1484 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset);
1485 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, (x & 0xff));
1486 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, ((x >> 8) & 0x0f));
1487 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, (y & 0xff));
1488 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, ((y >> 8) & 0x07));
1489
1490
1491 jreg = 0x02 |
1492 0x01;
1493 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg);
1494
1495 drm_gem_vram_vunmap(gbo, dst);
1496
1497 return 0;
1498}
1499
