LXR linux/drivers/gpu/drm/drm

   1/*
   2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
   3 * Copyright (c) 2007-2008 Intel Corporation
   4 *   Jesse Barnes <jesse.barnes@intel.com>
   5 * Copyright 2010 Red Hat, Inc.
   6 *
   7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
   8 * FB layer.
   9 *   Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
  10 *
  11 * Permission is hereby granted, free of charge, to any person obtaining a
  12 * copy of this software and associated documentation files (the "Software"),
  13 * to deal in the Software without restriction, including without limitation
  14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
  15 * and/or sell copies of the Software, and to permit persons to whom the
  16 * Software is furnished to do so, subject to the following conditions:
  17 *
  18 * The above copyright notice and this permission notice (including the
  19 * next paragraph) shall be included in all copies or substantial portions
  20 * of the Software.
  21 *
  22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  28 * DEALINGS IN THE SOFTWARE.
  29 */
  30
  31#include <linux/hdmi.h>
  32#include <linux/i2c.h>
  33#include <linux/kernel.h>
  34#include <linux/module.h>
  35#include <linux/slab.h>
  36#include <linux/vga_switcheroo.h>
  37
  38#include <drm/drm_displayid.h>
  39#include <drm/drm_drv.h>
  40#include <drm/drm_edid.h>
  41#include <drm/drm_encoder.h>
  42#include <drm/drm_print.h>
  43#include <drm/drm_scdc_helper.h>
  44
  45#include "drm_crtc_internal.h"
  46
  47#define version_greater(edid, maj, min) \
  48        (((edid)->version > (maj)) || \
  49         ((edid)->version == (maj) && (edid)->revision > (min)))
  50
  51#define EDID_EST_TIMINGS 16
  52#define EDID_STD_TIMINGS 8
  53#define EDID_DETAILED_TIMINGS 4
  54
  55/*
  56 * EDID blocks out in the wild have a variety of bugs, try to collect
  57 * them here (note that userspace may work around broken monitors first,
  58 * but fixes should make their way here so that the kernel "just works"
  59 * on as many displays as possible).
  60 */
  61
  62/* First detailed mode wrong, use largest 60Hz mode */
  63#define EDID_QUIRK_PREFER_LARGE_60              (1 << 0)
  64/* Reported 135MHz pixel clock is too high, needs adjustment */
  65#define EDID_QUIRK_135_CLOCK_TOO_HIGH           (1 << 1)
  66/* Prefer the largest mode at 75 Hz */
  67#define EDID_QUIRK_PREFER_LARGE_75              (1 << 2)
  68/* Detail timing is in cm not mm */
  69#define EDID_QUIRK_DETAILED_IN_CM               (1 << 3)
  70/* Detailed timing descriptors have bogus size values, so just take the
  71 * maximum size and use that.
  72 */
  73#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE    (1 << 4)
  74/* use +hsync +vsync for detailed mode */
  75#define EDID_QUIRK_DETAILED_SYNC_PP             (1 << 6)
  76/* Force reduced-blanking timings for detailed modes */
  77#define EDID_QUIRK_FORCE_REDUCED_BLANKING       (1 << 7)
  78/* Force 8bpc */
  79#define EDID_QUIRK_FORCE_8BPC                   (1 << 8)
  80/* Force 12bpc */
  81#define EDID_QUIRK_FORCE_12BPC                  (1 << 9)
  82/* Force 6bpc */
  83#define EDID_QUIRK_FORCE_6BPC                   (1 << 10)
  84/* Force 10bpc */
  85#define EDID_QUIRK_FORCE_10BPC                  (1 << 11)
  86/* Non desktop display (i.e. HMD) */
  87#define EDID_QUIRK_NON_DESKTOP                  (1 << 12)
  88
  89struct detailed_mode_closure {
  90        struct drm_connector *connector;
  91        struct edid *edid;
  92        bool preferred;
  93        u32 quirks;
  94        int modes;
  95};
  96
  97#define LEVEL_DMT       0
  98#define LEVEL_GTF       1
  99#define LEVEL_GTF2      2
 100#define LEVEL_CVT       3
 101
 102static const struct edid_quirk {
 103        char vendor[4];
 104        int product_id;
 105        u32 quirks;
 106} edid_quirk_list[] = {
 107        /* Acer AL1706 */
 108        { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
 109        /* Acer F51 */
 110        { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
 111
 112        /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
 113        { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
 114
 115        /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
 116        { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },
 117
 118        /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
 119        { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
 120
 121        /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
 122        { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
 123
 124        /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
 125        { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC },
 126
 127        /* Belinea 10 15 55 */
 128        { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
 129        { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
 130
 131        /* Envision Peripherals, Inc. EN-7100e */
 132        { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
 133        /* Envision EN2028 */
 134        { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
 135
 136        /* Funai Electronics PM36B */
 137        { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
 138          EDID_QUIRK_DETAILED_IN_CM },
 139
 140        /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
 141        { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
 142
 143        /* LG Philips LCD LP154W01-A5 */
 144        { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
 145        { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
 146
 147        /* Samsung SyncMaster 205BW.  Note: irony */
 148        { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
 149        /* Samsung SyncMaster 22[5-6]BW */
 150        { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
 151        { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
 152
 153        /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
 154        { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
 155
 156        /* ViewSonic VA2026w */
 157        { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
 158
 159        /* Medion MD 30217 PG */
 160        { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
 161
 162        /* Lenovo G50 */
 163        { "SDC", 18514, EDID_QUIRK_FORCE_6BPC },
 164
 165        /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
 166        { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
 167
 168        /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
 169        { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
 170
 171        /* Valve Index Headset */
 172        { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP },
 173        { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP },
 174        { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP },
 175        { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP },
 176        { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP },
 177        { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP },
 178        { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP },
 179        { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP },
 180        { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP },
 181        { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP },
 182        { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP },
 183        { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP },
 184        { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP },
 185        { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP },
 186        { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP },
 187        { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP },
 188        { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP },
 189
 190        /* HTC Vive and Vive Pro VR Headsets */
 191        { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
 192        { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
 193
 194        /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
 195        { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
 196        { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
 197        { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
 198        { "OVR", 0x0012, EDID_QUIRK_NON_DESKTOP },
 199
 200        /* Windows Mixed Reality Headsets */
 201        { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
 202        { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
 203        { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
 204        { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
 205        { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
 206        { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
 207        { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
 208        { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
 209
 210        /* Sony PlayStation VR Headset */
 211        { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
 212
 213        /* Sensics VR Headsets */
 214        { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP },
 215
 216        /* OSVR HDK and HDK2 VR Headsets */
 217        { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP },
 218};
 219
 220/*
 221 * Autogenerated from the DMT spec.
 222 * This table is copied from xfree86/modes/xf86EdidModes.c.
 223 */
 224static const struct drm_display_mode drm_dmt_modes[] = {
 225        /* 0x01 - 640x350@85Hz */
 226        { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
 227                   736, 832, 0, 350, 382, 385, 445, 0,
 228                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 229        /* 0x02 - 640x400@85Hz */
 230        { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
 231                   736, 832, 0, 400, 401, 404, 445, 0,
 232                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 233        /* 0x03 - 720x400@85Hz */
 234        { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
 235                   828, 936, 0, 400, 401, 404, 446, 0,
 236                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 237        /* 0x04 - 640x480@60Hz */
 238        { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
 239                   752, 800, 0, 480, 490, 492, 525, 0,
 240                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 241        /* 0x05 - 640x480@72Hz */
 242        { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
 243                   704, 832, 0, 480, 489, 492, 520, 0,
 244                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 245        /* 0x06 - 640x480@75Hz */
 246        { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
 247                   720, 840, 0, 480, 481, 484, 500, 0,
 248                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 249        /* 0x07 - 640x480@85Hz */
 250        { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
 251                   752, 832, 0, 480, 481, 484, 509, 0,
 252                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 253        /* 0x08 - 800x600@56Hz */
 254        { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
 255                   896, 1024, 0, 600, 601, 603, 625, 0,
 256                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 257        /* 0x09 - 800x600@60Hz */
 258        { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
 259                   968, 1056, 0, 600, 601, 605, 628, 0,
 260                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 261        /* 0x0a - 800x600@72Hz */
 262        { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
 263                   976, 1040, 0, 600, 637, 643, 666, 0,
 264                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 265        /* 0x0b - 800x600@75Hz */
 266        { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
 267                   896, 1056, 0, 600, 601, 604, 625, 0,
 268                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 269        /* 0x0c - 800x600@85Hz */
 270        { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
 271                   896, 1048, 0, 600, 601, 604, 631, 0,
 272                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 273        /* 0x0d - 800x600@120Hz RB */
 274        { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
 275                   880, 960, 0, 600, 603, 607, 636, 0,
 276                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 277        /* 0x0e - 848x480@60Hz */
 278        { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
 279                   976, 1088, 0, 480, 486, 494, 517, 0,
 280                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 281        /* 0x0f - 1024x768@43Hz, interlace */
 282        { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
 283                   1208, 1264, 0, 768, 768, 776, 817, 0,
 284                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
 285                   DRM_MODE_FLAG_INTERLACE) },
 286        /* 0x10 - 1024x768@60Hz */
 287        { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
 288                   1184, 1344, 0, 768, 771, 777, 806, 0,
 289                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 290        /* 0x11 - 1024x768@70Hz */
 291        { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
 292                   1184, 1328, 0, 768, 771, 777, 806, 0,
 293                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 294        /* 0x12 - 1024x768@75Hz */
 295        { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
 296                   1136, 1312, 0, 768, 769, 772, 800, 0,
 297                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 298        /* 0x13 - 1024x768@85Hz */
 299        { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
 300                   1168, 1376, 0, 768, 769, 772, 808, 0,
 301                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 302        /* 0x14 - 1024x768@120Hz RB */
 303        { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
 304                   1104, 1184, 0, 768, 771, 775, 813, 0,
 305                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 306        /* 0x15 - 1152x864@75Hz */
 307        { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
 308                   1344, 1600, 0, 864, 865, 868, 900, 0,
 309                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 310        /* 0x55 - 1280x720@60Hz */
 311        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
 312                   1430, 1650, 0, 720, 725, 730, 750, 0,
 313                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 314        /* 0x16 - 1280x768@60Hz RB */
 315        { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
 316                   1360, 1440, 0, 768, 771, 778, 790, 0,
 317                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 318        /* 0x17 - 1280x768@60Hz */
 319        { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
 320                   1472, 1664, 0, 768, 771, 778, 798, 0,
 321                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 322        /* 0x18 - 1280x768@75Hz */
 323        { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
 324                   1488, 1696, 0, 768, 771, 778, 805, 0,
 325                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 326        /* 0x19 - 1280x768@85Hz */
 327        { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
 328                   1496, 1712, 0, 768, 771, 778, 809, 0,
 329                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 330        /* 0x1a - 1280x768@120Hz RB */
 331        { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
 332                   1360, 1440, 0, 768, 771, 778, 813, 0,
 333                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 334        /* 0x1b - 1280x800@60Hz RB */
 335        { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
 336                   1360, 1440, 0, 800, 803, 809, 823, 0,
 337                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 338        /* 0x1c - 1280x800@60Hz */
 339        { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
 340                   1480, 1680, 0, 800, 803, 809, 831, 0,
 341                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 342        /* 0x1d - 1280x800@75Hz */
 343        { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
 344                   1488, 1696, 0, 800, 803, 809, 838, 0,
 345                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 346        /* 0x1e - 1280x800@85Hz */
 347        { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
 348                   1496, 1712, 0, 800, 803, 809, 843, 0,
 349                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 350        /* 0x1f - 1280x800@120Hz RB */
 351        { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
 352                   1360, 1440, 0, 800, 803, 809, 847, 0,
 353                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 354        /* 0x20 - 1280x960@60Hz */
 355        { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
 356                   1488, 1800, 0, 960, 961, 964, 1000, 0,
 357                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 358        /* 0x21 - 1280x960@85Hz */
 359        { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
 360                   1504, 1728, 0, 960, 961, 964, 1011, 0,
 361                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 362        /* 0x22 - 1280x960@120Hz RB */
 363        { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
 364                   1360, 1440, 0, 960, 963, 967, 1017, 0,
 365                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 366        /* 0x23 - 1280x1024@60Hz */
 367        { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
 368                   1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
 369                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 370        /* 0x24 - 1280x1024@75Hz */
 371        { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
 372                   1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
 373                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 374        /* 0x25 - 1280x1024@85Hz */
 375        { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
 376                   1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
 377                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 378        /* 0x26 - 1280x1024@120Hz RB */
 379        { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
 380                   1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
 381                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 382        /* 0x27 - 1360x768@60Hz */
 383        { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
 384                   1536, 1792, 0, 768, 771, 777, 795, 0,
 385                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 386        /* 0x28 - 1360x768@120Hz RB */
 387        { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
 388                   1440, 1520, 0, 768, 771, 776, 813, 0,
 389                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 390        /* 0x51 - 1366x768@60Hz */
 391        { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
 392                   1579, 1792, 0, 768, 771, 774, 798, 0,
 393                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 394        /* 0x56 - 1366x768@60Hz */
 395        { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
 396                   1436, 1500, 0, 768, 769, 772, 800, 0,
 397                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 398        /* 0x29 - 1400x1050@60Hz RB */
 399        { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
 400                   1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
 401                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 402        /* 0x2a - 1400x1050@60Hz */
 403        { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
 404                   1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
 405                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 406        /* 0x2b - 1400x1050@75Hz */
 407        { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
 408                   1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
 409                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 410        /* 0x2c - 1400x1050@85Hz */
 411        { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
 412                   1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
 413                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 414        /* 0x2d - 1400x1050@120Hz RB */
 415        { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
 416                   1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
 417                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 418        /* 0x2e - 1440x900@60Hz RB */
 419        { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
 420                   1520, 1600, 0, 900, 903, 909, 926, 0,
 421                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 422        /* 0x2f - 1440x900@60Hz */
 423        { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
 424                   1672, 1904, 0, 900, 903, 909, 934, 0,
 425                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 426        /* 0x30 - 1440x900@75Hz */
 427        { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
 428                   1688, 1936, 0, 900, 903, 909, 942, 0,
 429                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 430        /* 0x31 - 1440x900@85Hz */
 431        { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
 432                   1696, 1952, 0, 900, 903, 909, 948, 0,
 433                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 434        /* 0x32 - 1440x900@120Hz RB */
 435        { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
 436                   1520, 1600, 0, 900, 903, 909, 953, 0,
 437                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 438        /* 0x53 - 1600x900@60Hz */
 439        { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
 440                   1704, 1800, 0, 900, 901, 904, 1000, 0,
 441                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 442        /* 0x33 - 1600x1200@60Hz */
 443        { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
 444                   1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
 445                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 446        /* 0x34 - 1600x1200@65Hz */
 447        { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
 448                   1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
 449                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 450        /* 0x35 - 1600x1200@70Hz */
 451        { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
 452                   1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
 453                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 454        /* 0x36 - 1600x1200@75Hz */
 455        { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
 456                   1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
 457                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 458        /* 0x37 - 1600x1200@85Hz */
 459        { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
 460                   1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
 461                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 462        /* 0x38 - 1600x1200@120Hz RB */
 463        { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
 464                   1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
 465                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 466        /* 0x39 - 1680x1050@60Hz RB */
 467        { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
 468                   1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
 469                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 470        /* 0x3a - 1680x1050@60Hz */
 471        { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
 472                   1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
 473                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 474        /* 0x3b - 1680x1050@75Hz */
 475        { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
 476                   1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
 477                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 478        /* 0x3c - 1680x1050@85Hz */
 479        { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
 480                   1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
 481                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 482        /* 0x3d - 1680x1050@120Hz RB */
 483        { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
 484                   1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
 485                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 486        /* 0x3e - 1792x1344@60Hz */
 487        { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
 488                   2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
 489                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 490        /* 0x3f - 1792x1344@75Hz */
 491        { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
 492                   2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
 493                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 494        /* 0x40 - 1792x1344@120Hz RB */
 495        { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
 496                   1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
 497                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 498        /* 0x41 - 1856x1392@60Hz */
 499        { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
 500                   2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
 501                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 502        /* 0x42 - 1856x1392@75Hz */
 503        { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
 504                   2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
 505                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 506        /* 0x43 - 1856x1392@120Hz RB */
 507        { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
 508                   1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
 509                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 510        /* 0x52 - 1920x1080@60Hz */
 511        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
 512                   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
 513                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 514        /* 0x44 - 1920x1200@60Hz RB */
 515        { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
 516                   2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
 517                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 518        /* 0x45 - 1920x1200@60Hz */
 519        { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
 520                   2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
 521                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 522        /* 0x46 - 1920x1200@75Hz */
 523        { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
 524                   2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
 525                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 526        /* 0x47 - 1920x1200@85Hz */
 527        { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
 528                   2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
 529                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 530        /* 0x48 - 1920x1200@120Hz RB */
 531        { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
 532                   2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
 533                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 534        /* 0x49 - 1920x1440@60Hz */
 535        { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
 536                   2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
 537                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 538        /* 0x4a - 1920x1440@75Hz */
 539        { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
 540                   2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
 541                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 542        /* 0x4b - 1920x1440@120Hz RB */
 543        { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
 544                   2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
 545                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 546        /* 0x54 - 2048x1152@60Hz */
 547        { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
 548                   2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
 549                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 550        /* 0x4c - 2560x1600@60Hz RB */
 551        { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
 552                   2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
 553                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 554        /* 0x4d - 2560x1600@60Hz */
 555        { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
 556                   3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
 557                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 558        /* 0x4e - 2560x1600@75Hz */
 559        { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
 560                   3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
 561                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 562        /* 0x4f - 2560x1600@85Hz */
 563        { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
 564                   3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
 565                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 566        /* 0x50 - 2560x1600@120Hz RB */
 567        { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
 568                   2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
 569                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 570        /* 0x57 - 4096x2160@60Hz RB */
 571        { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
 572                   4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
 573                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 574        /* 0x58 - 4096x2160@59.94Hz RB */
 575        { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
 576                   4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
 577                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 578};
 579
 580/*
 581 * These more or less come from the DMT spec.  The 720x400 modes are
 582 * inferred from historical 80x25 practice.  The 640x480@67 and 832x624@75
 583 * modes are old-school Mac modes.  The EDID spec says the 1152x864@75 mode
 584 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
 585 * mode.
 586 *
 587 * The DMT modes have been fact-checked; the rest are mild guesses.
 588 */
 589static const struct drm_display_mode edid_est_modes[] = {
 590        { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
 591                   968, 1056, 0, 600, 601, 605, 628, 0,
 592                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
 593        { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
 594                   896, 1024, 0, 600, 601, 603,  625, 0,
 595                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
 596        { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
 597                   720, 840, 0, 480, 481, 484, 500, 0,
 598                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
 599        { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
 600                   704,  832, 0, 480, 489, 492, 520, 0,
 601                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
 602        { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
 603                   768,  864, 0, 480, 483, 486, 525, 0,
 604                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
 605        { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
 606                   752, 800, 0, 480, 490, 492, 525, 0,
 607                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
 608        { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
 609                   846, 900, 0, 400, 421, 423,  449, 0,
 610                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
 611        { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
 612                   846,  900, 0, 400, 412, 414, 449, 0,
 613                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
 614        { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
 615                   1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
 616                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
 617        { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
 618                   1136, 1312, 0,  768, 769, 772, 800, 0,
 619                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
 620        { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
 621                   1184, 1328, 0,  768, 771, 777, 806, 0,
 622                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
 623        { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
 624                   1184, 1344, 0,  768, 771, 777, 806, 0,
 625                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
 626        { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
 627                   1208, 1264, 0, 768, 768, 776, 817, 0,
 628                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
 629        { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
 630                   928, 1152, 0, 624, 625, 628, 667, 0,
 631                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
 632        { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
 633                   896, 1056, 0, 600, 601, 604,  625, 0,
 634                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
 635        { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
 636                   976, 1040, 0, 600, 637, 643, 666, 0,
 637                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
 638        { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
 639                   1344, 1600, 0,  864, 865, 868, 900, 0,
 640                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
 641};
 642
 643struct minimode {
 644        short w;
 645        short h;
 646        short r;
 647        short rb;
 648};
 649
 650static const struct minimode est3_modes[] = {
 651        /* byte 6 */
 652        { 640, 350, 85, 0 },
 653        { 640, 400, 85, 0 },
 654        { 720, 400, 85, 0 },
 655        { 640, 480, 85, 0 },
 656        { 848, 480, 60, 0 },
 657        { 800, 600, 85, 0 },
 658        { 1024, 768, 85, 0 },
 659        { 1152, 864, 75, 0 },
 660        /* byte 7 */
 661        { 1280, 768, 60, 1 },
 662        { 1280, 768, 60, 0 },
 663        { 1280, 768, 75, 0 },
 664        { 1280, 768, 85, 0 },
 665        { 1280, 960, 60, 0 },
 666        { 1280, 960, 85, 0 },
 667        { 1280, 1024, 60, 0 },
 668        { 1280, 1024, 85, 0 },
 669        /* byte 8 */
 670        { 1360, 768, 60, 0 },
 671        { 1440, 900, 60, 1 },
 672        { 1440, 900, 60, 0 },
 673        { 1440, 900, 75, 0 },
 674        { 1440, 900, 85, 0 },
 675        { 1400, 1050, 60, 1 },
 676        { 1400, 1050, 60, 0 },
 677        { 1400, 1050, 75, 0 },
 678        /* byte 9 */
 679        { 1400, 1050, 85, 0 },
 680        { 1680, 1050, 60, 1 },
 681        { 1680, 1050, 60, 0 },
 682        { 1680, 1050, 75, 0 },
 683        { 1680, 1050, 85, 0 },
 684        { 1600, 1200, 60, 0 },
 685        { 1600, 1200, 65, 0 },
 686        { 1600, 1200, 70, 0 },
 687        /* byte 10 */
 688        { 1600, 1200, 75, 0 },
 689        { 1600, 1200, 85, 0 },
 690        { 1792, 1344, 60, 0 },
 691        { 1792, 1344, 75, 0 },
 692        { 1856, 1392, 60, 0 },
 693        { 1856, 1392, 75, 0 },
 694        { 1920, 1200, 60, 1 },
 695        { 1920, 1200, 60, 0 },
 696        /* byte 11 */
 697        { 1920, 1200, 75, 0 },
 698        { 1920, 1200, 85, 0 },
 699        { 1920, 1440, 60, 0 },
 700        { 1920, 1440, 75, 0 },
 701};
 702
 703static const struct minimode extra_modes[] = {
 704        { 1024, 576,  60, 0 },
 705        { 1366, 768,  60, 0 },
 706        { 1600, 900,  60, 0 },
 707        { 1680, 945,  60, 0 },
 708        { 1920, 1080, 60, 0 },
 709        { 2048, 1152, 60, 0 },
 710        { 2048, 1536, 60, 0 },
 711};
 712
 713/*
 714 * From CEA/CTA-861 spec.
 715 *
 716 * Do not access directly, instead always use cea_mode_for_vic().
 717 */
 718static const struct drm_display_mode edid_cea_modes_1[] = {
 719        /* 1 - 640x480@60Hz 4:3 */
 720        { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
 721                   752, 800, 0, 480, 490, 492, 525, 0,
 722                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 723          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 724        /* 2 - 720x480@60Hz 4:3 */
 725        { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
 726                   798, 858, 0, 480, 489, 495, 525, 0,
 727                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 728          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 729        /* 3 - 720x480@60Hz 16:9 */
 730        { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
 731                   798, 858, 0, 480, 489, 495, 525, 0,
 732                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 733          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 734        /* 4 - 1280x720@60Hz 16:9 */
 735        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
 736                   1430, 1650, 0, 720, 725, 730, 750, 0,
 737                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 738          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 739        /* 5 - 1920x1080i@60Hz 16:9 */
 740        { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
 741                   2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
 742                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
 743                   DRM_MODE_FLAG_INTERLACE),
 744          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 745        /* 6 - 720(1440)x480i@60Hz 4:3 */
 746        { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
 747                   801, 858, 0, 480, 488, 494, 525, 0,
 748                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 749                   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 750          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 751        /* 7 - 720(1440)x480i@60Hz 16:9 */
 752        { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
 753                   801, 858, 0, 480, 488, 494, 525, 0,
 754                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 755                   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 756          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 757        /* 8 - 720(1440)x240@60Hz 4:3 */
 758        { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
 759                   801, 858, 0, 240, 244, 247, 262, 0,
 760                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 761                   DRM_MODE_FLAG_DBLCLK),
 762          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 763        /* 9 - 720(1440)x240@60Hz 16:9 */
 764        { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
 765                   801, 858, 0, 240, 244, 247, 262, 0,
 766                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 767                   DRM_MODE_FLAG_DBLCLK),
 768          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 769        /* 10 - 2880x480i@60Hz 4:3 */
 770        { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
 771                   3204, 3432, 0, 480, 488, 494, 525, 0,
 772                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 773                   DRM_MODE_FLAG_INTERLACE),
 774          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 775        /* 11 - 2880x480i@60Hz 16:9 */
 776        { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
 777                   3204, 3432, 0, 480, 488, 494, 525, 0,
 778                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 779                   DRM_MODE_FLAG_INTERLACE),
 780          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 781        /* 12 - 2880x240@60Hz 4:3 */
 782        { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
 783                   3204, 3432, 0, 240, 244, 247, 262, 0,
 784                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 785          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 786        /* 13 - 2880x240@60Hz 16:9 */
 787        { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
 788                   3204, 3432, 0, 240, 244, 247, 262, 0,
 789                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 790          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 791        /* 14 - 1440x480@60Hz 4:3 */
 792        { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
 793                   1596, 1716, 0, 480, 489, 495, 525, 0,
 794                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 795          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 796        /* 15 - 1440x480@60Hz 16:9 */
 797        { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
 798                   1596, 1716, 0, 480, 489, 495, 525, 0,
 799                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 800          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 801        /* 16 - 1920x1080@60Hz 16:9 */
 802        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
 803                   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
 804                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 805          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 806        /* 17 - 720x576@50Hz 4:3 */
 807        { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
 808                   796, 864, 0, 576, 581, 586, 625, 0,
 809                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 810          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 811        /* 18 - 720x576@50Hz 16:9 */
 812        { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
 813                   796, 864, 0, 576, 581, 586, 625, 0,
 814                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 815          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 816        /* 19 - 1280x720@50Hz 16:9 */
 817        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
 818                   1760, 1980, 0, 720, 725, 730, 750, 0,
 819                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 820          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 821        /* 20 - 1920x1080i@50Hz 16:9 */
 822        { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
 823                   2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
 824                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
 825                   DRM_MODE_FLAG_INTERLACE),
 826          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 827        /* 21 - 720(1440)x576i@50Hz 4:3 */
 828        { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
 829                   795, 864, 0, 576, 580, 586, 625, 0,
 830                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 831                   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 832          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 833        /* 22 - 720(1440)x576i@50Hz 16:9 */
 834        { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
 835                   795, 864, 0, 576, 580, 586, 625, 0,
 836                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 837                   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 838          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 839        /* 23 - 720(1440)x288@50Hz 4:3 */
 840        { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
 841                   795, 864, 0, 288, 290, 293, 312, 0,
 842                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 843                   DRM_MODE_FLAG_DBLCLK),
 844          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 845        /* 24 - 720(1440)x288@50Hz 16:9 */
 846        { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
 847                   795, 864, 0, 288, 290, 293, 312, 0,
 848                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 849                   DRM_MODE_FLAG_DBLCLK),
 850          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 851        /* 25 - 2880x576i@50Hz 4:3 */
 852        { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
 853                   3180, 3456, 0, 576, 580, 586, 625, 0,
 854                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 855                   DRM_MODE_FLAG_INTERLACE),
 856          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 857        /* 26 - 2880x576i@50Hz 16:9 */
 858        { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
 859                   3180, 3456, 0, 576, 580, 586, 625, 0,
 860                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 861                   DRM_MODE_FLAG_INTERLACE),
 862          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 863        /* 27 - 2880x288@50Hz 4:3 */
 864        { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
 865                   3180, 3456, 0, 288, 290, 293, 312, 0,
 866                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 867          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 868        /* 28 - 2880x288@50Hz 16:9 */
 869        { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
 870                   3180, 3456, 0, 288, 290, 293, 312, 0,
 871                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 872          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 873        /* 29 - 1440x576@50Hz 4:3 */
 874        { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
 875                   1592, 1728, 0, 576, 581, 586, 625, 0,
 876                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 877          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 878        /* 30 - 1440x576@50Hz 16:9 */
 879        { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
 880                   1592, 1728, 0, 576, 581, 586, 625, 0,
 881                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 882          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 883        /* 31 - 1920x1080@50Hz 16:9 */
 884        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
 885                   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
 886                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 887          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 888        /* 32 - 1920x1080@24Hz 16:9 */
 889        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
 890                   2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
 891                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 892          .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 893        /* 33 - 1920x1080@25Hz 16:9 */
 894        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
 895                   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
 896                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 897          .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 898        /* 34 - 1920x1080@30Hz 16:9 */
 899        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
 900                   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
 901                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 902          .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 903        /* 35 - 2880x480@60Hz 4:3 */
 904        { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
 905                   3192, 3432, 0, 480, 489, 495, 525, 0,
 906                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 907          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 908        /* 36 - 2880x480@60Hz 16:9 */
 909        { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
 910                   3192, 3432, 0, 480, 489, 495, 525, 0,
 911                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 912          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 913        /* 37 - 2880x576@50Hz 4:3 */
 914        { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
 915                   3184, 3456, 0, 576, 581, 586, 625, 0,
 916                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 917          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 918        /* 38 - 2880x576@50Hz 16:9 */
 919        { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
 920                   3184, 3456, 0, 576, 581, 586, 625, 0,
 921                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 922          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 923        /* 39 - 1920x1080i@50Hz 16:9 */
 924        { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
 925                   2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
 926                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
 927                   DRM_MODE_FLAG_INTERLACE),
 928          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 929        /* 40 - 1920x1080i@100Hz 16:9 */
 930        { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
 931                   2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
 932                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
 933                   DRM_MODE_FLAG_INTERLACE),
 934          .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 935        /* 41 - 1280x720@100Hz 16:9 */
 936        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
 937                   1760, 1980, 0, 720, 725, 730, 750, 0,
 938                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 939          .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 940        /* 42 - 720x576@100Hz 4:3 */
 941        { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
 942                   796, 864, 0, 576, 581, 586, 625, 0,
 943                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 944          .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 945        /* 43 - 720x576@100Hz 16:9 */
 946        { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
 947                   796, 864, 0, 576, 581, 586, 625, 0,
 948                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 949          .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 950        /* 44 - 720(1440)x576i@100Hz 4:3 */
 951        { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
 952                   795, 864, 0, 576, 580, 586, 625, 0,
 953                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 954                   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 955          .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 956        /* 45 - 720(1440)x576i@100Hz 16:9 */
 957        { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
 958                   795, 864, 0, 576, 580, 586, 625, 0,
 959                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 960                   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 961          .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 962        /* 46 - 1920x1080i@120Hz 16:9 */
 963        { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
 964                   2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
 965                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
 966                   DRM_MODE_FLAG_INTERLACE),
 967          .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 968        /* 47 - 1280x720@120Hz 16:9 */
 969        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
 970                   1430, 1650, 0, 720, 725, 730, 750, 0,
 971                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 972          .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 973        /* 48 - 720x480@120Hz 4:3 */
 974        { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
 975                   798, 858, 0, 480, 489, 495, 525, 0,
 976                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 977          .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 978        /* 49 - 720x480@120Hz 16:9 */
 979        { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
 980                   798, 858, 0, 480, 489, 495, 525, 0,
 981                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 982          .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 983        /* 50 - 720(1440)x480i@120Hz 4:3 */
 984        { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
 985                   801, 858, 0, 480, 488, 494, 525, 0,
 986                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 987                   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 988          .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 989        /* 51 - 720(1440)x480i@120Hz 16:9 */
 990        { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
 991                   801, 858, 0, 480, 488, 494, 525, 0,
 992                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 993                   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 994          .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 995        /* 52 - 720x576@200Hz 4:3 */
 996        { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
 997                   796, 864, 0, 576, 581, 586, 625, 0,
 998                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 999          .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1000        /* 53 - 720x576@200Hz 16:9 */

1001        { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1002                   796, 864, 0, 576, 581, 586, 625, 0,
1003                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1004          .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1005        /* 54 - 720(1440)x576i@200Hz 4:3 */
1006        { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1007                   795, 864, 0, 576, 580, 586, 625, 0,
1008                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1009                   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1010          .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1011        /* 55 - 720(1440)x576i@200Hz 16:9 */
1012        { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1013                   795, 864, 0, 576, 580, 586, 625, 0,
1014                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1015                   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1016          .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1017        /* 56 - 720x480@240Hz 4:3 */
1018        { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1019                   798, 858, 0, 480, 489, 495, 525, 0,
1020                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1021          .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1022        /* 57 - 720x480@240Hz 16:9 */
1023        { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1024                   798, 858, 0, 480, 489, 495, 525, 0,
1025                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1026          .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1027        /* 58 - 720(1440)x480i@240Hz 4:3 */
1028        { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1029                   801, 858, 0, 480, 488, 494, 525, 0,
1030                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1031                   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1032          .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1033        /* 59 - 720(1440)x480i@240Hz 16:9 */
1034        { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1035                   801, 858, 0, 480, 488, 494, 525, 0,
1036                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1037                   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1038          .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1039        /* 60 - 1280x720@24Hz 16:9 */
1040        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1041                   3080, 3300, 0, 720, 725, 730, 750, 0,
1042                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1043          .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1044        /* 61 - 1280x720@25Hz 16:9 */
1045        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1046                   3740, 3960, 0, 720, 725, 730, 750, 0,
1047                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1048          .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1049        /* 62 - 1280x720@30Hz 16:9 */
1050        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1051                   3080, 3300, 0, 720, 725, 730, 750, 0,
1052                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1053          .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1054        /* 63 - 1920x1080@120Hz 16:9 */
1055        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1056                   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1057                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1058          .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1059        /* 64 - 1920x1080@100Hz 16:9 */
1060        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1061                   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1062                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1063          .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1064        /* 65 - 1280x720@24Hz 64:27 */
1065        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1066                   3080, 3300, 0, 720, 725, 730, 750, 0,
1067                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1068          .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1069        /* 66 - 1280x720@25Hz 64:27 */
1070        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1071                   3740, 3960, 0, 720, 725, 730, 750, 0,
1072                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1073          .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1074        /* 67 - 1280x720@30Hz 64:27 */
1075        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1076                   3080, 3300, 0, 720, 725, 730, 750, 0,
1077                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1078          .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1079        /* 68 - 1280x720@50Hz 64:27 */
1080        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1081                   1760, 1980, 0, 720, 725, 730, 750, 0,
1082                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1083          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1084        /* 69 - 1280x720@60Hz 64:27 */
1085        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1086                   1430, 1650, 0, 720, 725, 730, 750, 0,
1087                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1088          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1089        /* 70 - 1280x720@100Hz 64:27 */
1090        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1091                   1760, 1980, 0, 720, 725, 730, 750, 0,
1092                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1093          .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1094        /* 71 - 1280x720@120Hz 64:27 */
1095        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1096                   1430, 1650, 0, 720, 725, 730, 750, 0,
1097                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1098          .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1099        /* 72 - 1920x1080@24Hz 64:27 */
1100        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1101                   2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1102                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1103          .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1104        /* 73 - 1920x1080@25Hz 64:27 */
1105        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1106                   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1107                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1108          .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1109        /* 74 - 1920x1080@30Hz 64:27 */
1110        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1111                   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1112                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1113          .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1114        /* 75 - 1920x1080@50Hz 64:27 */
1115        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1116                   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1117                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1118          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1119        /* 76 - 1920x1080@60Hz 64:27 */
1120        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1121                   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1122                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1123          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1124        /* 77 - 1920x1080@100Hz 64:27 */
1125        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1126                   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1127                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1128          .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1129        /* 78 - 1920x1080@120Hz 64:27 */
1130        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1131                   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1132                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1133          .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1134        /* 79 - 1680x720@24Hz 64:27 */
1135        { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1136                   3080, 3300, 0, 720, 725, 730, 750, 0,
1137                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1138          .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1139        /* 80 - 1680x720@25Hz 64:27 */
1140        { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1141                   2948, 3168, 0, 720, 725, 730, 750, 0,
1142                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1143          .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1144        /* 81 - 1680x720@30Hz 64:27 */
1145        { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1146                   2420, 2640, 0, 720, 725, 730, 750, 0,
1147                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1148          .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1149        /* 82 - 1680x720@50Hz 64:27 */
1150        { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1151                   1980, 2200, 0, 720, 725, 730, 750, 0,
1152                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1153          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1154        /* 83 - 1680x720@60Hz 64:27 */
1155        { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1156                   1980, 2200, 0, 720, 725, 730, 750, 0,
1157                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1158          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1159        /* 84 - 1680x720@100Hz 64:27 */
1160        { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1161                   1780, 2000, 0, 720, 725, 730, 825, 0,
1162                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1163          .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1164        /* 85 - 1680x720@120Hz 64:27 */
1165        { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1166                   1780, 2000, 0, 720, 725, 730, 825, 0,
1167                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1168          .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1169        /* 86 - 2560x1080@24Hz 64:27 */
1170        { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1171                   3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1172                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1173          .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1174        /* 87 - 2560x1080@25Hz 64:27 */
1175        { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1176                   3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1177                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1178          .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1179        /* 88 - 2560x1080@30Hz 64:27 */
1180        { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1181                   3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1182                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1183          .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1184        /* 89 - 2560x1080@50Hz 64:27 */
1185        { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1186                   3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1187                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1188          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1189        /* 90 - 2560x1080@60Hz 64:27 */
1190        { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1191                   2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1192                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1193          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1194        /* 91 - 2560x1080@100Hz 64:27 */
1195        { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1196                   2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1197                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1198          .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1199        /* 92 - 2560x1080@120Hz 64:27 */
1200        { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1201                   3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1202                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1203          .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1204        /* 93 - 3840x2160@24Hz 16:9 */
1205        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1206                   5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1207                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1208          .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1209        /* 94 - 3840x2160@25Hz 16:9 */
1210        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1211                   4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1212                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1213          .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1214        /* 95 - 3840x2160@30Hz 16:9 */
1215        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1216                   4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1217                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1218          .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1219        /* 96 - 3840x2160@50Hz 16:9 */
1220        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1221                   4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1222                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1223          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1224        /* 97 - 3840x2160@60Hz 16:9 */
1225        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1226                   4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1227                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1228          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1229        /* 98 - 4096x2160@24Hz 256:135 */
1230        { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1231                   5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1232                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1233          .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1234        /* 99 - 4096x2160@25Hz 256:135 */
1235        { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1236                   5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1237                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1238          .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1239        /* 100 - 4096x2160@30Hz 256:135 */
1240        { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1241                   4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1242                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1243          .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1244        /* 101 - 4096x2160@50Hz 256:135 */
1245        { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1246                   5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1247                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1248          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1249        /* 102 - 4096x2160@60Hz 256:135 */
1250        { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1251                   4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1252                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1253          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1254        /* 103 - 3840x2160@24Hz 64:27 */
1255        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1256                   5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1257                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1258          .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1259        /* 104 - 3840x2160@25Hz 64:27 */
1260        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1261                   4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1262                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1263          .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1264        /* 105 - 3840x2160@30Hz 64:27 */
1265        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1266                   4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1267                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1268          .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1269        /* 106 - 3840x2160@50Hz 64:27 */
1270        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1271                   4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1272                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1273          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1274        /* 107 - 3840x2160@60Hz 64:27 */
1275        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1276                   4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1277                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1278          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1279        /* 108 - 1280x720@48Hz 16:9 */
1280        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1281                   2280, 2500, 0, 720, 725, 730, 750, 0,
1282                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1283          .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1284        /* 109 - 1280x720@48Hz 64:27 */
1285        { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1286                   2280, 2500, 0, 720, 725, 730, 750, 0,
1287                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1288          .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1289        /* 110 - 1680x720@48Hz 64:27 */
1290        { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1291                   2530, 2750, 0, 720, 725, 730, 750, 0,
1292                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1293          .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1294        /* 111 - 1920x1080@48Hz 16:9 */
1295        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1296                   2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1297                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1298          .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1299        /* 112 - 1920x1080@48Hz 64:27 */
1300        { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1301                   2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1302                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1303          .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1304        /* 113 - 2560x1080@48Hz 64:27 */
1305        { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1306                   3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1307                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1308          .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1309        /* 114 - 3840x2160@48Hz 16:9 */
1310        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1311                   5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1312                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1313          .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1314        /* 115 - 4096x2160@48Hz 256:135 */
1315        { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1316                   5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1317                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1318          .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1319        /* 116 - 3840x2160@48Hz 64:27 */
1320        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1321                   5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1322                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1323          .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1324        /* 117 - 3840x2160@100Hz 16:9 */
1325        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1326                   4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1327                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1328          .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1329        /* 118 - 3840x2160@120Hz 16:9 */
1330        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1331                   4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1332                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1333          .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1334        /* 119 - 3840x2160@100Hz 64:27 */
1335        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1336                   4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1337                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1338          .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1339        /* 120 - 3840x2160@120Hz 64:27 */
1340        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1341                   4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1342                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1343          .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1344        /* 121 - 5120x2160@24Hz 64:27 */
1345        { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1346                   7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1347                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1348          .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1349        /* 122 - 5120x2160@25Hz 64:27 */
1350        { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1351                   6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1352                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1353          .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1354        /* 123 - 5120x2160@30Hz 64:27 */
1355        { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1356                   5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1357                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1358          .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1359        /* 124 - 5120x2160@48Hz 64:27 */
1360        { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1361                   5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1362                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1363          .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1364        /* 125 - 5120x2160@50Hz 64:27 */
1365        { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1366                   6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1367                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1368          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1369        /* 126 - 5120x2160@60Hz 64:27 */
1370        { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1371                   5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1372                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1373          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1374        /* 127 - 5120x2160@100Hz 64:27 */
1375        { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1376                   6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1377                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1378          .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1379};
1380
1381/*
1382 * From CEA/CTA-861 spec.
1383 *
1384 * Do not access directly, instead always use cea_mode_for_vic().
1385 */
1386static const struct drm_display_mode edid_cea_modes_193[] = {
1387        /* 193 - 5120x2160@120Hz 64:27 */
1388        { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1389                   5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1390                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1391          .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1392        /* 194 - 7680x4320@24Hz 16:9 */
1393        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1394                   10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1395                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1396          .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1397        /* 195 - 7680x4320@25Hz 16:9 */
1398        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1399                   10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1400                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1401          .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1402        /* 196 - 7680x4320@30Hz 16:9 */
1403        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1404                   8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1405                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1406          .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1407        /* 197 - 7680x4320@48Hz 16:9 */
1408        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1409                   10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1410                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1411          .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1412        /* 198 - 7680x4320@50Hz 16:9 */
1413        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1414                   10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1415                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1416          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1417        /* 199 - 7680x4320@60Hz 16:9 */
1418        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1419                   8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1420                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1421          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1422        /* 200 - 7680x4320@100Hz 16:9 */
1423        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1424                   9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1425                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1426          .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1427        /* 201 - 7680x4320@120Hz 16:9 */
1428        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1429                   8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1430                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1431          .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1432        /* 202 - 7680x4320@24Hz 64:27 */
1433        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1434                   10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1435                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1436          .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1437        /* 203 - 7680x4320@25Hz 64:27 */
1438        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1439                   10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1440                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1441          .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1442        /* 204 - 7680x4320@30Hz 64:27 */
1443        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1444                   8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1445                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1446          .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1447        /* 205 - 7680x4320@48Hz 64:27 */
1448        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1449                   10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1450                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1451          .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1452        /* 206 - 7680x4320@50Hz 64:27 */
1453        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1454                   10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1455                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1456          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1457        /* 207 - 7680x4320@60Hz 64:27 */
1458        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1459                   8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1460                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1461          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1462        /* 208 - 7680x4320@100Hz 64:27 */
1463        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1464                   9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1465                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1466          .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1467        /* 209 - 7680x4320@120Hz 64:27 */
1468        { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1469                   8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1470                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1471          .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1472        /* 210 - 10240x4320@24Hz 64:27 */
1473        { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1474                   11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1475                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1476          .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1477        /* 211 - 10240x4320@25Hz 64:27 */
1478        { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1479                   12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1480                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1481          .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1482        /* 212 - 10240x4320@30Hz 64:27 */
1483        { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1484                   10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1485                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1486          .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1487        /* 213 - 10240x4320@48Hz 64:27 */
1488        { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1489                   11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1490                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1491          .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1492        /* 214 - 10240x4320@50Hz 64:27 */
1493        { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1494                   12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1495                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1496          .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1497        /* 215 - 10240x4320@60Hz 64:27 */
1498        { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1499                   10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1500                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1501          .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1502        /* 216 - 10240x4320@100Hz 64:27 */
1503        { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1504                   12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1505                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1506          .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1507        /* 217 - 10240x4320@120Hz 64:27 */
1508        { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1509                   10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1510                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1511          .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1512        /* 218 - 4096x2160@100Hz 256:135 */
1513        { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1514                   4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1515                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1516          .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1517        /* 219 - 4096x2160@120Hz 256:135 */
1518        { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1519                   4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1520                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1521          .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1522};
1523
1524/*
1525 * HDMI 1.4 4k modes. Index using the VIC.
1526 */
1527static const struct drm_display_mode edid_4k_modes[] = {
1528        /* 0 - dummy, VICs start at 1 */
1529        { },
1530        /* 1 - 3840x2160@30Hz */
1531        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1532                   3840, 4016, 4104, 4400, 0,
1533                   2160, 2168, 2178, 2250, 0,
1534                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1535          .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1536        /* 2 - 3840x2160@25Hz */
1537        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1538                   3840, 4896, 4984, 5280, 0,
1539                   2160, 2168, 2178, 2250, 0,
1540                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1541          .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1542        /* 3 - 3840x2160@24Hz */
1543        { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1544                   3840, 5116, 5204, 5500, 0,
1545                   2160, 2168, 2178, 2250, 0,
1546                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1547          .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1548        /* 4 - 4096x2160@24Hz (SMPTE) */
1549        { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1550                   4096, 5116, 5204, 5500, 0,
1551                   2160, 2168, 2178, 2250, 0,
1552                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1553          .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1554};
1555
1556/*** DDC fetch and block validation ***/
1557
1558static const u8 edid_header[] = {
1559        0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1560};
1561
1562/**
1563 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1564 * @raw_edid: pointer to raw base EDID block
1565 *
1566 * Sanity check the header of the base EDID block.
1567 *
1568 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1569 */
1570int drm_edid_header_is_valid(const u8 *raw_edid)
1571{
1572        int i, score = 0;
1573
1574        for (i = 0; i < sizeof(edid_header); i++)
1575                if (raw_edid[i] == edid_header[i])
1576                        score++;
1577
1578        return score;
1579}
1580EXPORT_SYMBOL(drm_edid_header_is_valid);
1581
1582static int edid_fixup __read_mostly = 6;
1583module_param_named(edid_fixup, edid_fixup, int, 0400);
1584MODULE_PARM_DESC(edid_fixup,
1585                 "Minimum number of valid EDID header bytes (0-8, default 6)");
1586
1587static void drm_get_displayid(struct drm_connector *connector,
1588                              struct edid *edid);
1589static int validate_displayid(u8 *displayid, int length, int idx);
1590
1591static int drm_edid_block_checksum(const u8 *raw_edid)
1592{
1593        int i;
1594        u8 csum = 0;
1595        for (i = 0; i < EDID_LENGTH; i++)
1596                csum += raw_edid[i];
1597
1598        return csum;
1599}
1600
1601static bool drm_edid_is_zero(const u8 *in_edid, int length)
1602{
1603        if (memchr_inv(in_edid, 0, length))
1604                return false;
1605
1606        return true;
1607}
1608
1609/**
1610 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1611 * @raw_edid: pointer to raw EDID block
1612 * @block: type of block to validate (0 for base, extension otherwise)
1613 * @print_bad_edid: if true, dump bad EDID blocks to the console
1614 * @edid_corrupt: if true, the header or checksum is invalid
1615 *
1616 * Validate a base or extension EDID block and optionally dump bad blocks to
1617 * the console.
1618 *
1619 * Return: True if the block is valid, false otherwise.
1620 */
1621bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1622                          bool *edid_corrupt)
1623{
1624        u8 csum;
1625        struct edid *edid = (struct edid *)raw_edid;
1626
1627        if (WARN_ON(!raw_edid))
1628                return false;
1629
1630        if (edid_fixup > 8 || edid_fixup < 0)
1631                edid_fixup = 6;
1632
1633        if (block == 0) {
1634                int score = drm_edid_header_is_valid(raw_edid);
1635                if (score == 8) {
1636                        if (edid_corrupt)
1637                                *edid_corrupt = false;
1638                } else if (score >= edid_fixup) {
1639                        /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1640                         * The corrupt flag needs to be set here otherwise, the
1641                         * fix-up code here will correct the problem, the
1642                         * checksum is correct and the test fails
1643                         */
1644                        if (edid_corrupt)
1645                                *edid_corrupt = true;
1646                        DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1647                        memcpy(raw_edid, edid_header, sizeof(edid_header));
1648                } else {
1649                        if (edid_corrupt)
1650                                *edid_corrupt = true;
1651                        goto bad;
1652                }
1653        }
1654
1655        csum = drm_edid_block_checksum(raw_edid);
1656        if (csum) {
1657                if (edid_corrupt)
1658                        *edid_corrupt = true;
1659
1660                /* allow CEA to slide through, switches mangle this */
1661                if (raw_edid[0] == CEA_EXT) {
1662                        DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1663                        DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1664                } else {
1665                        if (print_bad_edid)
1666                                DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1667
1668                        goto bad;
1669                }
1670        }
1671
1672        /* per-block-type checks */
1673        switch (raw_edid[0]) {
1674        case 0: /* base */
1675                if (edid->version != 1) {
1676                        DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1677                        goto bad;
1678                }
1679
1680                if (edid->revision > 4)
1681                        DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1682                break;
1683
1684        default:
1685                break;
1686        }
1687
1688        return true;
1689
1690bad:
1691        if (print_bad_edid) {
1692                if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1693                        pr_notice("EDID block is all zeroes\n");
1694                } else {
1695                        pr_notice("Raw EDID:\n");
1696                        print_hex_dump(KERN_NOTICE,
1697                                       " \t", DUMP_PREFIX_NONE, 16, 1,
1698                                       raw_edid, EDID_LENGTH, false);
1699                }
1700        }
1701        return false;
1702}
1703EXPORT_SYMBOL(drm_edid_block_valid);
1704
1705/**
1706 * drm_edid_is_valid - sanity check EDID data
1707 * @edid: EDID data
1708 *
1709 * Sanity-check an entire EDID record (including extensions)
1710 *
1711 * Return: True if the EDID data is valid, false otherwise.
1712 */
1713bool drm_edid_is_valid(struct edid *edid)
1714{
1715        int i;
1716        u8 *raw = (u8 *)edid;
1717
1718        if (!edid)
1719                return false;
1720
1721        for (i = 0; i <= edid->extensions; i++)
1722                if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1723                        return false;
1724
1725        return true;
1726}
1727EXPORT_SYMBOL(drm_edid_is_valid);
1728
1729#define DDC_SEGMENT_ADDR 0x30
1730/**
1731 * drm_do_probe_ddc_edid() - get EDID information via I2C
1732 * @data: I2C device adapter
1733 * @buf: EDID data buffer to be filled
1734 * @block: 128 byte EDID block to start fetching from
1735 * @len: EDID data buffer length to fetch
1736 *
1737 * Try to fetch EDID information by calling I2C driver functions.
1738 *
1739 * Return: 0 on success or -1 on failure.
1740 */
1741static int
1742drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1743{
1744        struct i2c_adapter *adapter = data;
1745        unsigned char start = block * EDID_LENGTH;
1746        unsigned char segment = block >> 1;
1747        unsigned char xfers = segment ? 3 : 2;
1748        int ret, retries = 5;
1749
1750        /*
1751         * The core I2C driver will automatically retry the transfer if the
1752         * adapter reports EAGAIN. However, we find that bit-banging transfers
1753         * are susceptible to errors under a heavily loaded machine and
1754         * generate spurious NAKs and timeouts. Retrying the transfer
1755         * of the individual block a few times seems to overcome this.
1756         */
1757        do {
1758                struct i2c_msg msgs[] = {
1759                        {
1760                                .addr   = DDC_SEGMENT_ADDR,
1761                                .flags  = 0,
1762                                .len    = 1,
1763                                .buf    = &segment,
1764                        }, {
1765                                .addr   = DDC_ADDR,
1766                                .flags  = 0,
1767                                .len    = 1,
1768                                .buf    = &start,
1769                        }, {
1770                                .addr   = DDC_ADDR,
1771                                .flags  = I2C_M_RD,
1772                                .len    = len,
1773                                .buf    = buf,
1774                        }
1775                };
1776
1777                /*
1778                 * Avoid sending the segment addr to not upset non-compliant
1779                 * DDC monitors.
1780                 */
1781                ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1782
1783                if (ret == -ENXIO) {
1784                        DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1785                                        adapter->name);
1786                        break;
1787                }
1788        } while (ret != xfers && --retries);
1789
1790        return ret == xfers ? 0 : -1;
1791}
1792
1793static void connector_bad_edid(struct drm_connector *connector,
1794                               u8 *edid, int num_blocks)
1795{
1796        int i;
1797
1798        if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
1799                return;
1800
1801        dev_warn(connector->dev->dev,
1802                 "%s: EDID is invalid:\n",
1803                 connector->name);
1804        for (i = 0; i < num_blocks; i++) {
1805                u8 *block = edid + i * EDID_LENGTH;
1806                char prefix[20];
1807
1808                if (drm_edid_is_zero(block, EDID_LENGTH))
1809                        sprintf(prefix, "\t[%02x] ZERO ", i);
1810                else if (!drm_edid_block_valid(block, i, false, NULL))
1811                        sprintf(prefix, "\t[%02x] BAD  ", i);
1812                else
1813                        sprintf(prefix, "\t[%02x] GOOD ", i);
1814
1815                print_hex_dump(KERN_WARNING,
1816                               prefix, DUMP_PREFIX_NONE, 16, 1,
1817                               block, EDID_LENGTH, false);
1818        }
1819}
1820
1821/* Get override or firmware EDID */
1822static struct edid *drm_get_override_edid(struct drm_connector *connector)
1823{
1824        struct edid *override = NULL;
1825
1826        if (connector->override_edid)
1827                override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1828
1829        if (!override)
1830                override = drm_load_edid_firmware(connector);
1831
1832        return IS_ERR(override) ? NULL : override;
1833}
1834
1835/**
1836 * drm_add_override_edid_modes - add modes from override/firmware EDID
1837 * @connector: connector we're probing
1838 *
1839 * Add modes from the override/firmware EDID, if available. Only to be used from
1840 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
1841 * failed during drm_get_edid() and caused the override/firmware EDID to be
1842 * skipped.
1843 *
1844 * Return: The number of modes added or 0 if we couldn't find any.
1845 */
1846int drm_add_override_edid_modes(struct drm_connector *connector)
1847{
1848        struct edid *override;
1849        int num_modes = 0;
1850
1851        override = drm_get_override_edid(connector);
1852        if (override) {
1853                drm_connector_update_edid_property(connector, override);
1854                num_modes = drm_add_edid_modes(connector, override);
1855                kfree(override);
1856
1857                DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
1858                              connector->base.id, connector->name, num_modes);
1859        }
1860
1861        return num_modes;
1862}
1863EXPORT_SYMBOL(drm_add_override_edid_modes);
1864
1865/**
1866 * drm_do_get_edid - get EDID data using a custom EDID block read function
1867 * @connector: connector we're probing
1868 * @get_edid_block: EDID block read function
1869 * @data: private data passed to the block read function
1870 *
1871 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1872 * exposes a different interface to read EDID blocks this function can be used
1873 * to get EDID data using a custom block read function.
1874 *
1875 * As in the general case the DDC bus is accessible by the kernel at the I2C
1876 * level, drivers must make all reasonable efforts to expose it as an I2C
1877 * adapter and use drm_get_edid() instead of abusing this function.
1878 *
1879 * The EDID may be overridden using debugfs override_edid or firmare EDID
1880 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1881 * order. Having either of them bypasses actual EDID reads.
1882 *
1883 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1884 */
1885struct edid *drm_do_get_edid(struct drm_connector *connector,
1886        int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1887                              size_t len),
1888        void *data)
1889{
1890        int i, j = 0, valid_extensions = 0;
1891        u8 *edid, *new;
1892        struct edid *override;
1893
1894        override = drm_get_override_edid(connector);
1895        if (override)
1896                return override;
1897
1898        if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1899                return NULL;
1900
1901        /* base block fetch */
1902        for (i = 0; i < 4; i++) {
1903                if (get_edid_block(data, edid, 0, EDID_LENGTH))
1904                        goto out;
1905                if (drm_edid_block_valid(edid, 0, false,
1906                                         &connector->edid_corrupt))
1907                        break;
1908                if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1909                        connector->null_edid_counter++;
1910                        goto carp;
1911                }
1912        }
1913        if (i == 4)
1914                goto carp;
1915
1916        /* if there's no extensions, we're done */
1917        valid_extensions = edid[0x7e];
1918        if (valid_extensions == 0)
1919                return (struct edid *)edid;
1920
1921        new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1922        if (!new)
1923                goto out;
1924        edid = new;
1925
1926        for (j = 1; j <= edid[0x7e]; j++) {
1927                u8 *block = edid + j * EDID_LENGTH;
1928
1929                for (i = 0; i < 4; i++) {
1930                        if (get_edid_block(data, block, j, EDID_LENGTH))
1931                                goto out;
1932                        if (drm_edid_block_valid(block, j, false, NULL))
1933                                break;
1934                }
1935
1936                if (i == 4)
1937                        valid_extensions--;
1938        }
1939
1940        if (valid_extensions != edid[0x7e]) {
1941                u8 *base;
1942
1943                connector_bad_edid(connector, edid, edid[0x7e] + 1);
1944
1945                edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1946                edid[0x7e] = valid_extensions;
1947
1948                new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
1949                                    GFP_KERNEL);
1950                if (!new)
1951                        goto out;
1952
1953                base = new;
1954                for (i = 0; i <= edid[0x7e]; i++) {
1955                        u8 *block = edid + i * EDID_LENGTH;
1956
1957                        if (!drm_edid_block_valid(block, i, false, NULL))
1958                                continue;
1959
1960                        memcpy(base, block, EDID_LENGTH);
1961                        base += EDID_LENGTH;
1962                }
1963
1964                kfree(edid);
1965                edid = new;
1966        }
1967
1968        return (struct edid *)edid;
1969
1970carp:
1971        connector_bad_edid(connector, edid, 1);
1972out:
1973        kfree(edid);
1974        return NULL;
1975}
1976EXPORT_SYMBOL_GPL(drm_do_get_edid);
1977
1978/**
1979 * drm_probe_ddc() - probe DDC presence
1980 * @adapter: I2C adapter to probe
1981 *
1982 * Return: True on success, false on failure.
1983 */
1984bool
1985drm_probe_ddc(struct i2c_adapter *adapter)
1986{
1987        unsigned char out;
1988
1989        return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1990}
1991EXPORT_SYMBOL(drm_probe_ddc);
1992
1993/**
1994 * drm_get_edid - get EDID data, if available
1995 * @connector: connector we're probing
1996 * @adapter: I2C adapter to use for DDC
1997 *
1998 * Poke the given I2C channel to grab EDID data if possible.  If found,
1999 * attach it to the connector.
2000 *

2001 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2002 */
2003struct edid *drm_get_edid(struct drm_connector *connector,
2004                          struct i2c_adapter *adapter)
2005{
2006        struct edid *edid;
2007
2008        if (connector->force == DRM_FORCE_OFF)
2009                return NULL;
2010
2011        if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2012                return NULL;
2013
2014        edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
2015        if (edid)
2016                drm_get_displayid(connector, edid);
2017        return edid;
2018}
2019EXPORT_SYMBOL(drm_get_edid);
2020
2021/**
2022 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2023 * @connector: connector we're probing
2024 * @adapter: I2C adapter to use for DDC
2025 *
2026 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2027 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2028 * switch DDC to the GPU which is retrieving EDID.
2029 *
2030 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2031 */
2032struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2033                                     struct i2c_adapter *adapter)
2034{
2035        struct pci_dev *pdev = connector->dev->pdev;
2036        struct edid *edid;
2037
2038        vga_switcheroo_lock_ddc(pdev);
2039        edid = drm_get_edid(connector, adapter);
2040        vga_switcheroo_unlock_ddc(pdev);
2041
2042        return edid;
2043}
2044EXPORT_SYMBOL(drm_get_edid_switcheroo);
2045
2046/**
2047 * drm_edid_duplicate - duplicate an EDID and the extensions
2048 * @edid: EDID to duplicate
2049 *
2050 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2051 */
2052struct edid *drm_edid_duplicate(const struct edid *edid)
2053{
2054        return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
2055}
2056EXPORT_SYMBOL(drm_edid_duplicate);
2057
2058/*** EDID parsing ***/
2059
2060/**
2061 * edid_vendor - match a string against EDID's obfuscated vendor field
2062 * @edid: EDID to match
2063 * @vendor: vendor string
2064 *
2065 * Returns true if @vendor is in @edid, false otherwise
2066 */
2067static bool edid_vendor(const struct edid *edid, const char *vendor)
2068{
2069        char edid_vendor[3];
2070
2071        edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
2072        edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
2073                          ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
2074        edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
2075
2076        return !strncmp(edid_vendor, vendor, 3);
2077}
2078
2079/**
2080 * edid_get_quirks - return quirk flags for a given EDID
2081 * @edid: EDID to process
2082 *
2083 * This tells subsequent routines what fixes they need to apply.
2084 */
2085static u32 edid_get_quirks(const struct edid *edid)
2086{
2087        const struct edid_quirk *quirk;
2088        int i;
2089
2090        for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2091                quirk = &edid_quirk_list[i];
2092
2093                if (edid_vendor(edid, quirk->vendor) &&
2094                    (EDID_PRODUCT_ID(edid) == quirk->product_id))
2095                        return quirk->quirks;
2096        }
2097
2098        return 0;
2099}
2100
2101#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2102#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2103
2104/**
2105 * edid_fixup_preferred - set preferred modes based on quirk list
2106 * @connector: has mode list to fix up
2107 * @quirks: quirks list
2108 *
2109 * Walk the mode list for @connector, clearing the preferred status
2110 * on existing modes and setting it anew for the right mode ala @quirks.
2111 */
2112static void edid_fixup_preferred(struct drm_connector *connector,
2113                                 u32 quirks)
2114{
2115        struct drm_display_mode *t, *cur_mode, *preferred_mode;
2116        int target_refresh = 0;
2117        int cur_vrefresh, preferred_vrefresh;
2118
2119        if (list_empty(&connector->probed_modes))
2120                return;
2121
2122        if (quirks & EDID_QUIRK_PREFER_LARGE_60)
2123                target_refresh = 60;
2124        if (quirks & EDID_QUIRK_PREFER_LARGE_75)
2125                target_refresh = 75;
2126
2127        preferred_mode = list_first_entry(&connector->probed_modes,
2128                                          struct drm_display_mode, head);
2129
2130        list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2131                cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2132
2133                if (cur_mode == preferred_mode)
2134                        continue;
2135
2136                /* Largest mode is preferred */
2137                if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2138                        preferred_mode = cur_mode;
2139
2140                cur_vrefresh = cur_mode->vrefresh ?
2141                        cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
2142                preferred_vrefresh = preferred_mode->vrefresh ?
2143                        preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
2144                /* At a given size, try to get closest to target refresh */
2145                if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2146                    MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2147                    MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2148                        preferred_mode = cur_mode;
2149                }
2150        }
2151
2152        preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2153}
2154
2155static bool
2156mode_is_rb(const struct drm_display_mode *mode)
2157{
2158        return (mode->htotal - mode->hdisplay == 160) &&
2159               (mode->hsync_end - mode->hdisplay == 80) &&
2160               (mode->hsync_end - mode->hsync_start == 32) &&
2161               (mode->vsync_start - mode->vdisplay == 3);
2162}
2163
2164/*
2165 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2166 * @dev: Device to duplicate against
2167 * @hsize: Mode width
2168 * @vsize: Mode height
2169 * @fresh: Mode refresh rate
2170 * @rb: Mode reduced-blanking-ness
2171 *
2172 * Walk the DMT mode list looking for a match for the given parameters.
2173 *
2174 * Return: A newly allocated copy of the mode, or NULL if not found.
2175 */
2176struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
2177                                           int hsize, int vsize, int fresh,
2178                                           bool rb)
2179{
2180        int i;
2181
2182        for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2183                const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2184                if (hsize != ptr->hdisplay)
2185                        continue;
2186                if (vsize != ptr->vdisplay)
2187                        continue;
2188                if (fresh != drm_mode_vrefresh(ptr))
2189                        continue;
2190                if (rb != mode_is_rb(ptr))
2191                        continue;
2192
2193                return drm_mode_duplicate(dev, ptr);
2194        }
2195
2196        return NULL;
2197}
2198EXPORT_SYMBOL(drm_mode_find_dmt);
2199
2200typedef void detailed_cb(struct detailed_timing *timing, void *closure);
2201
2202static void
2203cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2204{
2205        int i, n = 0;
2206        u8 d = ext[0x02];
2207        u8 *det_base = ext + d;
2208
2209        n = (127 - d) / 18;
2210        for (i = 0; i < n; i++)
2211                cb((struct detailed_timing *)(det_base + 18 * i), closure);
2212}
2213
2214static void
2215vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2216{
2217        unsigned int i, n = min((int)ext[0x02], 6);
2218        u8 *det_base = ext + 5;
2219
2220        if (ext[0x01] != 1)
2221                return; /* unknown version */
2222
2223        for (i = 0; i < n; i++)
2224                cb((struct detailed_timing *)(det_base + 18 * i), closure);
2225}
2226
2227static void
2228drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
2229{
2230        int i;
2231        struct edid *edid = (struct edid *)raw_edid;
2232
2233        if (edid == NULL)
2234                return;
2235
2236        for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
2237                cb(&(edid->detailed_timings[i]), closure);
2238
2239        for (i = 1; i <= raw_edid[0x7e]; i++) {
2240                u8 *ext = raw_edid + (i * EDID_LENGTH);
2241                switch (*ext) {
2242                case CEA_EXT:
2243                        cea_for_each_detailed_block(ext, cb, closure);
2244                        break;
2245                case VTB_EXT:
2246                        vtb_for_each_detailed_block(ext, cb, closure);
2247                        break;
2248                default:
2249                        break;
2250                }
2251        }
2252}
2253
2254static void
2255is_rb(struct detailed_timing *t, void *data)
2256{
2257        u8 *r = (u8 *)t;
2258        if (r[3] == EDID_DETAIL_MONITOR_RANGE)
2259                if (r[15] & 0x10)
2260                        *(bool *)data = true;
2261}
2262
2263/* EDID 1.4 defines this explicitly.  For EDID 1.3, we guess, badly. */
2264static bool
2265drm_monitor_supports_rb(struct edid *edid)
2266{
2267        if (edid->revision >= 4) {
2268                bool ret = false;
2269                drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
2270                return ret;
2271        }
2272
2273        return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2274}
2275
2276static void
2277find_gtf2(struct detailed_timing *t, void *data)
2278{
2279        u8 *r = (u8 *)t;
2280        if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
2281                *(u8 **)data = r;
2282}
2283
2284/* Secondary GTF curve kicks in above some break frequency */
2285static int
2286drm_gtf2_hbreak(struct edid *edid)
2287{
2288        u8 *r = NULL;
2289        drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2290        return r ? (r[12] * 2) : 0;
2291}
2292
2293static int
2294drm_gtf2_2c(struct edid *edid)
2295{
2296        u8 *r = NULL;
2297        drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2298        return r ? r[13] : 0;
2299}
2300
2301static int
2302drm_gtf2_m(struct edid *edid)
2303{
2304        u8 *r = NULL;
2305        drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2306        return r ? (r[15] << 8) + r[14] : 0;
2307}
2308
2309static int
2310drm_gtf2_k(struct edid *edid)
2311{
2312        u8 *r = NULL;
2313        drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2314        return r ? r[16] : 0;
2315}
2316
2317static int
2318drm_gtf2_2j(struct edid *edid)
2319{
2320        u8 *r = NULL;
2321        drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2322        return r ? r[17] : 0;
2323}
2324
2325/**
2326 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2327 * @edid: EDID block to scan
2328 */
2329static int standard_timing_level(struct edid *edid)
2330{
2331        if (edid->revision >= 2) {
2332                if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2333                        return LEVEL_CVT;
2334                if (drm_gtf2_hbreak(edid))
2335                        return LEVEL_GTF2;
2336                if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
2337                        return LEVEL_GTF;
2338        }
2339        return LEVEL_DMT;
2340}
2341
2342/*
2343 * 0 is reserved.  The spec says 0x01 fill for unused timings.  Some old
2344 * monitors fill with ascii space (0x20) instead.
2345 */
2346static int
2347bad_std_timing(u8 a, u8 b)
2348{
2349        return (a == 0x00 && b == 0x00) ||
2350               (a == 0x01 && b == 0x01) ||
2351               (a == 0x20 && b == 0x20);
2352}
2353
2354/**
2355 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2356 * @connector: connector of for the EDID block
2357 * @edid: EDID block to scan
2358 * @t: standard timing params
2359 *
2360 * Take the standard timing params (in this case width, aspect, and refresh)
2361 * and convert them into a real mode using CVT/GTF/DMT.
2362 */
2363static struct drm_display_mode *
2364drm_mode_std(struct drm_connector *connector, struct edid *edid,
2365             struct std_timing *t)
2366{
2367        struct drm_device *dev = connector->dev;
2368        struct drm_display_mode *m, *mode = NULL;
2369        int hsize, vsize;
2370        int vrefresh_rate;
2371        unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2372                >> EDID_TIMING_ASPECT_SHIFT;
2373        unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2374                >> EDID_TIMING_VFREQ_SHIFT;
2375        int timing_level = standard_timing_level(edid);
2376
2377        if (bad_std_timing(t->hsize, t->vfreq_aspect))
2378                return NULL;
2379
2380        /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2381        hsize = t->hsize * 8 + 248;
2382        /* vrefresh_rate = vfreq + 60 */
2383        vrefresh_rate = vfreq + 60;
2384        /* the vdisplay is calculated based on the aspect ratio */
2385        if (aspect_ratio == 0) {
2386                if (edid->revision < 3)
2387                        vsize = hsize;
2388                else
2389                        vsize = (hsize * 10) / 16;
2390        } else if (aspect_ratio == 1)
2391                vsize = (hsize * 3) / 4;
2392        else if (aspect_ratio == 2)
2393                vsize = (hsize * 4) / 5;
2394        else
2395                vsize = (hsize * 9) / 16;
2396
2397        /* HDTV hack, part 1 */
2398        if (vrefresh_rate == 60 &&
2399            ((hsize == 1360 && vsize == 765) ||
2400             (hsize == 1368 && vsize == 769))) {
2401                hsize = 1366;
2402                vsize = 768;
2403        }
2404
2405        /*
2406         * If this connector already has a mode for this size and refresh
2407         * rate (because it came from detailed or CVT info), use that
2408         * instead.  This way we don't have to guess at interlace or
2409         * reduced blanking.
2410         */
2411        list_for_each_entry(m, &connector->probed_modes, head)
2412                if (m->hdisplay == hsize && m->vdisplay == vsize &&
2413                    drm_mode_vrefresh(m) == vrefresh_rate)
2414                        return NULL;
2415
2416        /* HDTV hack, part 2 */
2417        if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2418                mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2419                                    false);
2420                if (!mode)
2421                        return NULL;
2422                mode->hdisplay = 1366;
2423                mode->hsync_start = mode->hsync_start - 1;
2424                mode->hsync_end = mode->hsync_end - 1;
2425                return mode;
2426        }
2427
2428        /* check whether it can be found in default mode table */
2429        if (drm_monitor_supports_rb(edid)) {
2430                mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2431                                         true);
2432                if (mode)
2433                        return mode;
2434        }
2435        mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2436        if (mode)
2437                return mode;
2438
2439        /* okay, generate it */
2440        switch (timing_level) {
2441        case LEVEL_DMT:
2442                break;
2443        case LEVEL_GTF:
2444                mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2445                break;
2446        case LEVEL_GTF2:
2447                /*
2448                 * This is potentially wrong if there's ever a monitor with
2449                 * more than one ranges section, each claiming a different
2450                 * secondary GTF curve.  Please don't do that.
2451                 */
2452                mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2453                if (!mode)
2454                        return NULL;
2455                if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2456                        drm_mode_destroy(dev, mode);
2457                        mode = drm_gtf_mode_complex(dev, hsize, vsize,
2458                                                    vrefresh_rate, 0, 0,
2459                                                    drm_gtf2_m(edid),
2460                                                    drm_gtf2_2c(edid),
2461                                                    drm_gtf2_k(edid),
2462                                                    drm_gtf2_2j(edid));
2463                }
2464                break;
2465        case LEVEL_CVT:
2466                mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2467                                    false);
2468                break;
2469        }
2470        return mode;
2471}
2472
2473/*
2474 * EDID is delightfully ambiguous about how interlaced modes are to be
2475 * encoded.  Our internal representation is of frame height, but some
2476 * HDTV detailed timings are encoded as field height.
2477 *
2478 * The format list here is from CEA, in frame size.  Technically we
2479 * should be checking refresh rate too.  Whatever.
2480 */
2481static void
2482drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2483                            struct detailed_pixel_timing *pt)
2484{
2485        int i;
2486        static const struct {
2487                int w, h;
2488        } cea_interlaced[] = {
2489                { 1920, 1080 },
2490                {  720,  480 },
2491                { 1440,  480 },
2492                { 2880,  480 },
2493                {  720,  576 },
2494                { 1440,  576 },
2495                { 2880,  576 },
2496        };
2497
2498        if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2499                return;
2500
2501        for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2502                if ((mode->hdisplay == cea_interlaced[i].w) &&
2503                    (mode->vdisplay == cea_interlaced[i].h / 2)) {
2504                        mode->vdisplay *= 2;
2505                        mode->vsync_start *= 2;
2506                        mode->vsync_end *= 2;
2507                        mode->vtotal *= 2;
2508                        mode->vtotal |= 1;
2509                }
2510        }
2511
2512        mode->flags |= DRM_MODE_FLAG_INTERLACE;
2513}
2514
2515/**
2516 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2517 * @dev: DRM device (needed to create new mode)
2518 * @edid: EDID block
2519 * @timing: EDID detailed timing info
2520 * @quirks: quirks to apply
2521 *
2522 * An EDID detailed timing block contains enough info for us to create and
2523 * return a new struct drm_display_mode.
2524 */
2525static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2526                                                  struct edid *edid,
2527                                                  struct detailed_timing *timing,
2528                                                  u32 quirks)
2529{
2530        struct drm_display_mode *mode;
2531        struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2532        unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2533        unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2534        unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2535        unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2536        unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2537        unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2538        unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2539        unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2540
2541        /* ignore tiny modes */
2542        if (hactive < 64 || vactive < 64)
2543                return NULL;
2544
2545        if (pt->misc & DRM_EDID_PT_STEREO) {
2546                DRM_DEBUG_KMS("stereo mode not supported\n");
2547                return NULL;
2548        }
2549        if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2550                DRM_DEBUG_KMS("composite sync not supported\n");
2551        }
2552
2553        /* it is incorrect if hsync/vsync width is zero */
2554        if (!hsync_pulse_width || !vsync_pulse_width) {
2555                DRM_DEBUG_KMS("Incorrect Detailed timing. "
2556                                "Wrong Hsync/Vsync pulse width\n");
2557                return NULL;
2558        }
2559
2560        if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2561                mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2562                if (!mode)
2563                        return NULL;
2564
2565                goto set_size;
2566        }
2567
2568        mode = drm_mode_create(dev);
2569        if (!mode)
2570                return NULL;
2571
2572        if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2573                timing->pixel_clock = cpu_to_le16(1088);
2574
2575        mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2576
2577        mode->hdisplay = hactive;
2578        mode->hsync_start = mode->hdisplay + hsync_offset;
2579        mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2580        mode->htotal = mode->hdisplay + hblank;
2581
2582        mode->vdisplay = vactive;
2583        mode->vsync_start = mode->vdisplay + vsync_offset;
2584        mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2585        mode->vtotal = mode->vdisplay + vblank;
2586
2587        /* Some EDIDs have bogus h/vtotal values */
2588        if (mode->hsync_end > mode->htotal)
2589                mode->htotal = mode->hsync_end + 1;
2590        if (mode->vsync_end > mode->vtotal)
2591                mode->vtotal = mode->vsync_end + 1;
2592
2593        drm_mode_do_interlace_quirk(mode, pt);
2594
2595        if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2596                pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2597        }
2598
2599        mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2600                DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2601        mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2602                DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2603
2604set_size:
2605        mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2606        mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2607
2608        if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2609                mode->width_mm *= 10;
2610                mode->height_mm *= 10;
2611        }
2612
2613        if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2614                mode->width_mm = edid->width_cm * 10;
2615                mode->height_mm = edid->height_cm * 10;
2616        }
2617
2618        mode->type = DRM_MODE_TYPE_DRIVER;
2619        mode->vrefresh = drm_mode_vrefresh(mode);
2620        drm_mode_set_name(mode);
2621
2622        return mode;
2623}
2624
2625static bool
2626mode_in_hsync_range(const struct drm_display_mode *mode,
2627                    struct edid *edid, u8 *t)
2628{
2629        int hsync, hmin, hmax;
2630
2631        hmin = t[7];
2632        if (edid->revision >= 4)
2633            hmin += ((t[4] & 0x04) ? 255 : 0);
2634        hmax = t[8];
2635        if (edid->revision >= 4)
2636            hmax += ((t[4] & 0x08) ? 255 : 0);
2637        hsync = drm_mode_hsync(mode);
2638
2639        return (hsync <= hmax && hsync >= hmin);
2640}
2641
2642static bool
2643mode_in_vsync_range(const struct drm_display_mode *mode,
2644                    struct edid *edid, u8 *t)
2645{
2646        int vsync, vmin, vmax;
2647
2648        vmin = t[5];
2649        if (edid->revision >= 4)
2650            vmin += ((t[4] & 0x01) ? 255 : 0);
2651        vmax = t[6];
2652        if (edid->revision >= 4)
2653            vmax += ((t[4] & 0x02) ? 255 : 0);
2654        vsync = drm_mode_vrefresh(mode);
2655
2656        return (vsync <= vmax && vsync >= vmin);
2657}
2658
2659static u32
2660range_pixel_clock(struct edid *edid, u8 *t)
2661{
2662        /* unspecified */
2663        if (t[9] == 0 || t[9] == 255)
2664                return 0;
2665
2666        /* 1.4 with CVT support gives us real precision, yay */
2667        if (edid->revision >= 4 && t[10] == 0x04)
2668                return (t[9] * 10000) - ((t[12] >> 2) * 250);
2669
2670        /* 1.3 is pathetic, so fuzz up a bit */
2671        return t[9] * 10000 + 5001;
2672}
2673
2674static bool
2675mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2676              struct detailed_timing *timing)
2677{
2678        u32 max_clock;
2679        u8 *t = (u8 *)timing;
2680
2681        if (!mode_in_hsync_range(mode, edid, t))
2682                return false;
2683
2684        if (!mode_in_vsync_range(mode, edid, t))
2685                return false;
2686
2687        if ((max_clock = range_pixel_clock(edid, t)))
2688                if (mode->clock > max_clock)
2689                        return false;
2690
2691        /* 1.4 max horizontal check */
2692        if (edid->revision >= 4 && t[10] == 0x04)
2693                if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2694                        return false;
2695
2696        if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2697                return false;
2698
2699        return true;
2700}
2701
2702static bool valid_inferred_mode(const struct drm_connector *connector,
2703                                const struct drm_display_mode *mode)
2704{
2705        const struct drm_display_mode *m;
2706        bool ok = false;
2707
2708        list_for_each_entry(m, &connector->probed_modes, head) {
2709                if (mode->hdisplay == m->hdisplay &&
2710                    mode->vdisplay == m->vdisplay &&
2711                    drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2712                        return false; /* duplicated */
2713                if (mode->hdisplay <= m->hdisplay &&
2714                    mode->vdisplay <= m->vdisplay)
2715                        ok = true;
2716        }
2717        return ok;
2718}
2719
2720static int
2721drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2722                        struct detailed_timing *timing)
2723{
2724        int i, modes = 0;
2725        struct drm_display_mode *newmode;
2726        struct drm_device *dev = connector->dev;
2727
2728        for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2729                if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2730                    valid_inferred_mode(connector, drm_dmt_modes + i)) {
2731                        newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2732                        if (newmode) {
2733                                drm_mode_probed_add(connector, newmode);
2734                                modes++;
2735                        }
2736                }
2737        }
2738
2739        return modes;
2740}
2741
2742/* fix up 1366x768 mode from 1368x768;
2743 * GFT/CVT can't express 1366 width which isn't dividable by 8
2744 */
2745void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2746{
2747        if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2748                mode->hdisplay = 1366;
2749                mode->hsync_start--;
2750                mode->hsync_end--;
2751                drm_mode_set_name(mode);
2752        }
2753}
2754
2755static int
2756drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2757                        struct detailed_timing *timing)
2758{
2759        int i, modes = 0;
2760        struct drm_display_mode *newmode;
2761        struct drm_device *dev = connector->dev;
2762
2763        for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2764                const struct minimode *m = &extra_modes[i];
2765                newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2766                if (!newmode)
2767                        return modes;
2768
2769                drm_mode_fixup_1366x768(newmode);
2770                if (!mode_in_range(newmode, edid, timing) ||
2771                    !valid_inferred_mode(connector, newmode)) {
2772                        drm_mode_destroy(dev, newmode);
2773                        continue;
2774                }
2775
2776                drm_mode_probed_add(connector, newmode);
2777                modes++;
2778        }
2779
2780        return modes;
2781}
2782
2783static int
2784drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2785                        struct detailed_timing *timing)
2786{
2787        int i, modes = 0;
2788        struct drm_display_mode *newmode;
2789        struct drm_device *dev = connector->dev;
2790        bool rb = drm_monitor_supports_rb(edid);
2791
2792        for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2793                const struct minimode *m = &extra_modes[i];
2794                newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2795                if (!newmode)
2796                        return modes;
2797
2798                drm_mode_fixup_1366x768(newmode);
2799                if (!mode_in_range(newmode, edid, timing) ||
2800                    !valid_inferred_mode(connector, newmode)) {
2801                        drm_mode_destroy(dev, newmode);
2802                        continue;
2803                }
2804
2805                drm_mode_probed_add(connector, newmode);
2806                modes++;
2807        }
2808
2809        return modes;
2810}
2811
2812static void
2813do_inferred_modes(struct detailed_timing *timing, void *c)
2814{
2815        struct detailed_mode_closure *closure = c;
2816        struct detailed_non_pixel *data = &timing->data.other_data;
2817        struct detailed_data_monitor_range *range = &data->data.range;
2818
2819        if (data->type != EDID_DETAIL_MONITOR_RANGE)
2820                return;
2821
2822        closure->modes += drm_dmt_modes_for_range(closure->connector,
2823                                                  closure->edid,
2824                                                  timing);
2825        
2826        if (!version_greater(closure->edid, 1, 1))
2827                return; /* GTF not defined yet */
2828
2829        switch (range->flags) {
2830        case 0x02: /* secondary gtf, XXX could do more */
2831        case 0x00: /* default gtf */
2832                closure->modes += drm_gtf_modes_for_range(closure->connector,
2833                                                          closure->edid,
2834                                                          timing);
2835                break;
2836        case 0x04: /* cvt, only in 1.4+ */
2837                if (!version_greater(closure->edid, 1, 3))
2838                        break;
2839
2840                closure->modes += drm_cvt_modes_for_range(closure->connector,
2841                                                          closure->edid,
2842                                                          timing);
2843                break;
2844        case 0x01: /* just the ranges, no formula */
2845        default:
2846                break;
2847        }
2848}
2849
2850static int
2851add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2852{
2853        struct detailed_mode_closure closure = {
2854                .connector = connector,
2855                .edid = edid,
2856        };
2857
2858        if (version_greater(edid, 1, 0))
2859                drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2860                                            &closure);
2861
2862        return closure.modes;
2863}
2864
2865static int
2866drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2867{
2868        int i, j, m, modes = 0;
2869        struct drm_display_mode *mode;
2870        u8 *est = ((u8 *)timing) + 6;
2871
2872        for (i = 0; i < 6; i++) {
2873                for (j = 7; j >= 0; j--) {
2874                        m = (i * 8) + (7 - j);
2875                        if (m >= ARRAY_SIZE(est3_modes))
2876                                break;
2877                        if (est[i] & (1 << j)) {
2878                                mode = drm_mode_find_dmt(connector->dev,
2879                                                         est3_modes[m].w,
2880                                                         est3_modes[m].h,
2881                                                         est3_modes[m].r,
2882                                                         est3_modes[m].rb);
2883                                if (mode) {
2884                                        drm_mode_probed_add(connector, mode);
2885                                        modes++;
2886                                }
2887                        }
2888                }
2889        }
2890
2891        return modes;
2892}
2893
2894static void
2895do_established_modes(struct detailed_timing *timing, void *c)
2896{
2897        struct detailed_mode_closure *closure = c;
2898        struct detailed_non_pixel *data = &timing->data.other_data;
2899
2900        if (data->type == EDID_DETAIL_EST_TIMINGS)
2901                closure->modes += drm_est3_modes(closure->connector, timing);
2902}
2903
2904/**
2905 * add_established_modes - get est. modes from EDID and add them
2906 * @connector: connector to add mode(s) to
2907 * @edid: EDID block to scan
2908 *
2909 * Each EDID block contains a bitmap of the supported "established modes" list
2910 * (defined above).  Tease them out and add them to the global modes list.
2911 */
2912static int
2913add_established_modes(struct drm_connector *connector, struct edid *edid)
2914{
2915        struct drm_device *dev = connector->dev;
2916        unsigned long est_bits = edid->established_timings.t1 |
2917                (edid->established_timings.t2 << 8) |
2918                ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2919        int i, modes = 0;
2920        struct detailed_mode_closure closure = {
2921                .connector = connector,
2922                .edid = edid,
2923        };
2924
2925        for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2926                if (est_bits & (1<<i)) {
2927                        struct drm_display_mode *newmode;
2928                        newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2929                        if (newmode) {
2930                                drm_mode_probed_add(connector, newmode);
2931                                modes++;
2932                        }
2933                }
2934        }
2935
2936        if (version_greater(edid, 1, 0))
2937                    drm_for_each_detailed_block((u8 *)edid,
2938                                                do_established_modes, &closure);
2939
2940        return modes + closure.modes;
2941}
2942
2943static void
2944do_standard_modes(struct detailed_timing *timing, void *c)
2945{
2946        struct detailed_mode_closure *closure = c;
2947        struct detailed_non_pixel *data = &timing->data.other_data;
2948        struct drm_connector *connector = closure->connector;
2949        struct edid *edid = closure->edid;
2950
2951        if (data->type == EDID_DETAIL_STD_MODES) {
2952                int i;
2953                for (i = 0; i < 6; i++) {
2954                        struct std_timing *std;
2955                        struct drm_display_mode *newmode;
2956
2957                        std = &data->data.timings[i];
2958                        newmode = drm_mode_std(connector, edid, std);
2959                        if (newmode) {
2960                                drm_mode_probed_add(connector, newmode);
2961                                closure->modes++;
2962                        }
2963                }
2964        }
2965}
2966
2967/**
2968 * add_standard_modes - get std. modes from EDID and add them
2969 * @connector: connector to add mode(s) to
2970 * @edid: EDID block to scan
2971 *
2972 * Standard modes can be calculated using the appropriate standard (DMT,
2973 * GTF or CVT. Grab them from @edid and add them to the list.
2974 */
2975static int
2976add_standard_modes(struct drm_connector *connector, struct edid *edid)
2977{
2978        int i, modes = 0;
2979        struct detailed_mode_closure closure = {
2980                .connector = connector,
2981                .edid = edid,
2982        };
2983
2984        for (i = 0; i < EDID_STD_TIMINGS; i++) {
2985                struct drm_display_mode *newmode;
2986
2987                newmode = drm_mode_std(connector, edid,
2988                                       &edid->standard_timings[i]);
2989                if (newmode) {
2990                        drm_mode_probed_add(connector, newmode);
2991                        modes++;
2992                }
2993        }
2994
2995        if (version_greater(edid, 1, 0))
2996                drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2997                                            &closure);
2998
2999        /* XXX should also look for standard codes in VTB blocks */
3000

3001        return modes + closure.modes;
3002}
3003
3004static int drm_cvt_modes(struct drm_connector *connector,
3005                         struct detailed_timing *timing)
3006{
3007        int i, j, modes = 0;
3008        struct drm_display_mode *newmode;
3009        struct drm_device *dev = connector->dev;
3010        struct cvt_timing *cvt;
3011        const int rates[] = { 60, 85, 75, 60, 50 };
3012        const u8 empty[3] = { 0, 0, 0 };
3013
3014        for (i = 0; i < 4; i++) {
3015                int uninitialized_var(width), height;
3016                cvt = &(timing->data.other_data.data.cvt[i]);
3017
3018                if (!memcmp(cvt->code, empty, 3))
3019                        continue;
3020
3021                height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3022                switch (cvt->code[1] & 0x0c) {
3023                case 0x00:
3024                        width = height * 4 / 3;
3025                        break;
3026                case 0x04:
3027                        width = height * 16 / 9;
3028                        break;
3029                case 0x08:
3030                        width = height * 16 / 10;
3031                        break;
3032                case 0x0c:
3033                        width = height * 15 / 9;
3034                        break;
3035                }
3036
3037                for (j = 1; j < 5; j++) {
3038                        if (cvt->code[2] & (1 << j)) {
3039                                newmode = drm_cvt_mode(dev, width, height,
3040                                                       rates[j], j == 0,
3041                                                       false, false);
3042                                if (newmode) {
3043                                        drm_mode_probed_add(connector, newmode);
3044                                        modes++;
3045                                }
3046                        }
3047                }
3048        }
3049
3050        return modes;
3051}
3052
3053static void
3054do_cvt_mode(struct detailed_timing *timing, void *c)
3055{
3056        struct detailed_mode_closure *closure = c;
3057        struct detailed_non_pixel *data = &timing->data.other_data;
3058
3059        if (data->type == EDID_DETAIL_CVT_3BYTE)
3060                closure->modes += drm_cvt_modes(closure->connector, timing);
3061}
3062
3063static int
3064add_cvt_modes(struct drm_connector *connector, struct edid *edid)
3065{       
3066        struct detailed_mode_closure closure = {
3067                .connector = connector,
3068                .edid = edid,
3069        };
3070
3071        if (version_greater(edid, 1, 2))
3072                drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
3073
3074        /* XXX should also look for CVT codes in VTB blocks */
3075
3076        return closure.modes;
3077}
3078
3079static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
3080
3081static void
3082do_detailed_mode(struct detailed_timing *timing, void *c)
3083{
3084        struct detailed_mode_closure *closure = c;
3085        struct drm_display_mode *newmode;
3086
3087        if (timing->pixel_clock) {
3088                newmode = drm_mode_detailed(closure->connector->dev,
3089                                            closure->edid, timing,
3090                                            closure->quirks);
3091                if (!newmode)
3092                        return;
3093
3094                if (closure->preferred)
3095                        newmode->type |= DRM_MODE_TYPE_PREFERRED;
3096
3097                /*
3098                 * Detailed modes are limited to 10kHz pixel clock resolution,
3099                 * so fix up anything that looks like CEA/HDMI mode, but the clock
3100                 * is just slightly off.
3101                 */
3102                fixup_detailed_cea_mode_clock(newmode);
3103
3104                drm_mode_probed_add(closure->connector, newmode);
3105                closure->modes++;
3106                closure->preferred = false;
3107        }
3108}
3109
3110/*
3111 * add_detailed_modes - Add modes from detailed timings
3112 * @connector: attached connector
3113 * @edid: EDID block to scan
3114 * @quirks: quirks to apply
3115 */
3116static int
3117add_detailed_modes(struct drm_connector *connector, struct edid *edid,
3118                   u32 quirks)
3119{
3120        struct detailed_mode_closure closure = {
3121                .connector = connector,
3122                .edid = edid,
3123                .preferred = true,
3124                .quirks = quirks,
3125        };
3126
3127        if (closure.preferred && !version_greater(edid, 1, 3))
3128                closure.preferred =
3129                    (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
3130
3131        drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
3132
3133        return closure.modes;
3134}
3135
3136#define AUDIO_BLOCK     0x01
3137#define VIDEO_BLOCK     0x02
3138#define VENDOR_BLOCK    0x03
3139#define SPEAKER_BLOCK   0x04
3140#define HDR_STATIC_METADATA_BLOCK       0x6
3141#define USE_EXTENDED_TAG 0x07
3142#define EXT_VIDEO_CAPABILITY_BLOCK 0x00
3143#define EXT_VIDEO_DATA_BLOCK_420        0x0E
3144#define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
3145#define EDID_BASIC_AUDIO        (1 << 6)
3146#define EDID_CEA_YCRCB444       (1 << 5)
3147#define EDID_CEA_YCRCB422       (1 << 4)
3148#define EDID_CEA_VCDB_QS        (1 << 6)
3149
3150/*
3151 * Search EDID for CEA extension block.
3152 */
3153static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)
3154{
3155        u8 *edid_ext = NULL;
3156        int i;
3157
3158        /* No EDID or EDID extensions */
3159        if (edid == NULL || edid->extensions == 0)
3160                return NULL;
3161
3162        /* Find CEA extension */
3163        for (i = 0; i < edid->extensions; i++) {
3164                edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
3165                if (edid_ext[0] == ext_id)
3166                        break;
3167        }
3168
3169        if (i == edid->extensions)
3170                return NULL;
3171
3172        return edid_ext;
3173}
3174
3175
3176static u8 *drm_find_displayid_extension(const struct edid *edid)
3177{
3178        return drm_find_edid_extension(edid, DISPLAYID_EXT);
3179}
3180
3181static u8 *drm_find_cea_extension(const struct edid *edid)
3182{
3183        int ret;
3184        int idx = 1;
3185        int length = EDID_LENGTH;
3186        struct displayid_block *block;
3187        u8 *cea;
3188        u8 *displayid;
3189
3190        /* Look for a top level CEA extension block */
3191        cea = drm_find_edid_extension(edid, CEA_EXT);
3192        if (cea)
3193                return cea;
3194
3195        /* CEA blocks can also be found embedded in a DisplayID block */
3196        displayid = drm_find_displayid_extension(edid);
3197        if (!displayid)
3198                return NULL;
3199
3200        ret = validate_displayid(displayid, length, idx);
3201        if (ret)
3202                return NULL;
3203
3204        idx += sizeof(struct displayid_hdr);
3205        for_each_displayid_db(displayid, block, idx, length) {
3206                if (block->tag == DATA_BLOCK_CTA) {
3207                        cea = (u8 *)block;
3208                        break;
3209                }
3210        }
3211
3212        return cea;
3213}
3214
3215static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
3216{
3217        BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
3218        BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
3219
3220        if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
3221                return &edid_cea_modes_1[vic - 1];
3222        if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
3223                return &edid_cea_modes_193[vic - 193];
3224        return NULL;
3225}
3226
3227static u8 cea_num_vics(void)
3228{
3229        return 193 + ARRAY_SIZE(edid_cea_modes_193);
3230}
3231
3232static u8 cea_next_vic(u8 vic)
3233{
3234        if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
3235                vic = 193;
3236        return vic;
3237}
3238
3239/*
3240 * Calculate the alternate clock for the CEA mode
3241 * (60Hz vs. 59.94Hz etc.)
3242 */
3243static unsigned int
3244cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
3245{
3246        unsigned int clock = cea_mode->clock;
3247
3248        if (cea_mode->vrefresh % 6 != 0)
3249                return clock;
3250
3251        /*
3252         * edid_cea_modes contains the 59.94Hz
3253         * variant for 240 and 480 line modes,
3254         * and the 60Hz variant otherwise.
3255         */
3256        if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
3257                clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
3258        else
3259                clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
3260
3261        return clock;
3262}
3263
3264static bool
3265cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
3266{
3267        /*
3268         * For certain VICs the spec allows the vertical
3269         * front porch to vary by one or two lines.
3270         *
3271         * cea_modes[] stores the variant with the shortest
3272         * vertical front porch. We can adjust the mode to
3273         * get the other variants by simply increasing the
3274         * vertical front porch length.
3275         */
3276        BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
3277                     cea_mode_for_vic(9)->vtotal != 262 ||
3278                     cea_mode_for_vic(12)->vtotal != 262 ||
3279                     cea_mode_for_vic(13)->vtotal != 262 ||
3280                     cea_mode_for_vic(23)->vtotal != 312 ||
3281                     cea_mode_for_vic(24)->vtotal != 312 ||
3282                     cea_mode_for_vic(27)->vtotal != 312 ||
3283                     cea_mode_for_vic(28)->vtotal != 312);
3284
3285        if (((vic == 8 || vic == 9 ||
3286              vic == 12 || vic == 13) && mode->vtotal < 263) ||
3287            ((vic == 23 || vic == 24 ||
3288              vic == 27 || vic == 28) && mode->vtotal < 314)) {
3289                mode->vsync_start++;
3290                mode->vsync_end++;
3291                mode->vtotal++;
3292
3293                return true;
3294        }
3295
3296        return false;
3297}
3298
3299static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
3300                                             unsigned int clock_tolerance)
3301{
3302        unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3303        u8 vic;
3304
3305        if (!to_match->clock)
3306                return 0;
3307
3308        if (to_match->picture_aspect_ratio)
3309                match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3310
3311        for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3312                struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
3313                unsigned int clock1, clock2;
3314
3315                /* Check both 60Hz and 59.94Hz */
3316                clock1 = cea_mode.clock;
3317                clock2 = cea_mode_alternate_clock(&cea_mode);
3318
3319                if (abs(to_match->clock - clock1) > clock_tolerance &&
3320                    abs(to_match->clock - clock2) > clock_tolerance)
3321                        continue;
3322
3323                do {
3324                        if (drm_mode_match(to_match, &cea_mode, match_flags))
3325                                return vic;
3326                } while (cea_mode_alternate_timings(vic, &cea_mode));
3327        }
3328
3329        return 0;
3330}
3331
3332/**
3333 * drm_match_cea_mode - look for a CEA mode matching given mode
3334 * @to_match: display mode
3335 *
3336 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
3337 * mode.
3338 */
3339u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
3340{
3341        unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3342        u8 vic;
3343
3344        if (!to_match->clock)
3345                return 0;
3346
3347        if (to_match->picture_aspect_ratio)
3348                match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3349
3350        for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3351                struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
3352                unsigned int clock1, clock2;
3353
3354                /* Check both 60Hz and 59.94Hz */
3355                clock1 = cea_mode.clock;
3356                clock2 = cea_mode_alternate_clock(&cea_mode);
3357
3358                if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3359                    KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3360                        continue;
3361
3362                do {
3363                        if (drm_mode_match(to_match, &cea_mode, match_flags))
3364                                return vic;
3365                } while (cea_mode_alternate_timings(vic, &cea_mode));
3366        }
3367
3368        return 0;
3369}
3370EXPORT_SYMBOL(drm_match_cea_mode);
3371
3372static bool drm_valid_cea_vic(u8 vic)
3373{
3374        return cea_mode_for_vic(vic) != NULL;
3375}
3376
3377static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
3378{
3379        const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
3380
3381        if (mode)
3382                return mode->picture_aspect_ratio;
3383
3384        return HDMI_PICTURE_ASPECT_NONE;
3385}
3386
3387static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
3388{
3389        return edid_4k_modes[video_code].picture_aspect_ratio;
3390}
3391
3392/*
3393 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3394 * specific block).
3395 */
3396static unsigned int
3397hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3398{
3399        return cea_mode_alternate_clock(hdmi_mode);
3400}
3401
3402static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3403                                              unsigned int clock_tolerance)
3404{
3405        unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3406        u8 vic;
3407
3408        if (!to_match->clock)
3409                return 0;
3410
3411        if (to_match->picture_aspect_ratio)
3412                match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3413
3414        for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3415                const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3416                unsigned int clock1, clock2;
3417
3418                /* Make sure to also match alternate clocks */
3419                clock1 = hdmi_mode->clock;
3420                clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3421
3422                if (abs(to_match->clock - clock1) > clock_tolerance &&
3423                    abs(to_match->clock - clock2) > clock_tolerance)
3424                        continue;
3425
3426                if (drm_mode_match(to_match, hdmi_mode, match_flags))
3427                        return vic;
3428        }
3429
3430        return 0;
3431}
3432
3433/*
3434 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3435 * @to_match: display mode
3436 *
3437 * An HDMI mode is one defined in the HDMI vendor specific block.
3438 *
3439 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3440 */
3441static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3442{
3443        unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3444        u8 vic;
3445
3446        if (!to_match->clock)
3447                return 0;
3448
3449        if (to_match->picture_aspect_ratio)
3450                match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3451
3452        for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3453                const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3454                unsigned int clock1, clock2;
3455
3456                /* Make sure to also match alternate clocks */
3457                clock1 = hdmi_mode->clock;
3458                clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3459
3460                if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3461                     KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3462                    drm_mode_match(to_match, hdmi_mode, match_flags))
3463                        return vic;
3464        }
3465        return 0;
3466}
3467
3468static bool drm_valid_hdmi_vic(u8 vic)
3469{
3470        return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3471}
3472
3473static int
3474add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3475{
3476        struct drm_device *dev = connector->dev;
3477        struct drm_display_mode *mode, *tmp;
3478        LIST_HEAD(list);
3479        int modes = 0;
3480
3481        /* Don't add CEA modes if the CEA extension block is missing */
3482        if (!drm_find_cea_extension(edid))
3483                return 0;
3484
3485        /*
3486         * Go through all probed modes and create a new mode
3487         * with the alternate clock for certain CEA modes.
3488         */
3489        list_for_each_entry(mode, &connector->probed_modes, head) {
3490                const struct drm_display_mode *cea_mode = NULL;
3491                struct drm_display_mode *newmode;
3492                u8 vic = drm_match_cea_mode(mode);
3493                unsigned int clock1, clock2;
3494
3495                if (drm_valid_cea_vic(vic)) {
3496                        cea_mode = cea_mode_for_vic(vic);
3497                        clock2 = cea_mode_alternate_clock(cea_mode);
3498                } else {
3499                        vic = drm_match_hdmi_mode(mode);
3500                        if (drm_valid_hdmi_vic(vic)) {
3501                                cea_mode = &edid_4k_modes[vic];
3502                                clock2 = hdmi_mode_alternate_clock(cea_mode);
3503                        }
3504                }
3505
3506                if (!cea_mode)
3507                        continue;
3508
3509                clock1 = cea_mode->clock;
3510
3511                if (clock1 == clock2)
3512                        continue;
3513
3514                if (mode->clock != clock1 && mode->clock != clock2)
3515                        continue;
3516
3517                newmode = drm_mode_duplicate(dev, cea_mode);
3518                if (!newmode)
3519                        continue;
3520
3521                /* Carry over the stereo flags */
3522                newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3523
3524                /*
3525                 * The current mode could be either variant. Make
3526                 * sure to pick the "other" clock for the new mode.
3527                 */
3528                if (mode->clock != clock1)
3529                        newmode->clock = clock1;
3530                else
3531                        newmode->clock = clock2;
3532
3533                list_add_tail(&newmode->head, &list);
3534        }
3535
3536        list_for_each_entry_safe(mode, tmp, &list, head) {
3537                list_del(&mode->head);
3538                drm_mode_probed_add(connector, mode);
3539                modes++;
3540        }
3541
3542        return modes;
3543}
3544
3545static u8 svd_to_vic(u8 svd)
3546{
3547        /* 0-6 bit vic, 7th bit native mode indicator */
3548        if ((svd >= 1 &&  svd <= 64) || (svd >= 129 && svd <= 192))
3549                return svd & 127;
3550
3551        return svd;
3552}
3553
3554static struct drm_display_mode *
3555drm_display_mode_from_vic_index(struct drm_connector *connector,
3556                                const u8 *video_db, u8 video_len,
3557                                u8 video_index)
3558{
3559        struct drm_device *dev = connector->dev;
3560        struct drm_display_mode *newmode;
3561        u8 vic;
3562
3563        if (video_db == NULL || video_index >= video_len)
3564                return NULL;
3565
3566        /* CEA modes are numbered 1..127 */
3567        vic = svd_to_vic(video_db[video_index]);
3568        if (!drm_valid_cea_vic(vic))
3569                return NULL;
3570
3571        newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
3572        if (!newmode)
3573                return NULL;
3574
3575        newmode->vrefresh = 0;
3576
3577        return newmode;
3578}
3579
3580/*
3581 * do_y420vdb_modes - Parse YCBCR 420 only modes
3582 * @connector: connector corresponding to the HDMI sink
3583 * @svds: start of the data block of CEA YCBCR 420 VDB
3584 * @len: length of the CEA YCBCR 420 VDB
3585 *
3586 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3587 * which contains modes which can be supported in YCBCR 420
3588 * output format only.
3589 */
3590static int do_y420vdb_modes(struct drm_connector *connector,
3591                            const u8 *svds, u8 svds_len)
3592{
3593        int modes = 0, i;
3594        struct drm_device *dev = connector->dev;
3595        struct drm_display_info *info = &connector->display_info;
3596        struct drm_hdmi_info *hdmi = &info->hdmi;
3597
3598        for (i = 0; i < svds_len; i++) {
3599                u8 vic = svd_to_vic(svds[i]);
3600                struct drm_display_mode *newmode;
3601
3602                if (!drm_valid_cea_vic(vic))
3603                        continue;
3604
3605                newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
3606                if (!newmode)
3607                        break;
3608                bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3609                drm_mode_probed_add(connector, newmode);
3610                modes++;
3611        }
3612
3613        if (modes > 0)
3614                info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3615        return modes;
3616}
3617
3618/*
3619 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3620 * @connector: connector corresponding to the HDMI sink
3621 * @vic: CEA vic for the video mode to be added in the map
3622 *
3623 * Makes an entry for a videomode in the YCBCR 420 bitmap
3624 */
3625static void
3626drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3627{
3628        u8 vic = svd_to_vic(svd);
3629        struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3630
3631        if (!drm_valid_cea_vic(vic))
3632                return;
3633
3634        bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3635}
3636
3637static int
3638do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3639{
3640        int i, modes = 0;
3641        struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3642
3643        for (i = 0; i < len; i++) {
3644                struct drm_display_mode *mode;
3645                mode = drm_display_mode_from_vic_index(connector, db, len, i);
3646                if (mode) {
3647                        /*
3648                         * YCBCR420 capability block contains a bitmap which
3649                         * gives the index of CEA modes from CEA VDB, which
3650                         * can support YCBCR 420 sampling output also (apart
3651                         * from RGB/YCBCR444 etc).
3652                         * For example, if the bit 0 in bitmap is set,
3653                         * first mode in VDB can support YCBCR420 output too.
3654                         * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3655                         */
3656                        if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3657                                drm_add_cmdb_modes(connector, db[i]);
3658
3659                        drm_mode_probed_add(connector, mode);
3660                        modes++;
3661                }
3662        }
3663
3664        return modes;
3665}
3666
3667struct stereo_mandatory_mode {
3668        int width, height, vrefresh;
3669        unsigned int flags;
3670};
3671
3672static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3673        { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3674        { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3675        { 1920, 1080, 50,
3676          DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3677        { 1920, 1080, 60,
3678          DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3679        { 1280, 720,  50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3680        { 1280, 720,  50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3681        { 1280, 720,  60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3682        { 1280, 720,  60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3683};
3684
3685static bool
3686stereo_match_mandatory(const struct drm_display_mode *mode,
3687                       const struct stereo_mandatory_mode *stereo_mode)
3688{
3689        unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3690
3691        return mode->hdisplay == stereo_mode->width &&
3692               mode->vdisplay == stereo_mode->height &&
3693               interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3694               drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3695}
3696
3697static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3698{
3699        struct drm_device *dev = connector->dev;
3700        const struct drm_display_mode *mode;
3701        struct list_head stereo_modes;
3702        int modes = 0, i;
3703
3704        INIT_LIST_HEAD(&stereo_modes);
3705
3706        list_for_each_entry(mode, &connector->probed_modes, head) {
3707                for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3708                        const struct stereo_mandatory_mode *mandatory;
3709                        struct drm_display_mode *new_mode;
3710
3711                        if (!stereo_match_mandatory(mode,
3712                                                    &stereo_mandatory_modes[i]))
3713                                continue;
3714
3715                        mandatory = &stereo_mandatory_modes[i];
3716                        new_mode = drm_mode_duplicate(dev, mode);
3717                        if (!new_mode)
3718                                continue;
3719
3720                        new_mode->flags |= mandatory->flags;
3721                        list_add_tail(&new_mode->head, &stereo_modes);
3722                        modes++;
3723                }
3724        }
3725
3726        list_splice_tail(&stereo_modes, &connector->probed_modes);
3727
3728        return modes;
3729}
3730
3731static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3732{
3733        struct drm_device *dev = connector->dev;
3734        struct drm_display_mode *newmode;
3735
3736        if (!drm_valid_hdmi_vic(vic)) {
3737                DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3738                return 0;
3739        }
3740
3741        newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3742        if (!newmode)
3743                return 0;
3744
3745        drm_mode_probed_add(connector, newmode);
3746
3747        return 1;
3748}
3749
3750static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3751                               const u8 *video_db, u8 video_len, u8 video_index)
3752{
3753        struct drm_display_mode *newmode;
3754        int modes = 0;
3755
3756        if (structure & (1 << 0)) {
3757                newmode = drm_display_mode_from_vic_index(connector, video_db,
3758                                                          video_len,
3759                                                          video_index);
3760                if (newmode) {
3761                        newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3762                        drm_mode_probed_add(connector, newmode);
3763                        modes++;
3764                }
3765        }
3766        if (structure & (1 << 6)) {
3767                newmode = drm_display_mode_from_vic_index(connector, video_db,
3768                                                          video_len,
3769                                                          video_index);
3770                if (newmode) {
3771                        newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3772                        drm_mode_probed_add(connector, newmode);
3773                        modes++;
3774                }
3775        }
3776        if (structure & (1 << 8)) {
3777                newmode = drm_display_mode_from_vic_index(connector, video_db,
3778                                                          video_len,
3779                                                          video_index);
3780                if (newmode) {
3781                        newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3782                        drm_mode_probed_add(connector, newmode);
3783                        modes++;
3784                }
3785        }
3786
3787        return modes;
3788}
3789
3790/*
3791 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3792 * @connector: connector corresponding to the HDMI sink
3793 * @db: start of the CEA vendor specific block
3794 * @len: length of the CEA block payload, ie. one can access up to db[len]
3795 *
3796 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3797 * also adds the stereo 3d modes when applicable.
3798 */
3799static int
3800do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3801                   const u8 *video_db, u8 video_len)
3802{
3803        struct drm_display_info *info = &connector->display_info;
3804        int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3805        u8 vic_len, hdmi_3d_len = 0;
3806        u16 mask;
3807        u16 structure_all;
3808
3809        if (len < 8)
3810                goto out;
3811
3812        /* no HDMI_Video_Present */
3813        if (!(db[8] & (1 << 5)))
3814                goto out;
3815
3816        /* Latency_Fields_Present */
3817        if (db[8] & (1 << 7))
3818                offset += 2;
3819
3820        /* I_Latency_Fields_Present */
3821        if (db[8] & (1 << 6))
3822                offset += 2;
3823
3824        /* the declared length is not long enough for the 2 first bytes
3825         * of additional video format capabilities */
3826        if (len < (8 + offset + 2))
3827                goto out;
3828
3829        /* 3D_Present */
3830        offset++;
3831        if (db[8 + offset] & (1 << 7)) {
3832                modes += add_hdmi_mandatory_stereo_modes(connector);
3833
3834                /* 3D_Multi_present */
3835                multi_present = (db[8 + offset] & 0x60) >> 5;
3836        }
3837
3838        offset++;
3839        vic_len = db[8 + offset] >> 5;
3840        hdmi_3d_len = db[8 + offset] & 0x1f;
3841
3842        for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3843                u8 vic;
3844
3845                vic = db[9 + offset + i];
3846                modes += add_hdmi_mode(connector, vic);
3847        }
3848        offset += 1 + vic_len;
3849
3850        if (multi_present == 1)
3851                multi_len = 2;
3852        else if (multi_present == 2)
3853                multi_len = 4;
3854        else
3855                multi_len = 0;
3856
3857        if (len < (8 + offset + hdmi_3d_len - 1))
3858                goto out;
3859
3860        if (hdmi_3d_len < multi_len)
3861                goto out;
3862
3863        if (multi_present == 1 || multi_present == 2) {
3864                /* 3D_Structure_ALL */
3865                structure_all = (db[8 + offset] << 8) | db[9 + offset];
3866
3867                /* check if 3D_MASK is present */
3868                if (multi_present == 2)
3869                        mask = (db[10 + offset] << 8) | db[11 + offset];
3870                else
3871                        mask = 0xffff;
3872
3873                for (i = 0; i < 16; i++) {
3874                        if (mask & (1 << i))
3875                                modes += add_3d_struct_modes(connector,
3876                                                structure_all,
3877                                                video_db,
3878                                                video_len, i);
3879                }
3880        }
3881
3882        offset += multi_len;
3883
3884        for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3885                int vic_index;
3886                struct drm_display_mode *newmode = NULL;
3887                unsigned int newflag = 0;
3888                bool detail_present;
3889
3890                detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3891
3892                if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3893                        break;
3894
3895                /* 2D_VIC_order_X */
3896                vic_index = db[8 + offset + i] >> 4;
3897
3898                /* 3D_Structure_X */
3899                switch (db[8 + offset + i] & 0x0f) {
3900                case 0:
3901                        newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3902                        break;
3903                case 6:
3904                        newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3905                        break;
3906                case 8:
3907                        /* 3D_Detail_X */
3908                        if ((db[9 + offset + i] >> 4) == 1)
3909                                newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3910                        break;
3911                }
3912
3913                if (newflag != 0) {
3914                        newmode = drm_display_mode_from_vic_index(connector,
3915                                                                  video_db,
3916                                                                  video_len,
3917                                                                  vic_index);
3918
3919                        if (newmode) {
3920                                newmode->flags |= newflag;
3921                                drm_mode_probed_add(connector, newmode);
3922                                modes++;
3923                        }
3924                }
3925
3926                if (detail_present)
3927                        i++;
3928        }
3929
3930out:
3931        if (modes > 0)
3932                info->has_hdmi_infoframe = true;
3933        return modes;
3934}
3935
3936static int
3937cea_db_payload_len(const u8 *db)
3938{
3939        return db[0] & 0x1f;
3940}
3941
3942static int
3943cea_db_extended_tag(const u8 *db)
3944{
3945        return db[1];
3946}
3947
3948static int
3949cea_db_tag(const u8 *db)
3950{
3951        return db[0] >> 5;
3952}
3953
3954static int
3955cea_revision(const u8 *cea)
3956{
3957        return cea[1];
3958}
3959
3960static int
3961cea_db_offsets(const u8 *cea, int *start, int *end)
3962{
3963        /* DisplayID CTA extension blocks and top-level CEA EDID
3964         * block header definitions differ in the following bytes:
3965         *   1) Byte 2 of the header specifies length differently,
3966         *   2) Byte 3 is only present in the CEA top level block.
3967         *
3968         * The different definitions for byte 2 follow.
3969         *
3970         * DisplayID CTA extension block defines byte 2 as:
3971         *   Number of payload bytes
3972         *
3973         * CEA EDID block defines byte 2 as:
3974         *   Byte number (decimal) within this block where the 18-byte
3975         *   DTDs begin. If no non-DTD data is present in this extension
3976         *   block, the value should be set to 04h (the byte after next).
3977         *   If set to 00h, there are no DTDs present in this block and
3978         *   no non-DTD data.
3979         */
3980        if (cea[0] == DATA_BLOCK_CTA) {
3981                *start = 3;
3982                *end = *start + cea[2];
3983        } else if (cea[0] == CEA_EXT) {
3984                /* Data block offset in CEA extension block */
3985                *start = 4;
3986                *end = cea[2];
3987                if (*end == 0)
3988                        *end = 127;
3989                if (*end < 4 || *end > 127)
3990                        return -ERANGE;
3991        } else {
3992                return -EOPNOTSUPP;
3993        }
3994
3995        return 0;
3996}
3997
3998static bool cea_db_is_hdmi_vsdb(const u8 *db)
3999{
4000        int hdmi_id;

4001
4002        if (cea_db_tag(db) != VENDOR_BLOCK)
4003                return false;
4004
4005        if (cea_db_payload_len(db) < 5)
4006                return false;
4007
4008        hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
4009
4010        return hdmi_id == HDMI_IEEE_OUI;
4011}
4012
4013static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
4014{
4015        unsigned int oui;
4016
4017        if (cea_db_tag(db) != VENDOR_BLOCK)
4018                return false;
4019
4020        if (cea_db_payload_len(db) < 7)
4021                return false;
4022
4023        oui = db[3] << 16 | db[2] << 8 | db[1];
4024
4025        return oui == HDMI_FORUM_IEEE_OUI;
4026}
4027
4028static bool cea_db_is_vcdb(const u8 *db)
4029{
4030        if (cea_db_tag(db) != USE_EXTENDED_TAG)
4031                return false;
4032
4033        if (cea_db_payload_len(db) != 2)
4034                return false;
4035
4036        if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
4037                return false;
4038
4039        return true;
4040}
4041
4042static bool cea_db_is_y420cmdb(const u8 *db)
4043{
4044        if (cea_db_tag(db) != USE_EXTENDED_TAG)
4045                return false;
4046
4047        if (!cea_db_payload_len(db))
4048                return false;
4049
4050        if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
4051                return false;
4052
4053        return true;
4054}
4055
4056static bool cea_db_is_y420vdb(const u8 *db)
4057{
4058        if (cea_db_tag(db) != USE_EXTENDED_TAG)
4059                return false;
4060
4061        if (!cea_db_payload_len(db))
4062                return false;
4063
4064        if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
4065                return false;
4066
4067        return true;
4068}
4069
4070#define for_each_cea_db(cea, i, start, end) \
4071        for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
4072
4073static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
4074                                      const u8 *db)
4075{
4076        struct drm_display_info *info = &connector->display_info;
4077        struct drm_hdmi_info *hdmi = &info->hdmi;
4078        u8 map_len = cea_db_payload_len(db) - 1;
4079        u8 count;
4080        u64 map = 0;
4081
4082        if (map_len == 0) {
4083                /* All CEA modes support ycbcr420 sampling also.*/
4084                hdmi->y420_cmdb_map = U64_MAX;
4085                info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4086                return;
4087        }
4088
4089        /*
4090         * This map indicates which of the existing CEA block modes
4091         * from VDB can support YCBCR420 output too. So if bit=0 is
4092         * set, first mode from VDB can support YCBCR420 output too.
4093         * We will parse and keep this map, before parsing VDB itself
4094         * to avoid going through the same block again and again.
4095         *
4096         * Spec is not clear about max possible size of this block.
4097         * Clamping max bitmap block size at 8 bytes. Every byte can
4098         * address 8 CEA modes, in this way this map can address
4099         * 8*8 = first 64 SVDs.
4100         */
4101        if (WARN_ON_ONCE(map_len > 8))
4102                map_len = 8;
4103
4104        for (count = 0; count < map_len; count++)
4105                map |= (u64)db[2 + count] << (8 * count);
4106
4107        if (map)
4108                info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4109
4110        hdmi->y420_cmdb_map = map;
4111}
4112
4113static int
4114add_cea_modes(struct drm_connector *connector, struct edid *edid)
4115{
4116        const u8 *cea = drm_find_cea_extension(edid);
4117        const u8 *db, *hdmi = NULL, *video = NULL;
4118        u8 dbl, hdmi_len, video_len = 0;
4119        int modes = 0;
4120
4121        if (cea && cea_revision(cea) >= 3) {
4122                int i, start, end;
4123
4124                if (cea_db_offsets(cea, &start, &end))
4125                        return 0;
4126
4127                for_each_cea_db(cea, i, start, end) {
4128                        db = &cea[i];
4129                        dbl = cea_db_payload_len(db);
4130
4131                        if (cea_db_tag(db) == VIDEO_BLOCK) {
4132                                video = db + 1;
4133                                video_len = dbl;
4134                                modes += do_cea_modes(connector, video, dbl);
4135                        } else if (cea_db_is_hdmi_vsdb(db)) {
4136                                hdmi = db;
4137                                hdmi_len = dbl;
4138                        } else if (cea_db_is_y420vdb(db)) {
4139                                const u8 *vdb420 = &db[2];
4140
4141                                /* Add 4:2:0(only) modes present in EDID */
4142                                modes += do_y420vdb_modes(connector,
4143                                                          vdb420,
4144                                                          dbl - 1);
4145                        }
4146                }
4147        }
4148
4149        /*
4150         * We parse the HDMI VSDB after having added the cea modes as we will
4151         * be patching their flags when the sink supports stereo 3D.
4152         */
4153        if (hdmi)
4154                modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
4155                                            video_len);
4156
4157        return modes;
4158}
4159
4160static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
4161{
4162        const struct drm_display_mode *cea_mode;
4163        int clock1, clock2, clock;
4164        u8 vic;
4165        const char *type;
4166
4167        /*
4168         * allow 5kHz clock difference either way to account for
4169         * the 10kHz clock resolution limit of detailed timings.
4170         */
4171        vic = drm_match_cea_mode_clock_tolerance(mode, 5);
4172        if (drm_valid_cea_vic(vic)) {
4173                type = "CEA";
4174                cea_mode = cea_mode_for_vic(vic);
4175                clock1 = cea_mode->clock;
4176                clock2 = cea_mode_alternate_clock(cea_mode);
4177        } else {
4178                vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
4179                if (drm_valid_hdmi_vic(vic)) {
4180                        type = "HDMI";
4181                        cea_mode = &edid_4k_modes[vic];
4182                        clock1 = cea_mode->clock;
4183                        clock2 = hdmi_mode_alternate_clock(cea_mode);
4184                } else {
4185                        return;
4186                }
4187        }
4188
4189        /* pick whichever is closest */
4190        if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
4191                clock = clock1;
4192        else
4193                clock = clock2;
4194
4195        if (mode->clock == clock)
4196                return;
4197
4198        DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
4199                  type, vic, mode->clock, clock);
4200        mode->clock = clock;
4201}
4202
4203static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
4204{
4205        if (cea_db_tag(db) != USE_EXTENDED_TAG)
4206                return false;
4207
4208        if (db[1] != HDR_STATIC_METADATA_BLOCK)
4209                return false;
4210
4211        if (cea_db_payload_len(db) < 3)
4212                return false;
4213
4214        return true;
4215}
4216
4217static uint8_t eotf_supported(const u8 *edid_ext)
4218{
4219        return edid_ext[2] &
4220                (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
4221                 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
4222                 BIT(HDMI_EOTF_SMPTE_ST2084) |
4223                 BIT(HDMI_EOTF_BT_2100_HLG));
4224}
4225
4226static uint8_t hdr_metadata_type(const u8 *edid_ext)
4227{
4228        return edid_ext[3] &
4229                BIT(HDMI_STATIC_METADATA_TYPE1);
4230}
4231
4232static void
4233drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
4234{
4235        u16 len;
4236
4237        len = cea_db_payload_len(db);
4238
4239        connector->hdr_sink_metadata.hdmi_type1.eotf =
4240                                                eotf_supported(db);
4241        connector->hdr_sink_metadata.hdmi_type1.metadata_type =
4242                                                hdr_metadata_type(db);
4243
4244        if (len >= 4)
4245                connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
4246        if (len >= 5)
4247                connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
4248        if (len >= 6)
4249                connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
4250}
4251
4252static void
4253drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
4254{
4255        u8 len = cea_db_payload_len(db);
4256
4257        if (len >= 6 && (db[6] & (1 << 7)))
4258                connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
4259        if (len >= 8) {
4260                connector->latency_present[0] = db[8] >> 7;
4261                connector->latency_present[1] = (db[8] >> 6) & 1;
4262        }
4263        if (len >= 9)
4264                connector->video_latency[0] = db[9];
4265        if (len >= 10)
4266                connector->audio_latency[0] = db[10];
4267        if (len >= 11)
4268                connector->video_latency[1] = db[11];
4269        if (len >= 12)
4270                connector->audio_latency[1] = db[12];
4271
4272        DRM_DEBUG_KMS("HDMI: latency present %d %d, "
4273                      "video latency %d %d, "
4274                      "audio latency %d %d\n",
4275                      connector->latency_present[0],
4276                      connector->latency_present[1],
4277                      connector->video_latency[0],
4278                      connector->video_latency[1],
4279                      connector->audio_latency[0],
4280                      connector->audio_latency[1]);
4281}
4282
4283static void
4284monitor_name(struct detailed_timing *t, void *data)
4285{
4286        if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
4287                *(u8 **)data = t->data.other_data.data.str.str;
4288}
4289
4290static int get_monitor_name(struct edid *edid, char name[13])
4291{
4292        char *edid_name = NULL;
4293        int mnl;
4294
4295        if (!edid || !name)
4296                return 0;
4297
4298        drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
4299        for (mnl = 0; edid_name && mnl < 13; mnl++) {
4300                if (edid_name[mnl] == 0x0a)
4301                        break;
4302
4303                name[mnl] = edid_name[mnl];
4304        }
4305
4306        return mnl;
4307}
4308
4309/**
4310 * drm_edid_get_monitor_name - fetch the monitor name from the edid
4311 * @edid: monitor EDID information
4312 * @name: pointer to a character array to hold the name of the monitor
4313 * @bufsize: The size of the name buffer (should be at least 14 chars.)
4314 *
4315 */
4316void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
4317{
4318        int name_length;
4319        char buf[13];
4320        
4321        if (bufsize <= 0)
4322                return;
4323
4324        name_length = min(get_monitor_name(edid, buf), bufsize - 1);
4325        memcpy(name, buf, name_length);
4326        name[name_length] = '\0';
4327}
4328EXPORT_SYMBOL(drm_edid_get_monitor_name);
4329
4330static void clear_eld(struct drm_connector *connector)
4331{
4332        memset(connector->eld, 0, sizeof(connector->eld));
4333
4334        connector->latency_present[0] = false;
4335        connector->latency_present[1] = false;
4336        connector->video_latency[0] = 0;
4337        connector->audio_latency[0] = 0;
4338        connector->video_latency[1] = 0;
4339        connector->audio_latency[1] = 0;
4340}
4341
4342/*
4343 * drm_edid_to_eld - build ELD from EDID
4344 * @connector: connector corresponding to the HDMI/DP sink
4345 * @edid: EDID to parse
4346 *
4347 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
4348 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
4349 */
4350static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
4351{
4352        uint8_t *eld = connector->eld;
4353        u8 *cea;
4354        u8 *db;
4355        int total_sad_count = 0;
4356        int mnl;
4357        int dbl;
4358
4359        clear_eld(connector);
4360
4361        if (!edid)
4362                return;
4363
4364        cea = drm_find_cea_extension(edid);
4365        if (!cea) {
4366                DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
4367                return;
4368        }
4369
4370        mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
4371        DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
4372
4373        eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
4374        eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
4375
4376        eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
4377
4378        eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
4379        eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
4380        eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
4381        eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
4382
4383        if (cea_revision(cea) >= 3) {
4384                int i, start, end;
4385
4386                if (cea_db_offsets(cea, &start, &end)) {
4387                        start = 0;
4388                        end = 0;
4389                }
4390
4391                for_each_cea_db(cea, i, start, end) {
4392                        db = &cea[i];
4393                        dbl = cea_db_payload_len(db);
4394
4395                        switch (cea_db_tag(db)) {
4396                                int sad_count;
4397
4398                        case AUDIO_BLOCK:
4399                                /* Audio Data Block, contains SADs */
4400                                sad_count = min(dbl / 3, 15 - total_sad_count);
4401                                if (sad_count >= 1)
4402                                        memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
4403                                               &db[1], sad_count * 3);
4404                                total_sad_count += sad_count;
4405                                break;
4406                        case SPEAKER_BLOCK:
4407                                /* Speaker Allocation Data Block */
4408                                if (dbl >= 1)
4409                                        eld[DRM_ELD_SPEAKER] = db[1];
4410                                break;
4411                        case VENDOR_BLOCK:
4412                                /* HDMI Vendor-Specific Data Block */
4413                                if (cea_db_is_hdmi_vsdb(db))
4414                                        drm_parse_hdmi_vsdb_audio(connector, db);
4415                                break;
4416                        default:
4417                                break;
4418                        }
4419                }
4420        }
4421        eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
4422
4423        if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4424            connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4425                eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4426        else
4427                eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
4428
4429        eld[DRM_ELD_BASELINE_ELD_LEN] =
4430                DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
4431
4432        DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
4433                      drm_eld_size(eld), total_sad_count);
4434}
4435
4436/**
4437 * drm_edid_to_sad - extracts SADs from EDID
4438 * @edid: EDID to parse
4439 * @sads: pointer that will be set to the extracted SADs
4440 *
4441 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
4442 *
4443 * Note: The returned pointer needs to be freed using kfree().
4444 *
4445 * Return: The number of found SADs or negative number on error.
4446 */
4447int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
4448{
4449        int count = 0;
4450        int i, start, end, dbl;
4451        u8 *cea;
4452
4453        cea = drm_find_cea_extension(edid);
4454        if (!cea) {
4455                DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4456                return 0;
4457        }
4458
4459        if (cea_revision(cea) < 3) {
4460                DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4461                return 0;
4462        }
4463
4464        if (cea_db_offsets(cea, &start, &end)) {
4465                DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4466                return -EPROTO;
4467        }
4468
4469        for_each_cea_db(cea, i, start, end) {
4470                u8 *db = &cea[i];
4471
4472                if (cea_db_tag(db) == AUDIO_BLOCK) {
4473                        int j;
4474                        dbl = cea_db_payload_len(db);
4475
4476                        count = dbl / 3; /* SAD is 3B */
4477                        *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4478                        if (!*sads)
4479                                return -ENOMEM;
4480                        for (j = 0; j < count; j++) {
4481                                u8 *sad = &db[1 + j * 3];
4482
4483                                (*sads)[j].format = (sad[0] & 0x78) >> 3;
4484                                (*sads)[j].channels = sad[0] & 0x7;
4485                                (*sads)[j].freq = sad[1] & 0x7F;
4486                                (*sads)[j].byte2 = sad[2];
4487                        }
4488                        break;
4489                }
4490        }
4491
4492        return count;
4493}
4494EXPORT_SYMBOL(drm_edid_to_sad);
4495
4496/**
4497 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4498 * @edid: EDID to parse
4499 * @sadb: pointer to the speaker block
4500 *
4501 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4502 *
4503 * Note: The returned pointer needs to be freed using kfree().
4504 *
4505 * Return: The number of found Speaker Allocation Blocks or negative number on
4506 * error.
4507 */
4508int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4509{
4510        int count = 0;
4511        int i, start, end, dbl;
4512        const u8 *cea;
4513
4514        cea = drm_find_cea_extension(edid);
4515        if (!cea) {
4516                DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4517                return 0;
4518        }
4519
4520        if (cea_revision(cea) < 3) {
4521                DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4522                return 0;
4523        }
4524
4525        if (cea_db_offsets(cea, &start, &end)) {
4526                DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4527                return -EPROTO;
4528        }
4529
4530        for_each_cea_db(cea, i, start, end) {
4531                const u8 *db = &cea[i];
4532
4533                if (cea_db_tag(db) == SPEAKER_BLOCK) {
4534                        dbl = cea_db_payload_len(db);
4535
4536                        /* Speaker Allocation Data Block */
4537                        if (dbl == 3) {
4538                                *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4539                                if (!*sadb)
4540                                        return -ENOMEM;
4541                                count = dbl;
4542                                break;
4543                        }
4544                }
4545        }
4546
4547        return count;
4548}
4549EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4550
4551/**
4552 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4553 * @connector: connector associated with the HDMI/DP sink
4554 * @mode: the display mode
4555 *
4556 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4557 * the sink doesn't support audio or video.
4558 */
4559int drm_av_sync_delay(struct drm_connector *connector,
4560                      const struct drm_display_mode *mode)
4561{
4562        int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4563        int a, v;
4564
4565        if (!connector->latency_present[0])
4566                return 0;
4567        if (!connector->latency_present[1])
4568                i = 0;
4569
4570        a = connector->audio_latency[i];
4571        v = connector->video_latency[i];
4572
4573        /*
4574         * HDMI/DP sink doesn't support audio or video?
4575         */
4576        if (a == 255 || v == 255)
4577                return 0;
4578
4579        /*
4580         * Convert raw EDID values to millisecond.
4581         * Treat unknown latency as 0ms.
4582         */
4583        if (a)
4584                a = min(2 * (a - 1), 500);
4585        if (v)
4586                v = min(2 * (v - 1), 500);
4587
4588        return max(v - a, 0);
4589}
4590EXPORT_SYMBOL(drm_av_sync_delay);
4591
4592/**
4593 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4594 * @edid: monitor EDID information
4595 *
4596 * Parse the CEA extension according to CEA-861-B.
4597 *
4598 * Return: True if the monitor is HDMI, false if not or unknown.
4599 */
4600bool drm_detect_hdmi_monitor(struct edid *edid)
4601{
4602        u8 *edid_ext;
4603        int i;
4604        int start_offset, end_offset;
4605
4606        edid_ext = drm_find_cea_extension(edid);
4607        if (!edid_ext)
4608                return false;
4609
4610        if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4611                return false;
4612
4613        /*
4614         * Because HDMI identifier is in Vendor Specific Block,
4615         * search it from all data blocks of CEA extension.
4616         */
4617        for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4618                if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4619                        return true;
4620        }
4621
4622        return false;
4623}
4624EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4625
4626/**
4627 * drm_detect_monitor_audio - check monitor audio capability
4628 * @edid: EDID block to scan
4629 *
4630 * Monitor should have CEA extension block.
4631 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4632 * audio' only. If there is any audio extension block and supported
4633 * audio format, assume at least 'basic audio' support, even if 'basic
4634 * audio' is not defined in EDID.
4635 *
4636 * Return: True if the monitor supports audio, false otherwise.
4637 */
4638bool drm_detect_monitor_audio(struct edid *edid)
4639{
4640        u8 *edid_ext;
4641        int i, j;
4642        bool has_audio = false;
4643        int start_offset, end_offset;
4644
4645        edid_ext = drm_find_cea_extension(edid);
4646        if (!edid_ext)
4647                goto end;
4648
4649        has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4650
4651        if (has_audio) {
4652                DRM_DEBUG_KMS("Monitor has basic audio support\n");
4653                goto end;
4654        }
4655
4656        if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4657                goto end;
4658
4659        for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4660                if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4661                        has_audio = true;
4662                        for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4663                                DRM_DEBUG_KMS("CEA audio format %d\n",
4664                                              (edid_ext[i + j] >> 3) & 0xf);
4665                        goto end;
4666                }
4667        }
4668end:
4669        return has_audio;
4670}
4671EXPORT_SYMBOL(drm_detect_monitor_audio);
4672
4673
4674/**
4675 * drm_default_rgb_quant_range - default RGB quantization range
4676 * @mode: display mode
4677 *
4678 * Determine the default RGB quantization range for the mode,
4679 * as specified in CEA-861.
4680 *
4681 * Return: The default RGB quantization range for the mode
4682 */
4683enum hdmi_quantization_range
4684drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4685{
4686        /* All CEA modes other than VIC 1 use limited quantization range. */
4687        return drm_match_cea_mode(mode) > 1 ?
4688                HDMI_QUANTIZATION_RANGE_LIMITED :
4689                HDMI_QUANTIZATION_RANGE_FULL;
4690}
4691EXPORT_SYMBOL(drm_default_rgb_quant_range);
4692
4693static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
4694{
4695        struct drm_display_info *info = &connector->display_info;
4696
4697        DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
4698
4699        if (db[2] & EDID_CEA_VCDB_QS)
4700                info->rgb_quant_range_selectable = true;
4701}
4702
4703static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4704                                               const u8 *db)
4705{
4706        u8 dc_mask;
4707        struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4708
4709        dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4710        hdmi->y420_dc_modes = dc_mask;
4711}
4712
4713static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4714                                 const u8 *hf_vsdb)
4715{
4716        struct drm_display_info *display = &connector->display_info;
4717        struct drm_hdmi_info *hdmi = &display->hdmi;
4718
4719        display->has_hdmi_infoframe = true;
4720
4721        if (hf_vsdb[6] & 0x80) {
4722                hdmi->scdc.supported = true;
4723                if (hf_vsdb[6] & 0x40)
4724                        hdmi->scdc.read_request = true;
4725        }
4726
4727        /*
4728         * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4729         * And as per the spec, three factors confirm this:
4730         * * Availability of a HF-VSDB block in EDID (check)
4731         * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4732         * * SCDC support available (let's check)
4733         * Lets check it out.
4734         */
4735
4736        if (hf_vsdb[5]) {
4737                /* max clock is 5000 KHz times block value */
4738                u32 max_tmds_clock = hf_vsdb[5] * 5000;
4739                struct drm_scdc *scdc = &hdmi->scdc;
4740
4741                if (max_tmds_clock > 340000) {
4742                        display->max_tmds_clock = max_tmds_clock;
4743                        DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4744                                display->max_tmds_clock);
4745                }
4746
4747                if (scdc->supported) {
4748                        scdc->scrambling.supported = true;
4749
4750                        /* Few sinks support scrambling for clocks < 340M */
4751                        if ((hf_vsdb[6] & 0x8))
4752                                scdc->scrambling.low_rates = true;
4753                }
4754        }
4755
4756        drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
4757}
4758
4759static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4760                                           const u8 *hdmi)
4761{
4762        struct drm_display_info *info = &connector->display_info;
4763        unsigned int dc_bpc = 0;
4764
4765        /* HDMI supports at least 8 bpc */
4766        info->bpc = 8;
4767
4768        if (cea_db_payload_len(hdmi) < 6)
4769                return;
4770
4771        if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4772                dc_bpc = 10;
4773                info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4774                DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4775                          connector->name);
4776        }
4777
4778        if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4779                dc_bpc = 12;
4780                info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4781                DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4782                          connector->name);
4783        }
4784
4785        if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4786                dc_bpc = 16;
4787                info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4788                DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4789                          connector->name);
4790        }
4791
4792        if (dc_bpc == 0) {
4793                DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4794                          connector->name);
4795                return;
4796        }
4797
4798        DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4799                  connector->name, dc_bpc);
4800        info->bpc = dc_bpc;
4801
4802        /*
4803         * Deep color support mandates RGB444 support for all video
4804         * modes and forbids YCRCB422 support for all video modes per
4805         * HDMI 1.3 spec.
4806         */
4807        info->color_formats = DRM_COLOR_FORMAT_RGB444;
4808
4809        /* YCRCB444 is optional according to spec. */
4810        if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4811                info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4812                DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4813                          connector->name);
4814        }
4815
4816        /*
4817         * Spec says that if any deep color mode is supported at all,
4818         * then deep color 36 bit must be supported.
4819         */
4820        if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4821                DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4822                          connector->name);
4823        }
4824}
4825
4826static void
4827drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4828{
4829        struct drm_display_info *info = &connector->display_info;
4830        u8 len = cea_db_payload_len(db);
4831
4832        if (len >= 6)
4833                info->dvi_dual = db[6] & 1;
4834        if (len >= 7)
4835                info->max_tmds_clock = db[7] * 5000;
4836
4837        DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4838                      "max TMDS clock %d kHz\n",
4839                      info->dvi_dual,
4840                      info->max_tmds_clock);
4841
4842        drm_parse_hdmi_deep_color_info(connector, db);
4843}
4844
4845static void drm_parse_cea_ext(struct drm_connector *connector,
4846                              const struct edid *edid)
4847{
4848        struct drm_display_info *info = &connector->display_info;
4849        const u8 *edid_ext;
4850        int i, start, end;
4851
4852        edid_ext = drm_find_cea_extension(edid);
4853        if (!edid_ext)
4854                return;
4855
4856        info->cea_rev = edid_ext[1];
4857
4858        /* The existence of a CEA block should imply RGB support */
4859        info->color_formats = DRM_COLOR_FORMAT_RGB444;
4860        if (edid_ext[3] & EDID_CEA_YCRCB444)
4861                info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4862        if (edid_ext[3] & EDID_CEA_YCRCB422)
4863                info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4864
4865        if (cea_db_offsets(edid_ext, &start, &end))
4866                return;
4867
4868        for_each_cea_db(edid_ext, i, start, end) {
4869                const u8 *db = &edid_ext[i];
4870
4871                if (cea_db_is_hdmi_vsdb(db))
4872                        drm_parse_hdmi_vsdb_video(connector, db);
4873                if (cea_db_is_hdmi_forum_vsdb(db))
4874                        drm_parse_hdmi_forum_vsdb(connector, db);
4875                if (cea_db_is_y420cmdb(db))
4876                        drm_parse_y420cmdb_bitmap(connector, db);
4877                if (cea_db_is_vcdb(db))
4878                        drm_parse_vcdb(connector, db);
4879                if (cea_db_is_hdmi_hdr_metadata_block(db))
4880                        drm_parse_hdr_metadata_block(connector, db);
4881        }
4882}
4883
4884/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
4885 * all of the values which would have been set from EDID
4886 */
4887void
4888drm_reset_display_info(struct drm_connector *connector)
4889{
4890        struct drm_display_info *info = &connector->display_info;
4891
4892        info->width_mm = 0;
4893        info->height_mm = 0;
4894
4895        info->bpc = 0;
4896        info->color_formats = 0;
4897        info->cea_rev = 0;
4898        info->max_tmds_clock = 0;
4899        info->dvi_dual = false;
4900        info->has_hdmi_infoframe = false;
4901        info->rgb_quant_range_selectable = false;
4902        memset(&info->hdmi, 0, sizeof(info->hdmi));
4903
4904        info->non_desktop = 0;
4905}
4906
4907u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
4908{
4909        struct drm_display_info *info = &connector->display_info;
4910
4911        u32 quirks = edid_get_quirks(edid);
4912
4913        drm_reset_display_info(connector);
4914
4915        info->width_mm = edid->width_cm * 10;
4916        info->height_mm = edid->height_cm * 10;
4917
4918        info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4919
4920        DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
4921
4922        if (edid->revision < 3)
4923                return quirks;
4924
4925        if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4926                return quirks;
4927
4928        drm_parse_cea_ext(connector, edid);
4929
4930        /*
4931         * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4932         *
4933         * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4934         * tells us to assume 8 bpc color depth if the EDID doesn't have
4935         * extensions which tell otherwise.
4936         */
4937        if (info->bpc == 0 && edid->revision == 3 &&
4938            edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
4939                info->bpc = 8;
4940                DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4941                          connector->name, info->bpc);
4942        }
4943
4944        /* Only defined for 1.4 with digital displays */
4945        if (edid->revision < 4)
4946                return quirks;
4947
4948        switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4949        case DRM_EDID_DIGITAL_DEPTH_6:
4950                info->bpc = 6;
4951                break;
4952        case DRM_EDID_DIGITAL_DEPTH_8:
4953                info->bpc = 8;
4954                break;
4955        case DRM_EDID_DIGITAL_DEPTH_10:
4956                info->bpc = 10;
4957                break;
4958        case DRM_EDID_DIGITAL_DEPTH_12:
4959                info->bpc = 12;
4960                break;
4961        case DRM_EDID_DIGITAL_DEPTH_14:
4962                info->bpc = 14;
4963                break;
4964        case DRM_EDID_DIGITAL_DEPTH_16:
4965                info->bpc = 16;
4966                break;
4967        case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4968        default:
4969                info->bpc = 0;
4970                break;
4971        }
4972
4973        DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4974                          connector->name, info->bpc);
4975
4976        info->color_formats |= DRM_COLOR_FORMAT_RGB444;
4977        if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4978                info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4979        if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4980                info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4981        return quirks;
4982}
4983
4984static int validate_displayid(u8 *displayid, int length, int idx)
4985{
4986        int i;
4987        u8 csum = 0;
4988        struct displayid_hdr *base;
4989
4990        base = (struct displayid_hdr *)&displayid[idx];
4991
4992        DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4993                      base->rev, base->bytes, base->prod_id, base->ext_count);
4994
4995        if (base->bytes + 5 > length - idx)
4996                return -EINVAL;
4997        for (i = idx; i <= base->bytes + 5; i++) {
4998                csum += displayid[i];
4999        }
5000        if (csum) {

5001                DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
5002                return -EINVAL;
5003        }
5004        return 0;
5005}
5006
5007static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
5008                                                            struct displayid_detailed_timings_1 *timings)
5009{
5010        struct drm_display_mode *mode;
5011        unsigned pixel_clock = (timings->pixel_clock[0] |
5012                                (timings->pixel_clock[1] << 8) |
5013                                (timings->pixel_clock[2] << 16)) + 1;
5014        unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
5015        unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
5016        unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
5017        unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
5018        unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
5019        unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
5020        unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
5021        unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
5022        bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
5023        bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
5024        mode = drm_mode_create(dev);
5025        if (!mode)
5026                return NULL;
5027
5028        mode->clock = pixel_clock * 10;
5029        mode->hdisplay = hactive;
5030        mode->hsync_start = mode->hdisplay + hsync;
5031        mode->hsync_end = mode->hsync_start + hsync_width;
5032        mode->htotal = mode->hdisplay + hblank;
5033
5034        mode->vdisplay = vactive;
5035        mode->vsync_start = mode->vdisplay + vsync;
5036        mode->vsync_end = mode->vsync_start + vsync_width;
5037        mode->vtotal = mode->vdisplay + vblank;
5038
5039        mode->flags = 0;
5040        mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
5041        mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
5042        mode->type = DRM_MODE_TYPE_DRIVER;
5043
5044        if (timings->flags & 0x80)
5045                mode->type |= DRM_MODE_TYPE_PREFERRED;
5046        mode->vrefresh = drm_mode_vrefresh(mode);
5047        drm_mode_set_name(mode);
5048
5049        return mode;
5050}
5051
5052static int add_displayid_detailed_1_modes(struct drm_connector *connector,
5053                                          struct displayid_block *block)
5054{
5055        struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
5056        int i;
5057        int num_timings;
5058        struct drm_display_mode *newmode;
5059        int num_modes = 0;
5060        /* blocks must be multiple of 20 bytes length */
5061        if (block->num_bytes % 20)
5062                return 0;
5063
5064        num_timings = block->num_bytes / 20;
5065        for (i = 0; i < num_timings; i++) {
5066                struct displayid_detailed_timings_1 *timings = &det->timings[i];
5067
5068                newmode = drm_mode_displayid_detailed(connector->dev, timings);
5069                if (!newmode)
5070                        continue;
5071
5072                drm_mode_probed_add(connector, newmode);
5073                num_modes++;
5074        }
5075        return num_modes;
5076}
5077
5078static int add_displayid_detailed_modes(struct drm_connector *connector,
5079                                        struct edid *edid)
5080{
5081        u8 *displayid;
5082        int ret;
5083        int idx = 1;
5084        int length = EDID_LENGTH;
5085        struct displayid_block *block;
5086        int num_modes = 0;
5087
5088        displayid = drm_find_displayid_extension(edid);
5089        if (!displayid)
5090                return 0;
5091
5092        ret = validate_displayid(displayid, length, idx);
5093        if (ret)
5094                return 0;
5095
5096        idx += sizeof(struct displayid_hdr);
5097        for_each_displayid_db(displayid, block, idx, length) {
5098                switch (block->tag) {
5099                case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5100                        num_modes += add_displayid_detailed_1_modes(connector, block);
5101                        break;
5102                }
5103        }
5104        return num_modes;
5105}
5106
5107/**
5108 * drm_add_edid_modes - add modes from EDID data, if available
5109 * @connector: connector we're probing
5110 * @edid: EDID data
5111 *
5112 * Add the specified modes to the connector's mode list. Also fills out the
5113 * &drm_display_info structure and ELD in @connector with any information which
5114 * can be derived from the edid.
5115 *
5116 * Return: The number of modes added or 0 if we couldn't find any.
5117 */
5118int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
5119{
5120        int num_modes = 0;
5121        u32 quirks;
5122
5123        if (edid == NULL) {
5124                clear_eld(connector);
5125                return 0;
5126        }
5127        if (!drm_edid_is_valid(edid)) {
5128                clear_eld(connector);
5129                dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
5130                         connector->name);
5131                return 0;
5132        }
5133
5134        drm_edid_to_eld(connector, edid);
5135
5136        /*
5137         * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
5138         * To avoid multiple parsing of same block, lets parse that map
5139         * from sink info, before parsing CEA modes.
5140         */
5141        quirks = drm_add_display_info(connector, edid);
5142
5143        /*
5144         * EDID spec says modes should be preferred in this order:
5145         * - preferred detailed mode
5146         * - other detailed modes from base block
5147         * - detailed modes from extension blocks
5148         * - CVT 3-byte code modes
5149         * - standard timing codes
5150         * - established timing codes
5151         * - modes inferred from GTF or CVT range information
5152         *
5153         * We get this pretty much right.
5154         *
5155         * XXX order for additional mode types in extension blocks?
5156         */
5157        num_modes += add_detailed_modes(connector, edid, quirks);
5158        num_modes += add_cvt_modes(connector, edid);
5159        num_modes += add_standard_modes(connector, edid);
5160        num_modes += add_established_modes(connector, edid);
5161        num_modes += add_cea_modes(connector, edid);
5162        num_modes += add_alternate_cea_modes(connector, edid);
5163        num_modes += add_displayid_detailed_modes(connector, edid);
5164        if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
5165                num_modes += add_inferred_modes(connector, edid);
5166
5167        if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
5168                edid_fixup_preferred(connector, quirks);
5169
5170        if (quirks & EDID_QUIRK_FORCE_6BPC)
5171                connector->display_info.bpc = 6;
5172
5173        if (quirks & EDID_QUIRK_FORCE_8BPC)
5174                connector->display_info.bpc = 8;
5175
5176        if (quirks & EDID_QUIRK_FORCE_10BPC)
5177                connector->display_info.bpc = 10;
5178
5179        if (quirks & EDID_QUIRK_FORCE_12BPC)
5180                connector->display_info.bpc = 12;
5181
5182        return num_modes;
5183}
5184EXPORT_SYMBOL(drm_add_edid_modes);
5185
5186/**
5187 * drm_add_modes_noedid - add modes for the connectors without EDID
5188 * @connector: connector we're probing
5189 * @hdisplay: the horizontal display limit
5190 * @vdisplay: the vertical display limit
5191 *
5192 * Add the specified modes to the connector's mode list. Only when the
5193 * hdisplay/vdisplay is not beyond the given limit, it will be added.
5194 *
5195 * Return: The number of modes added or 0 if we couldn't find any.
5196 */
5197int drm_add_modes_noedid(struct drm_connector *connector,
5198                        int hdisplay, int vdisplay)
5199{
5200        int i, count, num_modes = 0;
5201        struct drm_display_mode *mode;
5202        struct drm_device *dev = connector->dev;
5203
5204        count = ARRAY_SIZE(drm_dmt_modes);
5205        if (hdisplay < 0)
5206                hdisplay = 0;
5207        if (vdisplay < 0)
5208                vdisplay = 0;
5209
5210        for (i = 0; i < count; i++) {
5211                const struct drm_display_mode *ptr = &drm_dmt_modes[i];
5212                if (hdisplay && vdisplay) {
5213                        /*
5214                         * Only when two are valid, they will be used to check
5215                         * whether the mode should be added to the mode list of
5216                         * the connector.
5217                         */
5218                        if (ptr->hdisplay > hdisplay ||
5219                                        ptr->vdisplay > vdisplay)
5220                                continue;
5221                }
5222                if (drm_mode_vrefresh(ptr) > 61)
5223                        continue;
5224                mode = drm_mode_duplicate(dev, ptr);
5225                if (mode) {
5226                        drm_mode_probed_add(connector, mode);
5227                        num_modes++;
5228                }
5229        }
5230        return num_modes;
5231}
5232EXPORT_SYMBOL(drm_add_modes_noedid);
5233
5234/**
5235 * drm_set_preferred_mode - Sets the preferred mode of a connector
5236 * @connector: connector whose mode list should be processed
5237 * @hpref: horizontal resolution of preferred mode
5238 * @vpref: vertical resolution of preferred mode
5239 *
5240 * Marks a mode as preferred if it matches the resolution specified by @hpref
5241 * and @vpref.
5242 */
5243void drm_set_preferred_mode(struct drm_connector *connector,
5244                           int hpref, int vpref)
5245{
5246        struct drm_display_mode *mode;
5247
5248        list_for_each_entry(mode, &connector->probed_modes, head) {
5249                if (mode->hdisplay == hpref &&
5250                    mode->vdisplay == vpref)
5251                        mode->type |= DRM_MODE_TYPE_PREFERRED;
5252        }
5253}
5254EXPORT_SYMBOL(drm_set_preferred_mode);
5255
5256static bool is_hdmi2_sink(struct drm_connector *connector)
5257{
5258        /*
5259         * FIXME: sil-sii8620 doesn't have a connector around when
5260         * we need one, so we have to be prepared for a NULL connector.
5261         */
5262        if (!connector)
5263                return true;
5264
5265        return connector->display_info.hdmi.scdc.supported ||
5266                connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
5267}
5268
5269static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
5270{
5271        return sink_eotf & BIT(output_eotf);
5272}
5273
5274/**
5275 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with
5276 *                                         HDR metadata from userspace
5277 * @frame: HDMI DRM infoframe
5278 * @conn_state: Connector state containing HDR metadata
5279 *
5280 * Return: 0 on success or a negative error code on failure.
5281 */
5282int
5283drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
5284                                    const struct drm_connector_state *conn_state)
5285{
5286        struct drm_connector *connector;
5287        struct hdr_output_metadata *hdr_metadata;
5288        int err;
5289
5290        if (!frame || !conn_state)
5291                return -EINVAL;
5292
5293        connector = conn_state->connector;
5294
5295        if (!conn_state->hdr_output_metadata)
5296                return -EINVAL;
5297
5298        hdr_metadata = conn_state->hdr_output_metadata->data;
5299
5300        if (!hdr_metadata || !connector)
5301                return -EINVAL;
5302
5303        /* Sink EOTF is Bit map while infoframe is absolute values */
5304        if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf,
5305            connector->hdr_sink_metadata.hdmi_type1.eotf)) {
5306                DRM_DEBUG_KMS("EOTF Not Supported\n");
5307                return -EINVAL;
5308        }
5309
5310        err = hdmi_drm_infoframe_init(frame);
5311        if (err < 0)
5312                return err;
5313
5314        frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
5315        frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
5316
5317        BUILD_BUG_ON(sizeof(frame->display_primaries) !=
5318                     sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries));
5319        BUILD_BUG_ON(sizeof(frame->white_point) !=
5320                     sizeof(hdr_metadata->hdmi_metadata_type1.white_point));
5321
5322        memcpy(&frame->display_primaries,
5323               &hdr_metadata->hdmi_metadata_type1.display_primaries,
5324               sizeof(frame->display_primaries));
5325
5326        memcpy(&frame->white_point,
5327               &hdr_metadata->hdmi_metadata_type1.white_point,
5328               sizeof(frame->white_point));
5329
5330        frame->max_display_mastering_luminance =
5331                hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance;
5332        frame->min_display_mastering_luminance =
5333                hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance;
5334        frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall;
5335        frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll;
5336
5337        return 0;
5338}
5339EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
5340
5341static u8 drm_mode_hdmi_vic(struct drm_connector *connector,
5342                            const struct drm_display_mode *mode)
5343{
5344        bool has_hdmi_infoframe = connector ?
5345                connector->display_info.has_hdmi_infoframe : false;
5346
5347        if (!has_hdmi_infoframe)
5348                return 0;
5349
5350        /* No HDMI VIC when signalling 3D video format */
5351        if (mode->flags & DRM_MODE_FLAG_3D_MASK)
5352                return 0;
5353
5354        return drm_match_hdmi_mode(mode);
5355}
5356
5357static u8 drm_mode_cea_vic(struct drm_connector *connector,
5358                           const struct drm_display_mode *mode)
5359{
5360        u8 vic;
5361
5362        /*
5363         * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
5364         * we should send its VIC in vendor infoframes, else send the
5365         * VIC in AVI infoframes. Lets check if this mode is present in
5366         * HDMI 1.4b 4K modes
5367         */
5368        if (drm_mode_hdmi_vic(connector, mode))
5369                return 0;
5370
5371        vic = drm_match_cea_mode(mode);
5372
5373        /*
5374         * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
5375         * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
5376         * have to make sure we dont break HDMI 1.4 sinks.
5377         */
5378        if (!is_hdmi2_sink(connector) && vic > 64)
5379                return 0;
5380
5381        return vic;
5382}
5383
5384/**
5385 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
5386 *                                              data from a DRM display mode
5387 * @frame: HDMI AVI infoframe
5388 * @connector: the connector
5389 * @mode: DRM display mode
5390 *
5391 * Return: 0 on success or a negative error code on failure.
5392 */
5393int
5394drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
5395                                         struct drm_connector *connector,
5396                                         const struct drm_display_mode *mode)
5397{
5398        enum hdmi_picture_aspect picture_aspect;
5399        u8 vic, hdmi_vic;
5400        int err;
5401
5402        if (!frame || !mode)
5403                return -EINVAL;
5404
5405        err = hdmi_avi_infoframe_init(frame);
5406        if (err < 0)
5407                return err;
5408
5409        if (mode->flags & DRM_MODE_FLAG_DBLCLK)
5410                frame->pixel_repeat = 1;
5411
5412        vic = drm_mode_cea_vic(connector, mode);
5413        hdmi_vic = drm_mode_hdmi_vic(connector, mode);
5414
5415        frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5416
5417        /*
5418         * As some drivers don't support atomic, we can't use connector state.
5419         * So just initialize the frame with default values, just the same way
5420         * as it's done with other properties here.
5421         */
5422        frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
5423        frame->itc = 0;
5424
5425        /*
5426         * Populate picture aspect ratio from either
5427         * user input (if specified) or from the CEA/HDMI mode lists.
5428         */
5429        picture_aspect = mode->picture_aspect_ratio;
5430        if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
5431                if (vic)
5432                        picture_aspect = drm_get_cea_aspect_ratio(vic);
5433                else if (hdmi_vic)
5434                        picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
5435        }
5436
5437        /*
5438         * The infoframe can't convey anything but none, 4:3
5439         * and 16:9, so if the user has asked for anything else
5440         * we can only satisfy it by specifying the right VIC.
5441         */
5442        if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
5443                if (vic) {
5444                        if (picture_aspect != drm_get_cea_aspect_ratio(vic))
5445                                return -EINVAL;
5446                } else if (hdmi_vic) {
5447                        if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
5448                                return -EINVAL;
5449                } else {
5450                        return -EINVAL;
5451                }
5452
5453                picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5454        }
5455
5456        frame->video_code = vic;
5457        frame->picture_aspect = picture_aspect;
5458        frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
5459        frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
5460
5461        return 0;
5462}
5463EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
5464
5465/* HDMI Colorspace Spec Definitions */
5466#define FULL_COLORIMETRY_MASK           0x1FF
5467#define NORMAL_COLORIMETRY_MASK         0x3
5468#define EXTENDED_COLORIMETRY_MASK       0x7
5469#define EXTENDED_ACE_COLORIMETRY_MASK   0xF
5470
5471#define C(x) ((x) << 0)
5472#define EC(x) ((x) << 2)
5473#define ACE(x) ((x) << 5)
5474
5475#define HDMI_COLORIMETRY_NO_DATA                0x0
5476#define HDMI_COLORIMETRY_SMPTE_170M_YCC         (C(1) | EC(0) | ACE(0))
5477#define HDMI_COLORIMETRY_BT709_YCC              (C(2) | EC(0) | ACE(0))
5478#define HDMI_COLORIMETRY_XVYCC_601              (C(3) | EC(0) | ACE(0))
5479#define HDMI_COLORIMETRY_XVYCC_709              (C(3) | EC(1) | ACE(0))
5480#define HDMI_COLORIMETRY_SYCC_601               (C(3) | EC(2) | ACE(0))
5481#define HDMI_COLORIMETRY_OPYCC_601              (C(3) | EC(3) | ACE(0))
5482#define HDMI_COLORIMETRY_OPRGB                  (C(3) | EC(4) | ACE(0))
5483#define HDMI_COLORIMETRY_BT2020_CYCC            (C(3) | EC(5) | ACE(0))
5484#define HDMI_COLORIMETRY_BT2020_RGB             (C(3) | EC(6) | ACE(0))
5485#define HDMI_COLORIMETRY_BT2020_YCC             (C(3) | EC(6) | ACE(0))
5486#define HDMI_COLORIMETRY_DCI_P3_RGB_D65         (C(3) | EC(7) | ACE(0))
5487#define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER     (C(3) | EC(7) | ACE(1))
5488
5489static const u32 hdmi_colorimetry_val[] = {
5490        [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
5491        [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
5492        [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
5493        [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
5494        [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
5495        [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
5496        [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
5497        [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
5498        [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
5499        [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
5500        [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
5501};
5502
5503#undef C
5504#undef EC
5505#undef ACE
5506
5507/**
5508 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe
5509 *                                       colorspace information
5510 * @frame: HDMI AVI infoframe
5511 * @conn_state: connector state
5512 */
5513void
5514drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
5515                                  const struct drm_connector_state *conn_state)
5516{
5517        u32 colorimetry_val;
5518        u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
5519
5520        if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
5521                colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
5522        else
5523                colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
5524
5525        frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
5526        /*
5527         * ToDo: Extend it for ACE formats as well. Modify the infoframe
5528         * structure and extend it in drivers/video/hdmi
5529         */
5530        frame->extended_colorimetry = (colorimetry_val >> 2) &
5531                                        EXTENDED_COLORIMETRY_MASK;
5532}
5533EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace);
5534
5535/**
5536 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
5537 *                                        quantization range information
5538 * @frame: HDMI AVI infoframe
5539 * @connector: the connector
5540 * @mode: DRM display mode
5541 * @rgb_quant_range: RGB quantization range (Q)
5542 */
5543void
5544drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
5545                                   struct drm_connector *connector,
5546                                   const struct drm_display_mode *mode,
5547                                   enum hdmi_quantization_range rgb_quant_range)
5548{
5549        const struct drm_display_info *info = &connector->display_info;
5550
5551        /*
5552         * CEA-861:
5553         * "A Source shall not send a non-zero Q value that does not correspond
5554         *  to the default RGB Quantization Range for the transmitted Picture
5555         *  unless the Sink indicates support for the Q bit in a Video
5556         *  Capabilities Data Block."
5557         *
5558         * HDMI 2.0 recommends sending non-zero Q when it does match the
5559         * default RGB quantization range for the mode, even when QS=0.
5560         */
5561        if (info->rgb_quant_range_selectable ||
5562            rgb_quant_range == drm_default_rgb_quant_range(mode))
5563                frame->quantization_range = rgb_quant_range;
5564        else
5565                frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
5566
5567        /*
5568         * CEA-861-F:
5569         * "When transmitting any RGB colorimetry, the Source should set the
5570         *  YQ-field to match the RGB Quantization Range being transmitted
5571         *  (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
5572         *  set YQ=1) and the Sink shall ignore the YQ-field."
5573         *
5574         * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
5575         * by non-zero YQ when receiving RGB. There doesn't seem to be any
5576         * good way to tell which version of CEA-861 the sink supports, so
5577         * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
5578         * on on CEA-861-F.
5579         */
5580        if (!is_hdmi2_sink(connector) ||
5581            rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
5582                frame->ycc_quantization_range =
5583                        HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
5584        else
5585                frame->ycc_quantization_range =
5586                        HDMI_YCC_QUANTIZATION_RANGE_FULL;
5587}
5588EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
5589
5590/**
5591 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe
5592 *                                 bar information
5593 * @frame: HDMI AVI infoframe
5594 * @conn_state: connector state
5595 */
5596void
5597drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
5598                            const struct drm_connector_state *conn_state)
5599{
5600        frame->right_bar = conn_state->tv.margins.right;
5601        frame->left_bar = conn_state->tv.margins.left;
5602        frame->top_bar = conn_state->tv.margins.top;
5603        frame->bottom_bar = conn_state->tv.margins.bottom;
5604}
5605EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars);
5606
5607static enum hdmi_3d_structure
5608s3d_structure_from_display_mode(const struct drm_display_mode *mode)
5609{
5610        u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
5611
5612        switch (layout) {
5613        case DRM_MODE_FLAG_3D_FRAME_PACKING:
5614                return HDMI_3D_STRUCTURE_FRAME_PACKING;
5615        case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
5616                return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
5617        case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
5618                return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
5619        case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
5620                return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
5621        case DRM_MODE_FLAG_3D_L_DEPTH:
5622                return HDMI_3D_STRUCTURE_L_DEPTH;
5623        case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
5624                return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
5625        case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
5626                return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
5627        case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
5628                return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
5629        default:
5630                return HDMI_3D_STRUCTURE_INVALID;
5631        }
5632}
5633
5634/**
5635 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
5636 * data from a DRM display mode
5637 * @frame: HDMI vendor infoframe
5638 * @connector: the connector
5639 * @mode: DRM display mode
5640 *
5641 * Note that there's is a need to send HDMI vendor infoframes only when using a
5642 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
5643 * function will return -EINVAL, error that can be safely ignored.
5644 *
5645 * Return: 0 on success or a negative error code on failure.
5646 */
5647int
5648drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
5649                                            struct drm_connector *connector,
5650                                            const struct drm_display_mode *mode)
5651{
5652        /*
5653         * FIXME: sil-sii8620 doesn't have a connector around when
5654         * we need one, so we have to be prepared for a NULL connector.
5655         */
5656        bool has_hdmi_infoframe = connector ?
5657                connector->display_info.has_hdmi_infoframe : false;
5658        int err;
5659
5660        if (!frame || !mode)
5661                return -EINVAL;
5662
5663        if (!has_hdmi_infoframe)
5664                return -EINVAL;
5665
5666        err = hdmi_vendor_infoframe_init(frame);
5667        if (err < 0)
5668                return err;
5669
5670        /*
5671         * Even if it's not absolutely necessary to send the infoframe
5672         * (ie.vic==0 and s3d_struct==0) we will still send it if we
5673         * know that the sink can handle it. This is based on a
5674         * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
5675         * have trouble realizing that they shuld switch from 3D to 2D
5676         * mode if the source simply stops sending the infoframe when
5677         * it wants to switch from 3D to 2D.
5678         */
5679        frame->vic = drm_mode_hdmi_vic(connector, mode);
5680        frame->s3d_struct = s3d_structure_from_display_mode(mode);
5681
5682        return 0;
5683}
5684EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
5685
5686static int drm_parse_tiled_block(struct drm_connector *connector,
5687                                 struct displayid_block *block)
5688{
5689        struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5690        u16 w, h;
5691        u8 tile_v_loc, tile_h_loc;
5692        u8 num_v_tile, num_h_tile;
5693        struct drm_tile_group *tg;
5694
5695        w = tile->tile_size[0] | tile->tile_size[1] << 8;
5696        h = tile->tile_size[2] | tile->tile_size[3] << 8;
5697
5698        num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
5699        num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5700        tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
5701        tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
5702
5703        connector->has_tile = true;
5704        if (tile->tile_cap & 0x80)
5705                connector->tile_is_single_monitor = true;
5706
5707        connector->num_h_tile = num_h_tile + 1;
5708        connector->num_v_tile = num_v_tile + 1;
5709        connector->tile_h_loc = tile_h_loc;
5710        connector->tile_v_loc = tile_v_loc;
5711        connector->tile_h_size = w + 1;
5712        connector->tile_v_size = h + 1;
5713
5714        DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5715        DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5716        DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5717                      num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5718        DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5719
5720        tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5721        if (!tg) {
5722                tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5723        }
5724        if (!tg)
5725                return -ENOMEM;
5726
5727        if (connector->tile_group != tg) {
5728                /* if we haven't got a pointer,
5729                   take the reference, drop ref to old tile group */
5730                if (connector->tile_group) {
5731                        drm_mode_put_tile_group(connector->dev, connector->tile_group);
5732                }
5733                connector->tile_group = tg;
5734        } else
5735                /* if same tile group, then release the ref we just took. */
5736                drm_mode_put_tile_group(connector->dev, tg);
5737        return 0;
5738}
5739
5740static int drm_parse_display_id(struct drm_connector *connector,
5741                                u8 *displayid, int length,
5742                                bool is_edid_extension)
5743{
5744        /* if this is an EDID extension the first byte will be 0x70 */
5745        int idx = 0;
5746        struct displayid_block *block;
5747        int ret;
5748
5749        if (is_edid_extension)
5750                idx = 1;
5751
5752        ret = validate_displayid(displayid, length, idx);
5753        if (ret)
5754                return ret;
5755
5756        idx += sizeof(struct displayid_hdr);
5757        for_each_displayid_db(displayid, block, idx, length) {
5758                DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5759                              block->tag, block->rev, block->num_bytes);
5760
5761                switch (block->tag) {
5762                case DATA_BLOCK_TILED_DISPLAY:
5763                        ret = drm_parse_tiled_block(connector, block);
5764                        if (ret)
5765                                return ret;
5766                        break;
5767                case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5768                        /* handled in mode gathering code. */
5769                        break;
5770                case DATA_BLOCK_CTA:
5771                        /* handled in the cea parser code. */
5772                        break;
5773                default:
5774                        DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5775                        break;
5776                }
5777        }
5778        return 0;
5779}
5780
5781static void drm_get_displayid(struct drm_connector *connector,
5782                              struct edid *edid)
5783{
5784        void *displayid = NULL;
5785        int ret;
5786        connector->has_tile = false;
5787        displayid = drm_find_displayid_extension(edid);
5788        if (!displayid) {
5789                /* drop reference to any tile group we had */
5790                goto out_drop_ref;
5791        }
5792
5793        ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
5794        if (ret < 0)
5795                goto out_drop_ref;
5796        if (!connector->has_tile)
5797                goto out_drop_ref;
5798        return;
5799out_drop_ref:
5800        if (connector->tile_group) {
5801                drm_mode_put_tile_group(connector->dev, connector->tile_group);
5802                connector->tile_group = NULL;
5803        }
5804        return;
5805}
5806