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9#include <linux/clk.h>
10#include <linux/component.h>
11#include <linux/crc-ccitt.h>
12#include <linux/of_address.h>
13#include <linux/pm_runtime.h>
14#include <linux/regmap.h>
15#include <linux/reset.h>
16
17#include <linux/phy/phy.h>
18
19#include <drm/drmP.h>
20#include <drm/drm_atomic_helper.h>
21#include <drm/drm_crtc_helper.h>
22#include <drm/drm_mipi_dsi.h>
23#include <drm/drm_panel.h>
24
25#include "sun4i_drv.h"
26#include "sun6i_mipi_dsi.h"
27
28#include <video/mipi_display.h>
29
30#define SUN6I_DSI_CTL_REG 0x000
31#define SUN6I_DSI_CTL_EN BIT(0)
32
33#define SUN6I_DSI_BASIC_CTL_REG 0x00c
34#define SUN6I_DSI_BASIC_CTL_HBP_DIS BIT(2)
35#define SUN6I_DSI_BASIC_CTL_HSA_HSE_DIS BIT(1)
36#define SUN6I_DSI_BASIC_CTL_VIDEO_BURST BIT(0)
37
38#define SUN6I_DSI_BASIC_CTL0_REG 0x010
39#define SUN6I_DSI_BASIC_CTL0_HS_EOTP_EN BIT(18)
40#define SUN6I_DSI_BASIC_CTL0_CRC_EN BIT(17)
41#define SUN6I_DSI_BASIC_CTL0_ECC_EN BIT(16)
42#define SUN6I_DSI_BASIC_CTL0_INST_ST BIT(0)
43
44#define SUN6I_DSI_BASIC_CTL1_REG 0x014
45#define SUN6I_DSI_BASIC_CTL1_VIDEO_ST_DELAY(n) (((n) & 0x1fff) << 4)
46#define SUN6I_DSI_BASIC_CTL1_VIDEO_FILL BIT(2)
47#define SUN6I_DSI_BASIC_CTL1_VIDEO_PRECISION BIT(1)
48#define SUN6I_DSI_BASIC_CTL1_VIDEO_MODE BIT(0)
49
50#define SUN6I_DSI_BASIC_SIZE0_REG 0x018
51#define SUN6I_DSI_BASIC_SIZE0_VBP(n) (((n) & 0xfff) << 16)
52#define SUN6I_DSI_BASIC_SIZE0_VSA(n) ((n) & 0xfff)
53
54#define SUN6I_DSI_BASIC_SIZE1_REG 0x01c
55#define SUN6I_DSI_BASIC_SIZE1_VT(n) (((n) & 0xfff) << 16)
56#define SUN6I_DSI_BASIC_SIZE1_VACT(n) ((n) & 0xfff)
57
58#define SUN6I_DSI_INST_FUNC_REG(n) (0x020 + (n) * 0x04)
59#define SUN6I_DSI_INST_FUNC_INST_MODE(n) (((n) & 0xf) << 28)
60#define SUN6I_DSI_INST_FUNC_ESCAPE_ENTRY(n) (((n) & 0xf) << 24)
61#define SUN6I_DSI_INST_FUNC_TRANS_PACKET(n) (((n) & 0xf) << 20)
62#define SUN6I_DSI_INST_FUNC_LANE_CEN BIT(4)
63#define SUN6I_DSI_INST_FUNC_LANE_DEN(n) ((n) & 0xf)
64
65#define SUN6I_DSI_INST_LOOP_SEL_REG 0x040
66
67#define SUN6I_DSI_INST_LOOP_NUM_REG(n) (0x044 + (n) * 0x10)
68#define SUN6I_DSI_INST_LOOP_NUM_N1(n) (((n) & 0xfff) << 16)
69#define SUN6I_DSI_INST_LOOP_NUM_N0(n) ((n) & 0xfff)
70
71#define SUN6I_DSI_INST_JUMP_SEL_REG 0x048
72
73#define SUN6I_DSI_INST_JUMP_CFG_REG(n) (0x04c + (n) * 0x04)
74#define SUN6I_DSI_INST_JUMP_CFG_TO(n) (((n) & 0xf) << 20)
75#define SUN6I_DSI_INST_JUMP_CFG_POINT(n) (((n) & 0xf) << 16)
76#define SUN6I_DSI_INST_JUMP_CFG_NUM(n) ((n) & 0xffff)
77
78#define SUN6I_DSI_TRANS_START_REG 0x060
79
80#define SUN6I_DSI_TRANS_ZERO_REG 0x078
81
82#define SUN6I_DSI_TCON_DRQ_REG 0x07c
83#define SUN6I_DSI_TCON_DRQ_ENABLE_MODE BIT(28)
84#define SUN6I_DSI_TCON_DRQ_SET(n) ((n) & 0x3ff)
85
86#define SUN6I_DSI_PIXEL_CTL0_REG 0x080
87#define SUN6I_DSI_PIXEL_CTL0_PD_PLUG_DISABLE BIT(16)
88#define SUN6I_DSI_PIXEL_CTL0_FORMAT(n) ((n) & 0xf)
89
90#define SUN6I_DSI_PIXEL_CTL1_REG 0x084
91
92#define SUN6I_DSI_PIXEL_PH_REG 0x090
93#define SUN6I_DSI_PIXEL_PH_ECC(n) (((n) & 0xff) << 24)
94#define SUN6I_DSI_PIXEL_PH_WC(n) (((n) & 0xffff) << 8)
95#define SUN6I_DSI_PIXEL_PH_VC(n) (((n) & 3) << 6)
96#define SUN6I_DSI_PIXEL_PH_DT(n) ((n) & 0x3f)
97
98#define SUN6I_DSI_PIXEL_PF0_REG 0x098
99#define SUN6I_DSI_PIXEL_PF0_CRC_FORCE(n) ((n) & 0xffff)
100
101#define SUN6I_DSI_PIXEL_PF1_REG 0x09c
102#define SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINEN(n) (((n) & 0xffff) << 16)
103#define SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINE0(n) ((n) & 0xffff)
104
105#define SUN6I_DSI_SYNC_HSS_REG 0x0b0
106
107#define SUN6I_DSI_SYNC_HSE_REG 0x0b4
108
109#define SUN6I_DSI_SYNC_VSS_REG 0x0b8
110
111#define SUN6I_DSI_SYNC_VSE_REG 0x0bc
112
113#define SUN6I_DSI_BLK_HSA0_REG 0x0c0
114
115#define SUN6I_DSI_BLK_HSA1_REG 0x0c4
116#define SUN6I_DSI_BLK_PF(n) (((n) & 0xffff) << 16)
117#define SUN6I_DSI_BLK_PD(n) ((n) & 0xff)
118
119#define SUN6I_DSI_BLK_HBP0_REG 0x0c8
120
121#define SUN6I_DSI_BLK_HBP1_REG 0x0cc
122
123#define SUN6I_DSI_BLK_HFP0_REG 0x0d0
124
125#define SUN6I_DSI_BLK_HFP1_REG 0x0d4
126
127#define SUN6I_DSI_BLK_HBLK0_REG 0x0e0
128
129#define SUN6I_DSI_BLK_HBLK1_REG 0x0e4
130
131#define SUN6I_DSI_BLK_VBLK0_REG 0x0e8
132
133#define SUN6I_DSI_BLK_VBLK1_REG 0x0ec
134
135#define SUN6I_DSI_BURST_LINE_REG 0x0f0
136#define SUN6I_DSI_BURST_LINE_SYNC_POINT(n) (((n) & 0xffff) << 16)
137#define SUN6I_DSI_BURST_LINE_NUM(n) ((n) & 0xffff)
138
139#define SUN6I_DSI_BURST_DRQ_REG 0x0f4
140#define SUN6I_DSI_BURST_DRQ_EDGE1(n) (((n) & 0xffff) << 16)
141#define SUN6I_DSI_BURST_DRQ_EDGE0(n) ((n) & 0xffff)
142
143#define SUN6I_DSI_CMD_CTL_REG 0x200
144#define SUN6I_DSI_CMD_CTL_RX_OVERFLOW BIT(26)
145#define SUN6I_DSI_CMD_CTL_RX_FLAG BIT(25)
146#define SUN6I_DSI_CMD_CTL_TX_FLAG BIT(9)
147
148#define SUN6I_DSI_CMD_RX_REG(n) (0x240 + (n) * 0x04)
149
150#define SUN6I_DSI_DEBUG_DATA_REG 0x2f8
151
152#define SUN6I_DSI_CMD_TX_REG(n) (0x300 + (n) * 0x04)
153
154enum sun6i_dsi_start_inst {
155 DSI_START_LPRX,
156 DSI_START_LPTX,
157 DSI_START_HSC,
158 DSI_START_HSD,
159};
160
161enum sun6i_dsi_inst_id {
162 DSI_INST_ID_LP11 = 0,
163 DSI_INST_ID_TBA,
164 DSI_INST_ID_HSC,
165 DSI_INST_ID_HSD,
166 DSI_INST_ID_LPDT,
167 DSI_INST_ID_HSCEXIT,
168 DSI_INST_ID_NOP,
169 DSI_INST_ID_DLY,
170 DSI_INST_ID_END = 15,
171};
172
173enum sun6i_dsi_inst_mode {
174 DSI_INST_MODE_STOP = 0,
175 DSI_INST_MODE_TBA,
176 DSI_INST_MODE_HS,
177 DSI_INST_MODE_ESCAPE,
178 DSI_INST_MODE_HSCEXIT,
179 DSI_INST_MODE_NOP,
180};
181
182enum sun6i_dsi_inst_escape {
183 DSI_INST_ESCA_LPDT = 0,
184 DSI_INST_ESCA_ULPS,
185 DSI_INST_ESCA_UN1,
186 DSI_INST_ESCA_UN2,
187 DSI_INST_ESCA_RESET,
188 DSI_INST_ESCA_UN3,
189 DSI_INST_ESCA_UN4,
190 DSI_INST_ESCA_UN5,
191};
192
193enum sun6i_dsi_inst_packet {
194 DSI_INST_PACK_PIXEL = 0,
195 DSI_INST_PACK_COMMAND,
196};
197
198static const u32 sun6i_dsi_ecc_array[] = {
199 [0] = (BIT(0) | BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(7) | BIT(10) |
200 BIT(11) | BIT(13) | BIT(16) | BIT(20) | BIT(21) | BIT(22) |
201 BIT(23)),
202 [1] = (BIT(0) | BIT(1) | BIT(3) | BIT(4) | BIT(6) | BIT(8) | BIT(10) |
203 BIT(12) | BIT(14) | BIT(17) | BIT(20) | BIT(21) | BIT(22) |
204 BIT(23)),
205 [2] = (BIT(0) | BIT(2) | BIT(3) | BIT(5) | BIT(6) | BIT(9) | BIT(11) |
206 BIT(12) | BIT(15) | BIT(18) | BIT(20) | BIT(21) | BIT(22)),
207 [3] = (BIT(1) | BIT(2) | BIT(3) | BIT(7) | BIT(8) | BIT(9) | BIT(13) |
208 BIT(14) | BIT(15) | BIT(19) | BIT(20) | BIT(21) | BIT(23)),
209 [4] = (BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(16) |
210 BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(22) | BIT(23)),
211 [5] = (BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) |
212 BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(21) | BIT(22) |
213 BIT(23)),
214};
215
216static u32 sun6i_dsi_ecc_compute(unsigned int data)
217{
218 int i;
219 u8 ecc = 0;
220
221 for (i = 0; i < ARRAY_SIZE(sun6i_dsi_ecc_array); i++) {
222 u32 field = sun6i_dsi_ecc_array[i];
223 bool init = false;
224 u8 val = 0;
225 int j;
226
227 for (j = 0; j < 24; j++) {
228 if (!(BIT(j) & field))
229 continue;
230
231 if (!init) {
232 val = (BIT(j) & data) ? 1 : 0;
233 init = true;
234 } else {
235 val ^= (BIT(j) & data) ? 1 : 0;
236 }
237 }
238
239 ecc |= val << i;
240 }
241
242 return ecc;
243}
244
245static u16 sun6i_dsi_crc_compute(u8 const *buffer, size_t len)
246{
247 return crc_ccitt(0xffff, buffer, len);
248}
249
250static u16 sun6i_dsi_crc_repeat_compute(u8 pd, size_t len)
251{
252 u8 buffer[len];
253
254 memset(buffer, pd, len);
255
256 return sun6i_dsi_crc_compute(buffer, len);
257}
258
259static u32 sun6i_dsi_build_sync_pkt(u8 dt, u8 vc, u8 d0, u8 d1)
260{
261 u32 val = dt & 0x3f;
262
263 val |= (vc & 3) << 6;
264 val |= (d0 & 0xff) << 8;
265 val |= (d1 & 0xff) << 16;
266 val |= sun6i_dsi_ecc_compute(val) << 24;
267
268 return val;
269}
270
271static u32 sun6i_dsi_build_blk0_pkt(u8 vc, u16 wc)
272{
273 return sun6i_dsi_build_sync_pkt(MIPI_DSI_BLANKING_PACKET, vc,
274 wc & 0xff, wc >> 8);
275}
276
277static u32 sun6i_dsi_build_blk1_pkt(u16 pd, size_t len)
278{
279 u32 val = SUN6I_DSI_BLK_PD(pd);
280
281 return val | SUN6I_DSI_BLK_PF(sun6i_dsi_crc_repeat_compute(pd, len));
282}
283
284static void sun6i_dsi_inst_abort(struct sun6i_dsi *dsi)
285{
286 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
287 SUN6I_DSI_BASIC_CTL0_INST_ST, 0);
288}
289
290static void sun6i_dsi_inst_commit(struct sun6i_dsi *dsi)
291{
292 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
293 SUN6I_DSI_BASIC_CTL0_INST_ST,
294 SUN6I_DSI_BASIC_CTL0_INST_ST);
295}
296
297static int sun6i_dsi_inst_wait_for_completion(struct sun6i_dsi *dsi)
298{
299 u32 val;
300
301 return regmap_read_poll_timeout(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
302 val,
303 !(val & SUN6I_DSI_BASIC_CTL0_INST_ST),
304 100, 5000);
305}
306
307static void sun6i_dsi_inst_setup(struct sun6i_dsi *dsi,
308 enum sun6i_dsi_inst_id id,
309 enum sun6i_dsi_inst_mode mode,
310 bool clock, u8 data,
311 enum sun6i_dsi_inst_packet packet,
312 enum sun6i_dsi_inst_escape escape)
313{
314 regmap_write(dsi->regs, SUN6I_DSI_INST_FUNC_REG(id),
315 SUN6I_DSI_INST_FUNC_INST_MODE(mode) |
316 SUN6I_DSI_INST_FUNC_ESCAPE_ENTRY(escape) |
317 SUN6I_DSI_INST_FUNC_TRANS_PACKET(packet) |
318 (clock ? SUN6I_DSI_INST_FUNC_LANE_CEN : 0) |
319 SUN6I_DSI_INST_FUNC_LANE_DEN(data));
320}
321
322static void sun6i_dsi_inst_init(struct sun6i_dsi *dsi,
323 struct mipi_dsi_device *device)
324{
325 u8 lanes_mask = GENMASK(device->lanes - 1, 0);
326
327 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_LP11, DSI_INST_MODE_STOP,
328 true, lanes_mask, 0, 0);
329
330 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_TBA, DSI_INST_MODE_TBA,
331 false, 1, 0, 0);
332
333 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_HSC, DSI_INST_MODE_HS,
334 true, 0, DSI_INST_PACK_PIXEL, 0);
335
336 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_HSD, DSI_INST_MODE_HS,
337 false, lanes_mask, DSI_INST_PACK_PIXEL, 0);
338
339 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_LPDT, DSI_INST_MODE_ESCAPE,
340 false, 1, DSI_INST_PACK_COMMAND,
341 DSI_INST_ESCA_LPDT);
342
343 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_HSCEXIT, DSI_INST_MODE_HSCEXIT,
344 true, 0, 0, 0);
345
346 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_NOP, DSI_INST_MODE_STOP,
347 false, lanes_mask, 0, 0);
348
349 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_DLY, DSI_INST_MODE_NOP,
350 true, lanes_mask, 0, 0);
351
352 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_CFG_REG(0),
353 SUN6I_DSI_INST_JUMP_CFG_POINT(DSI_INST_ID_NOP) |
354 SUN6I_DSI_INST_JUMP_CFG_TO(DSI_INST_ID_HSCEXIT) |
355 SUN6I_DSI_INST_JUMP_CFG_NUM(1));
356};
357
358static u16 sun6i_dsi_get_video_start_delay(struct sun6i_dsi *dsi,
359 struct drm_display_mode *mode)
360{
361 return mode->vtotal - (mode->vsync_end - mode->vdisplay) + 1;
362}
363
364static void sun6i_dsi_setup_burst(struct sun6i_dsi *dsi,
365 struct drm_display_mode *mode)
366{
367 struct mipi_dsi_device *device = dsi->device;
368 u32 val = 0;
369
370 if ((mode->hsync_end - mode->hdisplay) > 20) {
371
372 u16 drq = (mode->hsync_end - mode->hdisplay) - 20;
373
374 drq *= mipi_dsi_pixel_format_to_bpp(device->format);
375 drq /= 32;
376
377 val = (SUN6I_DSI_TCON_DRQ_ENABLE_MODE |
378 SUN6I_DSI_TCON_DRQ_SET(drq));
379 }
380
381 regmap_write(dsi->regs, SUN6I_DSI_TCON_DRQ_REG, val);
382}
383
384static void sun6i_dsi_setup_inst_loop(struct sun6i_dsi *dsi,
385 struct drm_display_mode *mode)
386{
387 u16 delay = 50 - 1;
388
389 regmap_write(dsi->regs, SUN6I_DSI_INST_LOOP_NUM_REG(0),
390 SUN6I_DSI_INST_LOOP_NUM_N0(50 - 1) |
391 SUN6I_DSI_INST_LOOP_NUM_N1(delay));
392 regmap_write(dsi->regs, SUN6I_DSI_INST_LOOP_NUM_REG(1),
393 SUN6I_DSI_INST_LOOP_NUM_N0(50 - 1) |
394 SUN6I_DSI_INST_LOOP_NUM_N1(delay));
395}
396
397static void sun6i_dsi_setup_format(struct sun6i_dsi *dsi,
398 struct drm_display_mode *mode)
399{
400 struct mipi_dsi_device *device = dsi->device;
401 u32 val = SUN6I_DSI_PIXEL_PH_VC(device->channel);
402 u8 dt, fmt;
403 u16 wc;
404
405
406
407
408
409 switch (device->format) {
410 case MIPI_DSI_FMT_RGB888:
411 dt = MIPI_DSI_PACKED_PIXEL_STREAM_24;
412 fmt = 8;
413 break;
414 case MIPI_DSI_FMT_RGB666:
415 dt = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
416 fmt = 9;
417 break;
418 case MIPI_DSI_FMT_RGB666_PACKED:
419 dt = MIPI_DSI_PACKED_PIXEL_STREAM_18;
420 fmt = 10;
421 break;
422 case MIPI_DSI_FMT_RGB565:
423 dt = MIPI_DSI_PACKED_PIXEL_STREAM_16;
424 fmt = 11;
425 break;
426 default:
427 return;
428 }
429 val |= SUN6I_DSI_PIXEL_PH_DT(dt);
430
431 wc = mode->hdisplay * mipi_dsi_pixel_format_to_bpp(device->format) / 8;
432 val |= SUN6I_DSI_PIXEL_PH_WC(wc);
433 val |= SUN6I_DSI_PIXEL_PH_ECC(sun6i_dsi_ecc_compute(val));
434
435 regmap_write(dsi->regs, SUN6I_DSI_PIXEL_PH_REG, val);
436
437 regmap_write(dsi->regs, SUN6I_DSI_PIXEL_PF0_REG,
438 SUN6I_DSI_PIXEL_PF0_CRC_FORCE(0xffff));
439
440 regmap_write(dsi->regs, SUN6I_DSI_PIXEL_PF1_REG,
441 SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINE0(0xffff) |
442 SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINEN(0xffff));
443
444 regmap_write(dsi->regs, SUN6I_DSI_PIXEL_CTL0_REG,
445 SUN6I_DSI_PIXEL_CTL0_PD_PLUG_DISABLE |
446 SUN6I_DSI_PIXEL_CTL0_FORMAT(fmt));
447}
448
449static void sun6i_dsi_setup_timings(struct sun6i_dsi *dsi,
450 struct drm_display_mode *mode)
451{
452 struct mipi_dsi_device *device = dsi->device;
453 unsigned int Bpp = mipi_dsi_pixel_format_to_bpp(device->format) / 8;
454 u16 hbp, hfp, hsa, hblk, vblk;
455
456 regmap_write(dsi->regs, SUN6I_DSI_BASIC_CTL_REG, 0);
457
458 regmap_write(dsi->regs, SUN6I_DSI_SYNC_HSS_REG,
459 sun6i_dsi_build_sync_pkt(MIPI_DSI_H_SYNC_START,
460 device->channel,
461 0, 0));
462
463 regmap_write(dsi->regs, SUN6I_DSI_SYNC_HSE_REG,
464 sun6i_dsi_build_sync_pkt(MIPI_DSI_H_SYNC_END,
465 device->channel,
466 0, 0));
467
468 regmap_write(dsi->regs, SUN6I_DSI_SYNC_VSS_REG,
469 sun6i_dsi_build_sync_pkt(MIPI_DSI_V_SYNC_START,
470 device->channel,
471 0, 0));
472
473 regmap_write(dsi->regs, SUN6I_DSI_SYNC_VSE_REG,
474 sun6i_dsi_build_sync_pkt(MIPI_DSI_V_SYNC_END,
475 device->channel,
476 0, 0));
477
478 regmap_write(dsi->regs, SUN6I_DSI_BASIC_SIZE0_REG,
479 SUN6I_DSI_BASIC_SIZE0_VSA(mode->vsync_end -
480 mode->vsync_start) |
481 SUN6I_DSI_BASIC_SIZE0_VBP(mode->vsync_start -
482 mode->vdisplay));
483
484 regmap_write(dsi->regs, SUN6I_DSI_BASIC_SIZE1_REG,
485 SUN6I_DSI_BASIC_SIZE1_VACT(mode->vdisplay) |
486 SUN6I_DSI_BASIC_SIZE1_VT(mode->vtotal));
487
488
489
490
491
492
493#define HSA_PACKET_OVERHEAD 10
494 hsa = max((unsigned int)HSA_PACKET_OVERHEAD,
495 (mode->hsync_end - mode->hsync_start) * Bpp - HSA_PACKET_OVERHEAD);
496 regmap_write(dsi->regs, SUN6I_DSI_BLK_HSA0_REG,
497 sun6i_dsi_build_blk0_pkt(device->channel, hsa));
498 regmap_write(dsi->regs, SUN6I_DSI_BLK_HSA1_REG,
499 sun6i_dsi_build_blk1_pkt(0, hsa));
500
501
502
503
504
505#define HBP_PACKET_OVERHEAD 6
506 hbp = max((unsigned int)HBP_PACKET_OVERHEAD,
507 (mode->hsync_start - mode->hdisplay) * Bpp - HBP_PACKET_OVERHEAD);
508 regmap_write(dsi->regs, SUN6I_DSI_BLK_HBP0_REG,
509 sun6i_dsi_build_blk0_pkt(device->channel, hbp));
510 regmap_write(dsi->regs, SUN6I_DSI_BLK_HBP1_REG,
511 sun6i_dsi_build_blk1_pkt(0, hbp));
512
513
514
515
516
517#define HFP_PACKET_OVERHEAD 6
518 hfp = max((unsigned int)HFP_PACKET_OVERHEAD,
519 (mode->htotal - mode->hsync_end) * Bpp - HFP_PACKET_OVERHEAD);
520 regmap_write(dsi->regs, SUN6I_DSI_BLK_HFP0_REG,
521 sun6i_dsi_build_blk0_pkt(device->channel, hfp));
522 regmap_write(dsi->regs, SUN6I_DSI_BLK_HFP1_REG,
523 sun6i_dsi_build_blk1_pkt(0, hfp));
524
525
526
527
528 hblk = mode->htotal * Bpp - hsa;
529 regmap_write(dsi->regs, SUN6I_DSI_BLK_HBLK0_REG,
530 sun6i_dsi_build_blk0_pkt(device->channel, hblk));
531 regmap_write(dsi->regs, SUN6I_DSI_BLK_HBLK1_REG,
532 sun6i_dsi_build_blk1_pkt(0, hblk));
533
534
535
536
537
538
539
540 vblk = 0;
541 regmap_write(dsi->regs, SUN6I_DSI_BLK_VBLK0_REG,
542 sun6i_dsi_build_blk0_pkt(device->channel, vblk));
543 regmap_write(dsi->regs, SUN6I_DSI_BLK_VBLK1_REG,
544 sun6i_dsi_build_blk1_pkt(0, vblk));
545}
546
547static int sun6i_dsi_start(struct sun6i_dsi *dsi,
548 enum sun6i_dsi_start_inst func)
549{
550 switch (func) {
551 case DSI_START_LPTX:
552 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
553 DSI_INST_ID_LPDT << (4 * DSI_INST_ID_LP11) |
554 DSI_INST_ID_END << (4 * DSI_INST_ID_LPDT));
555 break;
556 case DSI_START_LPRX:
557 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
558 DSI_INST_ID_LPDT << (4 * DSI_INST_ID_LP11) |
559 DSI_INST_ID_DLY << (4 * DSI_INST_ID_LPDT) |
560 DSI_INST_ID_TBA << (4 * DSI_INST_ID_DLY) |
561 DSI_INST_ID_END << (4 * DSI_INST_ID_TBA));
562 break;
563 case DSI_START_HSC:
564 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
565 DSI_INST_ID_HSC << (4 * DSI_INST_ID_LP11) |
566 DSI_INST_ID_END << (4 * DSI_INST_ID_HSC));
567 break;
568 case DSI_START_HSD:
569 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
570 DSI_INST_ID_NOP << (4 * DSI_INST_ID_LP11) |
571 DSI_INST_ID_HSD << (4 * DSI_INST_ID_NOP) |
572 DSI_INST_ID_DLY << (4 * DSI_INST_ID_HSD) |
573 DSI_INST_ID_NOP << (4 * DSI_INST_ID_DLY) |
574 DSI_INST_ID_END << (4 * DSI_INST_ID_HSCEXIT));
575 break;
576 default:
577 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
578 DSI_INST_ID_END << (4 * DSI_INST_ID_LP11));
579 break;
580 }
581
582 sun6i_dsi_inst_abort(dsi);
583 sun6i_dsi_inst_commit(dsi);
584
585 if (func == DSI_START_HSC)
586 regmap_write_bits(dsi->regs,
587 SUN6I_DSI_INST_FUNC_REG(DSI_INST_ID_LP11),
588 SUN6I_DSI_INST_FUNC_LANE_CEN, 0);
589
590 return 0;
591}
592
593static void sun6i_dsi_encoder_enable(struct drm_encoder *encoder)
594{
595 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
596 struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder);
597 struct mipi_dsi_device *device = dsi->device;
598 u16 delay;
599
600 DRM_DEBUG_DRIVER("Enabling DSI output\n");
601
602 pm_runtime_get_sync(dsi->dev);
603
604 delay = sun6i_dsi_get_video_start_delay(dsi, mode);
605 regmap_write(dsi->regs, SUN6I_DSI_BASIC_CTL1_REG,
606 SUN6I_DSI_BASIC_CTL1_VIDEO_ST_DELAY(delay) |
607 SUN6I_DSI_BASIC_CTL1_VIDEO_FILL |
608 SUN6I_DSI_BASIC_CTL1_VIDEO_PRECISION |
609 SUN6I_DSI_BASIC_CTL1_VIDEO_MODE);
610
611 sun6i_dsi_setup_burst(dsi, mode);
612 sun6i_dsi_setup_inst_loop(dsi, mode);
613 sun6i_dsi_setup_format(dsi, mode);
614 sun6i_dsi_setup_timings(dsi, mode);
615
616 sun6i_dphy_init(dsi->dphy, device->lanes);
617 sun6i_dphy_power_on(dsi->dphy, device->lanes);
618
619 if (!IS_ERR(dsi->panel))
620 drm_panel_prepare(dsi->panel);
621
622
623
624
625
626
627
628
629
630
631
632
633
634 if (!IS_ERR(dsi->panel))
635 drm_panel_enable(dsi->panel);
636
637 sun6i_dsi_start(dsi, DSI_START_HSC);
638
639 udelay(1000);
640
641 sun6i_dsi_start(dsi, DSI_START_HSD);
642}
643
644static void sun6i_dsi_encoder_disable(struct drm_encoder *encoder)
645{
646 struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder);
647
648 DRM_DEBUG_DRIVER("Disabling DSI output\n");
649
650 if (!IS_ERR(dsi->panel)) {
651 drm_panel_disable(dsi->panel);
652 drm_panel_unprepare(dsi->panel);
653 }
654
655 sun6i_dphy_power_off(dsi->dphy);
656 sun6i_dphy_exit(dsi->dphy);
657
658 pm_runtime_put(dsi->dev);
659}
660
661static int sun6i_dsi_get_modes(struct drm_connector *connector)
662{
663 struct sun6i_dsi *dsi = connector_to_sun6i_dsi(connector);
664
665 return drm_panel_get_modes(dsi->panel);
666}
667
668static struct drm_connector_helper_funcs sun6i_dsi_connector_helper_funcs = {
669 .get_modes = sun6i_dsi_get_modes,
670};
671
672static enum drm_connector_status
673sun6i_dsi_connector_detect(struct drm_connector *connector, bool force)
674{
675 return connector_status_connected;
676}
677
678static const struct drm_connector_funcs sun6i_dsi_connector_funcs = {
679 .detect = sun6i_dsi_connector_detect,
680 .fill_modes = drm_helper_probe_single_connector_modes,
681 .destroy = drm_connector_cleanup,
682 .reset = drm_atomic_helper_connector_reset,
683 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
684 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
685};
686
687static const struct drm_encoder_helper_funcs sun6i_dsi_enc_helper_funcs = {
688 .disable = sun6i_dsi_encoder_disable,
689 .enable = sun6i_dsi_encoder_enable,
690};
691
692static const struct drm_encoder_funcs sun6i_dsi_enc_funcs = {
693 .destroy = drm_encoder_cleanup,
694};
695
696static u32 sun6i_dsi_dcs_build_pkt_hdr(struct sun6i_dsi *dsi,
697 const struct mipi_dsi_msg *msg)
698{
699 u32 pkt = msg->type;
700
701 if (msg->type == MIPI_DSI_DCS_LONG_WRITE) {
702 pkt |= ((msg->tx_len + 1) & 0xffff) << 8;
703 pkt |= (((msg->tx_len + 1) >> 8) & 0xffff) << 16;
704 } else {
705 pkt |= (((u8 *)msg->tx_buf)[0] << 8);
706 if (msg->tx_len > 1)
707 pkt |= (((u8 *)msg->tx_buf)[1] << 16);
708 }
709
710 pkt |= sun6i_dsi_ecc_compute(pkt) << 24;
711
712 return pkt;
713}
714
715static int sun6i_dsi_dcs_write_short(struct sun6i_dsi *dsi,
716 const struct mipi_dsi_msg *msg)
717{
718 regmap_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(0),
719 sun6i_dsi_dcs_build_pkt_hdr(dsi, msg));
720 regmap_write_bits(dsi->regs, SUN6I_DSI_CMD_CTL_REG,
721 0xff, (4 - 1));
722
723 sun6i_dsi_start(dsi, DSI_START_LPTX);
724
725 return msg->tx_len;
726}
727
728static int sun6i_dsi_dcs_write_long(struct sun6i_dsi *dsi,
729 const struct mipi_dsi_msg *msg)
730{
731 int ret, len = 0;
732 u8 *bounce;
733 u16 crc;
734
735 regmap_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(0),
736 sun6i_dsi_dcs_build_pkt_hdr(dsi, msg));
737
738 bounce = kzalloc(msg->tx_len + sizeof(crc), GFP_KERNEL);
739 if (!bounce)
740 return -ENOMEM;
741
742 memcpy(bounce, msg->tx_buf, msg->tx_len);
743 len += msg->tx_len;
744
745 crc = sun6i_dsi_crc_compute(bounce, msg->tx_len);
746 memcpy((u8 *)bounce + msg->tx_len, &crc, sizeof(crc));
747 len += sizeof(crc);
748
749 regmap_bulk_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(1), bounce, len);
750 regmap_write(dsi->regs, SUN6I_DSI_CMD_CTL_REG, len + 4 - 1);
751 kfree(bounce);
752
753 sun6i_dsi_start(dsi, DSI_START_LPTX);
754
755 ret = sun6i_dsi_inst_wait_for_completion(dsi);
756 if (ret < 0) {
757 sun6i_dsi_inst_abort(dsi);
758 return ret;
759 }
760
761
762
763
764
765
766 return msg->tx_len;
767}
768
769static int sun6i_dsi_dcs_read(struct sun6i_dsi *dsi,
770 const struct mipi_dsi_msg *msg)
771{
772 u32 val;
773 int ret;
774 u8 byte0;
775
776 regmap_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(0),
777 sun6i_dsi_dcs_build_pkt_hdr(dsi, msg));
778 regmap_write(dsi->regs, SUN6I_DSI_CMD_CTL_REG,
779 (4 - 1));
780
781 sun6i_dsi_start(dsi, DSI_START_LPRX);
782
783 ret = sun6i_dsi_inst_wait_for_completion(dsi);
784 if (ret < 0) {
785 sun6i_dsi_inst_abort(dsi);
786 return ret;
787 }
788
789
790
791
792
793
794 regmap_read(dsi->regs, SUN6I_DSI_CMD_CTL_REG, &val);
795 if (val & SUN6I_DSI_CMD_CTL_RX_OVERFLOW)
796 return -EIO;
797
798 regmap_read(dsi->regs, SUN6I_DSI_CMD_RX_REG(0), &val);
799 byte0 = val & 0xff;
800 if (byte0 == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT)
801 return -EIO;
802
803 ((u8 *)msg->rx_buf)[0] = (val >> 8);
804
805 return 1;
806}
807
808static int sun6i_dsi_attach(struct mipi_dsi_host *host,
809 struct mipi_dsi_device *device)
810{
811 struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
812
813 dsi->device = device;
814 dsi->panel = of_drm_find_panel(device->dev.of_node);
815 if (!dsi->panel)
816 return -EINVAL;
817
818 dev_info(host->dev, "Attached device %s\n", device->name);
819
820 return 0;
821}
822
823static int sun6i_dsi_detach(struct mipi_dsi_host *host,
824 struct mipi_dsi_device *device)
825{
826 struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
827
828 dsi->panel = NULL;
829 dsi->device = NULL;
830
831 return 0;
832}
833
834static ssize_t sun6i_dsi_transfer(struct mipi_dsi_host *host,
835 const struct mipi_dsi_msg *msg)
836{
837 struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
838 int ret;
839
840 ret = sun6i_dsi_inst_wait_for_completion(dsi);
841 if (ret < 0)
842 sun6i_dsi_inst_abort(dsi);
843
844 regmap_write(dsi->regs, SUN6I_DSI_CMD_CTL_REG,
845 SUN6I_DSI_CMD_CTL_RX_OVERFLOW |
846 SUN6I_DSI_CMD_CTL_RX_FLAG |
847 SUN6I_DSI_CMD_CTL_TX_FLAG);
848
849 switch (msg->type) {
850 case MIPI_DSI_DCS_SHORT_WRITE:
851 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
852 ret = sun6i_dsi_dcs_write_short(dsi, msg);
853 break;
854
855 case MIPI_DSI_DCS_LONG_WRITE:
856 ret = sun6i_dsi_dcs_write_long(dsi, msg);
857 break;
858
859 case MIPI_DSI_DCS_READ:
860 if (msg->rx_len == 1) {
861 ret = sun6i_dsi_dcs_read(dsi, msg);
862 break;
863 }
864
865 default:
866 ret = -EINVAL;
867 }
868
869 return ret;
870}
871
872static const struct mipi_dsi_host_ops sun6i_dsi_host_ops = {
873 .attach = sun6i_dsi_attach,
874 .detach = sun6i_dsi_detach,
875 .transfer = sun6i_dsi_transfer,
876};
877
878static const struct regmap_config sun6i_dsi_regmap_config = {
879 .reg_bits = 32,
880 .val_bits = 32,
881 .reg_stride = 4,
882 .max_register = SUN6I_DSI_CMD_TX_REG(255),
883 .name = "mipi-dsi",
884};
885
886static int sun6i_dsi_bind(struct device *dev, struct device *master,
887 void *data)
888{
889 struct drm_device *drm = data;
890 struct sun4i_drv *drv = drm->dev_private;
891 struct sun6i_dsi *dsi = dev_get_drvdata(dev);
892 int ret;
893
894 if (!dsi->panel)
895 return -EPROBE_DEFER;
896
897 dsi->drv = drv;
898
899 drm_encoder_helper_add(&dsi->encoder,
900 &sun6i_dsi_enc_helper_funcs);
901 ret = drm_encoder_init(drm,
902 &dsi->encoder,
903 &sun6i_dsi_enc_funcs,
904 DRM_MODE_ENCODER_DSI,
905 NULL);
906 if (ret) {
907 dev_err(dsi->dev, "Couldn't initialise the DSI encoder\n");
908 return ret;
909 }
910 dsi->encoder.possible_crtcs = BIT(0);
911
912 drm_connector_helper_add(&dsi->connector,
913 &sun6i_dsi_connector_helper_funcs);
914 ret = drm_connector_init(drm, &dsi->connector,
915 &sun6i_dsi_connector_funcs,
916 DRM_MODE_CONNECTOR_DSI);
917 if (ret) {
918 dev_err(dsi->dev,
919 "Couldn't initialise the DSI connector\n");
920 goto err_cleanup_connector;
921 }
922
923 drm_mode_connector_attach_encoder(&dsi->connector, &dsi->encoder);
924 drm_panel_attach(dsi->panel, &dsi->connector);
925
926 return 0;
927
928err_cleanup_connector:
929 drm_encoder_cleanup(&dsi->encoder);
930 return ret;
931}
932
933static void sun6i_dsi_unbind(struct device *dev, struct device *master,
934 void *data)
935{
936 struct sun6i_dsi *dsi = dev_get_drvdata(dev);
937
938 drm_panel_detach(dsi->panel);
939}
940
941static const struct component_ops sun6i_dsi_ops = {
942 .bind = sun6i_dsi_bind,
943 .unbind = sun6i_dsi_unbind,
944};
945
946static int sun6i_dsi_probe(struct platform_device *pdev)
947{
948 struct device *dev = &pdev->dev;
949 struct device_node *dphy_node;
950 struct sun6i_dsi *dsi;
951 struct resource *res;
952 void __iomem *base;
953 int ret;
954
955 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
956 if (!dsi)
957 return -ENOMEM;
958 dev_set_drvdata(dev, dsi);
959 dsi->dev = dev;
960 dsi->host.ops = &sun6i_dsi_host_ops;
961 dsi->host.dev = dev;
962
963 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
964 base = devm_ioremap_resource(dev, res);
965 if (IS_ERR(base)) {
966 dev_err(dev, "Couldn't map the DSI encoder registers\n");
967 return PTR_ERR(base);
968 }
969
970 dsi->regs = devm_regmap_init_mmio_clk(dev, "bus", base,
971 &sun6i_dsi_regmap_config);
972 if (IS_ERR(dsi->regs)) {
973 dev_err(dev, "Couldn't create the DSI encoder regmap\n");
974 return PTR_ERR(dsi->regs);
975 }
976
977 dsi->reset = devm_reset_control_get_shared(dev, NULL);
978 if (IS_ERR(dsi->reset)) {
979 dev_err(dev, "Couldn't get our reset line\n");
980 return PTR_ERR(dsi->reset);
981 }
982
983 dsi->mod_clk = devm_clk_get(dev, "mod");
984 if (IS_ERR(dsi->mod_clk)) {
985 dev_err(dev, "Couldn't get the DSI mod clock\n");
986 return PTR_ERR(dsi->mod_clk);
987 }
988
989
990
991
992
993 clk_set_rate_exclusive(dsi->mod_clk, 297000000);
994
995 dphy_node = of_parse_phandle(dev->of_node, "phys", 0);
996 ret = sun6i_dphy_probe(dsi, dphy_node);
997 of_node_put(dphy_node);
998 if (ret) {
999 dev_err(dev, "Couldn't get the MIPI D-PHY\n");
1000 goto err_unprotect_clk;
1001 }
1002
1003 pm_runtime_enable(dev);
1004
1005 ret = mipi_dsi_host_register(&dsi->host);
1006 if (ret) {
1007 dev_err(dev, "Couldn't register MIPI-DSI host\n");
1008 goto err_remove_phy;
1009 }
1010
1011 ret = component_add(&pdev->dev, &sun6i_dsi_ops);
1012 if (ret) {
1013 dev_err(dev, "Couldn't register our component\n");
1014 goto err_remove_dsi_host;
1015 }
1016
1017 return 0;
1018
1019err_remove_dsi_host:
1020 mipi_dsi_host_unregister(&dsi->host);
1021err_remove_phy:
1022 pm_runtime_disable(dev);
1023 sun6i_dphy_remove(dsi);
1024err_unprotect_clk:
1025 clk_rate_exclusive_put(dsi->mod_clk);
1026 return ret;
1027}
1028
1029static int sun6i_dsi_remove(struct platform_device *pdev)
1030{
1031 struct device *dev = &pdev->dev;
1032 struct sun6i_dsi *dsi = dev_get_drvdata(dev);
1033
1034 component_del(&pdev->dev, &sun6i_dsi_ops);
1035 mipi_dsi_host_unregister(&dsi->host);
1036 pm_runtime_disable(dev);
1037 sun6i_dphy_remove(dsi);
1038 clk_rate_exclusive_put(dsi->mod_clk);
1039
1040 return 0;
1041}
1042
1043static int sun6i_dsi_runtime_resume(struct device *dev)
1044{
1045 struct sun6i_dsi *dsi = dev_get_drvdata(dev);
1046
1047 reset_control_deassert(dsi->reset);
1048 clk_prepare_enable(dsi->mod_clk);
1049
1050
1051
1052
1053
1054
1055
1056 regmap_write(dsi->regs, SUN6I_DSI_CTL_REG, SUN6I_DSI_CTL_EN);
1057
1058 regmap_write(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
1059 SUN6I_DSI_BASIC_CTL0_ECC_EN | SUN6I_DSI_BASIC_CTL0_CRC_EN);
1060
1061 regmap_write(dsi->regs, SUN6I_DSI_TRANS_START_REG, 10);
1062 regmap_write(dsi->regs, SUN6I_DSI_TRANS_ZERO_REG, 0);
1063
1064 if (dsi->device)
1065 sun6i_dsi_inst_init(dsi, dsi->device);
1066
1067 regmap_write(dsi->regs, SUN6I_DSI_DEBUG_DATA_REG, 0xff);
1068
1069 return 0;
1070}
1071
1072static int sun6i_dsi_runtime_suspend(struct device *dev)
1073{
1074 struct sun6i_dsi *dsi = dev_get_drvdata(dev);
1075
1076 clk_disable_unprepare(dsi->mod_clk);
1077 reset_control_assert(dsi->reset);
1078
1079 return 0;
1080}
1081
1082static const struct dev_pm_ops sun6i_dsi_pm_ops = {
1083 SET_RUNTIME_PM_OPS(sun6i_dsi_runtime_suspend,
1084 sun6i_dsi_runtime_resume,
1085 NULL)
1086};
1087
1088static const struct of_device_id sun6i_dsi_of_table[] = {
1089 { .compatible = "allwinner,sun6i-a31-mipi-dsi" },
1090 { }
1091};
1092MODULE_DEVICE_TABLE(of, sun6i_dsi_of_table);
1093
1094static struct platform_driver sun6i_dsi_platform_driver = {
1095 .probe = sun6i_dsi_probe,
1096 .remove = sun6i_dsi_remove,
1097 .driver = {
1098 .name = "sun6i-mipi-dsi",
1099 .of_match_table = sun6i_dsi_of_table,
1100 .pm = &sun6i_dsi_pm_ops,
1101 },
1102};
1103module_platform_driver(sun6i_dsi_platform_driver);
1104
1105MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1106MODULE_DESCRIPTION("Allwinner A31 DSI Driver");
1107MODULE_LICENSE("GPL");
1108
