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8#include <linux/module.h>
9#include <linux/platform_device.h>
10#include <linux/i2c.h>
11#include <linux/io.h>
12#include <linux/interrupt.h>
13#include <linux/err.h>
14#include <linux/clk.h>
15
16#define DRIVER_NAME "efm32-i2c"
17
18#define MASK_VAL(mask, val) ((val << __ffs(mask)) & mask)
19
20#define REG_CTRL 0x00
21#define REG_CTRL_EN 0x00001
22#define REG_CTRL_SLAVE 0x00002
23#define REG_CTRL_AUTOACK 0x00004
24#define REG_CTRL_AUTOSE 0x00008
25#define REG_CTRL_AUTOSN 0x00010
26#define REG_CTRL_ARBDIS 0x00020
27#define REG_CTRL_GCAMEN 0x00040
28#define REG_CTRL_CLHR__MASK 0x00300
29#define REG_CTRL_BITO__MASK 0x03000
30#define REG_CTRL_BITO_OFF 0x00000
31#define REG_CTRL_BITO_40PCC 0x01000
32#define REG_CTRL_BITO_80PCC 0x02000
33#define REG_CTRL_BITO_160PCC 0x03000
34#define REG_CTRL_GIBITO 0x08000
35#define REG_CTRL_CLTO__MASK 0x70000
36#define REG_CTRL_CLTO_OFF 0x00000
37
38#define REG_CMD 0x04
39#define REG_CMD_START 0x00001
40#define REG_CMD_STOP 0x00002
41#define REG_CMD_ACK 0x00004
42#define REG_CMD_NACK 0x00008
43#define REG_CMD_CONT 0x00010
44#define REG_CMD_ABORT 0x00020
45#define REG_CMD_CLEARTX 0x00040
46#define REG_CMD_CLEARPC 0x00080
47
48#define REG_STATE 0x08
49#define REG_STATE_BUSY 0x00001
50#define REG_STATE_MASTER 0x00002
51#define REG_STATE_TRANSMITTER 0x00004
52#define REG_STATE_NACKED 0x00008
53#define REG_STATE_BUSHOLD 0x00010
54#define REG_STATE_STATE__MASK 0x000e0
55#define REG_STATE_STATE_IDLE 0x00000
56#define REG_STATE_STATE_WAIT 0x00020
57#define REG_STATE_STATE_START 0x00040
58#define REG_STATE_STATE_ADDR 0x00060
59#define REG_STATE_STATE_ADDRACK 0x00080
60#define REG_STATE_STATE_DATA 0x000a0
61#define REG_STATE_STATE_DATAACK 0x000c0
62
63#define REG_STATUS 0x0c
64#define REG_STATUS_PSTART 0x00001
65#define REG_STATUS_PSTOP 0x00002
66#define REG_STATUS_PACK 0x00004
67#define REG_STATUS_PNACK 0x00008
68#define REG_STATUS_PCONT 0x00010
69#define REG_STATUS_PABORT 0x00020
70#define REG_STATUS_TXC 0x00040
71#define REG_STATUS_TXBL 0x00080
72#define REG_STATUS_RXDATAV 0x00100
73
74#define REG_CLKDIV 0x10
75#define REG_CLKDIV_DIV__MASK 0x001ff
76#define REG_CLKDIV_DIV(div) MASK_VAL(REG_CLKDIV_DIV__MASK, (div))
77
78#define REG_SADDR 0x14
79#define REG_SADDRMASK 0x18
80#define REG_RXDATA 0x1c
81#define REG_RXDATAP 0x20
82#define REG_TXDATA 0x24
83#define REG_IF 0x28
84#define REG_IF_START 0x00001
85#define REG_IF_RSTART 0x00002
86#define REG_IF_ADDR 0x00004
87#define REG_IF_TXC 0x00008
88#define REG_IF_TXBL 0x00010
89#define REG_IF_RXDATAV 0x00020
90#define REG_IF_ACK 0x00040
91#define REG_IF_NACK 0x00080
92#define REG_IF_MSTOP 0x00100
93#define REG_IF_ARBLOST 0x00200
94#define REG_IF_BUSERR 0x00400
95#define REG_IF_BUSHOLD 0x00800
96#define REG_IF_TXOF 0x01000
97#define REG_IF_RXUF 0x02000
98#define REG_IF_BITO 0x04000
99#define REG_IF_CLTO 0x08000
100#define REG_IF_SSTOP 0x10000
101
102#define REG_IFS 0x2c
103#define REG_IFC 0x30
104#define REG_IFC__MASK 0x1ffcf
105
106#define REG_IEN 0x34
107
108#define REG_ROUTE 0x38
109#define REG_ROUTE_SDAPEN 0x00001
110#define REG_ROUTE_SCLPEN 0x00002
111#define REG_ROUTE_LOCATION__MASK 0x00700
112#define REG_ROUTE_LOCATION(n) MASK_VAL(REG_ROUTE_LOCATION__MASK, (n))
113
114struct efm32_i2c_ddata {
115 struct i2c_adapter adapter;
116
117 struct clk *clk;
118 void __iomem *base;
119 unsigned int irq;
120 u8 location;
121 unsigned long frequency;
122
123
124 struct completion done;
125 struct i2c_msg *msgs;
126 size_t num_msgs;
127 size_t current_word, current_msg;
128 int retval;
129};
130
131static u32 efm32_i2c_read32(struct efm32_i2c_ddata *ddata, unsigned offset)
132{
133 return readl(ddata->base + offset);
134}
135
136static void efm32_i2c_write32(struct efm32_i2c_ddata *ddata,
137 unsigned offset, u32 value)
138{
139 writel(value, ddata->base + offset);
140}
141
142static void efm32_i2c_send_next_msg(struct efm32_i2c_ddata *ddata)
143{
144 struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg];
145
146 efm32_i2c_write32(ddata, REG_CMD, REG_CMD_START);
147 efm32_i2c_write32(ddata, REG_TXDATA, i2c_8bit_addr_from_msg(cur_msg));
148}
149
150static void efm32_i2c_send_next_byte(struct efm32_i2c_ddata *ddata)
151{
152 struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg];
153
154 if (ddata->current_word >= cur_msg->len) {
155
156 ddata->current_word = 0;
157 ddata->current_msg += 1;
158
159 if (ddata->current_msg >= ddata->num_msgs) {
160 efm32_i2c_write32(ddata, REG_CMD, REG_CMD_STOP);
161 complete(&ddata->done);
162 } else {
163 efm32_i2c_send_next_msg(ddata);
164 }
165 } else {
166 efm32_i2c_write32(ddata, REG_TXDATA,
167 cur_msg->buf[ddata->current_word++]);
168 }
169}
170
171static void efm32_i2c_recv_next_byte(struct efm32_i2c_ddata *ddata)
172{
173 struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg];
174
175 cur_msg->buf[ddata->current_word] = efm32_i2c_read32(ddata, REG_RXDATA);
176 ddata->current_word += 1;
177 if (ddata->current_word >= cur_msg->len) {
178
179 ddata->current_word = 0;
180 ddata->current_msg += 1;
181
182 efm32_i2c_write32(ddata, REG_CMD, REG_CMD_NACK);
183
184 if (ddata->current_msg >= ddata->num_msgs) {
185 efm32_i2c_write32(ddata, REG_CMD, REG_CMD_STOP);
186 complete(&ddata->done);
187 } else {
188 efm32_i2c_send_next_msg(ddata);
189 }
190 } else {
191 efm32_i2c_write32(ddata, REG_CMD, REG_CMD_ACK);
192 }
193}
194
195static irqreturn_t efm32_i2c_irq(int irq, void *dev_id)
196{
197 struct efm32_i2c_ddata *ddata = dev_id;
198 struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg];
199 u32 irqflag = efm32_i2c_read32(ddata, REG_IF);
200 u32 state = efm32_i2c_read32(ddata, REG_STATE);
201
202 efm32_i2c_write32(ddata, REG_IFC, irqflag & REG_IFC__MASK);
203
204 switch (state & REG_STATE_STATE__MASK) {
205 case REG_STATE_STATE_IDLE:
206
207 ddata->retval = -EAGAIN;
208 complete(&ddata->done);
209 break;
210 case REG_STATE_STATE_WAIT:
211
212
213
214
215 ddata->retval = -EIO;
216 efm32_i2c_write32(ddata, REG_CMD,
217 REG_CMD_STOP | REG_CMD_ABORT |
218 REG_CMD_CLEARTX | REG_CMD_CLEARPC);
219 complete(&ddata->done);
220 break;
221 case REG_STATE_STATE_START:
222
223 break;
224 case REG_STATE_STATE_ADDR:
225
226 break;
227 case REG_STATE_STATE_ADDRACK:
228 if (state & REG_STATE_NACKED) {
229 efm32_i2c_write32(ddata, REG_CMD, REG_CMD_STOP);
230 ddata->retval = -ENXIO;
231 complete(&ddata->done);
232 } else if (cur_msg->flags & I2C_M_RD) {
233
234 } else {
235 efm32_i2c_send_next_byte(ddata);
236 }
237 break;
238 case REG_STATE_STATE_DATA:
239 if (cur_msg->flags & I2C_M_RD) {
240 efm32_i2c_recv_next_byte(ddata);
241 } else {
242
243 }
244 break;
245 case REG_STATE_STATE_DATAACK:
246 if (state & REG_STATE_NACKED) {
247 efm32_i2c_write32(ddata, REG_CMD, REG_CMD_STOP);
248 complete(&ddata->done);
249 } else {
250 efm32_i2c_send_next_byte(ddata);
251 }
252 }
253
254 return IRQ_HANDLED;
255}
256
257static int efm32_i2c_master_xfer(struct i2c_adapter *adap,
258 struct i2c_msg *msgs, int num)
259{
260 struct efm32_i2c_ddata *ddata = i2c_get_adapdata(adap);
261 int ret;
262
263 if (ddata->msgs)
264 return -EBUSY;
265
266 ddata->msgs = msgs;
267 ddata->num_msgs = num;
268 ddata->current_word = 0;
269 ddata->current_msg = 0;
270 ddata->retval = -EIO;
271
272 reinit_completion(&ddata->done);
273
274 dev_dbg(&ddata->adapter.dev, "state: %08x, status: %08x\n",
275 efm32_i2c_read32(ddata, REG_STATE),
276 efm32_i2c_read32(ddata, REG_STATUS));
277
278 efm32_i2c_send_next_msg(ddata);
279
280 wait_for_completion(&ddata->done);
281
282 if (ddata->current_msg >= ddata->num_msgs)
283 ret = ddata->num_msgs;
284 else
285 ret = ddata->retval;
286
287 return ret;
288}
289
290static u32 efm32_i2c_functionality(struct i2c_adapter *adap)
291{
292 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
293}
294
295static const struct i2c_algorithm efm32_i2c_algo = {
296 .master_xfer = efm32_i2c_master_xfer,
297 .functionality = efm32_i2c_functionality,
298};
299
300static u32 efm32_i2c_get_configured_location(struct efm32_i2c_ddata *ddata)
301{
302 u32 reg = efm32_i2c_read32(ddata, REG_ROUTE);
303
304 return (reg & REG_ROUTE_LOCATION__MASK) >>
305 __ffs(REG_ROUTE_LOCATION__MASK);
306}
307
308static int efm32_i2c_probe(struct platform_device *pdev)
309{
310 struct efm32_i2c_ddata *ddata;
311 struct resource *res;
312 unsigned long rate;
313 struct device_node *np = pdev->dev.of_node;
314 u32 location, frequency;
315 int ret;
316 u32 clkdiv;
317
318 if (!np)
319 return -EINVAL;
320
321 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
322 if (!ddata)
323 return -ENOMEM;
324 platform_set_drvdata(pdev, ddata);
325
326 init_completion(&ddata->done);
327 strlcpy(ddata->adapter.name, pdev->name, sizeof(ddata->adapter.name));
328 ddata->adapter.owner = THIS_MODULE;
329 ddata->adapter.algo = &efm32_i2c_algo;
330 ddata->adapter.dev.parent = &pdev->dev;
331 ddata->adapter.dev.of_node = pdev->dev.of_node;
332 i2c_set_adapdata(&ddata->adapter, ddata);
333
334 ddata->clk = devm_clk_get(&pdev->dev, NULL);
335 if (IS_ERR(ddata->clk)) {
336 ret = PTR_ERR(ddata->clk);
337 dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
338 return ret;
339 }
340
341 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
342 if (!res) {
343 dev_err(&pdev->dev, "failed to determine base address\n");
344 return -ENODEV;
345 }
346
347 if (resource_size(res) < 0x42) {
348 dev_err(&pdev->dev, "memory resource too small\n");
349 return -EINVAL;
350 }
351
352 ddata->base = devm_ioremap_resource(&pdev->dev, res);
353 if (IS_ERR(ddata->base))
354 return PTR_ERR(ddata->base);
355
356 ret = platform_get_irq(pdev, 0);
357 if (ret <= 0) {
358 dev_err(&pdev->dev, "failed to get irq (%d)\n", ret);
359 if (!ret)
360 ret = -EINVAL;
361 return ret;
362 }
363
364 ddata->irq = ret;
365
366 ret = clk_prepare_enable(ddata->clk);
367 if (ret < 0) {
368 dev_err(&pdev->dev, "failed to enable clock (%d)\n", ret);
369 return ret;
370 }
371
372
373 ret = of_property_read_u32(np, "energymicro,location", &location);
374
375 if (ret)
376
377 ret = of_property_read_u32(np, "efm32,location", &location);
378
379 if (!ret) {
380 dev_dbg(&pdev->dev, "using location %u\n", location);
381 } else {
382
383 location = efm32_i2c_get_configured_location(ddata);
384
385 dev_info(&pdev->dev, "fall back to location %u\n", location);
386 }
387
388 ddata->location = location;
389
390 ret = of_property_read_u32(np, "clock-frequency", &frequency);
391 if (!ret) {
392 dev_dbg(&pdev->dev, "using frequency %u\n", frequency);
393 } else {
394 frequency = 100000;
395 dev_info(&pdev->dev, "defaulting to 100 kHz\n");
396 }
397 ddata->frequency = frequency;
398
399 rate = clk_get_rate(ddata->clk);
400 if (!rate) {
401 dev_err(&pdev->dev, "there is no input clock available\n");
402 ret = -EINVAL;
403 goto err_disable_clk;
404 }
405 clkdiv = DIV_ROUND_UP(rate, 8 * ddata->frequency) - 1;
406 if (clkdiv >= 0x200) {
407 dev_err(&pdev->dev,
408 "input clock too fast (%lu) to divide down to bus freq (%lu)",
409 rate, ddata->frequency);
410 ret = -EINVAL;
411 goto err_disable_clk;
412 }
413
414 dev_dbg(&pdev->dev, "input clock = %lu, bus freq = %lu, clkdiv = %lu\n",
415 rate, ddata->frequency, (unsigned long)clkdiv);
416 efm32_i2c_write32(ddata, REG_CLKDIV, REG_CLKDIV_DIV(clkdiv));
417
418 efm32_i2c_write32(ddata, REG_ROUTE, REG_ROUTE_SDAPEN |
419 REG_ROUTE_SCLPEN |
420 REG_ROUTE_LOCATION(ddata->location));
421
422 efm32_i2c_write32(ddata, REG_CTRL, REG_CTRL_EN |
423 REG_CTRL_BITO_160PCC | 0 * REG_CTRL_GIBITO);
424
425 efm32_i2c_write32(ddata, REG_IFC, REG_IFC__MASK);
426 efm32_i2c_write32(ddata, REG_IEN, REG_IF_TXC | REG_IF_ACK | REG_IF_NACK
427 | REG_IF_ARBLOST | REG_IF_BUSERR | REG_IF_RXDATAV);
428
429
430 efm32_i2c_write32(ddata, REG_CMD, REG_CMD_ABORT);
431
432 ret = request_irq(ddata->irq, efm32_i2c_irq, 0, DRIVER_NAME, ddata);
433 if (ret < 0) {
434 dev_err(&pdev->dev, "failed to request irq (%d)\n", ret);
435 goto err_disable_clk;
436 }
437
438 ret = i2c_add_adapter(&ddata->adapter);
439 if (ret) {
440 free_irq(ddata->irq, ddata);
441
442err_disable_clk:
443 clk_disable_unprepare(ddata->clk);
444 }
445 return ret;
446}
447
448static int efm32_i2c_remove(struct platform_device *pdev)
449{
450 struct efm32_i2c_ddata *ddata = platform_get_drvdata(pdev);
451
452 i2c_del_adapter(&ddata->adapter);
453 free_irq(ddata->irq, ddata);
454 clk_disable_unprepare(ddata->clk);
455
456 return 0;
457}
458
459static const struct of_device_id efm32_i2c_dt_ids[] = {
460 {
461 .compatible = "energymicro,efm32-i2c",
462 }, {
463
464 }
465};
466MODULE_DEVICE_TABLE(of, efm32_i2c_dt_ids);
467
468static struct platform_driver efm32_i2c_driver = {
469 .probe = efm32_i2c_probe,
470 .remove = efm32_i2c_remove,
471
472 .driver = {
473 .name = DRIVER_NAME,
474 .of_match_table = efm32_i2c_dt_ids,
475 },
476};
477module_platform_driver(efm32_i2c_driver);
478
479MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
480MODULE_DESCRIPTION("EFM32 i2c driver");
481MODULE_LICENSE("GPL v2");
482MODULE_ALIAS("platform:" DRIVER_NAME);
483
