linux/drivers/net/ethernet/broadcom/sb1250-mac.c
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   1/*
   2 * Copyright (C) 2001,2002,2003,2004 Broadcom Corporation
   3 * Copyright (c) 2006, 2007  Maciej W. Rozycki
   4 *
   5 * This program is free software; you can redistribute it and/or
   6 * modify it under the terms of the GNU General Public License
   7 * as published by the Free Software Foundation; either version 2
   8 * of the License, or (at your option) any later version.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, see <http://www.gnu.org/licenses/>.
  17 *
  18 *
  19 * This driver is designed for the Broadcom SiByte SOC built-in
  20 * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp.
  21 *
  22 * Updated to the driver model and the PHY abstraction layer
  23 * by Maciej W. Rozycki.
  24 */
  25
  26#include <linux/bug.h>
  27#include <linux/module.h>
  28#include <linux/kernel.h>
  29#include <linux/string.h>
  30#include <linux/timer.h>
  31#include <linux/errno.h>
  32#include <linux/ioport.h>
  33#include <linux/slab.h>
  34#include <linux/interrupt.h>
  35#include <linux/netdevice.h>
  36#include <linux/etherdevice.h>
  37#include <linux/skbuff.h>
  38#include <linux/bitops.h>
  39#include <linux/err.h>
  40#include <linux/ethtool.h>
  41#include <linux/mii.h>
  42#include <linux/phy.h>
  43#include <linux/platform_device.h>
  44#include <linux/prefetch.h>
  45
  46#include <asm/cache.h>
  47#include <asm/io.h>
  48#include <asm/processor.h>      /* Processor type for cache alignment. */
  49
  50/* Operational parameters that usually are not changed. */
  51
  52#define CONFIG_SBMAC_COALESCE
  53
  54/* Time in jiffies before concluding the transmitter is hung. */
  55#define TX_TIMEOUT  (2*HZ)
  56
  57
  58MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)");
  59MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver");
  60
  61/* A few user-configurable values which may be modified when a driver
  62   module is loaded. */
  63
  64/* 1 normal messages, 0 quiet .. 7 verbose. */
  65static int debug = 1;
  66module_param(debug, int, 0444);
  67MODULE_PARM_DESC(debug, "Debug messages");
  68
  69#ifdef CONFIG_SBMAC_COALESCE
  70static int int_pktcnt_tx = 255;
  71module_param(int_pktcnt_tx, int, 0444);
  72MODULE_PARM_DESC(int_pktcnt_tx, "TX packet count");
  73
  74static int int_timeout_tx = 255;
  75module_param(int_timeout_tx, int, 0444);
  76MODULE_PARM_DESC(int_timeout_tx, "TX timeout value");
  77
  78static int int_pktcnt_rx = 64;
  79module_param(int_pktcnt_rx, int, 0444);
  80MODULE_PARM_DESC(int_pktcnt_rx, "RX packet count");
  81
  82static int int_timeout_rx = 64;
  83module_param(int_timeout_rx, int, 0444);
  84MODULE_PARM_DESC(int_timeout_rx, "RX timeout value");
  85#endif
  86
  87#include <asm/sibyte/board.h>
  88#include <asm/sibyte/sb1250.h>
  89#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
  90#include <asm/sibyte/bcm1480_regs.h>
  91#include <asm/sibyte/bcm1480_int.h>
  92#define R_MAC_DMA_OODPKTLOST_RX R_MAC_DMA_OODPKTLOST
  93#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
  94#include <asm/sibyte/sb1250_regs.h>
  95#include <asm/sibyte/sb1250_int.h>
  96#else
  97#error invalid SiByte MAC configuration
  98#endif
  99#include <asm/sibyte/sb1250_scd.h>
 100#include <asm/sibyte/sb1250_mac.h>
 101#include <asm/sibyte/sb1250_dma.h>
 102
 103#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
 104#define UNIT_INT(n)             (K_BCM1480_INT_MAC_0 + ((n) * 2))
 105#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
 106#define UNIT_INT(n)             (K_INT_MAC_0 + (n))
 107#else
 108#error invalid SiByte MAC configuration
 109#endif
 110
 111#ifdef K_INT_PHY
 112#define SBMAC_PHY_INT                   K_INT_PHY
 113#else
 114#define SBMAC_PHY_INT                   PHY_POLL
 115#endif
 116
 117/**********************************************************************
 118 *  Simple types
 119 ********************************************************************* */
 120
 121enum sbmac_speed {
 122        sbmac_speed_none = 0,
 123        sbmac_speed_10 = SPEED_10,
 124        sbmac_speed_100 = SPEED_100,
 125        sbmac_speed_1000 = SPEED_1000,
 126};
 127
 128enum sbmac_duplex {
 129        sbmac_duplex_none = -1,
 130        sbmac_duplex_half = DUPLEX_HALF,
 131        sbmac_duplex_full = DUPLEX_FULL,
 132};
 133
 134enum sbmac_fc {
 135        sbmac_fc_none,
 136        sbmac_fc_disabled,
 137        sbmac_fc_frame,
 138        sbmac_fc_collision,
 139        sbmac_fc_carrier,
 140};
 141
 142enum sbmac_state {
 143        sbmac_state_uninit,
 144        sbmac_state_off,
 145        sbmac_state_on,
 146        sbmac_state_broken,
 147};
 148
 149
 150/**********************************************************************
 151 *  Macros
 152 ********************************************************************* */
 153
 154
 155#define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \
 156                          (d)->sbdma_dscrtable : (d)->f+1)
 157
 158
 159#define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
 160
 161#define SBMAC_MAX_TXDESCR       256
 162#define SBMAC_MAX_RXDESCR       256
 163
 164#define ENET_PACKET_SIZE        1518
 165/*#define ENET_PACKET_SIZE      9216 */
 166
 167/**********************************************************************
 168 *  DMA Descriptor structure
 169 ********************************************************************* */
 170
 171struct sbdmadscr {
 172        uint64_t  dscr_a;
 173        uint64_t  dscr_b;
 174};
 175
 176/**********************************************************************
 177 *  DMA Controller structure
 178 ********************************************************************* */
 179
 180struct sbmacdma {
 181
 182        /*
 183         * This stuff is used to identify the channel and the registers
 184         * associated with it.
 185         */
 186        struct sbmac_softc      *sbdma_eth;     /* back pointer to associated
 187                                                   MAC */
 188        int                     sbdma_channel;  /* channel number */
 189        int                     sbdma_txdir;    /* direction (1=transmit) */
 190        int                     sbdma_maxdescr; /* total # of descriptors
 191                                                   in ring */
 192#ifdef CONFIG_SBMAC_COALESCE
 193        int                     sbdma_int_pktcnt;
 194                                                /* # descriptors rx/tx
 195                                                   before interrupt */
 196        int                     sbdma_int_timeout;
 197                                                /* # usec rx/tx interrupt */
 198#endif
 199        void __iomem            *sbdma_config0; /* DMA config register 0 */
 200        void __iomem            *sbdma_config1; /* DMA config register 1 */
 201        void __iomem            *sbdma_dscrbase;
 202                                                /* descriptor base address */
 203        void __iomem            *sbdma_dscrcnt; /* descriptor count register */
 204        void __iomem            *sbdma_curdscr; /* current descriptor
 205                                                   address */
 206        void __iomem            *sbdma_oodpktlost;
 207                                                /* pkt drop (rx only) */
 208
 209        /*
 210         * This stuff is for maintenance of the ring
 211         */
 212        void                    *sbdma_dscrtable_unaligned;
 213        struct sbdmadscr        *sbdma_dscrtable;
 214                                                /* base of descriptor table */
 215        struct sbdmadscr        *sbdma_dscrtable_end;
 216                                                /* end of descriptor table */
 217        struct sk_buff          **sbdma_ctxtable;
 218                                                /* context table, one
 219                                                   per descr */
 220        dma_addr_t              sbdma_dscrtable_phys;
 221                                                /* and also the phys addr */
 222        struct sbdmadscr        *sbdma_addptr;  /* next dscr for sw to add */
 223        struct sbdmadscr        *sbdma_remptr;  /* next dscr for sw
 224                                                   to remove */
 225};
 226
 227
 228/**********************************************************************
 229 *  Ethernet softc structure
 230 ********************************************************************* */
 231
 232struct sbmac_softc {
 233
 234        /*
 235         * Linux-specific things
 236         */
 237        struct net_device       *sbm_dev;       /* pointer to linux device */
 238        struct napi_struct      napi;
 239        struct phy_device       *phy_dev;       /* the associated PHY device */
 240        struct mii_bus          *mii_bus;       /* the MII bus */
 241        spinlock_t              sbm_lock;       /* spin lock */
 242        int                     sbm_devflags;   /* current device flags */
 243
 244        /*
 245         * Controller-specific things
 246         */
 247        void __iomem            *sbm_base;      /* MAC's base address */
 248        enum sbmac_state        sbm_state;      /* current state */
 249
 250        void __iomem            *sbm_macenable; /* MAC Enable Register */
 251        void __iomem            *sbm_maccfg;    /* MAC Config Register */
 252        void __iomem            *sbm_fifocfg;   /* FIFO Config Register */
 253        void __iomem            *sbm_framecfg;  /* Frame Config Register */
 254        void __iomem            *sbm_rxfilter;  /* Receive Filter Register */
 255        void __iomem            *sbm_isr;       /* Interrupt Status Register */
 256        void __iomem            *sbm_imr;       /* Interrupt Mask Register */
 257        void __iomem            *sbm_mdio;      /* MDIO Register */
 258
 259        enum sbmac_speed        sbm_speed;      /* current speed */
 260        enum sbmac_duplex       sbm_duplex;     /* current duplex */
 261        enum sbmac_fc           sbm_fc;         /* cur. flow control setting */
 262        int                     sbm_pause;      /* current pause setting */
 263        int                     sbm_link;       /* current link state */
 264
 265        unsigned char           sbm_hwaddr[ETH_ALEN];
 266
 267        struct sbmacdma         sbm_txdma;      /* only channel 0 for now */
 268        struct sbmacdma         sbm_rxdma;
 269        int                     rx_hw_checksum;
 270        int                     sbe_idx;
 271};
 272
 273
 274/**********************************************************************
 275 *  Externs
 276 ********************************************************************* */
 277
 278/**********************************************************************
 279 *  Prototypes
 280 ********************************************************************* */
 281
 282static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan,
 283                          int txrx, int maxdescr);
 284static void sbdma_channel_start(struct sbmacdma *d, int rxtx);
 285static int sbdma_add_rcvbuffer(struct sbmac_softc *sc, struct sbmacdma *d,
 286                               struct sk_buff *m);
 287static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *m);
 288static void sbdma_emptyring(struct sbmacdma *d);
 289static void sbdma_fillring(struct sbmac_softc *sc, struct sbmacdma *d);
 290static int sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d,
 291                            int work_to_do, int poll);
 292static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d,
 293                             int poll);
 294static int sbmac_initctx(struct sbmac_softc *s);
 295static void sbmac_channel_start(struct sbmac_softc *s);
 296static void sbmac_channel_stop(struct sbmac_softc *s);
 297static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *,
 298                                                enum sbmac_state);
 299static void sbmac_promiscuous_mode(struct sbmac_softc *sc, int onoff);
 300static uint64_t sbmac_addr2reg(unsigned char *ptr);
 301static irqreturn_t sbmac_intr(int irq, void *dev_instance);
 302static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev);
 303static void sbmac_setmulti(struct sbmac_softc *sc);
 304static int sbmac_init(struct platform_device *pldev, long long base);
 305static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed);
 306static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex,
 307                            enum sbmac_fc fc);
 308
 309static int sbmac_open(struct net_device *dev);
 310static void sbmac_tx_timeout (struct net_device *dev, unsigned int txqueue);
 311static void sbmac_set_rx_mode(struct net_device *dev);
 312static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 313static int sbmac_close(struct net_device *dev);
 314static int sbmac_poll(struct napi_struct *napi, int budget);
 315
 316static void sbmac_mii_poll(struct net_device *dev);
 317static int sbmac_mii_probe(struct net_device *dev);
 318
 319static void sbmac_mii_sync(void __iomem *sbm_mdio);
 320static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data,
 321                               int bitcnt);
 322static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx);
 323static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
 324                           u16 val);
 325
 326
 327/**********************************************************************
 328 *  Globals
 329 ********************************************************************* */
 330
 331static char sbmac_string[] = "sb1250-mac";
 332
 333static char sbmac_mdio_string[] = "sb1250-mac-mdio";
 334
 335
 336/**********************************************************************
 337 *  MDIO constants
 338 ********************************************************************* */
 339
 340#define MII_COMMAND_START       0x01
 341#define MII_COMMAND_READ        0x02
 342#define MII_COMMAND_WRITE       0x01
 343#define MII_COMMAND_ACK         0x02
 344
 345#define M_MAC_MDIO_DIR_OUTPUT   0               /* for clarity */
 346
 347#define ENABLE          1
 348#define DISABLE         0
 349
 350/**********************************************************************
 351 *  SBMAC_MII_SYNC(sbm_mdio)
 352 *
 353 *  Synchronize with the MII - send a pattern of bits to the MII
 354 *  that will guarantee that it is ready to accept a command.
 355 *
 356 *  Input parameters:
 357 *         sbm_mdio - address of the MAC's MDIO register
 358 *
 359 *  Return value:
 360 *         nothing
 361 ********************************************************************* */
 362
 363static void sbmac_mii_sync(void __iomem *sbm_mdio)
 364{
 365        int cnt;
 366        uint64_t bits;
 367        int mac_mdio_genc;
 368
 369        mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
 370
 371        bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT;
 372
 373        __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
 374
 375        for (cnt = 0; cnt < 32; cnt++) {
 376                __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio);
 377                __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
 378        }
 379}
 380
 381/**********************************************************************
 382 *  SBMAC_MII_SENDDATA(sbm_mdio, data, bitcnt)
 383 *
 384 *  Send some bits to the MII.  The bits to be sent are right-
 385 *  justified in the 'data' parameter.
 386 *
 387 *  Input parameters:
 388 *         sbm_mdio - address of the MAC's MDIO register
 389 *         data     - data to send
 390 *         bitcnt   - number of bits to send
 391 ********************************************************************* */
 392
 393static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data,
 394                               int bitcnt)
 395{
 396        int i;
 397        uint64_t bits;
 398        unsigned int curmask;
 399        int mac_mdio_genc;
 400
 401        mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
 402
 403        bits = M_MAC_MDIO_DIR_OUTPUT;
 404        __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
 405
 406        curmask = 1 << (bitcnt - 1);
 407
 408        for (i = 0; i < bitcnt; i++) {
 409                if (data & curmask)
 410                        bits |= M_MAC_MDIO_OUT;
 411                else bits &= ~M_MAC_MDIO_OUT;
 412                __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
 413                __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio);
 414                __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
 415                curmask >>= 1;
 416        }
 417}
 418
 419
 420
 421/**********************************************************************
 422 *  SBMAC_MII_READ(bus, phyaddr, regidx)
 423 *  Read a PHY register.
 424 *
 425 *  Input parameters:
 426 *         bus     - MDIO bus handle
 427 *         phyaddr - PHY's address
 428 *         regnum  - index of register to read
 429 *
 430 *  Return value:
 431 *         value read, or 0xffff if an error occurred.
 432 ********************************************************************* */
 433
 434static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
 435{
 436        struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv;
 437        void __iomem *sbm_mdio = sc->sbm_mdio;
 438        int idx;
 439        int error;
 440        int regval;
 441        int mac_mdio_genc;
 442
 443        /*
 444         * Synchronize ourselves so that the PHY knows the next
 445         * thing coming down is a command
 446         */
 447        sbmac_mii_sync(sbm_mdio);
 448
 449        /*
 450         * Send the data to the PHY.  The sequence is
 451         * a "start" command (2 bits)
 452         * a "read" command (2 bits)
 453         * the PHY addr (5 bits)
 454         * the register index (5 bits)
 455         */
 456        sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2);
 457        sbmac_mii_senddata(sbm_mdio, MII_COMMAND_READ, 2);
 458        sbmac_mii_senddata(sbm_mdio, phyaddr, 5);
 459        sbmac_mii_senddata(sbm_mdio, regidx, 5);
 460
 461        mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
 462
 463        /*
 464         * Switch the port around without a clock transition.
 465         */
 466        __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
 467
 468        /*
 469         * Send out a clock pulse to signal we want the status
 470         */
 471        __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc,
 472                     sbm_mdio);
 473        __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
 474
 475        /*
 476         * If an error occurred, the PHY will signal '1' back
 477         */
 478        error = __raw_readq(sbm_mdio) & M_MAC_MDIO_IN;
 479
 480        /*
 481         * Issue an 'idle' clock pulse, but keep the direction
 482         * the same.
 483         */
 484        __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc,
 485                     sbm_mdio);
 486        __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
 487
 488        regval = 0;
 489
 490        for (idx = 0; idx < 16; idx++) {
 491                regval <<= 1;
 492
 493                if (error == 0) {
 494                        if (__raw_readq(sbm_mdio) & M_MAC_MDIO_IN)
 495                                regval |= 1;
 496                }
 497
 498                __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc,
 499                             sbm_mdio);
 500                __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
 501        }
 502
 503        /* Switch back to output */
 504        __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio);
 505
 506        if (error == 0)
 507                return regval;
 508        return 0xffff;
 509}
 510
 511
 512/**********************************************************************
 513 *  SBMAC_MII_WRITE(bus, phyaddr, regidx, regval)
 514 *
 515 *  Write a value to a PHY register.
 516 *
 517 *  Input parameters:
 518 *         bus     - MDIO bus handle
 519 *         phyaddr - PHY to use
 520 *         regidx  - register within the PHY
 521 *         regval  - data to write to register
 522 *
 523 *  Return value:
 524 *         0 for success
 525 ********************************************************************* */
 526
 527static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
 528                           u16 regval)
 529{
 530        struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv;
 531        void __iomem *sbm_mdio = sc->sbm_mdio;
 532        int mac_mdio_genc;
 533
 534        sbmac_mii_sync(sbm_mdio);
 535
 536        sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2);
 537        sbmac_mii_senddata(sbm_mdio, MII_COMMAND_WRITE, 2);
 538        sbmac_mii_senddata(sbm_mdio, phyaddr, 5);
 539        sbmac_mii_senddata(sbm_mdio, regidx, 5);
 540        sbmac_mii_senddata(sbm_mdio, MII_COMMAND_ACK, 2);
 541        sbmac_mii_senddata(sbm_mdio, regval, 16);
 542
 543        mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
 544
 545        __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio);
 546
 547        return 0;
 548}
 549
 550
 551
 552/**********************************************************************
 553 *  SBDMA_INITCTX(d,s,chan,txrx,maxdescr)
 554 *
 555 *  Initialize a DMA channel context.  Since there are potentially
 556 *  eight DMA channels per MAC, it's nice to do this in a standard
 557 *  way.
 558 *
 559 *  Input parameters:
 560 *         d - struct sbmacdma (DMA channel context)
 561 *         s - struct sbmac_softc (pointer to a MAC)
 562 *         chan - channel number (0..1 right now)
 563 *         txrx - Identifies DMA_TX or DMA_RX for channel direction
 564 *      maxdescr - number of descriptors
 565 *
 566 *  Return value:
 567 *         nothing
 568 ********************************************************************* */
 569
 570static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan,
 571                          int txrx, int maxdescr)
 572{
 573#ifdef CONFIG_SBMAC_COALESCE
 574        int int_pktcnt, int_timeout;
 575#endif
 576
 577        /*
 578         * Save away interesting stuff in the structure
 579         */
 580
 581        d->sbdma_eth       = s;
 582        d->sbdma_channel   = chan;
 583        d->sbdma_txdir     = txrx;
 584
 585#if 0
 586        /* RMON clearing */
 587        s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING;
 588#endif
 589
 590        __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BYTES);
 591        __raw_writeq(0, s->sbm_base + R_MAC_RMON_COLLISIONS);
 592        __raw_writeq(0, s->sbm_base + R_MAC_RMON_LATE_COL);
 593        __raw_writeq(0, s->sbm_base + R_MAC_RMON_EX_COL);
 594        __raw_writeq(0, s->sbm_base + R_MAC_RMON_FCS_ERROR);
 595        __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_ABORT);
 596        __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BAD);
 597        __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_GOOD);
 598        __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_RUNT);
 599        __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_OVERSIZE);
 600        __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BYTES);
 601        __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_MCAST);
 602        __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BCAST);
 603        __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BAD);
 604        __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_GOOD);
 605        __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_RUNT);
 606        __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_OVERSIZE);
 607        __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_FCS_ERROR);
 608        __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_LENGTH_ERROR);
 609        __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_CODE_ERROR);
 610        __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_ALIGN_ERROR);
 611
 612        /*
 613         * initialize register pointers
 614         */
 615
 616        d->sbdma_config0 =
 617                s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0);
 618        d->sbdma_config1 =
 619                s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1);
 620        d->sbdma_dscrbase =
 621                s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE);
 622        d->sbdma_dscrcnt =
 623                s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT);
 624        d->sbdma_curdscr =
 625                s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR);
 626        if (d->sbdma_txdir)
 627                d->sbdma_oodpktlost = NULL;
 628        else
 629                d->sbdma_oodpktlost =
 630                        s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_OODPKTLOST_RX);
 631
 632        /*
 633         * Allocate memory for the ring
 634         */
 635
 636        d->sbdma_maxdescr = maxdescr;
 637
 638        d->sbdma_dscrtable_unaligned = kcalloc(d->sbdma_maxdescr + 1,
 639                                               sizeof(*d->sbdma_dscrtable),
 640                                               GFP_KERNEL);
 641
 642        /*
 643         * The descriptor table must be aligned to at least 16 bytes or the
 644         * MAC will corrupt it.
 645         */
 646        d->sbdma_dscrtable = (struct sbdmadscr *)
 647                             ALIGN((unsigned long)d->sbdma_dscrtable_unaligned,
 648                                   sizeof(*d->sbdma_dscrtable));
 649
 650        d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr;
 651
 652        d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable);
 653
 654        /*
 655         * And context table
 656         */
 657
 658        d->sbdma_ctxtable = kcalloc(d->sbdma_maxdescr,
 659                                    sizeof(*d->sbdma_ctxtable), GFP_KERNEL);
 660
 661#ifdef CONFIG_SBMAC_COALESCE
 662        /*
 663         * Setup Rx/Tx DMA coalescing defaults
 664         */
 665
 666        int_pktcnt = (txrx == DMA_TX) ? int_pktcnt_tx : int_pktcnt_rx;
 667        if ( int_pktcnt ) {
 668                d->sbdma_int_pktcnt = int_pktcnt;
 669        } else {
 670                d->sbdma_int_pktcnt = 1;
 671        }
 672
 673        int_timeout = (txrx == DMA_TX) ? int_timeout_tx : int_timeout_rx;
 674        if ( int_timeout ) {
 675                d->sbdma_int_timeout = int_timeout;
 676        } else {
 677                d->sbdma_int_timeout = 0;
 678        }
 679#endif
 680
 681}
 682
 683/**********************************************************************
 684 *  SBDMA_CHANNEL_START(d)
 685 *
 686 *  Initialize the hardware registers for a DMA channel.
 687 *
 688 *  Input parameters:
 689 *         d - DMA channel to init (context must be previously init'd
 690 *         rxtx - DMA_RX or DMA_TX depending on what type of channel
 691 *
 692 *  Return value:
 693 *         nothing
 694 ********************************************************************* */
 695
 696static void sbdma_channel_start(struct sbmacdma *d, int rxtx)
 697{
 698        /*
 699         * Turn on the DMA channel
 700         */
 701
 702#ifdef CONFIG_SBMAC_COALESCE
 703        __raw_writeq(V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) |
 704                       0, d->sbdma_config1);
 705        __raw_writeq(M_DMA_EOP_INT_EN |
 706                       V_DMA_RINGSZ(d->sbdma_maxdescr) |
 707                       V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) |
 708                       0, d->sbdma_config0);
 709#else
 710        __raw_writeq(0, d->sbdma_config1);
 711        __raw_writeq(V_DMA_RINGSZ(d->sbdma_maxdescr) |
 712                       0, d->sbdma_config0);
 713#endif
 714
 715        __raw_writeq(d->sbdma_dscrtable_phys, d->sbdma_dscrbase);
 716
 717        /*
 718         * Initialize ring pointers
 719         */
 720
 721        d->sbdma_addptr = d->sbdma_dscrtable;
 722        d->sbdma_remptr = d->sbdma_dscrtable;
 723}
 724
 725/**********************************************************************
 726 *  SBDMA_CHANNEL_STOP(d)
 727 *
 728 *  Initialize the hardware registers for a DMA channel.
 729 *
 730 *  Input parameters:
 731 *         d - DMA channel to init (context must be previously init'd
 732 *
 733 *  Return value:
 734 *         nothing
 735 ********************************************************************* */
 736
 737static void sbdma_channel_stop(struct sbmacdma *d)
 738{
 739        /*
 740         * Turn off the DMA channel
 741         */
 742
 743        __raw_writeq(0, d->sbdma_config1);
 744
 745        __raw_writeq(0, d->sbdma_dscrbase);
 746
 747        __raw_writeq(0, d->sbdma_config0);
 748
 749        /*
 750         * Zero ring pointers
 751         */
 752
 753        d->sbdma_addptr = NULL;
 754        d->sbdma_remptr = NULL;
 755}
 756
 757static inline void sbdma_align_skb(struct sk_buff *skb,
 758                                   unsigned int power2, unsigned int offset)
 759{
 760        unsigned char *addr = skb->data;
 761        unsigned char *newaddr = PTR_ALIGN(addr, power2);
 762
 763        skb_reserve(skb, newaddr - addr + offset);
 764}
 765
 766
 767/**********************************************************************
 768 *  SBDMA_ADD_RCVBUFFER(d,sb)
 769 *
 770 *  Add a buffer to the specified DMA channel.   For receive channels,
 771 *  this queues a buffer for inbound packets.
 772 *
 773 *  Input parameters:
 774 *         sc - softc structure
 775 *          d - DMA channel descriptor
 776 *         sb - sk_buff to add, or NULL if we should allocate one
 777 *
 778 *  Return value:
 779 *         0 if buffer could not be added (ring is full)
 780 *         1 if buffer added successfully
 781 ********************************************************************* */
 782
 783
 784static int sbdma_add_rcvbuffer(struct sbmac_softc *sc, struct sbmacdma *d,
 785                               struct sk_buff *sb)
 786{
 787        struct net_device *dev = sc->sbm_dev;
 788        struct sbdmadscr *dsc;
 789        struct sbdmadscr *nextdsc;
 790        struct sk_buff *sb_new = NULL;
 791        int pktsize = ENET_PACKET_SIZE;
 792
 793        /* get pointer to our current place in the ring */
 794
 795        dsc = d->sbdma_addptr;
 796        nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
 797
 798        /*
 799         * figure out if the ring is full - if the next descriptor
 800         * is the same as the one that we're going to remove from
 801         * the ring, the ring is full
 802         */
 803
 804        if (nextdsc == d->sbdma_remptr) {
 805                return -ENOSPC;
 806        }
 807
 808        /*
 809         * Allocate a sk_buff if we don't already have one.
 810         * If we do have an sk_buff, reset it so that it's empty.
 811         *
 812         * Note: sk_buffs don't seem to be guaranteed to have any sort
 813         * of alignment when they are allocated.  Therefore, allocate enough
 814         * extra space to make sure that:
 815         *
 816         *    1. the data does not start in the middle of a cache line.
 817         *    2. The data does not end in the middle of a cache line
 818         *    3. The buffer can be aligned such that the IP addresses are
 819         *       naturally aligned.
 820         *
 821         *  Remember, the SOCs MAC writes whole cache lines at a time,
 822         *  without reading the old contents first.  So, if the sk_buff's
 823         *  data portion starts in the middle of a cache line, the SOC
 824         *  DMA will trash the beginning (and ending) portions.
 825         */
 826
 827        if (sb == NULL) {
 828                sb_new = netdev_alloc_skb(dev, ENET_PACKET_SIZE +
 829                                               SMP_CACHE_BYTES * 2 +
 830                                               NET_IP_ALIGN);
 831                if (sb_new == NULL)
 832                        return -ENOBUFS;
 833
 834                sbdma_align_skb(sb_new, SMP_CACHE_BYTES, NET_IP_ALIGN);
 835        }
 836        else {
 837                sb_new = sb;
 838                /*
 839                 * nothing special to reinit buffer, it's already aligned
 840                 * and sb->data already points to a good place.
 841                 */
 842        }
 843
 844        /*
 845         * fill in the descriptor
 846         */
 847
 848#ifdef CONFIG_SBMAC_COALESCE
 849        /*
 850         * Do not interrupt per DMA transfer.
 851         */
 852        dsc->dscr_a = virt_to_phys(sb_new->data) |
 853                V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize + NET_IP_ALIGN)) | 0;
 854#else
 855        dsc->dscr_a = virt_to_phys(sb_new->data) |
 856                V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize + NET_IP_ALIGN)) |
 857                M_DMA_DSCRA_INTERRUPT;
 858#endif
 859
 860        /* receiving: no options */
 861        dsc->dscr_b = 0;
 862
 863        /*
 864         * fill in the context
 865         */
 866
 867        d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new;
 868
 869        /*
 870         * point at next packet
 871         */
 872
 873        d->sbdma_addptr = nextdsc;
 874
 875        /*
 876         * Give the buffer to the DMA engine.
 877         */
 878
 879        __raw_writeq(1, d->sbdma_dscrcnt);
 880
 881        return 0;                                       /* we did it */
 882}
 883
 884/**********************************************************************
 885 *  SBDMA_ADD_TXBUFFER(d,sb)
 886 *
 887 *  Add a transmit buffer to the specified DMA channel, causing a
 888 *  transmit to start.
 889 *
 890 *  Input parameters:
 891 *         d - DMA channel descriptor
 892 *         sb - sk_buff to add
 893 *
 894 *  Return value:
 895 *         0 transmit queued successfully
 896 *         otherwise error code
 897 ********************************************************************* */
 898
 899
 900static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *sb)
 901{
 902        struct sbdmadscr *dsc;
 903        struct sbdmadscr *nextdsc;
 904        uint64_t phys;
 905        uint64_t ncb;
 906        int length;
 907
 908        /* get pointer to our current place in the ring */
 909
 910        dsc = d->sbdma_addptr;
 911        nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
 912
 913        /*
 914         * figure out if the ring is full - if the next descriptor
 915         * is the same as the one that we're going to remove from
 916         * the ring, the ring is full
 917         */
 918
 919        if (nextdsc == d->sbdma_remptr) {
 920                return -ENOSPC;
 921        }
 922
 923        /*
 924         * Under Linux, it's not necessary to copy/coalesce buffers
 925         * like it is on NetBSD.  We think they're all contiguous,
 926         * but that may not be true for GBE.
 927         */
 928
 929        length = sb->len;
 930
 931        /*
 932         * fill in the descriptor.  Note that the number of cache
 933         * blocks in the descriptor is the number of blocks
 934         * *spanned*, so we need to add in the offset (if any)
 935         * while doing the calculation.
 936         */
 937
 938        phys = virt_to_phys(sb->data);
 939        ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1)));
 940
 941        dsc->dscr_a = phys |
 942                V_DMA_DSCRA_A_SIZE(ncb) |
 943#ifndef CONFIG_SBMAC_COALESCE
 944                M_DMA_DSCRA_INTERRUPT |
 945#endif
 946                M_DMA_ETHTX_SOP;
 947
 948        /* transmitting: set outbound options and length */
 949
 950        dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) |
 951                V_DMA_DSCRB_PKT_SIZE(length);
 952
 953        /*
 954         * fill in the context
 955         */
 956
 957        d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb;
 958
 959        /*
 960         * point at next packet
 961         */
 962
 963        d->sbdma_addptr = nextdsc;
 964
 965        /*
 966         * Give the buffer to the DMA engine.
 967         */
 968
 969        __raw_writeq(1, d->sbdma_dscrcnt);
 970
 971        return 0;                                       /* we did it */
 972}
 973
 974
 975
 976
 977/**********************************************************************
 978 *  SBDMA_EMPTYRING(d)
 979 *
 980 *  Free all allocated sk_buffs on the specified DMA channel;
 981 *
 982 *  Input parameters:
 983 *         d  - DMA channel
 984 *
 985 *  Return value:
 986 *         nothing
 987 ********************************************************************* */
 988
 989static void sbdma_emptyring(struct sbmacdma *d)
 990{
 991        int idx;
 992        struct sk_buff *sb;
 993
 994        for (idx = 0; idx < d->sbdma_maxdescr; idx++) {
 995                sb = d->sbdma_ctxtable[idx];
 996                if (sb) {
 997                        dev_kfree_skb(sb);
 998                        d->sbdma_ctxtable[idx] = NULL;
 999                }
1000        }
1001}
1002
1003
1004/**********************************************************************
1005 *  SBDMA_FILLRING(d)
1006 *
1007 *  Fill the specified DMA channel (must be receive channel)
1008 *  with sk_buffs
1009 *
1010 *  Input parameters:
1011 *         sc - softc structure
1012 *          d - DMA channel
1013 *
1014 *  Return value:
1015 *         nothing
1016 ********************************************************************* */
1017
1018static void sbdma_fillring(struct sbmac_softc *sc, struct sbmacdma *d)
1019{
1020        int idx;
1021
1022        for (idx = 0; idx < SBMAC_MAX_RXDESCR - 1; idx++) {
1023                if (sbdma_add_rcvbuffer(sc, d, NULL) != 0)
1024                        break;
1025        }
1026}
1027
1028#ifdef CONFIG_NET_POLL_CONTROLLER
1029static void sbmac_netpoll(struct net_device *netdev)
1030{
1031        struct sbmac_softc *sc = netdev_priv(netdev);
1032        int irq = sc->sbm_dev->irq;
1033
1034        __raw_writeq(0, sc->sbm_imr);
1035
1036        sbmac_intr(irq, netdev);
1037
1038#ifdef CONFIG_SBMAC_COALESCE
1039        __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1040        ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0),
1041        sc->sbm_imr);
1042#else
1043        __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1044        (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr);
1045#endif
1046}
1047#endif
1048
1049/**********************************************************************
1050 *  SBDMA_RX_PROCESS(sc,d,work_to_do,poll)
1051 *
1052 *  Process "completed" receive buffers on the specified DMA channel.
1053 *
1054 *  Input parameters:
1055 *            sc - softc structure
1056 *             d - DMA channel context
1057 *    work_to_do - no. of packets to process before enabling interrupt
1058 *                 again (for NAPI)
1059 *          poll - 1: using polling (for NAPI)
1060 *
1061 *  Return value:
1062 *         nothing
1063 ********************************************************************* */
1064
1065static int sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d,
1066                            int work_to_do, int poll)
1067{
1068        struct net_device *dev = sc->sbm_dev;
1069        int curidx;
1070        int hwidx;
1071        struct sbdmadscr *dsc;
1072        struct sk_buff *sb;
1073        int len;
1074        int work_done = 0;
1075        int dropped = 0;
1076
1077        prefetch(d);
1078
1079again:
1080        /* Check if the HW dropped any frames */
1081        dev->stats.rx_fifo_errors
1082            += __raw_readq(sc->sbm_rxdma.sbdma_oodpktlost) & 0xffff;
1083        __raw_writeq(0, sc->sbm_rxdma.sbdma_oodpktlost);
1084
1085        while (work_to_do-- > 0) {
1086                /*
1087                 * figure out where we are (as an index) and where
1088                 * the hardware is (also as an index)
1089                 *
1090                 * This could be done faster if (for example) the
1091                 * descriptor table was page-aligned and contiguous in
1092                 * both virtual and physical memory -- you could then
1093                 * just compare the low-order bits of the virtual address
1094                 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1095                 */
1096
1097                dsc = d->sbdma_remptr;
1098                curidx = dsc - d->sbdma_dscrtable;
1099
1100                prefetch(dsc);
1101                prefetch(&d->sbdma_ctxtable[curidx]);
1102
1103                hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1104                         d->sbdma_dscrtable_phys) /
1105                        sizeof(*d->sbdma_dscrtable);
1106
1107                /*
1108                 * If they're the same, that means we've processed all
1109                 * of the descriptors up to (but not including) the one that
1110                 * the hardware is working on right now.
1111                 */
1112
1113                if (curidx == hwidx)
1114                        goto done;
1115
1116                /*
1117                 * Otherwise, get the packet's sk_buff ptr back
1118                 */
1119
1120                sb = d->sbdma_ctxtable[curidx];
1121                d->sbdma_ctxtable[curidx] = NULL;
1122
1123                len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4;
1124
1125                /*
1126                 * Check packet status.  If good, process it.
1127                 * If not, silently drop it and put it back on the
1128                 * receive ring.
1129                 */
1130
1131                if (likely (!(dsc->dscr_a & M_DMA_ETHRX_BAD))) {
1132
1133                        /*
1134                         * Add a new buffer to replace the old one.  If we fail
1135                         * to allocate a buffer, we're going to drop this
1136                         * packet and put it right back on the receive ring.
1137                         */
1138
1139                        if (unlikely(sbdma_add_rcvbuffer(sc, d, NULL) ==
1140                                     -ENOBUFS)) {
1141                                dev->stats.rx_dropped++;
1142                                /* Re-add old buffer */
1143                                sbdma_add_rcvbuffer(sc, d, sb);
1144                                /* No point in continuing at the moment */
1145                                printk(KERN_ERR "dropped packet (1)\n");
1146                                d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1147                                goto done;
1148                        } else {
1149                                /*
1150                                 * Set length into the packet
1151                                 */
1152                                skb_put(sb,len);
1153
1154                                /*
1155                                 * Buffer has been replaced on the
1156                                 * receive ring.  Pass the buffer to
1157                                 * the kernel
1158                                 */
1159                                sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev);
1160                                /* Check hw IPv4/TCP checksum if supported */
1161                                if (sc->rx_hw_checksum == ENABLE) {
1162                                        if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) &&
1163                                            !((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) {
1164                                                sb->ip_summed = CHECKSUM_UNNECESSARY;
1165                                                /* don't need to set sb->csum */
1166                                        } else {
1167                                                skb_checksum_none_assert(sb);
1168                                        }
1169                                }
1170                                prefetch(sb->data);
1171                                prefetch((const void *)(((char *)sb->data)+32));
1172                                if (poll)
1173                                        dropped = netif_receive_skb(sb);
1174                                else
1175                                        dropped = netif_rx(sb);
1176
1177                                if (dropped == NET_RX_DROP) {
1178                                        dev->stats.rx_dropped++;
1179                                        d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1180                                        goto done;
1181                                }
1182                                else {
1183                                        dev->stats.rx_bytes += len;
1184                                        dev->stats.rx_packets++;
1185                                }
1186                        }
1187                } else {
1188                        /*
1189                         * Packet was mangled somehow.  Just drop it and
1190                         * put it back on the receive ring.
1191                         */
1192                        dev->stats.rx_errors++;
1193                        sbdma_add_rcvbuffer(sc, d, sb);
1194                }
1195
1196
1197                /*
1198                 * .. and advance to the next buffer.
1199                 */
1200
1201                d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1202                work_done++;
1203        }
1204        if (!poll) {
1205                work_to_do = 32;
1206                goto again; /* collect fifo drop statistics again */
1207        }
1208done:
1209        return work_done;
1210}
1211
1212/**********************************************************************
1213 *  SBDMA_TX_PROCESS(sc,d)
1214 *
1215 *  Process "completed" transmit buffers on the specified DMA channel.
1216 *  This is normally called within the interrupt service routine.
1217 *  Note that this isn't really ideal for priority channels, since
1218 *  it processes all of the packets on a given channel before
1219 *  returning.
1220 *
1221 *  Input parameters:
1222 *      sc - softc structure
1223 *       d - DMA channel context
1224 *    poll - 1: using polling (for NAPI)
1225 *
1226 *  Return value:
1227 *         nothing
1228 ********************************************************************* */
1229
1230static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d,
1231                             int poll)
1232{
1233        struct net_device *dev = sc->sbm_dev;
1234        int curidx;
1235        int hwidx;
1236        struct sbdmadscr *dsc;
1237        struct sk_buff *sb;
1238        unsigned long flags;
1239        int packets_handled = 0;
1240
1241        spin_lock_irqsave(&(sc->sbm_lock), flags);
1242
1243        if (d->sbdma_remptr == d->sbdma_addptr)
1244          goto end_unlock;
1245
1246        hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1247                 d->sbdma_dscrtable_phys) / sizeof(*d->sbdma_dscrtable);
1248
1249        for (;;) {
1250                /*
1251                 * figure out where we are (as an index) and where
1252                 * the hardware is (also as an index)
1253                 *
1254                 * This could be done faster if (for example) the
1255                 * descriptor table was page-aligned and contiguous in
1256                 * both virtual and physical memory -- you could then
1257                 * just compare the low-order bits of the virtual address
1258                 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1259                 */
1260
1261                curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1262
1263                /*
1264                 * If they're the same, that means we've processed all
1265                 * of the descriptors up to (but not including) the one that
1266                 * the hardware is working on right now.
1267                 */
1268
1269                if (curidx == hwidx)
1270                        break;
1271
1272                /*
1273                 * Otherwise, get the packet's sk_buff ptr back
1274                 */
1275
1276                dsc = &(d->sbdma_dscrtable[curidx]);
1277                sb = d->sbdma_ctxtable[curidx];
1278                d->sbdma_ctxtable[curidx] = NULL;
1279
1280                /*
1281                 * Stats
1282                 */
1283
1284                dev->stats.tx_bytes += sb->len;
1285                dev->stats.tx_packets++;
1286
1287                /*
1288                 * for transmits, we just free buffers.
1289                 */
1290
1291                dev_kfree_skb_irq(sb);
1292
1293                /*
1294                 * .. and advance to the next buffer.
1295                 */
1296
1297                d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1298
1299                packets_handled++;
1300
1301        }
1302
1303        /*
1304         * Decide if we should wake up the protocol or not.
1305         * Other drivers seem to do this when we reach a low
1306         * watermark on the transmit queue.
1307         */
1308
1309        if (packets_handled)
1310                netif_wake_queue(d->sbdma_eth->sbm_dev);
1311
1312end_unlock:
1313        spin_unlock_irqrestore(&(sc->sbm_lock), flags);
1314
1315}
1316
1317
1318
1319/**********************************************************************
1320 *  SBMAC_INITCTX(s)
1321 *
1322 *  Initialize an Ethernet context structure - this is called
1323 *  once per MAC on the 1250.  Memory is allocated here, so don't
1324 *  call it again from inside the ioctl routines that bring the
1325 *  interface up/down
1326 *
1327 *  Input parameters:
1328 *         s - sbmac context structure
1329 *
1330 *  Return value:
1331 *         0
1332 ********************************************************************* */
1333
1334static int sbmac_initctx(struct sbmac_softc *s)
1335{
1336
1337        /*
1338         * figure out the addresses of some ports
1339         */
1340
1341        s->sbm_macenable = s->sbm_base + R_MAC_ENABLE;
1342        s->sbm_maccfg    = s->sbm_base + R_MAC_CFG;
1343        s->sbm_fifocfg   = s->sbm_base + R_MAC_THRSH_CFG;
1344        s->sbm_framecfg  = s->sbm_base + R_MAC_FRAMECFG;
1345        s->sbm_rxfilter  = s->sbm_base + R_MAC_ADFILTER_CFG;
1346        s->sbm_isr       = s->sbm_base + R_MAC_STATUS;
1347        s->sbm_imr       = s->sbm_base + R_MAC_INT_MASK;
1348        s->sbm_mdio      = s->sbm_base + R_MAC_MDIO;
1349
1350        /*
1351         * Initialize the DMA channels.  Right now, only one per MAC is used
1352         * Note: Only do this _once_, as it allocates memory from the kernel!
1353         */
1354
1355        sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR);
1356        sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR);
1357
1358        /*
1359         * initial state is OFF
1360         */
1361
1362        s->sbm_state = sbmac_state_off;
1363
1364        return 0;
1365}
1366
1367
1368static void sbdma_uninitctx(struct sbmacdma *d)
1369{
1370        kfree(d->sbdma_dscrtable_unaligned);
1371        d->sbdma_dscrtable_unaligned = d->sbdma_dscrtable = NULL;
1372
1373        kfree(d->sbdma_ctxtable);
1374        d->sbdma_ctxtable = NULL;
1375}
1376
1377
1378static void sbmac_uninitctx(struct sbmac_softc *sc)
1379{
1380        sbdma_uninitctx(&(sc->sbm_txdma));
1381        sbdma_uninitctx(&(sc->sbm_rxdma));
1382}
1383
1384
1385/**********************************************************************
1386 *  SBMAC_CHANNEL_START(s)
1387 *
1388 *  Start packet processing on this MAC.
1389 *
1390 *  Input parameters:
1391 *         s - sbmac structure
1392 *
1393 *  Return value:
1394 *         nothing
1395 ********************************************************************* */
1396
1397static void sbmac_channel_start(struct sbmac_softc *s)
1398{
1399        uint64_t reg;
1400        void __iomem *port;
1401        uint64_t cfg,fifo,framecfg;
1402        int idx, th_value;
1403
1404        /*
1405         * Don't do this if running
1406         */
1407
1408        if (s->sbm_state == sbmac_state_on)
1409                return;
1410
1411        /*
1412         * Bring the controller out of reset, but leave it off.
1413         */
1414
1415        __raw_writeq(0, s->sbm_macenable);
1416
1417        /*
1418         * Ignore all received packets
1419         */
1420
1421        __raw_writeq(0, s->sbm_rxfilter);
1422
1423        /*
1424         * Calculate values for various control registers.
1425         */
1426
1427        cfg = M_MAC_RETRY_EN |
1428                M_MAC_TX_HOLD_SOP_EN |
1429                V_MAC_TX_PAUSE_CNT_16K |
1430                M_MAC_AP_STAT_EN |
1431                M_MAC_FAST_SYNC |
1432                M_MAC_SS_EN |
1433                0;
1434
1435        /*
1436         * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars
1437         * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above
1438         * Use a larger RD_THRSH for gigabit
1439         */
1440        if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2)
1441                th_value = 28;
1442        else
1443                th_value = 64;
1444
1445        fifo = V_MAC_TX_WR_THRSH(4) |   /* Must be '4' or '8' */
1446                ((s->sbm_speed == sbmac_speed_1000)
1447                 ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) |
1448                V_MAC_TX_RL_THRSH(4) |
1449                V_MAC_RX_PL_THRSH(4) |
1450                V_MAC_RX_RD_THRSH(4) |  /* Must be '4' */
1451                V_MAC_RX_RL_THRSH(8) |
1452                0;
1453
1454        framecfg = V_MAC_MIN_FRAMESZ_DEFAULT |
1455                V_MAC_MAX_FRAMESZ_DEFAULT |
1456                V_MAC_BACKOFF_SEL(1);
1457
1458        /*
1459         * Clear out the hash address map
1460         */
1461
1462        port = s->sbm_base + R_MAC_HASH_BASE;
1463        for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
1464                __raw_writeq(0, port);
1465                port += sizeof(uint64_t);
1466        }
1467
1468        /*
1469         * Clear out the exact-match table
1470         */
1471
1472        port = s->sbm_base + R_MAC_ADDR_BASE;
1473        for (idx = 0; idx < MAC_ADDR_COUNT; idx++) {
1474                __raw_writeq(0, port);
1475                port += sizeof(uint64_t);
1476        }
1477
1478        /*
1479         * Clear out the DMA Channel mapping table registers
1480         */
1481
1482        port = s->sbm_base + R_MAC_CHUP0_BASE;
1483        for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1484                __raw_writeq(0, port);
1485                port += sizeof(uint64_t);
1486        }
1487
1488
1489        port = s->sbm_base + R_MAC_CHLO0_BASE;
1490        for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1491                __raw_writeq(0, port);
1492                port += sizeof(uint64_t);
1493        }
1494
1495        /*
1496         * Program the hardware address.  It goes into the hardware-address
1497         * register as well as the first filter register.
1498         */
1499
1500        reg = sbmac_addr2reg(s->sbm_hwaddr);
1501
1502        port = s->sbm_base + R_MAC_ADDR_BASE;
1503        __raw_writeq(reg, port);
1504        port = s->sbm_base + R_MAC_ETHERNET_ADDR;
1505
1506        __raw_writeq(reg, port);
1507
1508        /*
1509         * Set the receive filter for no packets, and write values
1510         * to the various config registers
1511         */
1512
1513        __raw_writeq(0, s->sbm_rxfilter);
1514        __raw_writeq(0, s->sbm_imr);
1515        __raw_writeq(framecfg, s->sbm_framecfg);
1516        __raw_writeq(fifo, s->sbm_fifocfg);
1517        __raw_writeq(cfg, s->sbm_maccfg);
1518
1519        /*
1520         * Initialize DMA channels (rings should be ok now)
1521         */
1522
1523        sbdma_channel_start(&(s->sbm_rxdma), DMA_RX);
1524        sbdma_channel_start(&(s->sbm_txdma), DMA_TX);
1525
1526        /*
1527         * Configure the speed, duplex, and flow control
1528         */
1529
1530        sbmac_set_speed(s,s->sbm_speed);
1531        sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc);
1532
1533        /*
1534         * Fill the receive ring
1535         */
1536
1537        sbdma_fillring(s, &(s->sbm_rxdma));
1538
1539        /*
1540         * Turn on the rest of the bits in the enable register
1541         */
1542
1543#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
1544        __raw_writeq(M_MAC_RXDMA_EN0 |
1545                       M_MAC_TXDMA_EN0, s->sbm_macenable);
1546#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
1547        __raw_writeq(M_MAC_RXDMA_EN0 |
1548                       M_MAC_TXDMA_EN0 |
1549                       M_MAC_RX_ENABLE |
1550                       M_MAC_TX_ENABLE, s->sbm_macenable);
1551#else
1552#error invalid SiByte MAC configuration
1553#endif
1554
1555#ifdef CONFIG_SBMAC_COALESCE
1556        __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1557                       ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), s->sbm_imr);
1558#else
1559        __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1560                       (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), s->sbm_imr);
1561#endif
1562
1563        /*
1564         * Enable receiving unicasts and broadcasts
1565         */
1566
1567        __raw_writeq(M_MAC_UCAST_EN | M_MAC_BCAST_EN, s->sbm_rxfilter);
1568
1569        /*
1570         * we're running now.
1571         */
1572
1573        s->sbm_state = sbmac_state_on;
1574
1575        /*
1576         * Program multicast addresses
1577         */
1578
1579        sbmac_setmulti(s);
1580
1581        /*
1582         * If channel was in promiscuous mode before, turn that on
1583         */
1584
1585        if (s->sbm_devflags & IFF_PROMISC) {
1586                sbmac_promiscuous_mode(s,1);
1587        }
1588
1589}
1590
1591
1592/**********************************************************************
1593 *  SBMAC_CHANNEL_STOP(s)
1594 *
1595 *  Stop packet processing on this MAC.
1596 *
1597 *  Input parameters:
1598 *         s - sbmac structure
1599 *
1600 *  Return value:
1601 *         nothing
1602 ********************************************************************* */
1603
1604static void sbmac_channel_stop(struct sbmac_softc *s)
1605{
1606        /* don't do this if already stopped */
1607
1608        if (s->sbm_state == sbmac_state_off)
1609                return;
1610
1611        /* don't accept any packets, disable all interrupts */
1612
1613        __raw_writeq(0, s->sbm_rxfilter);
1614        __raw_writeq(0, s->sbm_imr);
1615
1616        /* Turn off ticker */
1617
1618        /* XXX */
1619
1620        /* turn off receiver and transmitter */
1621
1622        __raw_writeq(0, s->sbm_macenable);
1623
1624        /* We're stopped now. */
1625
1626        s->sbm_state = sbmac_state_off;
1627
1628        /*
1629         * Stop DMA channels (rings should be ok now)
1630         */
1631
1632        sbdma_channel_stop(&(s->sbm_rxdma));
1633        sbdma_channel_stop(&(s->sbm_txdma));
1634
1635        /* Empty the receive and transmit rings */
1636
1637        sbdma_emptyring(&(s->sbm_rxdma));
1638        sbdma_emptyring(&(s->sbm_txdma));
1639
1640}
1641
1642/**********************************************************************
1643 *  SBMAC_SET_CHANNEL_STATE(state)
1644 *
1645 *  Set the channel's state ON or OFF
1646 *
1647 *  Input parameters:
1648 *         state - new state
1649 *
1650 *  Return value:
1651 *         old state
1652 ********************************************************************* */
1653static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *sc,
1654                                                enum sbmac_state state)
1655{
1656        enum sbmac_state oldstate = sc->sbm_state;
1657
1658        /*
1659         * If same as previous state, return
1660         */
1661
1662        if (state == oldstate) {
1663                return oldstate;
1664        }
1665
1666        /*
1667         * If new state is ON, turn channel on
1668         */
1669
1670        if (state == sbmac_state_on) {
1671                sbmac_channel_start(sc);
1672        }
1673        else {
1674                sbmac_channel_stop(sc);
1675        }
1676
1677        /*
1678         * Return previous state
1679         */
1680
1681        return oldstate;
1682}
1683
1684
1685/**********************************************************************
1686 *  SBMAC_PROMISCUOUS_MODE(sc,onoff)
1687 *
1688 *  Turn on or off promiscuous mode
1689 *
1690 *  Input parameters:
1691 *         sc - softc
1692 *      onoff - 1 to turn on, 0 to turn off
1693 *
1694 *  Return value:
1695 *         nothing
1696 ********************************************************************* */
1697
1698static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff)
1699{
1700        uint64_t reg;
1701
1702        if (sc->sbm_state != sbmac_state_on)
1703                return;
1704
1705        if (onoff) {
1706                reg = __raw_readq(sc->sbm_rxfilter);
1707                reg |= M_MAC_ALLPKT_EN;
1708                __raw_writeq(reg, sc->sbm_rxfilter);
1709        }
1710        else {
1711                reg = __raw_readq(sc->sbm_rxfilter);
1712                reg &= ~M_MAC_ALLPKT_EN;
1713                __raw_writeq(reg, sc->sbm_rxfilter);
1714        }
1715}
1716
1717/**********************************************************************
1718 *  SBMAC_SETIPHDR_OFFSET(sc,onoff)
1719 *
1720 *  Set the iphdr offset as 15 assuming ethernet encapsulation
1721 *
1722 *  Input parameters:
1723 *         sc - softc
1724 *
1725 *  Return value:
1726 *         nothing
1727 ********************************************************************* */
1728
1729static void sbmac_set_iphdr_offset(struct sbmac_softc *sc)
1730{
1731        uint64_t reg;
1732
1733        /* Hard code the off set to 15 for now */
1734        reg = __raw_readq(sc->sbm_rxfilter);
1735        reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15);
1736        __raw_writeq(reg, sc->sbm_rxfilter);
1737
1738        /* BCM1250 pass1 didn't have hardware checksum.  Everything
1739           later does.  */
1740        if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) {
1741                sc->rx_hw_checksum = DISABLE;
1742        } else {
1743                sc->rx_hw_checksum = ENABLE;
1744        }
1745}
1746
1747
1748/**********************************************************************
1749 *  SBMAC_ADDR2REG(ptr)
1750 *
1751 *  Convert six bytes into the 64-bit register value that
1752 *  we typically write into the SBMAC's address/mcast registers
1753 *
1754 *  Input parameters:
1755 *         ptr - pointer to 6 bytes
1756 *
1757 *  Return value:
1758 *         register value
1759 ********************************************************************* */
1760
1761static uint64_t sbmac_addr2reg(unsigned char *ptr)
1762{
1763        uint64_t reg = 0;
1764
1765        ptr += 6;
1766
1767        reg |= (uint64_t) *(--ptr);
1768        reg <<= 8;
1769        reg |= (uint64_t) *(--ptr);
1770        reg <<= 8;
1771        reg |= (uint64_t) *(--ptr);
1772        reg <<= 8;
1773        reg |= (uint64_t) *(--ptr);
1774        reg <<= 8;
1775        reg |= (uint64_t) *(--ptr);
1776        reg <<= 8;
1777        reg |= (uint64_t) *(--ptr);
1778
1779        return reg;
1780}
1781
1782
1783/**********************************************************************
1784 *  SBMAC_SET_SPEED(s,speed)
1785 *
1786 *  Configure LAN speed for the specified MAC.
1787 *  Warning: must be called when MAC is off!
1788 *
1789 *  Input parameters:
1790 *         s - sbmac structure
1791 *         speed - speed to set MAC to (see enum sbmac_speed)
1792 *
1793 *  Return value:
1794 *         1 if successful
1795 *      0 indicates invalid parameters
1796 ********************************************************************* */
1797
1798static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed)
1799{
1800        uint64_t cfg;
1801        uint64_t framecfg;
1802
1803        /*
1804         * Save new current values
1805         */
1806
1807        s->sbm_speed = speed;
1808
1809        if (s->sbm_state == sbmac_state_on)
1810                return 0;       /* save for next restart */
1811
1812        /*
1813         * Read current register values
1814         */
1815
1816        cfg = __raw_readq(s->sbm_maccfg);
1817        framecfg = __raw_readq(s->sbm_framecfg);
1818
1819        /*
1820         * Mask out the stuff we want to change
1821         */
1822
1823        cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL);
1824        framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH |
1825                      M_MAC_SLOT_SIZE);
1826
1827        /*
1828         * Now add in the new bits
1829         */
1830
1831        switch (speed) {
1832        case sbmac_speed_10:
1833                framecfg |= V_MAC_IFG_RX_10 |
1834                        V_MAC_IFG_TX_10 |
1835                        K_MAC_IFG_THRSH_10 |
1836                        V_MAC_SLOT_SIZE_10;
1837                cfg |= V_MAC_SPEED_SEL_10MBPS;
1838                break;
1839
1840        case sbmac_speed_100:
1841                framecfg |= V_MAC_IFG_RX_100 |
1842                        V_MAC_IFG_TX_100 |
1843                        V_MAC_IFG_THRSH_100 |
1844                        V_MAC_SLOT_SIZE_100;
1845                cfg |= V_MAC_SPEED_SEL_100MBPS ;
1846                break;
1847
1848        case sbmac_speed_1000:
1849                framecfg |= V_MAC_IFG_RX_1000 |
1850                        V_MAC_IFG_TX_1000 |
1851                        V_MAC_IFG_THRSH_1000 |
1852                        V_MAC_SLOT_SIZE_1000;
1853                cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN;
1854                break;
1855
1856        default:
1857                return 0;
1858        }
1859
1860        /*
1861         * Send the bits back to the hardware
1862         */
1863
1864        __raw_writeq(framecfg, s->sbm_framecfg);
1865        __raw_writeq(cfg, s->sbm_maccfg);
1866
1867        return 1;
1868}
1869
1870/**********************************************************************
1871 *  SBMAC_SET_DUPLEX(s,duplex,fc)
1872 *
1873 *  Set Ethernet duplex and flow control options for this MAC
1874 *  Warning: must be called when MAC is off!
1875 *
1876 *  Input parameters:
1877 *         s - sbmac structure
1878 *         duplex - duplex setting (see enum sbmac_duplex)
1879 *         fc - flow control setting (see enum sbmac_fc)
1880 *
1881 *  Return value:
1882 *         1 if ok
1883 *         0 if an invalid parameter combination was specified
1884 ********************************************************************* */
1885
1886static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex,
1887                            enum sbmac_fc fc)
1888{
1889        uint64_t cfg;
1890
1891        /*
1892         * Save new current values
1893         */
1894
1895        s->sbm_duplex = duplex;
1896        s->sbm_fc = fc;
1897
1898        if (s->sbm_state == sbmac_state_on)
1899                return 0;       /* save for next restart */
1900
1901        /*
1902         * Read current register values
1903         */
1904
1905        cfg = __raw_readq(s->sbm_maccfg);
1906
1907        /*
1908         * Mask off the stuff we're about to change
1909         */
1910
1911        cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN);
1912
1913
1914        switch (duplex) {
1915        case sbmac_duplex_half:
1916                switch (fc) {
1917                case sbmac_fc_disabled:
1918                        cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED;
1919                        break;
1920
1921                case sbmac_fc_collision:
1922                        cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED;
1923                        break;
1924
1925                case sbmac_fc_carrier:
1926                        cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR;
1927                        break;
1928
1929                case sbmac_fc_frame:            /* not valid in half duplex */
1930                default:                        /* invalid selection */
1931                        return 0;
1932                }
1933                break;
1934
1935        case sbmac_duplex_full:
1936                switch (fc) {
1937                case sbmac_fc_disabled:
1938                        cfg |= V_MAC_FC_CMD_DISABLED;
1939                        break;
1940
1941                case sbmac_fc_frame:
1942                        cfg |= V_MAC_FC_CMD_ENABLED;
1943                        break;
1944
1945                case sbmac_fc_collision:        /* not valid in full duplex */
1946                case sbmac_fc_carrier:          /* not valid in full duplex */
1947                default:
1948                        return 0;
1949                }
1950                break;
1951        default:
1952                return 0;
1953        }
1954
1955        /*
1956         * Send the bits back to the hardware
1957         */
1958
1959        __raw_writeq(cfg, s->sbm_maccfg);
1960
1961        return 1;
1962}
1963
1964
1965
1966
1967/**********************************************************************
1968 *  SBMAC_INTR()
1969 *
1970 *  Interrupt handler for MAC interrupts
1971 *
1972 *  Input parameters:
1973 *         MAC structure
1974 *
1975 *  Return value:
1976 *         nothing
1977 ********************************************************************* */
1978static irqreturn_t sbmac_intr(int irq,void *dev_instance)
1979{
1980        struct net_device *dev = (struct net_device *) dev_instance;
1981        struct sbmac_softc *sc = netdev_priv(dev);
1982        uint64_t isr;
1983        int handled = 0;
1984
1985        /*
1986         * Read the ISR (this clears the bits in the real
1987         * register, except for counter addr)
1988         */
1989
1990        isr = __raw_readq(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR;
1991
1992        if (isr == 0)
1993                return IRQ_RETVAL(0);
1994        handled = 1;
1995
1996        /*
1997         * Transmits on channel 0
1998         */
1999
2000        if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0))
2001                sbdma_tx_process(sc,&(sc->sbm_txdma), 0);
2002
2003        if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) {
2004                if (napi_schedule_prep(&sc->napi)) {
2005                        __raw_writeq(0, sc->sbm_imr);
2006                        __napi_schedule(&sc->napi);
2007                        /* Depend on the exit from poll to reenable intr */
2008                }
2009                else {
2010                        /* may leave some packets behind */
2011                        sbdma_rx_process(sc,&(sc->sbm_rxdma),
2012                                         SBMAC_MAX_RXDESCR * 2, 0);
2013                }
2014        }
2015        return IRQ_RETVAL(handled);
2016}
2017
2018/**********************************************************************
2019 *  SBMAC_START_TX(skb,dev)
2020 *
2021 *  Start output on the specified interface.  Basically, we
2022 *  queue as many buffers as we can until the ring fills up, or
2023 *  we run off the end of the queue, whichever comes first.
2024 *
2025 *  Input parameters:
2026 *
2027 *
2028 *  Return value:
2029 *         nothing
2030 ********************************************************************* */
2031static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev)
2032{
2033        struct sbmac_softc *sc = netdev_priv(dev);
2034        unsigned long flags;
2035
2036        /* lock eth irq */
2037        spin_lock_irqsave(&sc->sbm_lock, flags);
2038
2039        /*
2040         * Put the buffer on the transmit ring.  If we
2041         * don't have room, stop the queue.
2042         */
2043
2044        if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) {
2045                /* XXX save skb that we could not send */
2046                netif_stop_queue(dev);
2047                spin_unlock_irqrestore(&sc->sbm_lock, flags);
2048
2049                return NETDEV_TX_BUSY;
2050        }
2051
2052        spin_unlock_irqrestore(&sc->sbm_lock, flags);
2053
2054        return NETDEV_TX_OK;
2055}
2056
2057/**********************************************************************
2058 *  SBMAC_SETMULTI(sc)
2059 *
2060 *  Reprogram the multicast table into the hardware, given
2061 *  the list of multicasts associated with the interface
2062 *  structure.
2063 *
2064 *  Input parameters:
2065 *         sc - softc
2066 *
2067 *  Return value:
2068 *         nothing
2069 ********************************************************************* */
2070
2071static void sbmac_setmulti(struct sbmac_softc *sc)
2072{
2073        uint64_t reg;
2074        void __iomem *port;
2075        int idx;
2076        struct netdev_hw_addr *ha;
2077        struct net_device *dev = sc->sbm_dev;
2078
2079        /*
2080         * Clear out entire multicast table.  We do this by nuking
2081         * the entire hash table and all the direct matches except
2082         * the first one, which is used for our station address
2083         */
2084
2085        for (idx = 1; idx < MAC_ADDR_COUNT; idx++) {
2086                port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t));
2087                __raw_writeq(0, port);
2088        }
2089
2090        for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
2091                port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t));
2092                __raw_writeq(0, port);
2093        }
2094
2095        /*
2096         * Clear the filter to say we don't want any multicasts.
2097         */
2098
2099        reg = __raw_readq(sc->sbm_rxfilter);
2100        reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2101        __raw_writeq(reg, sc->sbm_rxfilter);
2102
2103        if (dev->flags & IFF_ALLMULTI) {
2104                /*
2105                 * Enable ALL multicasts.  Do this by inverting the
2106                 * multicast enable bit.
2107                 */
2108                reg = __raw_readq(sc->sbm_rxfilter);
2109                reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2110                __raw_writeq(reg, sc->sbm_rxfilter);
2111                return;
2112        }
2113
2114
2115        /*
2116         * Progam new multicast entries.  For now, only use the
2117         * perfect filter.  In the future we'll need to use the
2118         * hash filter if the perfect filter overflows
2119         */
2120
2121        /* XXX only using perfect filter for now, need to use hash
2122         * XXX if the table overflows */
2123
2124        idx = 1;                /* skip station address */
2125        netdev_for_each_mc_addr(ha, dev) {
2126                if (idx == MAC_ADDR_COUNT)
2127                        break;
2128                reg = sbmac_addr2reg(ha->addr);
2129                port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t));
2130                __raw_writeq(reg, port);
2131                idx++;
2132        }
2133
2134        /*
2135         * Enable the "accept multicast bits" if we programmed at least one
2136         * multicast.
2137         */
2138
2139        if (idx > 1) {
2140                reg = __raw_readq(sc->sbm_rxfilter);
2141                reg |= M_MAC_MCAST_EN;
2142                __raw_writeq(reg, sc->sbm_rxfilter);
2143        }
2144}
2145
2146static const struct net_device_ops sbmac_netdev_ops = {
2147        .ndo_open               = sbmac_open,
2148        .ndo_stop               = sbmac_close,
2149        .ndo_start_xmit         = sbmac_start_tx,
2150        .ndo_set_rx_mode        = sbmac_set_rx_mode,
2151        .ndo_tx_timeout         = sbmac_tx_timeout,
2152        .ndo_do_ioctl           = sbmac_mii_ioctl,
2153        .ndo_validate_addr      = eth_validate_addr,
2154        .ndo_set_mac_address    = eth_mac_addr,
2155#ifdef CONFIG_NET_POLL_CONTROLLER
2156        .ndo_poll_controller    = sbmac_netpoll,
2157#endif
2158};
2159
2160/**********************************************************************
2161 *  SBMAC_INIT(dev)
2162 *
2163 *  Attach routine - init hardware and hook ourselves into linux
2164 *
2165 *  Input parameters:
2166 *         dev - net_device structure
2167 *
2168 *  Return value:
2169 *         status
2170 ********************************************************************* */
2171
2172static int sbmac_init(struct platform_device *pldev, long long base)
2173{
2174        struct net_device *dev = platform_get_drvdata(pldev);
2175        int idx = pldev->id;
2176        struct sbmac_softc *sc = netdev_priv(dev);
2177        unsigned char *eaddr;
2178        uint64_t ea_reg;
2179        int i;
2180        int err;
2181
2182        sc->sbm_dev = dev;
2183        sc->sbe_idx = idx;
2184
2185        eaddr = sc->sbm_hwaddr;
2186
2187        /*
2188         * Read the ethernet address.  The firmware left this programmed
2189         * for us in the ethernet address register for each mac.
2190         */
2191
2192        ea_reg = __raw_readq(sc->sbm_base + R_MAC_ETHERNET_ADDR);
2193        __raw_writeq(0, sc->sbm_base + R_MAC_ETHERNET_ADDR);
2194        for (i = 0; i < 6; i++) {
2195                eaddr[i] = (uint8_t) (ea_reg & 0xFF);
2196                ea_reg >>= 8;
2197        }
2198
2199        for (i = 0; i < 6; i++) {
2200                dev->dev_addr[i] = eaddr[i];
2201        }
2202
2203        /*
2204         * Initialize context (get pointers to registers and stuff), then
2205         * allocate the memory for the descriptor tables.
2206         */
2207
2208        sbmac_initctx(sc);
2209
2210        /*
2211         * Set up Linux device callins
2212         */
2213
2214        spin_lock_init(&(sc->sbm_lock));
2215
2216        dev->netdev_ops = &sbmac_netdev_ops;
2217        dev->watchdog_timeo = TX_TIMEOUT;
2218        dev->min_mtu = 0;
2219        dev->max_mtu = ENET_PACKET_SIZE;
2220
2221        netif_napi_add(dev, &sc->napi, sbmac_poll, 16);
2222
2223        dev->irq                = UNIT_INT(idx);
2224
2225        /* This is needed for PASS2 for Rx H/W checksum feature */
2226        sbmac_set_iphdr_offset(sc);
2227
2228        sc->mii_bus = mdiobus_alloc();
2229        if (sc->mii_bus == NULL) {
2230                err = -ENOMEM;
2231                goto uninit_ctx;
2232        }
2233
2234        sc->mii_bus->name = sbmac_mdio_string;
2235        snprintf(sc->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2236                pldev->name, idx);
2237        sc->mii_bus->priv = sc;
2238        sc->mii_bus->read = sbmac_mii_read;
2239        sc->mii_bus->write = sbmac_mii_write;
2240
2241        sc->mii_bus->parent = &pldev->dev;
2242        /*
2243         * Probe PHY address
2244         */
2245        err = mdiobus_register(sc->mii_bus);
2246        if (err) {
2247                printk(KERN_ERR "%s: unable to register MDIO bus\n",
2248                       dev->name);
2249                goto free_mdio;
2250        }
2251        platform_set_drvdata(pldev, sc->mii_bus);
2252
2253        err = register_netdev(dev);
2254        if (err) {
2255                printk(KERN_ERR "%s.%d: unable to register netdev\n",
2256                       sbmac_string, idx);
2257                goto unreg_mdio;
2258        }
2259
2260        pr_info("%s.%d: registered as %s\n", sbmac_string, idx, dev->name);
2261
2262        if (sc->rx_hw_checksum == ENABLE)
2263                pr_info("%s: enabling TCP rcv checksum\n", dev->name);
2264
2265        /*
2266         * Display Ethernet address (this is called during the config
2267         * process so we need to finish off the config message that
2268         * was being displayed)
2269         */
2270        pr_info("%s: SiByte Ethernet at 0x%08Lx, address: %pM\n",
2271               dev->name, base, eaddr);
2272
2273        return 0;
2274unreg_mdio:
2275        mdiobus_unregister(sc->mii_bus);
2276free_mdio:
2277        mdiobus_free(sc->mii_bus);
2278uninit_ctx:
2279        sbmac_uninitctx(sc);
2280        return err;
2281}
2282
2283
2284static int sbmac_open(struct net_device *dev)
2285{
2286        struct sbmac_softc *sc = netdev_priv(dev);
2287        int err;
2288
2289        if (debug > 1)
2290                pr_debug("%s: sbmac_open() irq %d.\n", dev->name, dev->irq);
2291
2292        /*
2293         * map/route interrupt (clear status first, in case something
2294         * weird is pending; we haven't initialized the mac registers
2295         * yet)
2296         */
2297
2298        __raw_readq(sc->sbm_isr);
2299        err = request_irq(dev->irq, sbmac_intr, IRQF_SHARED, dev->name, dev);
2300        if (err) {
2301                printk(KERN_ERR "%s: unable to get IRQ %d\n", dev->name,
2302                       dev->irq);
2303                goto out_err;
2304        }
2305
2306        sc->sbm_speed = sbmac_speed_none;
2307        sc->sbm_duplex = sbmac_duplex_none;
2308        sc->sbm_fc = sbmac_fc_none;
2309        sc->sbm_pause = -1;
2310        sc->sbm_link = 0;
2311
2312        /*
2313         * Attach to the PHY
2314         */
2315        err = sbmac_mii_probe(dev);
2316        if (err)
2317                goto out_unregister;
2318
2319        /*
2320         * Turn on the channel
2321         */
2322
2323        sbmac_set_channel_state(sc,sbmac_state_on);
2324
2325        netif_start_queue(dev);
2326
2327        sbmac_set_rx_mode(dev);
2328
2329        phy_start(sc->phy_dev);
2330
2331        napi_enable(&sc->napi);
2332
2333        return 0;
2334
2335out_unregister:
2336        free_irq(dev->irq, dev);
2337out_err:
2338        return err;
2339}
2340
2341static int sbmac_mii_probe(struct net_device *dev)
2342{
2343        struct sbmac_softc *sc = netdev_priv(dev);
2344        struct phy_device *phy_dev;
2345
2346        phy_dev = phy_find_first(sc->mii_bus);
2347        if (!phy_dev) {
2348                printk(KERN_ERR "%s: no PHY found\n", dev->name);
2349                return -ENXIO;
2350        }
2351
2352        phy_dev = phy_connect(dev, dev_name(&phy_dev->mdio.dev),
2353                              &sbmac_mii_poll, PHY_INTERFACE_MODE_GMII);
2354        if (IS_ERR(phy_dev)) {
2355                printk(KERN_ERR "%s: could not attach to PHY\n", dev->name);
2356                return PTR_ERR(phy_dev);
2357        }
2358
2359        /* Remove any features not supported by the controller */
2360        phy_set_max_speed(phy_dev, SPEED_1000);
2361        phy_support_asym_pause(phy_dev);
2362
2363        phy_attached_info(phy_dev);
2364
2365        sc->phy_dev = phy_dev;
2366
2367        return 0;
2368}
2369
2370
2371static void sbmac_mii_poll(struct net_device *dev)
2372{
2373        struct sbmac_softc *sc = netdev_priv(dev);
2374        struct phy_device *phy_dev = sc->phy_dev;
2375        unsigned long flags;
2376        enum sbmac_fc fc;
2377        int link_chg, speed_chg, duplex_chg, pause_chg, fc_chg;
2378
2379        link_chg = (sc->sbm_link != phy_dev->link);
2380        speed_chg = (sc->sbm_speed != phy_dev->speed);
2381        duplex_chg = (sc->sbm_duplex != phy_dev->duplex);
2382        pause_chg = (sc->sbm_pause != phy_dev->pause);
2383
2384        if (!link_chg && !speed_chg && !duplex_chg && !pause_chg)
2385                return;                                 /* Hmmm... */
2386
2387        if (!phy_dev->link) {
2388                if (link_chg) {
2389                        sc->sbm_link = phy_dev->link;
2390                        sc->sbm_speed = sbmac_speed_none;
2391                        sc->sbm_duplex = sbmac_duplex_none;
2392                        sc->sbm_fc = sbmac_fc_disabled;
2393                        sc->sbm_pause = -1;
2394                        pr_info("%s: link unavailable\n", dev->name);
2395                }
2396                return;
2397        }
2398
2399        if (phy_dev->duplex == DUPLEX_FULL) {
2400                if (phy_dev->pause)
2401                        fc = sbmac_fc_frame;
2402                else
2403                        fc = sbmac_fc_disabled;
2404        } else
2405                fc = sbmac_fc_collision;
2406        fc_chg = (sc->sbm_fc != fc);
2407
2408        pr_info("%s: link available: %dbase-%cD\n", dev->name, phy_dev->speed,
2409                phy_dev->duplex == DUPLEX_FULL ? 'F' : 'H');
2410
2411        spin_lock_irqsave(&sc->sbm_lock, flags);
2412
2413        sc->sbm_speed = phy_dev->speed;
2414        sc->sbm_duplex = phy_dev->duplex;
2415        sc->sbm_fc = fc;
2416        sc->sbm_pause = phy_dev->pause;
2417        sc->sbm_link = phy_dev->link;
2418
2419        if ((speed_chg || duplex_chg || fc_chg) &&
2420            sc->sbm_state != sbmac_state_off) {
2421                /*
2422                 * something changed, restart the channel
2423                 */
2424                if (debug > 1)
2425                        pr_debug("%s: restarting channel "
2426                                 "because PHY state changed\n", dev->name);
2427                sbmac_channel_stop(sc);
2428                sbmac_channel_start(sc);
2429        }
2430
2431        spin_unlock_irqrestore(&sc->sbm_lock, flags);
2432}
2433
2434
2435static void sbmac_tx_timeout (struct net_device *dev, unsigned int txqueue)
2436{
2437        struct sbmac_softc *sc = netdev_priv(dev);
2438        unsigned long flags;
2439
2440        spin_lock_irqsave(&sc->sbm_lock, flags);
2441
2442
2443        netif_trans_update(dev); /* prevent tx timeout */
2444        dev->stats.tx_errors++;
2445
2446        spin_unlock_irqrestore(&sc->sbm_lock, flags);
2447
2448        printk (KERN_WARNING "%s: Transmit timed out\n",dev->name);
2449}
2450
2451
2452
2453
2454static void sbmac_set_rx_mode(struct net_device *dev)
2455{
2456        unsigned long flags;
2457        struct sbmac_softc *sc = netdev_priv(dev);
2458
2459        spin_lock_irqsave(&sc->sbm_lock, flags);
2460        if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) {
2461                /*
2462                 * Promiscuous changed.
2463                 */
2464
2465                if (dev->flags & IFF_PROMISC) {
2466                        sbmac_promiscuous_mode(sc,1);
2467                }
2468                else {
2469                        sbmac_promiscuous_mode(sc,0);
2470                }
2471        }
2472        spin_unlock_irqrestore(&sc->sbm_lock, flags);
2473
2474        /*
2475         * Program the multicasts.  Do this every time.
2476         */
2477
2478        sbmac_setmulti(sc);
2479
2480}
2481
2482static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2483{
2484        struct sbmac_softc *sc = netdev_priv(dev);
2485
2486        if (!netif_running(dev) || !sc->phy_dev)
2487                return -EINVAL;
2488
2489        return phy_mii_ioctl(sc->phy_dev, rq, cmd);
2490}
2491
2492static int sbmac_close(struct net_device *dev)
2493{
2494        struct sbmac_softc *sc = netdev_priv(dev);
2495
2496        napi_disable(&sc->napi);
2497
2498        phy_stop(sc->phy_dev);
2499
2500        sbmac_set_channel_state(sc, sbmac_state_off);
2501
2502        netif_stop_queue(dev);
2503
2504        if (debug > 1)
2505                pr_debug("%s: Shutting down ethercard\n", dev->name);
2506
2507        phy_disconnect(sc->phy_dev);
2508        sc->phy_dev = NULL;
2509        free_irq(dev->irq, dev);
2510
2511        sbdma_emptyring(&(sc->sbm_txdma));
2512        sbdma_emptyring(&(sc->sbm_rxdma));
2513
2514        return 0;
2515}
2516
2517static int sbmac_poll(struct napi_struct *napi, int budget)
2518{
2519        struct sbmac_softc *sc = container_of(napi, struct sbmac_softc, napi);
2520        int work_done;
2521
2522        work_done = sbdma_rx_process(sc, &(sc->sbm_rxdma), budget, 1);
2523        sbdma_tx_process(sc, &(sc->sbm_txdma), 1);
2524
2525        if (work_done < budget) {
2526                napi_complete_done(napi, work_done);
2527
2528#ifdef CONFIG_SBMAC_COALESCE
2529                __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
2530                             ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0),
2531                             sc->sbm_imr);
2532#else
2533                __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
2534                             (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr);
2535#endif
2536        }
2537
2538        return work_done;
2539}
2540
2541
2542static int sbmac_probe(struct platform_device *pldev)
2543{
2544        struct net_device *dev;
2545        struct sbmac_softc *sc;
2546        void __iomem *sbm_base;
2547        struct resource *res;
2548        u64 sbmac_orig_hwaddr;
2549        int err;
2550
2551        res = platform_get_resource(pldev, IORESOURCE_MEM, 0);
2552        BUG_ON(!res);
2553        sbm_base = ioremap_nocache(res->start, resource_size(res));
2554        if (!sbm_base) {
2555                printk(KERN_ERR "%s: unable to map device registers\n",
2556                       dev_name(&pldev->dev));
2557                err = -ENOMEM;
2558                goto out_out;
2559        }
2560
2561        /*
2562         * The R_MAC_ETHERNET_ADDR register will be set to some nonzero
2563         * value for us by the firmware if we're going to use this MAC.
2564         * If we find a zero, skip this MAC.
2565         */
2566        sbmac_orig_hwaddr = __raw_readq(sbm_base + R_MAC_ETHERNET_ADDR);
2567        pr_debug("%s: %sconfiguring MAC at 0x%08Lx\n", dev_name(&pldev->dev),
2568                 sbmac_orig_hwaddr ? "" : "not ", (long long)res->start);
2569        if (sbmac_orig_hwaddr == 0) {
2570                err = 0;
2571                goto out_unmap;
2572        }
2573
2574        /*
2575         * Okay, cool.  Initialize this MAC.
2576         */
2577        dev = alloc_etherdev(sizeof(struct sbmac_softc));
2578        if (!dev) {
2579                err = -ENOMEM;
2580                goto out_unmap;
2581        }
2582
2583        platform_set_drvdata(pldev, dev);
2584        SET_NETDEV_DEV(dev, &pldev->dev);
2585
2586        sc = netdev_priv(dev);
2587        sc->sbm_base = sbm_base;
2588
2589        err = sbmac_init(pldev, res->start);
2590        if (err)
2591                goto out_kfree;
2592
2593        return 0;
2594
2595out_kfree:
2596        free_netdev(dev);
2597        __raw_writeq(sbmac_orig_hwaddr, sbm_base + R_MAC_ETHERNET_ADDR);
2598
2599out_unmap:
2600        iounmap(sbm_base);
2601
2602out_out:
2603        return err;
2604}
2605
2606static int sbmac_remove(struct platform_device *pldev)
2607{
2608        struct net_device *dev = platform_get_drvdata(pldev);
2609        struct sbmac_softc *sc = netdev_priv(dev);
2610
2611        unregister_netdev(dev);
2612        sbmac_uninitctx(sc);
2613        mdiobus_unregister(sc->mii_bus);
2614        mdiobus_free(sc->mii_bus);
2615        iounmap(sc->sbm_base);
2616        free_netdev(dev);
2617
2618        return 0;
2619}
2620
2621static struct platform_driver sbmac_driver = {
2622        .probe = sbmac_probe,
2623        .remove = sbmac_remove,
2624        .driver = {
2625                .name = sbmac_string,
2626        },
2627};
2628
2629module_platform_driver(sbmac_driver);
2630MODULE_LICENSE("GPL");
2631