1
2
3
4
5
6#include <linux/interrupt.h>
7#include <linux/types.h>
8#include <linux/module.h>
9#include <linux/slab.h>
10#include <linux/pci.h>
11#include <linux/netdevice.h>
12#include <linux/ethtool.h>
13#include <linux/vmalloc.h>
14#include <linux/highmem.h>
15#include <linux/uaccess.h>
16
17#include "ixgbe.h"
18#include "ixgbe_phy.h"
19
20
21#define IXGBE_ALL_RAR_ENTRIES 16
22
23enum {NETDEV_STATS, IXGBE_STATS};
24
25struct ixgbe_stats {
26 char stat_string[ETH_GSTRING_LEN];
27 int type;
28 int sizeof_stat;
29 int stat_offset;
30};
31
32#define IXGBE_STAT(m) IXGBE_STATS, \
33 sizeof(((struct ixgbe_adapter *)0)->m), \
34 offsetof(struct ixgbe_adapter, m)
35#define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \
36 sizeof(((struct rtnl_link_stats64 *)0)->m), \
37 offsetof(struct rtnl_link_stats64, m)
38
39static const struct ixgbe_stats ixgbe_gstrings_stats[] = {
40 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
41 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
42 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
43 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
44 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
45 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
46 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
47 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
48 {"lsc_int", IXGBE_STAT(lsc_int)},
49 {"tx_busy", IXGBE_STAT(tx_busy)},
50 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
51 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
52 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
53 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
54 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
55 {"multicast", IXGBE_NETDEV_STAT(multicast)},
56 {"broadcast", IXGBE_STAT(stats.bprc)},
57 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
58 {"collisions", IXGBE_NETDEV_STAT(collisions)},
59 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
60 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
61 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
62 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
63 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
64 {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
65 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
66 {"fdir_overflow", IXGBE_STAT(fdir_overflow)},
67 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
68 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
69 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
70 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
71 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
72 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
73 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
74 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
75 {"rx_length_errors", IXGBE_STAT(stats.rlec)},
76 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
77 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
78 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
79 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
80 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
81 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
82 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
83 {"alloc_rx_page", IXGBE_STAT(alloc_rx_page)},
84 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
85 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
86 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
87 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)},
88 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)},
89 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)},
90 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)},
91 {"tx_hwtstamp_timeouts", IXGBE_STAT(tx_hwtstamp_timeouts)},
92 {"tx_hwtstamp_skipped", IXGBE_STAT(tx_hwtstamp_skipped)},
93 {"rx_hwtstamp_cleared", IXGBE_STAT(rx_hwtstamp_cleared)},
94 {"tx_ipsec", IXGBE_STAT(tx_ipsec)},
95 {"rx_ipsec", IXGBE_STAT(rx_ipsec)},
96#ifdef IXGBE_FCOE
97 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
98 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
99 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
100 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
101 {"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)},
102 {"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)},
103 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
104 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
105#endif
106};
107
108
109
110
111
112
113#define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues
114
115#define IXGBE_QUEUE_STATS_LEN ( \
116 (netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \
117 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
118#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
119#define IXGBE_PB_STATS_LEN ( \
120 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
121 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
122 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
123 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
124 / sizeof(u64))
125#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
126 IXGBE_PB_STATS_LEN + \
127 IXGBE_QUEUE_STATS_LEN)
128
129static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
130 "Register test (offline)", "Eeprom test (offline)",
131 "Interrupt test (offline)", "Loopback test (offline)",
132 "Link test (on/offline)"
133};
134#define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
135
136static const char ixgbe_priv_flags_strings[][ETH_GSTRING_LEN] = {
137#define IXGBE_PRIV_FLAGS_LEGACY_RX BIT(0)
138 "legacy-rx",
139#define IXGBE_PRIV_FLAGS_VF_IPSEC_EN BIT(1)
140 "vf-ipsec",
141};
142
143#define IXGBE_PRIV_FLAGS_STR_LEN ARRAY_SIZE(ixgbe_priv_flags_strings)
144
145#define ixgbe_isbackplane(type) ((type) == ixgbe_media_type_backplane)
146
147static void ixgbe_set_supported_10gtypes(struct ixgbe_hw *hw,
148 struct ethtool_link_ksettings *cmd)
149{
150 if (!ixgbe_isbackplane(hw->phy.media_type)) {
151 ethtool_link_ksettings_add_link_mode(cmd, supported,
152 10000baseT_Full);
153 return;
154 }
155
156 switch (hw->device_id) {
157 case IXGBE_DEV_ID_82598:
158 case IXGBE_DEV_ID_82599_KX4:
159 case IXGBE_DEV_ID_82599_KX4_MEZZ:
160 case IXGBE_DEV_ID_X550EM_X_KX4:
161 ethtool_link_ksettings_add_link_mode
162 (cmd, supported, 10000baseKX4_Full);
163 break;
164 case IXGBE_DEV_ID_82598_BX:
165 case IXGBE_DEV_ID_82599_KR:
166 case IXGBE_DEV_ID_X550EM_X_KR:
167 case IXGBE_DEV_ID_X550EM_X_XFI:
168 ethtool_link_ksettings_add_link_mode
169 (cmd, supported, 10000baseKR_Full);
170 break;
171 default:
172 ethtool_link_ksettings_add_link_mode
173 (cmd, supported, 10000baseKX4_Full);
174 ethtool_link_ksettings_add_link_mode
175 (cmd, supported, 10000baseKR_Full);
176 break;
177 }
178}
179
180static void ixgbe_set_advertising_10gtypes(struct ixgbe_hw *hw,
181 struct ethtool_link_ksettings *cmd)
182{
183 if (!ixgbe_isbackplane(hw->phy.media_type)) {
184 ethtool_link_ksettings_add_link_mode(cmd, advertising,
185 10000baseT_Full);
186 return;
187 }
188
189 switch (hw->device_id) {
190 case IXGBE_DEV_ID_82598:
191 case IXGBE_DEV_ID_82599_KX4:
192 case IXGBE_DEV_ID_82599_KX4_MEZZ:
193 case IXGBE_DEV_ID_X550EM_X_KX4:
194 ethtool_link_ksettings_add_link_mode
195 (cmd, advertising, 10000baseKX4_Full);
196 break;
197 case IXGBE_DEV_ID_82598_BX:
198 case IXGBE_DEV_ID_82599_KR:
199 case IXGBE_DEV_ID_X550EM_X_KR:
200 case IXGBE_DEV_ID_X550EM_X_XFI:
201 ethtool_link_ksettings_add_link_mode
202 (cmd, advertising, 10000baseKR_Full);
203 break;
204 default:
205 ethtool_link_ksettings_add_link_mode
206 (cmd, advertising, 10000baseKX4_Full);
207 ethtool_link_ksettings_add_link_mode
208 (cmd, advertising, 10000baseKR_Full);
209 break;
210 }
211}
212
213static int ixgbe_get_link_ksettings(struct net_device *netdev,
214 struct ethtool_link_ksettings *cmd)
215{
216 struct ixgbe_adapter *adapter = netdev_priv(netdev);
217 struct ixgbe_hw *hw = &adapter->hw;
218 ixgbe_link_speed supported_link;
219 bool autoneg = false;
220
221 ethtool_link_ksettings_zero_link_mode(cmd, supported);
222 ethtool_link_ksettings_zero_link_mode(cmd, advertising);
223
224 hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg);
225
226
227 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) {
228 ixgbe_set_supported_10gtypes(hw, cmd);
229 ixgbe_set_advertising_10gtypes(hw, cmd);
230 }
231 if (supported_link & IXGBE_LINK_SPEED_5GB_FULL)
232 ethtool_link_ksettings_add_link_mode(cmd, supported,
233 5000baseT_Full);
234
235 if (supported_link & IXGBE_LINK_SPEED_2_5GB_FULL)
236 ethtool_link_ksettings_add_link_mode(cmd, supported,
237 2500baseT_Full);
238
239 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL) {
240 if (ixgbe_isbackplane(hw->phy.media_type)) {
241 ethtool_link_ksettings_add_link_mode(cmd, supported,
242 1000baseKX_Full);
243 ethtool_link_ksettings_add_link_mode(cmd, advertising,
244 1000baseKX_Full);
245 } else {
246 ethtool_link_ksettings_add_link_mode(cmd, supported,
247 1000baseT_Full);
248 ethtool_link_ksettings_add_link_mode(cmd, advertising,
249 1000baseT_Full);
250 }
251 }
252 if (supported_link & IXGBE_LINK_SPEED_100_FULL) {
253 ethtool_link_ksettings_add_link_mode(cmd, supported,
254 100baseT_Full);
255 ethtool_link_ksettings_add_link_mode(cmd, advertising,
256 100baseT_Full);
257 }
258 if (supported_link & IXGBE_LINK_SPEED_10_FULL) {
259 ethtool_link_ksettings_add_link_mode(cmd, supported,
260 10baseT_Full);
261 ethtool_link_ksettings_add_link_mode(cmd, advertising,
262 10baseT_Full);
263 }
264
265
266 if (hw->phy.autoneg_advertised) {
267 ethtool_link_ksettings_zero_link_mode(cmd, advertising);
268 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL)
269 ethtool_link_ksettings_add_link_mode(cmd, advertising,
270 10baseT_Full);
271 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
272 ethtool_link_ksettings_add_link_mode(cmd, advertising,
273 100baseT_Full);
274 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
275 ixgbe_set_advertising_10gtypes(hw, cmd);
276 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) {
277 if (ethtool_link_ksettings_test_link_mode
278 (cmd, supported, 1000baseKX_Full))
279 ethtool_link_ksettings_add_link_mode
280 (cmd, advertising, 1000baseKX_Full);
281 else
282 ethtool_link_ksettings_add_link_mode
283 (cmd, advertising, 1000baseT_Full);
284 }
285 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL)
286 ethtool_link_ksettings_add_link_mode(cmd, advertising,
287 5000baseT_Full);
288 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
289 ethtool_link_ksettings_add_link_mode(cmd, advertising,
290 2500baseT_Full);
291 } else {
292 if (hw->phy.multispeed_fiber && !autoneg) {
293 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
294 ethtool_link_ksettings_add_link_mode
295 (cmd, advertising, 10000baseT_Full);
296 }
297 }
298
299 if (autoneg) {
300 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
301 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
302 cmd->base.autoneg = AUTONEG_ENABLE;
303 } else
304 cmd->base.autoneg = AUTONEG_DISABLE;
305
306
307 switch (adapter->hw.phy.type) {
308 case ixgbe_phy_tn:
309 case ixgbe_phy_aq:
310 case ixgbe_phy_x550em_ext_t:
311 case ixgbe_phy_fw:
312 case ixgbe_phy_cu_unknown:
313 ethtool_link_ksettings_add_link_mode(cmd, supported, TP);
314 ethtool_link_ksettings_add_link_mode(cmd, advertising, TP);
315 cmd->base.port = PORT_TP;
316 break;
317 case ixgbe_phy_qt:
318 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
319 ethtool_link_ksettings_add_link_mode(cmd, advertising, FIBRE);
320 cmd->base.port = PORT_FIBRE;
321 break;
322 case ixgbe_phy_nl:
323 case ixgbe_phy_sfp_passive_tyco:
324 case ixgbe_phy_sfp_passive_unknown:
325 case ixgbe_phy_sfp_ftl:
326 case ixgbe_phy_sfp_avago:
327 case ixgbe_phy_sfp_intel:
328 case ixgbe_phy_sfp_unknown:
329 case ixgbe_phy_qsfp_passive_unknown:
330 case ixgbe_phy_qsfp_active_unknown:
331 case ixgbe_phy_qsfp_intel:
332 case ixgbe_phy_qsfp_unknown:
333
334 switch (adapter->hw.phy.sfp_type) {
335 case ixgbe_sfp_type_da_cu:
336 case ixgbe_sfp_type_da_cu_core0:
337 case ixgbe_sfp_type_da_cu_core1:
338 ethtool_link_ksettings_add_link_mode(cmd, supported,
339 FIBRE);
340 ethtool_link_ksettings_add_link_mode(cmd, advertising,
341 FIBRE);
342 cmd->base.port = PORT_DA;
343 break;
344 case ixgbe_sfp_type_sr:
345 case ixgbe_sfp_type_lr:
346 case ixgbe_sfp_type_srlr_core0:
347 case ixgbe_sfp_type_srlr_core1:
348 case ixgbe_sfp_type_1g_sx_core0:
349 case ixgbe_sfp_type_1g_sx_core1:
350 case ixgbe_sfp_type_1g_lx_core0:
351 case ixgbe_sfp_type_1g_lx_core1:
352 ethtool_link_ksettings_add_link_mode(cmd, supported,
353 FIBRE);
354 ethtool_link_ksettings_add_link_mode(cmd, advertising,
355 FIBRE);
356 cmd->base.port = PORT_FIBRE;
357 break;
358 case ixgbe_sfp_type_not_present:
359 ethtool_link_ksettings_add_link_mode(cmd, supported,
360 FIBRE);
361 ethtool_link_ksettings_add_link_mode(cmd, advertising,
362 FIBRE);
363 cmd->base.port = PORT_NONE;
364 break;
365 case ixgbe_sfp_type_1g_cu_core0:
366 case ixgbe_sfp_type_1g_cu_core1:
367 ethtool_link_ksettings_add_link_mode(cmd, supported,
368 TP);
369 ethtool_link_ksettings_add_link_mode(cmd, advertising,
370 TP);
371 cmd->base.port = PORT_TP;
372 break;
373 case ixgbe_sfp_type_unknown:
374 default:
375 ethtool_link_ksettings_add_link_mode(cmd, supported,
376 FIBRE);
377 ethtool_link_ksettings_add_link_mode(cmd, advertising,
378 FIBRE);
379 cmd->base.port = PORT_OTHER;
380 break;
381 }
382 break;
383 case ixgbe_phy_xaui:
384 ethtool_link_ksettings_add_link_mode(cmd, supported,
385 FIBRE);
386 ethtool_link_ksettings_add_link_mode(cmd, advertising,
387 FIBRE);
388 cmd->base.port = PORT_NONE;
389 break;
390 case ixgbe_phy_unknown:
391 case ixgbe_phy_generic:
392 case ixgbe_phy_sfp_unsupported:
393 default:
394 ethtool_link_ksettings_add_link_mode(cmd, supported,
395 FIBRE);
396 ethtool_link_ksettings_add_link_mode(cmd, advertising,
397 FIBRE);
398 cmd->base.port = PORT_OTHER;
399 break;
400 }
401
402
403 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
404
405 switch (hw->fc.requested_mode) {
406 case ixgbe_fc_full:
407 ethtool_link_ksettings_add_link_mode(cmd, advertising, Pause);
408 break;
409 case ixgbe_fc_rx_pause:
410 ethtool_link_ksettings_add_link_mode(cmd, advertising, Pause);
411 ethtool_link_ksettings_add_link_mode(cmd, advertising,
412 Asym_Pause);
413 break;
414 case ixgbe_fc_tx_pause:
415 ethtool_link_ksettings_add_link_mode(cmd, advertising,
416 Asym_Pause);
417 break;
418 default:
419 ethtool_link_ksettings_del_link_mode(cmd, advertising, Pause);
420 ethtool_link_ksettings_del_link_mode(cmd, advertising,
421 Asym_Pause);
422 }
423
424 if (netif_carrier_ok(netdev)) {
425 switch (adapter->link_speed) {
426 case IXGBE_LINK_SPEED_10GB_FULL:
427 cmd->base.speed = SPEED_10000;
428 break;
429 case IXGBE_LINK_SPEED_5GB_FULL:
430 cmd->base.speed = SPEED_5000;
431 break;
432 case IXGBE_LINK_SPEED_2_5GB_FULL:
433 cmd->base.speed = SPEED_2500;
434 break;
435 case IXGBE_LINK_SPEED_1GB_FULL:
436 cmd->base.speed = SPEED_1000;
437 break;
438 case IXGBE_LINK_SPEED_100_FULL:
439 cmd->base.speed = SPEED_100;
440 break;
441 case IXGBE_LINK_SPEED_10_FULL:
442 cmd->base.speed = SPEED_10;
443 break;
444 default:
445 break;
446 }
447 cmd->base.duplex = DUPLEX_FULL;
448 } else {
449 cmd->base.speed = SPEED_UNKNOWN;
450 cmd->base.duplex = DUPLEX_UNKNOWN;
451 }
452
453 return 0;
454}
455
456static int ixgbe_set_link_ksettings(struct net_device *netdev,
457 const struct ethtool_link_ksettings *cmd)
458{
459 struct ixgbe_adapter *adapter = netdev_priv(netdev);
460 struct ixgbe_hw *hw = &adapter->hw;
461 u32 advertised, old;
462 s32 err = 0;
463
464 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
465 (hw->phy.multispeed_fiber)) {
466
467
468
469
470 if (!bitmap_subset(cmd->link_modes.advertising,
471 cmd->link_modes.supported,
472 __ETHTOOL_LINK_MODE_MASK_NBITS))
473 return -EINVAL;
474
475
476 if (!cmd->base.autoneg && hw->phy.multispeed_fiber) {
477 if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
478 10000baseT_Full) &&
479 ethtool_link_ksettings_test_link_mode(cmd, advertising,
480 1000baseT_Full))
481 return -EINVAL;
482 }
483
484 old = hw->phy.autoneg_advertised;
485 advertised = 0;
486 if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
487 10000baseT_Full))
488 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
489 if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
490 5000baseT_Full))
491 advertised |= IXGBE_LINK_SPEED_5GB_FULL;
492 if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
493 2500baseT_Full))
494 advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
495 if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
496 1000baseT_Full))
497 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
498
499 if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
500 100baseT_Full))
501 advertised |= IXGBE_LINK_SPEED_100_FULL;
502
503 if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
504 10baseT_Full))
505 advertised |= IXGBE_LINK_SPEED_10_FULL;
506
507 if (old == advertised)
508 return err;
509
510 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
511 usleep_range(1000, 2000);
512
513 hw->mac.autotry_restart = true;
514 err = hw->mac.ops.setup_link(hw, advertised, true);
515 if (err) {
516 e_info(probe, "setup link failed with code %d\n", err);
517 hw->mac.ops.setup_link(hw, old, true);
518 }
519 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
520 } else {
521
522 u32 speed = cmd->base.speed;
523
524 if ((cmd->base.autoneg == AUTONEG_ENABLE) ||
525 (!ethtool_link_ksettings_test_link_mode(cmd, advertising,
526 10000baseT_Full)) ||
527 (speed + cmd->base.duplex != SPEED_10000 + DUPLEX_FULL))
528 return -EINVAL;
529 }
530
531 return err;
532}
533
534static void ixgbe_get_pauseparam(struct net_device *netdev,
535 struct ethtool_pauseparam *pause)
536{
537 struct ixgbe_adapter *adapter = netdev_priv(netdev);
538 struct ixgbe_hw *hw = &adapter->hw;
539
540 if (ixgbe_device_supports_autoneg_fc(hw) &&
541 !hw->fc.disable_fc_autoneg)
542 pause->autoneg = 1;
543 else
544 pause->autoneg = 0;
545
546 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
547 pause->rx_pause = 1;
548 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
549 pause->tx_pause = 1;
550 } else if (hw->fc.current_mode == ixgbe_fc_full) {
551 pause->rx_pause = 1;
552 pause->tx_pause = 1;
553 }
554}
555
556static int ixgbe_set_pauseparam(struct net_device *netdev,
557 struct ethtool_pauseparam *pause)
558{
559 struct ixgbe_adapter *adapter = netdev_priv(netdev);
560 struct ixgbe_hw *hw = &adapter->hw;
561 struct ixgbe_fc_info fc = hw->fc;
562
563
564 if ((hw->mac.type == ixgbe_mac_82598EB) &&
565 (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
566 return -EINVAL;
567
568
569 if ((pause->autoneg == AUTONEG_ENABLE) &&
570 !ixgbe_device_supports_autoneg_fc(hw))
571 return -EINVAL;
572
573 fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE);
574
575 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
576 fc.requested_mode = ixgbe_fc_full;
577 else if (pause->rx_pause && !pause->tx_pause)
578 fc.requested_mode = ixgbe_fc_rx_pause;
579 else if (!pause->rx_pause && pause->tx_pause)
580 fc.requested_mode = ixgbe_fc_tx_pause;
581 else
582 fc.requested_mode = ixgbe_fc_none;
583
584
585 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
586 hw->fc = fc;
587 if (netif_running(netdev))
588 ixgbe_reinit_locked(adapter);
589 else
590 ixgbe_reset(adapter);
591 }
592
593 return 0;
594}
595
596static u32 ixgbe_get_msglevel(struct net_device *netdev)
597{
598 struct ixgbe_adapter *adapter = netdev_priv(netdev);
599 return adapter->msg_enable;
600}
601
602static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
603{
604 struct ixgbe_adapter *adapter = netdev_priv(netdev);
605 adapter->msg_enable = data;
606}
607
608static int ixgbe_get_regs_len(struct net_device *netdev)
609{
610#define IXGBE_REGS_LEN 1145
611 return IXGBE_REGS_LEN * sizeof(u32);
612}
613
614#define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
615
616static void ixgbe_get_regs(struct net_device *netdev,
617 struct ethtool_regs *regs, void *p)
618{
619 struct ixgbe_adapter *adapter = netdev_priv(netdev);
620 struct ixgbe_hw *hw = &adapter->hw;
621 u32 *regs_buff = p;
622 u8 i;
623
624 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
625
626 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
627 hw->device_id;
628
629
630 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
631 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
632 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
633 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
634 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
635 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
636 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
637 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
638
639
640 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
641 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
642 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA(hw));
643 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
644 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
645 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
646 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
647 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
648 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
649 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC(hw));
650
651
652
653
654 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
655 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
656 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
657 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
658 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
659 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
660 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
661 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
662 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
663 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
664 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
665 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
666
667
668 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
669 for (i = 0; i < 4; i++)
670 regs_buff[31 + i] = IXGBE_READ_REG(hw, IXGBE_FCTTV(i));
671 for (i = 0; i < 8; i++) {
672 switch (hw->mac.type) {
673 case ixgbe_mac_82598EB:
674 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
675 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
676 break;
677 case ixgbe_mac_82599EB:
678 case ixgbe_mac_X540:
679 case ixgbe_mac_X550:
680 case ixgbe_mac_X550EM_x:
681 case ixgbe_mac_x550em_a:
682 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
683 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
684 break;
685 default:
686 break;
687 }
688 }
689 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
690 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
691
692
693 for (i = 0; i < 64; i++)
694 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
695 for (i = 0; i < 64; i++)
696 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
697 for (i = 0; i < 64; i++)
698 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
699 for (i = 0; i < 64; i++)
700 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
701 for (i = 0; i < 64; i++)
702 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
703 for (i = 0; i < 64; i++)
704 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
705 for (i = 0; i < 16; i++)
706 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
707 for (i = 0; i < 16; i++)
708 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
709 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
710 for (i = 0; i < 8; i++)
711 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
712 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
713 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
714
715
716 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
717 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
718 for (i = 0; i < 16; i++)
719 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
720 for (i = 0; i < 16; i++)
721 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
722 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
723 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
724 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
725 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
726 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
727 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
728 for (i = 0; i < 8; i++)
729 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
730 for (i = 0; i < 8; i++)
731 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
732 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
733
734
735 for (i = 0; i < 32; i++)
736 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
737 for (i = 0; i < 32; i++)
738 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
739 for (i = 0; i < 32; i++)
740 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
741 for (i = 0; i < 32; i++)
742 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
743 for (i = 0; i < 32; i++)
744 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
745 for (i = 0; i < 32; i++)
746 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
747 for (i = 0; i < 32; i++)
748 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
749 for (i = 0; i < 32; i++)
750 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
751 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
752 for (i = 0; i < 16; i++)
753 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
754 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
755 for (i = 0; i < 8; i++)
756 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
757 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
758
759
760 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
761 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
762 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
763 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
764 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
765 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
766 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
767 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
768 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
769
770
771 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
772 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
773
774 switch (hw->mac.type) {
775 case ixgbe_mac_82598EB:
776 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
777 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
778 for (i = 0; i < 8; i++)
779 regs_buff[833 + i] =
780 IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
781 for (i = 0; i < 8; i++)
782 regs_buff[841 + i] =
783 IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
784 for (i = 0; i < 8; i++)
785 regs_buff[849 + i] =
786 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
787 for (i = 0; i < 8; i++)
788 regs_buff[857 + i] =
789 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
790 break;
791 case ixgbe_mac_82599EB:
792 case ixgbe_mac_X540:
793 case ixgbe_mac_X550:
794 case ixgbe_mac_X550EM_x:
795 case ixgbe_mac_x550em_a:
796 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
797 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RTRPCS);
798 for (i = 0; i < 8; i++)
799 regs_buff[833 + i] =
800 IXGBE_READ_REG(hw, IXGBE_RTRPT4C(i));
801 for (i = 0; i < 8; i++)
802 regs_buff[841 + i] =
803 IXGBE_READ_REG(hw, IXGBE_RTRPT4S(i));
804 for (i = 0; i < 8; i++)
805 regs_buff[849 + i] =
806 IXGBE_READ_REG(hw, IXGBE_RTTDT2C(i));
807 for (i = 0; i < 8; i++)
808 regs_buff[857 + i] =
809 IXGBE_READ_REG(hw, IXGBE_RTTDT2S(i));
810 break;
811 default:
812 break;
813 }
814
815 for (i = 0; i < 8; i++)
816 regs_buff[865 + i] =
817 IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
818 for (i = 0; i < 8; i++)
819 regs_buff[873 + i] =
820 IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
821
822
823 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
824 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
825 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
826 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
827 for (i = 0; i < 8; i++)
828 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
829 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
830 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
831 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
832 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
833 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
834 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
835 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
836 for (i = 0; i < 8; i++)
837 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
838 for (i = 0; i < 8; i++)
839 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
840 for (i = 0; i < 8; i++)
841 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
842 for (i = 0; i < 8; i++)
843 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
844 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
845 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
846 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
847 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
848 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
849 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
850 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
851 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
852 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
853 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
854 regs_buff[942] = (u32)IXGBE_GET_STAT(adapter, gorc);
855 regs_buff[943] = (u32)(IXGBE_GET_STAT(adapter, gorc) >> 32);
856 regs_buff[944] = (u32)IXGBE_GET_STAT(adapter, gotc);
857 regs_buff[945] = (u32)(IXGBE_GET_STAT(adapter, gotc) >> 32);
858 for (i = 0; i < 8; i++)
859 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
860 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
861 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
862 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
863 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
864 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
865 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
866 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
867 regs_buff[961] = (u32)IXGBE_GET_STAT(adapter, tor);
868 regs_buff[962] = (u32)(IXGBE_GET_STAT(adapter, tor) >> 32);
869 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
870 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
871 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
872 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
873 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
874 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
875 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
876 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
877 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
878 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
879 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
880 for (i = 0; i < 16; i++)
881 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
882 for (i = 0; i < 16; i++)
883 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
884 for (i = 0; i < 16; i++)
885 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
886 for (i = 0; i < 16; i++)
887 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
888
889
890 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
891 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
892 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
893 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
894 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
895 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
896 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
897 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
898 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
899 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
900 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
901 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
902 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
903 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
904 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
905 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
906 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
907 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
908 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
909 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
910 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
911 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
912 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
913 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
914 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
915 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
916 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
917 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
918 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
919 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
920 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
921 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
922 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
923
924
925 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
926 for (i = 0; i < 8; i++)
927 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
928 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
929 for (i = 0; i < 4; i++)
930 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
931 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
932 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
933 for (i = 0; i < 8; i++)
934 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
935 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
936 for (i = 0; i < 4; i++)
937 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
938 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
939 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
940 for (i = 0; i < 4; i++)
941 regs_buff[1102 + i] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA(i));
942 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
943 for (i = 0; i < 4; i++)
944 regs_buff[1107 + i] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA(i));
945 for (i = 0; i < 8; i++)
946 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
947 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
948 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
949 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
950 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
951 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
952 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
953 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
954 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
955 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
956
957
958 regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN);
959
960
961 regs_buff[1129] = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
962 regs_buff[1130] = IXGBE_READ_REG(hw, IXGBE_RTTUP2TC);
963 for (i = 0; i < 4; i++)
964 regs_buff[1131 + i] = IXGBE_READ_REG(hw, IXGBE_TXLLQ(i));
965 regs_buff[1135] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRM);
966
967 regs_buff[1136] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRD);
968
969
970
971 regs_buff[1137] = IXGBE_READ_REG(hw, IXGBE_RTTQCNCR);
972 regs_buff[1138] = IXGBE_READ_REG(hw, IXGBE_RTTQCNTG);
973
974
975 regs_buff[1139] = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
976 regs_buff[1140] = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
977 regs_buff[1141] = IXGBE_READ_REG(hw, IXGBE_SECTXBUFFAF);
978 regs_buff[1142] = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
979 regs_buff[1143] = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
980 regs_buff[1144] = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
981}
982
983static int ixgbe_get_eeprom_len(struct net_device *netdev)
984{
985 struct ixgbe_adapter *adapter = netdev_priv(netdev);
986 return adapter->hw.eeprom.word_size * 2;
987}
988
989static int ixgbe_get_eeprom(struct net_device *netdev,
990 struct ethtool_eeprom *eeprom, u8 *bytes)
991{
992 struct ixgbe_adapter *adapter = netdev_priv(netdev);
993 struct ixgbe_hw *hw = &adapter->hw;
994 u16 *eeprom_buff;
995 int first_word, last_word, eeprom_len;
996 int ret_val = 0;
997 u16 i;
998
999 if (eeprom->len == 0)
1000 return -EINVAL;
1001
1002 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
1003
1004 first_word = eeprom->offset >> 1;
1005 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
1006 eeprom_len = last_word - first_word + 1;
1007
1008 eeprom_buff = kmalloc_array(eeprom_len, sizeof(u16), GFP_KERNEL);
1009 if (!eeprom_buff)
1010 return -ENOMEM;
1011
1012 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len,
1013 eeprom_buff);
1014
1015
1016 for (i = 0; i < eeprom_len; i++)
1017 le16_to_cpus(&eeprom_buff[i]);
1018
1019 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
1020 kfree(eeprom_buff);
1021
1022 return ret_val;
1023}
1024
1025static int ixgbe_set_eeprom(struct net_device *netdev,
1026 struct ethtool_eeprom *eeprom, u8 *bytes)
1027{
1028 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1029 struct ixgbe_hw *hw = &adapter->hw;
1030 u16 *eeprom_buff;
1031 void *ptr;
1032 int max_len, first_word, last_word, ret_val = 0;
1033 u16 i;
1034
1035 if (eeprom->len == 0)
1036 return -EINVAL;
1037
1038 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
1039 return -EINVAL;
1040
1041 max_len = hw->eeprom.word_size * 2;
1042
1043 first_word = eeprom->offset >> 1;
1044 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
1045 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
1046 if (!eeprom_buff)
1047 return -ENOMEM;
1048
1049 ptr = eeprom_buff;
1050
1051 if (eeprom->offset & 1) {
1052
1053
1054
1055
1056 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]);
1057 if (ret_val)
1058 goto err;
1059
1060 ptr++;
1061 }
1062 if ((eeprom->offset + eeprom->len) & 1) {
1063
1064
1065
1066
1067 ret_val = hw->eeprom.ops.read(hw, last_word,
1068 &eeprom_buff[last_word - first_word]);
1069 if (ret_val)
1070 goto err;
1071 }
1072
1073
1074 for (i = 0; i < last_word - first_word + 1; i++)
1075 le16_to_cpus(&eeprom_buff[i]);
1076
1077 memcpy(ptr, bytes, eeprom->len);
1078
1079 for (i = 0; i < last_word - first_word + 1; i++)
1080 cpu_to_le16s(&eeprom_buff[i]);
1081
1082 ret_val = hw->eeprom.ops.write_buffer(hw, first_word,
1083 last_word - first_word + 1,
1084 eeprom_buff);
1085
1086
1087 if (ret_val == 0)
1088 hw->eeprom.ops.update_checksum(hw);
1089
1090err:
1091 kfree(eeprom_buff);
1092 return ret_val;
1093}
1094
1095static void ixgbe_get_drvinfo(struct net_device *netdev,
1096 struct ethtool_drvinfo *drvinfo)
1097{
1098 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1099
1100 strlcpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver));
1101 strlcpy(drvinfo->version, ixgbe_driver_version,
1102 sizeof(drvinfo->version));
1103
1104 strlcpy(drvinfo->fw_version, adapter->eeprom_id,
1105 sizeof(drvinfo->fw_version));
1106
1107 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
1108 sizeof(drvinfo->bus_info));
1109
1110 drvinfo->n_priv_flags = IXGBE_PRIV_FLAGS_STR_LEN;
1111}
1112
1113static void ixgbe_get_ringparam(struct net_device *netdev,
1114 struct ethtool_ringparam *ring)
1115{
1116 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1117 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
1118 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
1119
1120 ring->rx_max_pending = IXGBE_MAX_RXD;
1121 ring->tx_max_pending = IXGBE_MAX_TXD;
1122 ring->rx_pending = rx_ring->count;
1123 ring->tx_pending = tx_ring->count;
1124}
1125
1126static int ixgbe_set_ringparam(struct net_device *netdev,
1127 struct ethtool_ringparam *ring)
1128{
1129 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1130 struct ixgbe_ring *temp_ring;
1131 int i, j, err = 0;
1132 u32 new_rx_count, new_tx_count;
1133
1134 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
1135 return -EINVAL;
1136
1137 new_tx_count = clamp_t(u32, ring->tx_pending,
1138 IXGBE_MIN_TXD, IXGBE_MAX_TXD);
1139 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
1140
1141 new_rx_count = clamp_t(u32, ring->rx_pending,
1142 IXGBE_MIN_RXD, IXGBE_MAX_RXD);
1143 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
1144
1145 if ((new_tx_count == adapter->tx_ring_count) &&
1146 (new_rx_count == adapter->rx_ring_count)) {
1147
1148 return 0;
1149 }
1150
1151 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
1152 usleep_range(1000, 2000);
1153
1154 if (!netif_running(adapter->netdev)) {
1155 for (i = 0; i < adapter->num_tx_queues; i++)
1156 adapter->tx_ring[i]->count = new_tx_count;
1157 for (i = 0; i < adapter->num_xdp_queues; i++)
1158 adapter->xdp_ring[i]->count = new_tx_count;
1159 for (i = 0; i < adapter->num_rx_queues; i++)
1160 adapter->rx_ring[i]->count = new_rx_count;
1161 adapter->tx_ring_count = new_tx_count;
1162 adapter->xdp_ring_count = new_tx_count;
1163 adapter->rx_ring_count = new_rx_count;
1164 goto clear_reset;
1165 }
1166
1167
1168 i = max_t(int, adapter->num_tx_queues + adapter->num_xdp_queues,
1169 adapter->num_rx_queues);
1170 temp_ring = vmalloc(array_size(i, sizeof(struct ixgbe_ring)));
1171
1172 if (!temp_ring) {
1173 err = -ENOMEM;
1174 goto clear_reset;
1175 }
1176
1177 ixgbe_down(adapter);
1178
1179
1180
1181
1182
1183
1184
1185 if (new_tx_count != adapter->tx_ring_count) {
1186 for (i = 0; i < adapter->num_tx_queues; i++) {
1187 memcpy(&temp_ring[i], adapter->tx_ring[i],
1188 sizeof(struct ixgbe_ring));
1189
1190 temp_ring[i].count = new_tx_count;
1191 err = ixgbe_setup_tx_resources(&temp_ring[i]);
1192 if (err) {
1193 while (i) {
1194 i--;
1195 ixgbe_free_tx_resources(&temp_ring[i]);
1196 }
1197 goto err_setup;
1198 }
1199 }
1200
1201 for (j = 0; j < adapter->num_xdp_queues; j++, i++) {
1202 memcpy(&temp_ring[i], adapter->xdp_ring[j],
1203 sizeof(struct ixgbe_ring));
1204
1205 temp_ring[i].count = new_tx_count;
1206 err = ixgbe_setup_tx_resources(&temp_ring[i]);
1207 if (err) {
1208 while (i) {
1209 i--;
1210 ixgbe_free_tx_resources(&temp_ring[i]);
1211 }
1212 goto err_setup;
1213 }
1214 }
1215
1216 for (i = 0; i < adapter->num_tx_queues; i++) {
1217 ixgbe_free_tx_resources(adapter->tx_ring[i]);
1218
1219 memcpy(adapter->tx_ring[i], &temp_ring[i],
1220 sizeof(struct ixgbe_ring));
1221 }
1222 for (j = 0; j < adapter->num_xdp_queues; j++, i++) {
1223 ixgbe_free_tx_resources(adapter->xdp_ring[j]);
1224
1225 memcpy(adapter->xdp_ring[j], &temp_ring[i],
1226 sizeof(struct ixgbe_ring));
1227 }
1228
1229 adapter->tx_ring_count = new_tx_count;
1230 }
1231
1232
1233 if (new_rx_count != adapter->rx_ring_count) {
1234 for (i = 0; i < adapter->num_rx_queues; i++) {
1235 memcpy(&temp_ring[i], adapter->rx_ring[i],
1236 sizeof(struct ixgbe_ring));
1237
1238
1239 memset(&temp_ring[i].xdp_rxq, 0,
1240 sizeof(temp_ring[i].xdp_rxq));
1241
1242 temp_ring[i].count = new_rx_count;
1243 err = ixgbe_setup_rx_resources(adapter, &temp_ring[i]);
1244 if (err) {
1245 while (i) {
1246 i--;
1247 ixgbe_free_rx_resources(&temp_ring[i]);
1248 }
1249 goto err_setup;
1250 }
1251
1252 }
1253
1254 for (i = 0; i < adapter->num_rx_queues; i++) {
1255 ixgbe_free_rx_resources(adapter->rx_ring[i]);
1256
1257 memcpy(adapter->rx_ring[i], &temp_ring[i],
1258 sizeof(struct ixgbe_ring));
1259 }
1260
1261 adapter->rx_ring_count = new_rx_count;
1262 }
1263
1264err_setup:
1265 ixgbe_up(adapter);
1266 vfree(temp_ring);
1267clear_reset:
1268 clear_bit(__IXGBE_RESETTING, &adapter->state);
1269 return err;
1270}
1271
1272static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
1273{
1274 switch (sset) {
1275 case ETH_SS_TEST:
1276 return IXGBE_TEST_LEN;
1277 case ETH_SS_STATS:
1278 return IXGBE_STATS_LEN;
1279 case ETH_SS_PRIV_FLAGS:
1280 return IXGBE_PRIV_FLAGS_STR_LEN;
1281 default:
1282 return -EOPNOTSUPP;
1283 }
1284}
1285
1286static void ixgbe_get_ethtool_stats(struct net_device *netdev,
1287 struct ethtool_stats *stats, u64 *data)
1288{
1289 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1290 struct rtnl_link_stats64 temp;
1291 const struct rtnl_link_stats64 *net_stats;
1292 unsigned int start;
1293 struct ixgbe_ring *ring;
1294 int i, j;
1295 char *p = NULL;
1296
1297 ixgbe_update_stats(adapter);
1298 net_stats = dev_get_stats(netdev, &temp);
1299 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1300 switch (ixgbe_gstrings_stats[i].type) {
1301 case NETDEV_STATS:
1302 p = (char *) net_stats +
1303 ixgbe_gstrings_stats[i].stat_offset;
1304 break;
1305 case IXGBE_STATS:
1306 p = (char *) adapter +
1307 ixgbe_gstrings_stats[i].stat_offset;
1308 break;
1309 default:
1310 data[i] = 0;
1311 continue;
1312 }
1313
1314 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
1315 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1316 }
1317 for (j = 0; j < netdev->num_tx_queues; j++) {
1318 ring = adapter->tx_ring[j];
1319 if (!ring) {
1320 data[i] = 0;
1321 data[i+1] = 0;
1322 i += 2;
1323 continue;
1324 }
1325
1326 do {
1327 start = u64_stats_fetch_begin_irq(&ring->syncp);
1328 data[i] = ring->stats.packets;
1329 data[i+1] = ring->stats.bytes;
1330 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1331 i += 2;
1332 }
1333 for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) {
1334 ring = adapter->rx_ring[j];
1335 if (!ring) {
1336 data[i] = 0;
1337 data[i+1] = 0;
1338 i += 2;
1339 continue;
1340 }
1341
1342 do {
1343 start = u64_stats_fetch_begin_irq(&ring->syncp);
1344 data[i] = ring->stats.packets;
1345 data[i+1] = ring->stats.bytes;
1346 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1347 i += 2;
1348 }
1349
1350 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1351 data[i++] = adapter->stats.pxontxc[j];
1352 data[i++] = adapter->stats.pxofftxc[j];
1353 }
1354 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1355 data[i++] = adapter->stats.pxonrxc[j];
1356 data[i++] = adapter->stats.pxoffrxc[j];
1357 }
1358}
1359
1360static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
1361 u8 *data)
1362{
1363 char *p = (char *)data;
1364 unsigned int i;
1365
1366 switch (stringset) {
1367 case ETH_SS_TEST:
1368 for (i = 0; i < IXGBE_TEST_LEN; i++) {
1369 memcpy(data, ixgbe_gstrings_test[i], ETH_GSTRING_LEN);
1370 data += ETH_GSTRING_LEN;
1371 }
1372 break;
1373 case ETH_SS_STATS:
1374 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1375 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1376 ETH_GSTRING_LEN);
1377 p += ETH_GSTRING_LEN;
1378 }
1379 for (i = 0; i < netdev->num_tx_queues; i++) {
1380 sprintf(p, "tx_queue_%u_packets", i);
1381 p += ETH_GSTRING_LEN;
1382 sprintf(p, "tx_queue_%u_bytes", i);
1383 p += ETH_GSTRING_LEN;
1384 }
1385 for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) {
1386 sprintf(p, "rx_queue_%u_packets", i);
1387 p += ETH_GSTRING_LEN;
1388 sprintf(p, "rx_queue_%u_bytes", i);
1389 p += ETH_GSTRING_LEN;
1390 }
1391 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1392 sprintf(p, "tx_pb_%u_pxon", i);
1393 p += ETH_GSTRING_LEN;
1394 sprintf(p, "tx_pb_%u_pxoff", i);
1395 p += ETH_GSTRING_LEN;
1396 }
1397 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1398 sprintf(p, "rx_pb_%u_pxon", i);
1399 p += ETH_GSTRING_LEN;
1400 sprintf(p, "rx_pb_%u_pxoff", i);
1401 p += ETH_GSTRING_LEN;
1402 }
1403
1404 break;
1405 case ETH_SS_PRIV_FLAGS:
1406 memcpy(data, ixgbe_priv_flags_strings,
1407 IXGBE_PRIV_FLAGS_STR_LEN * ETH_GSTRING_LEN);
1408 }
1409}
1410
1411static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1412{
1413 struct ixgbe_hw *hw = &adapter->hw;
1414 bool link_up;
1415 u32 link_speed = 0;
1416
1417 if (ixgbe_removed(hw->hw_addr)) {
1418 *data = 1;
1419 return 1;
1420 }
1421 *data = 0;
1422
1423 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1424 if (link_up)
1425 return *data;
1426 else
1427 *data = 1;
1428 return *data;
1429}
1430
1431
1432struct ixgbe_reg_test {
1433 u16 reg;
1434 u8 array_len;
1435 u8 test_type;
1436 u32 mask;
1437 u32 write;
1438};
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450#define PATTERN_TEST 1
1451#define SET_READ_TEST 2
1452#define WRITE_NO_TEST 3
1453#define TABLE32_TEST 4
1454#define TABLE64_TEST_LO 5
1455#define TABLE64_TEST_HI 6
1456
1457
1458static const struct ixgbe_reg_test reg_test_82599[] = {
1459 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1460 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1461 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1462 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1463 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1464 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1465 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1466 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1467 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1468 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1469 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1470 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1471 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1472 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1473 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1474 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1475 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1476 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1477 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1478 { .reg = 0 }
1479};
1480
1481
1482static const struct ixgbe_reg_test reg_test_82598[] = {
1483 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1484 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1485 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1486 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1487 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1488 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1489 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1490
1491 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1492
1493 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1494 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1495 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1496 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1497 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1498 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1499 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1500 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1501 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1502 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1503 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1504 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1505 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1506 { .reg = 0 }
1507};
1508
1509static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg,
1510 u32 mask, u32 write)
1511{
1512 u32 pat, val, before;
1513 static const u32 test_pattern[] = {
1514 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1515
1516 if (ixgbe_removed(adapter->hw.hw_addr)) {
1517 *data = 1;
1518 return true;
1519 }
1520 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {
1521 before = ixgbe_read_reg(&adapter->hw, reg);
1522 ixgbe_write_reg(&adapter->hw, reg, test_pattern[pat] & write);
1523 val = ixgbe_read_reg(&adapter->hw, reg);
1524 if (val != (test_pattern[pat] & write & mask)) {
1525 e_err(drv, "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
1526 reg, val, (test_pattern[pat] & write & mask));
1527 *data = reg;
1528 ixgbe_write_reg(&adapter->hw, reg, before);
1529 return true;
1530 }
1531 ixgbe_write_reg(&adapter->hw, reg, before);
1532 }
1533 return false;
1534}
1535
1536static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg,
1537 u32 mask, u32 write)
1538{
1539 u32 val, before;
1540
1541 if (ixgbe_removed(adapter->hw.hw_addr)) {
1542 *data = 1;
1543 return true;
1544 }
1545 before = ixgbe_read_reg(&adapter->hw, reg);
1546 ixgbe_write_reg(&adapter->hw, reg, write & mask);
1547 val = ixgbe_read_reg(&adapter->hw, reg);
1548 if ((write & mask) != (val & mask)) {
1549 e_err(drv, "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n",
1550 reg, (val & mask), (write & mask));
1551 *data = reg;
1552 ixgbe_write_reg(&adapter->hw, reg, before);
1553 return true;
1554 }
1555 ixgbe_write_reg(&adapter->hw, reg, before);
1556 return false;
1557}
1558
1559static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1560{
1561 const struct ixgbe_reg_test *test;
1562 u32 value, before, after;
1563 u32 i, toggle;
1564
1565 if (ixgbe_removed(adapter->hw.hw_addr)) {
1566 e_err(drv, "Adapter removed - register test blocked\n");
1567 *data = 1;
1568 return 1;
1569 }
1570 switch (adapter->hw.mac.type) {
1571 case ixgbe_mac_82598EB:
1572 toggle = 0x7FFFF3FF;
1573 test = reg_test_82598;
1574 break;
1575 case ixgbe_mac_82599EB:
1576 case ixgbe_mac_X540:
1577 case ixgbe_mac_X550:
1578 case ixgbe_mac_X550EM_x:
1579 case ixgbe_mac_x550em_a:
1580 toggle = 0x7FFFF30F;
1581 test = reg_test_82599;
1582 break;
1583 default:
1584 *data = 1;
1585 return 1;
1586 }
1587
1588
1589
1590
1591
1592
1593
1594 before = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS);
1595 value = (ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle);
1596 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, toggle);
1597 after = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle;
1598 if (value != after) {
1599 e_err(drv, "failed STATUS register test got: 0x%08X expected: 0x%08X\n",
1600 after, value);
1601 *data = 1;
1602 return 1;
1603 }
1604
1605 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, before);
1606
1607
1608
1609
1610
1611 while (test->reg) {
1612 for (i = 0; i < test->array_len; i++) {
1613 bool b = false;
1614
1615 switch (test->test_type) {
1616 case PATTERN_TEST:
1617 b = reg_pattern_test(adapter, data,
1618 test->reg + (i * 0x40),
1619 test->mask,
1620 test->write);
1621 break;
1622 case SET_READ_TEST:
1623 b = reg_set_and_check(adapter, data,
1624 test->reg + (i * 0x40),
1625 test->mask,
1626 test->write);
1627 break;
1628 case WRITE_NO_TEST:
1629 ixgbe_write_reg(&adapter->hw,
1630 test->reg + (i * 0x40),
1631 test->write);
1632 break;
1633 case TABLE32_TEST:
1634 b = reg_pattern_test(adapter, data,
1635 test->reg + (i * 4),
1636 test->mask,
1637 test->write);
1638 break;
1639 case TABLE64_TEST_LO:
1640 b = reg_pattern_test(adapter, data,
1641 test->reg + (i * 8),
1642 test->mask,
1643 test->write);
1644 break;
1645 case TABLE64_TEST_HI:
1646 b = reg_pattern_test(adapter, data,
1647 (test->reg + 4) + (i * 8),
1648 test->mask,
1649 test->write);
1650 break;
1651 }
1652 if (b)
1653 return 1;
1654 }
1655 test++;
1656 }
1657
1658 *data = 0;
1659 return 0;
1660}
1661
1662static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1663{
1664 struct ixgbe_hw *hw = &adapter->hw;
1665 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1666 *data = 1;
1667 else
1668 *data = 0;
1669 return *data;
1670}
1671
1672static irqreturn_t ixgbe_test_intr(int irq, void *data)
1673{
1674 struct net_device *netdev = (struct net_device *) data;
1675 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1676
1677 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1678
1679 return IRQ_HANDLED;
1680}
1681
1682static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1683{
1684 struct net_device *netdev = adapter->netdev;
1685 u32 mask, i = 0, shared_int = true;
1686 u32 irq = adapter->pdev->irq;
1687
1688 *data = 0;
1689
1690
1691 if (adapter->msix_entries) {
1692
1693 return 0;
1694 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1695 shared_int = false;
1696 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
1697 netdev)) {
1698 *data = 1;
1699 return -1;
1700 }
1701 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
1702 netdev->name, netdev)) {
1703 shared_int = false;
1704 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
1705 netdev->name, netdev)) {
1706 *data = 1;
1707 return -1;
1708 }
1709 e_info(hw, "testing %s interrupt\n", shared_int ?
1710 "shared" : "unshared");
1711
1712
1713 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1714 IXGBE_WRITE_FLUSH(&adapter->hw);
1715 usleep_range(10000, 20000);
1716
1717
1718 for (; i < 10; i++) {
1719
1720 mask = BIT(i);
1721
1722 if (!shared_int) {
1723
1724
1725
1726
1727
1728
1729
1730 adapter->test_icr = 0;
1731 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1732 ~mask & 0x00007FFF);
1733 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1734 ~mask & 0x00007FFF);
1735 IXGBE_WRITE_FLUSH(&adapter->hw);
1736 usleep_range(10000, 20000);
1737
1738 if (adapter->test_icr & mask) {
1739 *data = 3;
1740 break;
1741 }
1742 }
1743
1744
1745
1746
1747
1748
1749
1750 adapter->test_icr = 0;
1751 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1752 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1753 IXGBE_WRITE_FLUSH(&adapter->hw);
1754 usleep_range(10000, 20000);
1755
1756 if (!(adapter->test_icr & mask)) {
1757 *data = 4;
1758 break;
1759 }
1760
1761 if (!shared_int) {
1762
1763
1764
1765
1766
1767
1768
1769 adapter->test_icr = 0;
1770 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1771 ~mask & 0x00007FFF);
1772 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1773 ~mask & 0x00007FFF);
1774 IXGBE_WRITE_FLUSH(&adapter->hw);
1775 usleep_range(10000, 20000);
1776
1777 if (adapter->test_icr) {
1778 *data = 5;
1779 break;
1780 }
1781 }
1782 }
1783
1784
1785 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1786 IXGBE_WRITE_FLUSH(&adapter->hw);
1787 usleep_range(10000, 20000);
1788
1789
1790 free_irq(irq, netdev);
1791
1792 return *data;
1793}
1794
1795static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1796{
1797
1798
1799
1800
1801
1802
1803
1804 ixgbe_disable_rx(adapter);
1805
1806
1807 ixgbe_disable_tx(adapter);
1808
1809 ixgbe_reset(adapter);
1810
1811 ixgbe_free_tx_resources(&adapter->test_tx_ring);
1812 ixgbe_free_rx_resources(&adapter->test_rx_ring);
1813}
1814
1815static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1816{
1817 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1818 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1819 struct ixgbe_hw *hw = &adapter->hw;
1820 u32 rctl, reg_data;
1821 int ret_val;
1822 int err;
1823
1824
1825 tx_ring->count = IXGBE_DEFAULT_TXD;
1826 tx_ring->queue_index = 0;
1827 tx_ring->dev = &adapter->pdev->dev;
1828 tx_ring->netdev = adapter->netdev;
1829 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx;
1830
1831 err = ixgbe_setup_tx_resources(tx_ring);
1832 if (err)
1833 return 1;
1834
1835 switch (adapter->hw.mac.type) {
1836 case ixgbe_mac_82599EB:
1837 case ixgbe_mac_X540:
1838 case ixgbe_mac_X550:
1839 case ixgbe_mac_X550EM_x:
1840 case ixgbe_mac_x550em_a:
1841 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1842 reg_data |= IXGBE_DMATXCTL_TE;
1843 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1844 break;
1845 default:
1846 break;
1847 }
1848
1849 ixgbe_configure_tx_ring(adapter, tx_ring);
1850
1851
1852 rx_ring->count = IXGBE_DEFAULT_RXD;
1853 rx_ring->queue_index = 0;
1854 rx_ring->dev = &adapter->pdev->dev;
1855 rx_ring->netdev = adapter->netdev;
1856 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx;
1857
1858 err = ixgbe_setup_rx_resources(adapter, rx_ring);
1859 if (err) {
1860 ret_val = 4;
1861 goto err_nomem;
1862 }
1863
1864 hw->mac.ops.disable_rx(hw);
1865
1866 ixgbe_configure_rx_ring(adapter, rx_ring);
1867
1868 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1869 rctl |= IXGBE_RXCTRL_DMBYPS;
1870 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1871
1872 hw->mac.ops.enable_rx(hw);
1873
1874 return 0;
1875
1876err_nomem:
1877 ixgbe_free_desc_rings(adapter);
1878 return ret_val;
1879}
1880
1881static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1882{
1883 struct ixgbe_hw *hw = &adapter->hw;
1884 u32 reg_data;
1885
1886
1887
1888 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1889 reg_data |= IXGBE_HLREG0_LPBK;
1890 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data);
1891
1892 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1893 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1894 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data);
1895
1896
1897 switch (adapter->hw.mac.type) {
1898 case ixgbe_mac_X540:
1899 case ixgbe_mac_X550:
1900 case ixgbe_mac_X550EM_x:
1901 case ixgbe_mac_x550em_a:
1902 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC);
1903 reg_data |= IXGBE_MACC_FLU;
1904 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data);
1905 break;
1906 default:
1907 if (hw->mac.orig_autoc) {
1908 reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU;
1909 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data);
1910 } else {
1911 return 10;
1912 }
1913 }
1914 IXGBE_WRITE_FLUSH(hw);
1915 usleep_range(10000, 20000);
1916
1917
1918 if (hw->mac.type == ixgbe_mac_82598EB) {
1919 u8 atlas;
1920
1921 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1922 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1923 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1924
1925 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1926 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1927 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1928
1929 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1930 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1931 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1932
1933 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1934 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1935 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1936 }
1937
1938 return 0;
1939}
1940
1941static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1942{
1943 u32 reg_data;
1944
1945 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1946 reg_data &= ~IXGBE_HLREG0_LPBK;
1947 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1948}
1949
1950static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1951 unsigned int frame_size)
1952{
1953 memset(skb->data, 0xFF, frame_size);
1954 frame_size >>= 1;
1955 memset(&skb->data[frame_size], 0xAA, frame_size / 2 - 1);
1956 memset(&skb->data[frame_size + 10], 0xBE, 1);
1957 memset(&skb->data[frame_size + 12], 0xAF, 1);
1958}
1959
1960static bool ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer *rx_buffer,
1961 unsigned int frame_size)
1962{
1963 unsigned char *data;
1964 bool match = true;
1965
1966 frame_size >>= 1;
1967
1968 data = kmap(rx_buffer->page) + rx_buffer->page_offset;
1969
1970 if (data[3] != 0xFF ||
1971 data[frame_size + 10] != 0xBE ||
1972 data[frame_size + 12] != 0xAF)
1973 match = false;
1974
1975 kunmap(rx_buffer->page);
1976
1977 return match;
1978}
1979
1980static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,
1981 struct ixgbe_ring *tx_ring,
1982 unsigned int size)
1983{
1984 union ixgbe_adv_rx_desc *rx_desc;
1985 u16 rx_ntc, tx_ntc, count = 0;
1986
1987
1988 rx_ntc = rx_ring->next_to_clean;
1989 tx_ntc = tx_ring->next_to_clean;
1990 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
1991
1992 while (tx_ntc != tx_ring->next_to_use) {
1993 union ixgbe_adv_tx_desc *tx_desc;
1994 struct ixgbe_tx_buffer *tx_buffer;
1995
1996 tx_desc = IXGBE_TX_DESC(tx_ring, tx_ntc);
1997
1998
1999 if (!(tx_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
2000 return count;
2001
2002
2003 tx_buffer = &tx_ring->tx_buffer_info[tx_ntc];
2004
2005
2006 dev_kfree_skb_any(tx_buffer->skb);
2007
2008
2009 dma_unmap_single(tx_ring->dev,
2010 dma_unmap_addr(tx_buffer, dma),
2011 dma_unmap_len(tx_buffer, len),
2012 DMA_TO_DEVICE);
2013 dma_unmap_len_set(tx_buffer, len, 0);
2014
2015
2016 tx_ntc++;
2017 if (tx_ntc == tx_ring->count)
2018 tx_ntc = 0;
2019 }
2020
2021 while (rx_desc->wb.upper.length) {
2022 struct ixgbe_rx_buffer *rx_buffer;
2023
2024
2025 rx_buffer = &rx_ring->rx_buffer_info[rx_ntc];
2026
2027
2028 dma_sync_single_for_cpu(rx_ring->dev,
2029 rx_buffer->dma,
2030 ixgbe_rx_bufsz(rx_ring),
2031 DMA_FROM_DEVICE);
2032
2033
2034 if (ixgbe_check_lbtest_frame(rx_buffer, size))
2035 count++;
2036 else
2037 break;
2038
2039
2040 dma_sync_single_for_device(rx_ring->dev,
2041 rx_buffer->dma,
2042 ixgbe_rx_bufsz(rx_ring),
2043 DMA_FROM_DEVICE);
2044
2045
2046 rx_ntc++;
2047 if (rx_ntc == rx_ring->count)
2048 rx_ntc = 0;
2049
2050
2051 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
2052 }
2053
2054 netdev_tx_reset_queue(txring_txq(tx_ring));
2055
2056
2057 ixgbe_alloc_rx_buffers(rx_ring, count);
2058 rx_ring->next_to_clean = rx_ntc;
2059 tx_ring->next_to_clean = tx_ntc;
2060
2061 return count;
2062}
2063
2064static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
2065{
2066 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
2067 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
2068 int i, j, lc, good_cnt, ret_val = 0;
2069 unsigned int size = 1024;
2070 netdev_tx_t tx_ret_val;
2071 struct sk_buff *skb;
2072 u32 flags_orig = adapter->flags;
2073
2074
2075 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
2076
2077
2078 skb = alloc_skb(size, GFP_KERNEL);
2079 if (!skb)
2080 return 11;
2081
2082
2083 ixgbe_create_lbtest_frame(skb, size);
2084 skb_put(skb, size);
2085
2086
2087
2088
2089
2090
2091
2092 if (rx_ring->count <= tx_ring->count)
2093 lc = ((tx_ring->count / 64) * 2) + 1;
2094 else
2095 lc = ((rx_ring->count / 64) * 2) + 1;
2096
2097 for (j = 0; j <= lc; j++) {
2098
2099 good_cnt = 0;
2100
2101
2102 for (i = 0; i < 64; i++) {
2103 skb_get(skb);
2104 tx_ret_val = ixgbe_xmit_frame_ring(skb,
2105 adapter,
2106 tx_ring);
2107 if (tx_ret_val == NETDEV_TX_OK)
2108 good_cnt++;
2109 }
2110
2111 if (good_cnt != 64) {
2112 ret_val = 12;
2113 break;
2114 }
2115
2116
2117 msleep(200);
2118
2119 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size);
2120 if (good_cnt != 64) {
2121 ret_val = 13;
2122 break;
2123 }
2124 }
2125
2126
2127 kfree_skb(skb);
2128 adapter->flags = flags_orig;
2129
2130 return ret_val;
2131}
2132
2133static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
2134{
2135 *data = ixgbe_setup_desc_rings(adapter);
2136 if (*data)
2137 goto out;
2138 *data = ixgbe_setup_loopback_test(adapter);
2139 if (*data)
2140 goto err_loopback;
2141 *data = ixgbe_run_loopback_test(adapter);
2142 ixgbe_loopback_cleanup(adapter);
2143
2144err_loopback:
2145 ixgbe_free_desc_rings(adapter);
2146out:
2147 return *data;
2148}
2149
2150static void ixgbe_diag_test(struct net_device *netdev,
2151 struct ethtool_test *eth_test, u64 *data)
2152{
2153 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2154 bool if_running = netif_running(netdev);
2155
2156 if (ixgbe_removed(adapter->hw.hw_addr)) {
2157 e_err(hw, "Adapter removed - test blocked\n");
2158 data[0] = 1;
2159 data[1] = 1;
2160 data[2] = 1;
2161 data[3] = 1;
2162 data[4] = 1;
2163 eth_test->flags |= ETH_TEST_FL_FAILED;
2164 return;
2165 }
2166 set_bit(__IXGBE_TESTING, &adapter->state);
2167 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
2168 struct ixgbe_hw *hw = &adapter->hw;
2169
2170 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2171 int i;
2172 for (i = 0; i < adapter->num_vfs; i++) {
2173 if (adapter->vfinfo[i].clear_to_send) {
2174 netdev_warn(netdev, "offline diagnostic is not supported when VFs are present\n");
2175 data[0] = 1;
2176 data[1] = 1;
2177 data[2] = 1;
2178 data[3] = 1;
2179 data[4] = 1;
2180 eth_test->flags |= ETH_TEST_FL_FAILED;
2181 clear_bit(__IXGBE_TESTING,
2182 &adapter->state);
2183 goto skip_ol_tests;
2184 }
2185 }
2186 }
2187
2188
2189 e_info(hw, "offline testing starting\n");
2190
2191
2192
2193
2194 if (ixgbe_link_test(adapter, &data[4]))
2195 eth_test->flags |= ETH_TEST_FL_FAILED;
2196
2197 if (if_running)
2198
2199 ixgbe_close(netdev);
2200 else
2201 ixgbe_reset(adapter);
2202
2203 e_info(hw, "register testing starting\n");
2204 if (ixgbe_reg_test(adapter, &data[0]))
2205 eth_test->flags |= ETH_TEST_FL_FAILED;
2206
2207 ixgbe_reset(adapter);
2208 e_info(hw, "eeprom testing starting\n");
2209 if (ixgbe_eeprom_test(adapter, &data[1]))
2210 eth_test->flags |= ETH_TEST_FL_FAILED;
2211
2212 ixgbe_reset(adapter);
2213 e_info(hw, "interrupt testing starting\n");
2214 if (ixgbe_intr_test(adapter, &data[2]))
2215 eth_test->flags |= ETH_TEST_FL_FAILED;
2216
2217
2218
2219 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
2220 IXGBE_FLAG_VMDQ_ENABLED)) {
2221 e_info(hw, "Skip MAC loopback diagnostic in VT mode\n");
2222 data[3] = 0;
2223 goto skip_loopback;
2224 }
2225
2226 ixgbe_reset(adapter);
2227 e_info(hw, "loopback testing starting\n");
2228 if (ixgbe_loopback_test(adapter, &data[3]))
2229 eth_test->flags |= ETH_TEST_FL_FAILED;
2230
2231skip_loopback:
2232 ixgbe_reset(adapter);
2233
2234
2235 clear_bit(__IXGBE_TESTING, &adapter->state);
2236 if (if_running)
2237 ixgbe_open(netdev);
2238 else if (hw->mac.ops.disable_tx_laser)
2239 hw->mac.ops.disable_tx_laser(hw);
2240 } else {
2241 e_info(hw, "online testing starting\n");
2242
2243
2244 if (ixgbe_link_test(adapter, &data[4]))
2245 eth_test->flags |= ETH_TEST_FL_FAILED;
2246
2247
2248 data[0] = 0;
2249 data[1] = 0;
2250 data[2] = 0;
2251 data[3] = 0;
2252
2253 clear_bit(__IXGBE_TESTING, &adapter->state);
2254 }
2255
2256skip_ol_tests:
2257 msleep_interruptible(4 * 1000);
2258}
2259
2260static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
2261 struct ethtool_wolinfo *wol)
2262{
2263 struct ixgbe_hw *hw = &adapter->hw;
2264 int retval = 0;
2265
2266
2267 if (!ixgbe_wol_supported(adapter, hw->device_id,
2268 hw->subsystem_device_id)) {
2269 retval = 1;
2270 wol->supported = 0;
2271 }
2272
2273 return retval;
2274}
2275
2276static void ixgbe_get_wol(struct net_device *netdev,
2277 struct ethtool_wolinfo *wol)
2278{
2279 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2280
2281 wol->supported = WAKE_UCAST | WAKE_MCAST |
2282 WAKE_BCAST | WAKE_MAGIC;
2283 wol->wolopts = 0;
2284
2285 if (ixgbe_wol_exclusion(adapter, wol) ||
2286 !device_can_wakeup(&adapter->pdev->dev))
2287 return;
2288
2289 if (adapter->wol & IXGBE_WUFC_EX)
2290 wol->wolopts |= WAKE_UCAST;
2291 if (adapter->wol & IXGBE_WUFC_MC)
2292 wol->wolopts |= WAKE_MCAST;
2293 if (adapter->wol & IXGBE_WUFC_BC)
2294 wol->wolopts |= WAKE_BCAST;
2295 if (adapter->wol & IXGBE_WUFC_MAG)
2296 wol->wolopts |= WAKE_MAGIC;
2297}
2298
2299static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2300{
2301 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2302
2303 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE |
2304 WAKE_FILTER))
2305 return -EOPNOTSUPP;
2306
2307 if (ixgbe_wol_exclusion(adapter, wol))
2308 return wol->wolopts ? -EOPNOTSUPP : 0;
2309
2310 adapter->wol = 0;
2311
2312 if (wol->wolopts & WAKE_UCAST)
2313 adapter->wol |= IXGBE_WUFC_EX;
2314 if (wol->wolopts & WAKE_MCAST)
2315 adapter->wol |= IXGBE_WUFC_MC;
2316 if (wol->wolopts & WAKE_BCAST)
2317 adapter->wol |= IXGBE_WUFC_BC;
2318 if (wol->wolopts & WAKE_MAGIC)
2319 adapter->wol |= IXGBE_WUFC_MAG;
2320
2321 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2322
2323 return 0;
2324}
2325
2326static int ixgbe_nway_reset(struct net_device *netdev)
2327{
2328 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2329
2330 if (netif_running(netdev))
2331 ixgbe_reinit_locked(adapter);
2332
2333 return 0;
2334}
2335
2336static int ixgbe_set_phys_id(struct net_device *netdev,
2337 enum ethtool_phys_id_state state)
2338{
2339 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2340 struct ixgbe_hw *hw = &adapter->hw;
2341
2342 if (!hw->mac.ops.led_on || !hw->mac.ops.led_off)
2343 return -EOPNOTSUPP;
2344
2345 switch (state) {
2346 case ETHTOOL_ID_ACTIVE:
2347 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2348 return 2;
2349
2350 case ETHTOOL_ID_ON:
2351 hw->mac.ops.led_on(hw, hw->mac.led_link_act);
2352 break;
2353
2354 case ETHTOOL_ID_OFF:
2355 hw->mac.ops.led_off(hw, hw->mac.led_link_act);
2356 break;
2357
2358 case ETHTOOL_ID_INACTIVE:
2359
2360 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg);
2361 break;
2362 }
2363
2364 return 0;
2365}
2366
2367static int ixgbe_get_coalesce(struct net_device *netdev,
2368 struct ethtool_coalesce *ec)
2369{
2370 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2371
2372
2373 if (adapter->rx_itr_setting <= 1)
2374 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2375 else
2376 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2377
2378
2379 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2380 return 0;
2381
2382
2383 if (adapter->tx_itr_setting <= 1)
2384 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2385 else
2386 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2387
2388 return 0;
2389}
2390
2391
2392
2393
2394
2395static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter)
2396{
2397 struct net_device *netdev = adapter->netdev;
2398
2399
2400 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) ||
2401 !(netdev->features & NETIF_F_LRO))
2402 return false;
2403
2404
2405 if (adapter->rx_itr_setting == 1 ||
2406 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
2407 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
2408 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
2409 e_info(probe, "rx-usecs value high enough to re-enable RSC\n");
2410 return true;
2411 }
2412
2413 } else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2414 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
2415 e_info(probe, "rx-usecs set too low, disabling RSC\n");
2416 return true;
2417 }
2418 return false;
2419}
2420
2421static int ixgbe_set_coalesce(struct net_device *netdev,
2422 struct ethtool_coalesce *ec)
2423{
2424 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2425 struct ixgbe_q_vector *q_vector;
2426 int i;
2427 u16 tx_itr_param, rx_itr_param, tx_itr_prev;
2428 bool need_reset = false;
2429
2430 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) {
2431
2432 if (ec->tx_coalesce_usecs)
2433 return -EINVAL;
2434 tx_itr_prev = adapter->rx_itr_setting;
2435 } else {
2436 tx_itr_prev = adapter->tx_itr_setting;
2437 }
2438
2439 if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) ||
2440 (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)))
2441 return -EINVAL;
2442
2443 if (ec->rx_coalesce_usecs > 1)
2444 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2445 else
2446 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2447
2448 if (adapter->rx_itr_setting == 1)
2449 rx_itr_param = IXGBE_20K_ITR;
2450 else
2451 rx_itr_param = adapter->rx_itr_setting;
2452
2453 if (ec->tx_coalesce_usecs > 1)
2454 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2455 else
2456 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2457
2458 if (adapter->tx_itr_setting == 1)
2459 tx_itr_param = IXGBE_12K_ITR;
2460 else
2461 tx_itr_param = adapter->tx_itr_setting;
2462
2463
2464 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2465 adapter->tx_itr_setting = adapter->rx_itr_setting;
2466
2467
2468 if ((adapter->tx_itr_setting != 1) &&
2469 (adapter->tx_itr_setting < IXGBE_100K_ITR)) {
2470 if ((tx_itr_prev == 1) ||
2471 (tx_itr_prev >= IXGBE_100K_ITR))
2472 need_reset = true;
2473 } else {
2474 if ((tx_itr_prev != 1) &&
2475 (tx_itr_prev < IXGBE_100K_ITR))
2476 need_reset = true;
2477 }
2478
2479
2480 need_reset |= ixgbe_update_rsc(adapter);
2481
2482 for (i = 0; i < adapter->num_q_vectors; i++) {
2483 q_vector = adapter->q_vector[i];
2484 if (q_vector->tx.count && !q_vector->rx.count)
2485
2486 q_vector->itr = tx_itr_param;
2487 else
2488
2489 q_vector->itr = rx_itr_param;
2490 ixgbe_write_eitr(q_vector);
2491 }
2492
2493
2494
2495
2496
2497
2498 if (need_reset)
2499 ixgbe_do_reset(netdev);
2500
2501 return 0;
2502}
2503
2504static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2505 struct ethtool_rxnfc *cmd)
2506{
2507 union ixgbe_atr_input *mask = &adapter->fdir_mask;
2508 struct ethtool_rx_flow_spec *fsp =
2509 (struct ethtool_rx_flow_spec *)&cmd->fs;
2510 struct hlist_node *node2;
2511 struct ixgbe_fdir_filter *rule = NULL;
2512
2513
2514 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2515
2516 hlist_for_each_entry_safe(rule, node2,
2517 &adapter->fdir_filter_list, fdir_node) {
2518 if (fsp->location <= rule->sw_idx)
2519 break;
2520 }
2521
2522 if (!rule || fsp->location != rule->sw_idx)
2523 return -EINVAL;
2524
2525
2526
2527
2528 switch (rule->filter.formatted.flow_type) {
2529 case IXGBE_ATR_FLOW_TYPE_TCPV4:
2530 fsp->flow_type = TCP_V4_FLOW;
2531 break;
2532 case IXGBE_ATR_FLOW_TYPE_UDPV4:
2533 fsp->flow_type = UDP_V4_FLOW;
2534 break;
2535 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2536 fsp->flow_type = SCTP_V4_FLOW;
2537 break;
2538 case IXGBE_ATR_FLOW_TYPE_IPV4:
2539 fsp->flow_type = IP_USER_FLOW;
2540 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
2541 fsp->h_u.usr_ip4_spec.proto = 0;
2542 fsp->m_u.usr_ip4_spec.proto = 0;
2543 break;
2544 default:
2545 return -EINVAL;
2546 }
2547
2548 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port;
2549 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port;
2550 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port;
2551 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port;
2552 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0];
2553 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0];
2554 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0];
2555 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0];
2556 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id;
2557 fsp->m_ext.vlan_tci = mask->formatted.vlan_id;
2558 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes;
2559 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes;
2560 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool);
2561 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool);
2562 fsp->flow_type |= FLOW_EXT;
2563
2564
2565 if (rule->action == IXGBE_FDIR_DROP_QUEUE)
2566 fsp->ring_cookie = RX_CLS_FLOW_DISC;
2567 else
2568 fsp->ring_cookie = rule->action;
2569
2570 return 0;
2571}
2572
2573static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter,
2574 struct ethtool_rxnfc *cmd,
2575 u32 *rule_locs)
2576{
2577 struct hlist_node *node2;
2578 struct ixgbe_fdir_filter *rule;
2579 int cnt = 0;
2580
2581
2582 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2583
2584 hlist_for_each_entry_safe(rule, node2,
2585 &adapter->fdir_filter_list, fdir_node) {
2586 if (cnt == cmd->rule_cnt)
2587 return -EMSGSIZE;
2588 rule_locs[cnt] = rule->sw_idx;
2589 cnt++;
2590 }
2591
2592 cmd->rule_cnt = cnt;
2593
2594 return 0;
2595}
2596
2597static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter,
2598 struct ethtool_rxnfc *cmd)
2599{
2600 cmd->data = 0;
2601
2602
2603 switch (cmd->flow_type) {
2604 case TCP_V4_FLOW:
2605 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2606
2607 case UDP_V4_FLOW:
2608 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2609 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2610
2611 case SCTP_V4_FLOW:
2612 case AH_ESP_V4_FLOW:
2613 case AH_V4_FLOW:
2614 case ESP_V4_FLOW:
2615 case IPV4_FLOW:
2616 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2617 break;
2618 case TCP_V6_FLOW:
2619 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2620
2621 case UDP_V6_FLOW:
2622 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2623 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2624
2625 case SCTP_V6_FLOW:
2626 case AH_ESP_V6_FLOW:
2627 case AH_V6_FLOW:
2628 case ESP_V6_FLOW:
2629 case IPV6_FLOW:
2630 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2631 break;
2632 default:
2633 return -EINVAL;
2634 }
2635
2636 return 0;
2637}
2638
2639static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2640 u32 *rule_locs)
2641{
2642 struct ixgbe_adapter *adapter = netdev_priv(dev);
2643 int ret = -EOPNOTSUPP;
2644
2645 switch (cmd->cmd) {
2646 case ETHTOOL_GRXRINGS:
2647 cmd->data = adapter->num_rx_queues;
2648 ret = 0;
2649 break;
2650 case ETHTOOL_GRXCLSRLCNT:
2651 cmd->rule_cnt = adapter->fdir_filter_count;
2652 ret = 0;
2653 break;
2654 case ETHTOOL_GRXCLSRULE:
2655 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd);
2656 break;
2657 case ETHTOOL_GRXCLSRLALL:
2658 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs);
2659 break;
2660 case ETHTOOL_GRXFH:
2661 ret = ixgbe_get_rss_hash_opts(adapter, cmd);
2662 break;
2663 default:
2664 break;
2665 }
2666
2667 return ret;
2668}
2669
2670int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2671 struct ixgbe_fdir_filter *input,
2672 u16 sw_idx)
2673{
2674 struct ixgbe_hw *hw = &adapter->hw;
2675 struct hlist_node *node2;
2676 struct ixgbe_fdir_filter *rule, *parent;
2677 int err = -EINVAL;
2678
2679 parent = NULL;
2680 rule = NULL;
2681
2682 hlist_for_each_entry_safe(rule, node2,
2683 &adapter->fdir_filter_list, fdir_node) {
2684
2685 if (rule->sw_idx >= sw_idx)
2686 break;
2687 parent = rule;
2688 }
2689
2690
2691 if (rule && (rule->sw_idx == sw_idx)) {
2692 if (!input || (rule->filter.formatted.bkt_hash !=
2693 input->filter.formatted.bkt_hash)) {
2694 err = ixgbe_fdir_erase_perfect_filter_82599(hw,
2695 &rule->filter,
2696 sw_idx);
2697 }
2698
2699 hlist_del(&rule->fdir_node);
2700 kfree(rule);
2701 adapter->fdir_filter_count--;
2702 }
2703
2704
2705
2706
2707
2708 if (!input)
2709 return err;
2710
2711
2712 INIT_HLIST_NODE(&input->fdir_node);
2713
2714
2715 if (parent)
2716 hlist_add_behind(&input->fdir_node, &parent->fdir_node);
2717 else
2718 hlist_add_head(&input->fdir_node,
2719 &adapter->fdir_filter_list);
2720
2721
2722 adapter->fdir_filter_count++;
2723
2724 return 0;
2725}
2726
2727static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp,
2728 u8 *flow_type)
2729{
2730 switch (fsp->flow_type & ~FLOW_EXT) {
2731 case TCP_V4_FLOW:
2732 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2733 break;
2734 case UDP_V4_FLOW:
2735 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2736 break;
2737 case SCTP_V4_FLOW:
2738 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2739 break;
2740 case IP_USER_FLOW:
2741 switch (fsp->h_u.usr_ip4_spec.proto) {
2742 case IPPROTO_TCP:
2743 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2744 break;
2745 case IPPROTO_UDP:
2746 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2747 break;
2748 case IPPROTO_SCTP:
2749 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2750 break;
2751 case 0:
2752 if (!fsp->m_u.usr_ip4_spec.proto) {
2753 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
2754 break;
2755 }
2756
2757 default:
2758 return 0;
2759 }
2760 break;
2761 default:
2762 return 0;
2763 }
2764
2765 return 1;
2766}
2767
2768static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2769 struct ethtool_rxnfc *cmd)
2770{
2771 struct ethtool_rx_flow_spec *fsp =
2772 (struct ethtool_rx_flow_spec *)&cmd->fs;
2773 struct ixgbe_hw *hw = &adapter->hw;
2774 struct ixgbe_fdir_filter *input;
2775 union ixgbe_atr_input mask;
2776 u8 queue;
2777 int err;
2778
2779 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
2780 return -EOPNOTSUPP;
2781
2782
2783
2784
2785 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
2786 queue = IXGBE_FDIR_DROP_QUEUE;
2787 } else {
2788 u32 ring = ethtool_get_flow_spec_ring(fsp->ring_cookie);
2789 u8 vf = ethtool_get_flow_spec_ring_vf(fsp->ring_cookie);
2790
2791 if (!vf && (ring >= adapter->num_rx_queues))
2792 return -EINVAL;
2793 else if (vf &&
2794 ((vf > adapter->num_vfs) ||
2795 ring >= adapter->num_rx_queues_per_pool))
2796 return -EINVAL;
2797
2798
2799 if (!vf)
2800 queue = adapter->rx_ring[ring]->reg_idx;
2801 else
2802 queue = ((vf - 1) *
2803 adapter->num_rx_queues_per_pool) + ring;
2804 }
2805
2806
2807 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) {
2808 e_err(drv, "Location out of range\n");
2809 return -EINVAL;
2810 }
2811
2812 input = kzalloc(sizeof(*input), GFP_ATOMIC);
2813 if (!input)
2814 return -ENOMEM;
2815
2816 memset(&mask, 0, sizeof(union ixgbe_atr_input));
2817
2818
2819 input->sw_idx = fsp->location;
2820
2821
2822 if (!ixgbe_flowspec_to_flow_type(fsp,
2823 &input->filter.formatted.flow_type)) {
2824 e_err(drv, "Unrecognized flow type\n");
2825 goto err_out;
2826 }
2827
2828 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2829 IXGBE_ATR_L4TYPE_MASK;
2830
2831 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
2832 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
2833
2834
2835 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src;
2836 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src;
2837 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst;
2838 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst;
2839 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc;
2840 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc;
2841 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst;
2842 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst;
2843
2844 if (fsp->flow_type & FLOW_EXT) {
2845 input->filter.formatted.vm_pool =
2846 (unsigned char)ntohl(fsp->h_ext.data[1]);
2847 mask.formatted.vm_pool =
2848 (unsigned char)ntohl(fsp->m_ext.data[1]);
2849 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci;
2850 mask.formatted.vlan_id = fsp->m_ext.vlan_tci;
2851 input->filter.formatted.flex_bytes =
2852 fsp->h_ext.vlan_etype;
2853 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype;
2854 }
2855
2856
2857 if (fsp->ring_cookie == RX_CLS_FLOW_DISC)
2858 input->action = IXGBE_FDIR_DROP_QUEUE;
2859 else
2860 input->action = fsp->ring_cookie;
2861
2862 spin_lock(&adapter->fdir_perfect_lock);
2863
2864 if (hlist_empty(&adapter->fdir_filter_list)) {
2865
2866 memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
2867 err = ixgbe_fdir_set_input_mask_82599(hw, &mask);
2868 if (err) {
2869 e_err(drv, "Error writing mask\n");
2870 goto err_out_w_lock;
2871 }
2872 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {
2873 e_err(drv, "Only one mask supported per port\n");
2874 goto err_out_w_lock;
2875 }
2876
2877
2878 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);
2879
2880
2881 err = ixgbe_fdir_write_perfect_filter_82599(hw,
2882 &input->filter, input->sw_idx, queue);
2883 if (err)
2884 goto err_out_w_lock;
2885
2886 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
2887
2888 spin_unlock(&adapter->fdir_perfect_lock);
2889
2890 return err;
2891err_out_w_lock:
2892 spin_unlock(&adapter->fdir_perfect_lock);
2893err_out:
2894 kfree(input);
2895 return -EINVAL;
2896}
2897
2898static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2899 struct ethtool_rxnfc *cmd)
2900{
2901 struct ethtool_rx_flow_spec *fsp =
2902 (struct ethtool_rx_flow_spec *)&cmd->fs;
2903 int err;
2904
2905 spin_lock(&adapter->fdir_perfect_lock);
2906 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location);
2907 spin_unlock(&adapter->fdir_perfect_lock);
2908
2909 return err;
2910}
2911
2912#define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \
2913 IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2914static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter,
2915 struct ethtool_rxnfc *nfc)
2916{
2917 u32 flags2 = adapter->flags2;
2918
2919
2920
2921
2922
2923 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2924 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2925 return -EINVAL;
2926
2927 switch (nfc->flow_type) {
2928 case TCP_V4_FLOW:
2929 case TCP_V6_FLOW:
2930 if (!(nfc->data & RXH_IP_SRC) ||
2931 !(nfc->data & RXH_IP_DST) ||
2932 !(nfc->data & RXH_L4_B_0_1) ||
2933 !(nfc->data & RXH_L4_B_2_3))
2934 return -EINVAL;
2935 break;
2936 case UDP_V4_FLOW:
2937 if (!(nfc->data & RXH_IP_SRC) ||
2938 !(nfc->data & RXH_IP_DST))
2939 return -EINVAL;
2940 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2941 case 0:
2942 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2943 break;
2944 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2945 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2946 break;
2947 default:
2948 return -EINVAL;
2949 }
2950 break;
2951 case UDP_V6_FLOW:
2952 if (!(nfc->data & RXH_IP_SRC) ||
2953 !(nfc->data & RXH_IP_DST))
2954 return -EINVAL;
2955 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2956 case 0:
2957 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2958 break;
2959 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2960 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2961 break;
2962 default:
2963 return -EINVAL;
2964 }
2965 break;
2966 case AH_ESP_V4_FLOW:
2967 case AH_V4_FLOW:
2968 case ESP_V4_FLOW:
2969 case SCTP_V4_FLOW:
2970 case AH_ESP_V6_FLOW:
2971 case AH_V6_FLOW:
2972 case ESP_V6_FLOW:
2973 case SCTP_V6_FLOW:
2974 if (!(nfc->data & RXH_IP_SRC) ||
2975 !(nfc->data & RXH_IP_DST) ||
2976 (nfc->data & RXH_L4_B_0_1) ||
2977 (nfc->data & RXH_L4_B_2_3))
2978 return -EINVAL;
2979 break;
2980 default:
2981 return -EINVAL;
2982 }
2983
2984
2985 if (flags2 != adapter->flags2) {
2986 struct ixgbe_hw *hw = &adapter->hw;
2987 u32 mrqc;
2988 unsigned int pf_pool = adapter->num_vfs;
2989
2990 if ((hw->mac.type >= ixgbe_mac_X550) &&
2991 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2992 mrqc = IXGBE_READ_REG(hw, IXGBE_PFVFMRQC(pf_pool));
2993 else
2994 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2995
2996 if ((flags2 & UDP_RSS_FLAGS) &&
2997 !(adapter->flags2 & UDP_RSS_FLAGS))
2998 e_warn(drv, "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n");
2999
3000 adapter->flags2 = flags2;
3001
3002
3003 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
3004 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
3005 | IXGBE_MRQC_RSS_FIELD_IPV6
3006 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3007
3008 mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP |
3009 IXGBE_MRQC_RSS_FIELD_IPV6_UDP);
3010
3011 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3012 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3013
3014 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3015 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3016
3017 if ((hw->mac.type >= ixgbe_mac_X550) &&
3018 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3019 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), mrqc);
3020 else
3021 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3022 }
3023
3024 return 0;
3025}
3026
3027static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
3028{
3029 struct ixgbe_adapter *adapter = netdev_priv(dev);
3030 int ret = -EOPNOTSUPP;
3031
3032 switch (cmd->cmd) {
3033 case ETHTOOL_SRXCLSRLINS:
3034 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd);
3035 break;
3036 case ETHTOOL_SRXCLSRLDEL:
3037 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd);
3038 break;
3039 case ETHTOOL_SRXFH:
3040 ret = ixgbe_set_rss_hash_opt(adapter, cmd);
3041 break;
3042 default:
3043 break;
3044 }
3045
3046 return ret;
3047}
3048
3049static int ixgbe_rss_indir_tbl_max(struct ixgbe_adapter *adapter)
3050{
3051 if (adapter->hw.mac.type < ixgbe_mac_X550)
3052 return 16;
3053 else
3054 return 64;
3055}
3056
3057static u32 ixgbe_get_rxfh_key_size(struct net_device *netdev)
3058{
3059 return IXGBE_RSS_KEY_SIZE;
3060}
3061
3062static u32 ixgbe_rss_indir_size(struct net_device *netdev)
3063{
3064 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3065
3066 return ixgbe_rss_indir_tbl_entries(adapter);
3067}
3068
3069static void ixgbe_get_reta(struct ixgbe_adapter *adapter, u32 *indir)
3070{
3071 int i, reta_size = ixgbe_rss_indir_tbl_entries(adapter);
3072 u16 rss_m = adapter->ring_feature[RING_F_RSS].mask;
3073
3074 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3075 rss_m = adapter->ring_feature[RING_F_RSS].indices - 1;
3076
3077 for (i = 0; i < reta_size; i++)
3078 indir[i] = adapter->rss_indir_tbl[i] & rss_m;
3079}
3080
3081static int ixgbe_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
3082 u8 *hfunc)
3083{
3084 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3085
3086 if (hfunc)
3087 *hfunc = ETH_RSS_HASH_TOP;
3088
3089 if (indir)
3090 ixgbe_get_reta(adapter, indir);
3091
3092 if (key)
3093 memcpy(key, adapter->rss_key, ixgbe_get_rxfh_key_size(netdev));
3094
3095 return 0;
3096}
3097
3098static int ixgbe_set_rxfh(struct net_device *netdev, const u32 *indir,
3099 const u8 *key, const u8 hfunc)
3100{
3101 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3102 int i;
3103 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3104
3105 if (hfunc)
3106 return -EINVAL;
3107
3108
3109 if (indir) {
3110 int max_queues = min_t(int, adapter->num_rx_queues,
3111 ixgbe_rss_indir_tbl_max(adapter));
3112
3113
3114 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3115 (max_queues < 2))
3116 max_queues = 2;
3117
3118
3119 for (i = 0; i < reta_entries; i++)
3120 if (indir[i] >= max_queues)
3121 return -EINVAL;
3122
3123 for (i = 0; i < reta_entries; i++)
3124 adapter->rss_indir_tbl[i] = indir[i];
3125
3126 ixgbe_store_reta(adapter);
3127 }
3128
3129
3130 if (key) {
3131 memcpy(adapter->rss_key, key, ixgbe_get_rxfh_key_size(netdev));
3132 ixgbe_store_key(adapter);
3133 }
3134
3135 return 0;
3136}
3137
3138static int ixgbe_get_ts_info(struct net_device *dev,
3139 struct ethtool_ts_info *info)
3140{
3141 struct ixgbe_adapter *adapter = netdev_priv(dev);
3142
3143
3144 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE);
3145
3146 switch (adapter->hw.mac.type) {
3147 case ixgbe_mac_X550:
3148 case ixgbe_mac_X550EM_x:
3149 case ixgbe_mac_x550em_a:
3150 info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL);
3151 break;
3152 case ixgbe_mac_X540:
3153 case ixgbe_mac_82599EB:
3154 info->rx_filters |=
3155 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
3156 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
3157 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT);
3158 break;
3159 default:
3160 return ethtool_op_get_ts_info(dev, info);
3161 }
3162
3163 info->so_timestamping =
3164 SOF_TIMESTAMPING_TX_SOFTWARE |
3165 SOF_TIMESTAMPING_RX_SOFTWARE |
3166 SOF_TIMESTAMPING_SOFTWARE |
3167 SOF_TIMESTAMPING_TX_HARDWARE |
3168 SOF_TIMESTAMPING_RX_HARDWARE |
3169 SOF_TIMESTAMPING_RAW_HARDWARE;
3170
3171 if (adapter->ptp_clock)
3172 info->phc_index = ptp_clock_index(adapter->ptp_clock);
3173 else
3174 info->phc_index = -1;
3175
3176 info->tx_types =
3177 BIT(HWTSTAMP_TX_OFF) |
3178 BIT(HWTSTAMP_TX_ON);
3179
3180 return 0;
3181}
3182
3183static unsigned int ixgbe_max_channels(struct ixgbe_adapter *adapter)
3184{
3185 unsigned int max_combined;
3186 u8 tcs = adapter->hw_tcs;
3187
3188 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
3189
3190 max_combined = 1;
3191 } else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3192
3193 max_combined = adapter->ring_feature[RING_F_RSS].mask + 1;
3194 } else if (tcs > 1) {
3195
3196 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3197
3198 max_combined = 4;
3199 } else if (tcs > 4) {
3200
3201 max_combined = 8;
3202 } else {
3203
3204 max_combined = 16;
3205 }
3206 } else if (adapter->atr_sample_rate) {
3207
3208 max_combined = IXGBE_MAX_FDIR_INDICES;
3209 } else {
3210
3211 max_combined = ixgbe_max_rss_indices(adapter);
3212 }
3213
3214 return max_combined;
3215}
3216
3217static void ixgbe_get_channels(struct net_device *dev,
3218 struct ethtool_channels *ch)
3219{
3220 struct ixgbe_adapter *adapter = netdev_priv(dev);
3221
3222
3223 ch->max_combined = ixgbe_max_channels(adapter);
3224
3225
3226 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3227 ch->max_other = NON_Q_VECTORS;
3228 ch->other_count = NON_Q_VECTORS;
3229 }
3230
3231
3232 ch->combined_count = adapter->ring_feature[RING_F_RSS].indices;
3233
3234
3235 if (ch->combined_count == 1)
3236 return;
3237
3238
3239 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3240 return;
3241
3242
3243 if (adapter->hw_tcs > 1)
3244 return;
3245
3246
3247 if (!adapter->atr_sample_rate)
3248 return;
3249
3250
3251 ch->combined_count = adapter->ring_feature[RING_F_FDIR].indices;
3252}
3253
3254static int ixgbe_set_channels(struct net_device *dev,
3255 struct ethtool_channels *ch)
3256{
3257 struct ixgbe_adapter *adapter = netdev_priv(dev);
3258 unsigned int count = ch->combined_count;
3259 u8 max_rss_indices = ixgbe_max_rss_indices(adapter);
3260
3261
3262 if (!count || ch->rx_count || ch->tx_count)
3263 return -EINVAL;
3264
3265
3266 if (ch->other_count != NON_Q_VECTORS)
3267 return -EINVAL;
3268
3269
3270 if (count > ixgbe_max_channels(adapter))
3271 return -EINVAL;
3272
3273
3274 adapter->ring_feature[RING_F_FDIR].limit = count;
3275
3276
3277 if (count > max_rss_indices)
3278 count = max_rss_indices;
3279 adapter->ring_feature[RING_F_RSS].limit = count;
3280
3281#ifdef IXGBE_FCOE
3282
3283 if (count > IXGBE_FCRETA_SIZE)
3284 count = IXGBE_FCRETA_SIZE;
3285 adapter->ring_feature[RING_F_FCOE].limit = count;
3286
3287#endif
3288
3289 return ixgbe_setup_tc(dev, adapter->hw_tcs);
3290}
3291
3292static int ixgbe_get_module_info(struct net_device *dev,
3293 struct ethtool_modinfo *modinfo)
3294{
3295 struct ixgbe_adapter *adapter = netdev_priv(dev);
3296 struct ixgbe_hw *hw = &adapter->hw;
3297 s32 status;
3298 u8 sff8472_rev, addr_mode;
3299 bool page_swap = false;
3300
3301 if (hw->phy.type == ixgbe_phy_fw)
3302 return -ENXIO;
3303
3304
3305 status = hw->phy.ops.read_i2c_eeprom(hw,
3306 IXGBE_SFF_SFF_8472_COMP,
3307 &sff8472_rev);
3308 if (status)
3309 return -EIO;
3310
3311
3312 status = hw->phy.ops.read_i2c_eeprom(hw,
3313 IXGBE_SFF_SFF_8472_SWAP,
3314 &addr_mode);
3315 if (status)
3316 return -EIO;
3317
3318 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
3319 e_err(drv, "Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
3320 page_swap = true;
3321 }
3322
3323 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap ||
3324 !(addr_mode & IXGBE_SFF_DDM_IMPLEMENTED)) {
3325
3326 modinfo->type = ETH_MODULE_SFF_8079;
3327 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
3328 } else {
3329
3330 modinfo->type = ETH_MODULE_SFF_8472;
3331 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
3332 }
3333
3334 return 0;
3335}
3336
3337static int ixgbe_get_module_eeprom(struct net_device *dev,
3338 struct ethtool_eeprom *ee,
3339 u8 *data)
3340{
3341 struct ixgbe_adapter *adapter = netdev_priv(dev);
3342 struct ixgbe_hw *hw = &adapter->hw;
3343 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
3344 u8 databyte = 0xFF;
3345 int i = 0;
3346
3347 if (ee->len == 0)
3348 return -EINVAL;
3349
3350 if (hw->phy.type == ixgbe_phy_fw)
3351 return -ENXIO;
3352
3353 for (i = ee->offset; i < ee->offset + ee->len; i++) {
3354
3355 if (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3356 return -EBUSY;
3357
3358 if (i < ETH_MODULE_SFF_8079_LEN)
3359 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
3360 else
3361 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
3362
3363 if (status)
3364 return -EIO;
3365
3366 data[i - ee->offset] = databyte;
3367 }
3368
3369 return 0;
3370}
3371
3372static const struct {
3373 ixgbe_link_speed mac_speed;
3374 u32 supported;
3375} ixgbe_ls_map[] = {
3376 { IXGBE_LINK_SPEED_10_FULL, SUPPORTED_10baseT_Full },
3377 { IXGBE_LINK_SPEED_100_FULL, SUPPORTED_100baseT_Full },
3378 { IXGBE_LINK_SPEED_1GB_FULL, SUPPORTED_1000baseT_Full },
3379 { IXGBE_LINK_SPEED_2_5GB_FULL, SUPPORTED_2500baseX_Full },
3380 { IXGBE_LINK_SPEED_10GB_FULL, SUPPORTED_10000baseT_Full },
3381};
3382
3383static const struct {
3384 u32 lp_advertised;
3385 u32 mac_speed;
3386} ixgbe_lp_map[] = {
3387 { FW_PHY_ACT_UD_2_100M_TX_EEE, SUPPORTED_100baseT_Full },
3388 { FW_PHY_ACT_UD_2_1G_T_EEE, SUPPORTED_1000baseT_Full },
3389 { FW_PHY_ACT_UD_2_10G_T_EEE, SUPPORTED_10000baseT_Full },
3390 { FW_PHY_ACT_UD_2_1G_KX_EEE, SUPPORTED_1000baseKX_Full },
3391 { FW_PHY_ACT_UD_2_10G_KX4_EEE, SUPPORTED_10000baseKX4_Full },
3392 { FW_PHY_ACT_UD_2_10G_KR_EEE, SUPPORTED_10000baseKR_Full},
3393};
3394
3395static int
3396ixgbe_get_eee_fw(struct ixgbe_adapter *adapter, struct ethtool_eee *edata)
3397{
3398 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
3399 struct ixgbe_hw *hw = &adapter->hw;
3400 s32 rc;
3401 u16 i;
3402
3403 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_UD_2, &info);
3404 if (rc)
3405 return rc;
3406
3407 edata->lp_advertised = 0;
3408 for (i = 0; i < ARRAY_SIZE(ixgbe_lp_map); ++i) {
3409 if (info[0] & ixgbe_lp_map[i].lp_advertised)
3410 edata->lp_advertised |= ixgbe_lp_map[i].mac_speed;
3411 }
3412
3413 edata->supported = 0;
3414 for (i = 0; i < ARRAY_SIZE(ixgbe_ls_map); ++i) {
3415 if (hw->phy.eee_speeds_supported & ixgbe_ls_map[i].mac_speed)
3416 edata->supported |= ixgbe_ls_map[i].supported;
3417 }
3418
3419 edata->advertised = 0;
3420 for (i = 0; i < ARRAY_SIZE(ixgbe_ls_map); ++i) {
3421 if (hw->phy.eee_speeds_advertised & ixgbe_ls_map[i].mac_speed)
3422 edata->advertised |= ixgbe_ls_map[i].supported;
3423 }
3424
3425 edata->eee_enabled = !!edata->advertised;
3426 edata->tx_lpi_enabled = edata->eee_enabled;
3427 if (edata->advertised & edata->lp_advertised)
3428 edata->eee_active = true;
3429
3430 return 0;
3431}
3432
3433static int ixgbe_get_eee(struct net_device *netdev, struct ethtool_eee *edata)
3434{
3435 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3436 struct ixgbe_hw *hw = &adapter->hw;
3437
3438 if (!(adapter->flags2 & IXGBE_FLAG2_EEE_CAPABLE))
3439 return -EOPNOTSUPP;
3440
3441 if (hw->phy.eee_speeds_supported && hw->phy.type == ixgbe_phy_fw)
3442 return ixgbe_get_eee_fw(adapter, edata);
3443
3444 return -EOPNOTSUPP;
3445}
3446
3447static int ixgbe_set_eee(struct net_device *netdev, struct ethtool_eee *edata)
3448{
3449 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3450 struct ixgbe_hw *hw = &adapter->hw;
3451 struct ethtool_eee eee_data;
3452 s32 ret_val;
3453
3454 if (!(adapter->flags2 & IXGBE_FLAG2_EEE_CAPABLE))
3455 return -EOPNOTSUPP;
3456
3457 memset(&eee_data, 0, sizeof(struct ethtool_eee));
3458
3459 ret_val = ixgbe_get_eee(netdev, &eee_data);
3460 if (ret_val)
3461 return ret_val;
3462
3463 if (eee_data.eee_enabled && !edata->eee_enabled) {
3464 if (eee_data.tx_lpi_enabled != edata->tx_lpi_enabled) {
3465 e_err(drv, "Setting EEE tx-lpi is not supported\n");
3466 return -EINVAL;
3467 }
3468
3469 if (eee_data.tx_lpi_timer != edata->tx_lpi_timer) {
3470 e_err(drv,
3471 "Setting EEE Tx LPI timer is not supported\n");
3472 return -EINVAL;
3473 }
3474
3475 if (eee_data.advertised != edata->advertised) {
3476 e_err(drv,
3477 "Setting EEE advertised speeds is not supported\n");
3478 return -EINVAL;
3479 }
3480 }
3481
3482 if (eee_data.eee_enabled != edata->eee_enabled) {
3483 if (edata->eee_enabled) {
3484 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED;
3485 hw->phy.eee_speeds_advertised =
3486 hw->phy.eee_speeds_supported;
3487 } else {
3488 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED;
3489 hw->phy.eee_speeds_advertised = 0;
3490 }
3491
3492
3493 if (netif_running(netdev))
3494 ixgbe_reinit_locked(adapter);
3495 else
3496 ixgbe_reset(adapter);
3497 }
3498
3499 return 0;
3500}
3501
3502static u32 ixgbe_get_priv_flags(struct net_device *netdev)
3503{
3504 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3505 u32 priv_flags = 0;
3506
3507 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY)
3508 priv_flags |= IXGBE_PRIV_FLAGS_LEGACY_RX;
3509
3510 if (adapter->flags2 & IXGBE_FLAG2_VF_IPSEC_ENABLED)
3511 priv_flags |= IXGBE_PRIV_FLAGS_VF_IPSEC_EN;
3512
3513 return priv_flags;
3514}
3515
3516static int ixgbe_set_priv_flags(struct net_device *netdev, u32 priv_flags)
3517{
3518 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3519 unsigned int flags2 = adapter->flags2;
3520
3521 flags2 &= ~IXGBE_FLAG2_RX_LEGACY;
3522 if (priv_flags & IXGBE_PRIV_FLAGS_LEGACY_RX)
3523 flags2 |= IXGBE_FLAG2_RX_LEGACY;
3524
3525 flags2 &= ~IXGBE_FLAG2_VF_IPSEC_ENABLED;
3526 if (priv_flags & IXGBE_PRIV_FLAGS_VF_IPSEC_EN)
3527 flags2 |= IXGBE_FLAG2_VF_IPSEC_ENABLED;
3528
3529 if (flags2 != adapter->flags2) {
3530 adapter->flags2 = flags2;
3531
3532
3533 if (netif_running(netdev))
3534 ixgbe_reinit_locked(adapter);
3535 }
3536
3537 return 0;
3538}
3539
3540static const struct ethtool_ops ixgbe_ethtool_ops = {
3541 .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
3542 .get_drvinfo = ixgbe_get_drvinfo,
3543 .get_regs_len = ixgbe_get_regs_len,
3544 .get_regs = ixgbe_get_regs,
3545 .get_wol = ixgbe_get_wol,
3546 .set_wol = ixgbe_set_wol,
3547 .nway_reset = ixgbe_nway_reset,
3548 .get_link = ethtool_op_get_link,
3549 .get_eeprom_len = ixgbe_get_eeprom_len,
3550 .get_eeprom = ixgbe_get_eeprom,
3551 .set_eeprom = ixgbe_set_eeprom,
3552 .get_ringparam = ixgbe_get_ringparam,
3553 .set_ringparam = ixgbe_set_ringparam,
3554 .get_pauseparam = ixgbe_get_pauseparam,
3555 .set_pauseparam = ixgbe_set_pauseparam,
3556 .get_msglevel = ixgbe_get_msglevel,
3557 .set_msglevel = ixgbe_set_msglevel,
3558 .self_test = ixgbe_diag_test,
3559 .get_strings = ixgbe_get_strings,
3560 .set_phys_id = ixgbe_set_phys_id,
3561 .get_sset_count = ixgbe_get_sset_count,
3562 .get_ethtool_stats = ixgbe_get_ethtool_stats,
3563 .get_coalesce = ixgbe_get_coalesce,
3564 .set_coalesce = ixgbe_set_coalesce,
3565 .get_rxnfc = ixgbe_get_rxnfc,
3566 .set_rxnfc = ixgbe_set_rxnfc,
3567 .get_rxfh_indir_size = ixgbe_rss_indir_size,
3568 .get_rxfh_key_size = ixgbe_get_rxfh_key_size,
3569 .get_rxfh = ixgbe_get_rxfh,
3570 .set_rxfh = ixgbe_set_rxfh,
3571 .get_eee = ixgbe_get_eee,
3572 .set_eee = ixgbe_set_eee,
3573 .get_channels = ixgbe_get_channels,
3574 .set_channels = ixgbe_set_channels,
3575 .get_priv_flags = ixgbe_get_priv_flags,
3576 .set_priv_flags = ixgbe_set_priv_flags,
3577 .get_ts_info = ixgbe_get_ts_info,
3578 .get_module_info = ixgbe_get_module_info,
3579 .get_module_eeprom = ixgbe_get_module_eeprom,
3580 .get_link_ksettings = ixgbe_get_link_ksettings,
3581 .set_link_ksettings = ixgbe_set_link_ksettings,
3582};
3583
3584void ixgbe_set_ethtool_ops(struct net_device *netdev)
3585{
3586 netdev->ethtool_ops = &ixgbe_ethtool_ops;
3587}
3588
