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7#ifndef __MT76x02_H
8#define __MT76x02_H
9
10#include <linux/kfifo.h>
11
12#include "mt76.h"
13#include "mt76x02_regs.h"
14#include "mt76x02_mac.h"
15#include "mt76x02_dfs.h"
16#include "mt76x02_dma.h"
17
18#define MT_CALIBRATE_INTERVAL HZ
19#define MT_MAC_WORK_INTERVAL (HZ / 10)
20
21#define MT_WATCHDOG_TIME (HZ / 10)
22#define MT_TX_HANG_TH 10
23
24#define MT_MAX_CHAINS 2
25struct mt76x02_rx_freq_cal {
26 s8 high_gain[MT_MAX_CHAINS];
27 s8 rssi_offset[MT_MAX_CHAINS];
28 s8 lna_gain;
29 u32 mcu_gain;
30 s16 temp_offset;
31 u8 freq_offset;
32};
33
34struct mt76x02_calibration {
35 struct mt76x02_rx_freq_cal rx;
36
37 u8 agc_gain_init[MT_MAX_CHAINS];
38 u8 agc_gain_cur[MT_MAX_CHAINS];
39
40 u16 false_cca;
41 s8 avg_rssi_all;
42 s8 agc_gain_adjust;
43 s8 agc_lowest_gain;
44 s8 low_gain;
45
46 s8 temp_vco;
47 s8 temp;
48
49 bool init_cal_done;
50 bool tssi_cal_done;
51 bool tssi_comp_pending;
52 bool dpd_cal_done;
53 bool channel_cal_done;
54 bool gain_init_done;
55
56 int tssi_target;
57 s8 tssi_dc;
58};
59
60struct mt76x02_beacon_ops {
61 unsigned int nslots;
62 unsigned int slot_size;
63 void (*pre_tbtt_enable)(struct mt76x02_dev *dev, bool en);
64 void (*beacon_enable)(struct mt76x02_dev *dev, bool en);
65};
66
67#define mt76x02_beacon_enable(dev, enable) \
68 (dev)->beacon_ops->beacon_enable(dev, enable)
69#define mt76x02_pre_tbtt_enable(dev, enable) \
70 (dev)->beacon_ops->pre_tbtt_enable(dev, enable)
71
72struct mt76x02_dev {
73 struct mt76_dev mt76;
74
75 struct mac_address macaddr_list[8];
76
77 struct mutex phy_mutex;
78
79 u16 vif_mask;
80
81 u8 txdone_seq;
82 DECLARE_KFIFO_PTR(txstatus_fifo, struct mt76x02_tx_status);
83 spinlock_t txstatus_fifo_lock;
84 u32 tx_airtime;
85
86 struct sk_buff *rx_head;
87
88 struct delayed_work cal_work;
89 struct delayed_work wdt_work;
90
91 struct hrtimer pre_tbtt_timer;
92 struct work_struct pre_tbtt_work;
93
94 const struct mt76x02_beacon_ops *beacon_ops;
95
96 struct sk_buff *beacons[8];
97 u8 beacon_data_mask;
98
99 u8 tbtt_count;
100
101 u32 tx_hang_reset;
102 u8 tx_hang_check;
103 u8 mcu_timeout;
104
105 struct mt76x02_calibration cal;
106
107 s8 target_power;
108 s8 target_power_delta[2];
109 bool enable_tpc;
110
111 bool no_2ghz;
112
113 s16 coverage_class;
114 u8 slottime;
115
116 struct mt76x02_dfs_pattern_detector dfs_pd;
117
118
119 unsigned long ed_trigger_timeout;
120 bool ed_tx_blocked;
121 bool ed_monitor;
122 u8 ed_monitor_enabled;
123 u8 ed_monitor_learning;
124 u8 ed_trigger;
125 u8 ed_silent;
126 ktime_t ed_time;
127};
128
129extern struct ieee80211_rate mt76x02_rates[12];
130
131void mt76x02_init_device(struct mt76x02_dev *dev);
132void mt76x02_configure_filter(struct ieee80211_hw *hw,
133 unsigned int changed_flags,
134 unsigned int *total_flags, u64 multicast);
135int mt76x02_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
136 struct ieee80211_sta *sta);
137void mt76x02_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif,
138 struct ieee80211_sta *sta);
139
140void mt76x02_config_mac_addr_list(struct mt76x02_dev *dev);
141
142int mt76x02_add_interface(struct ieee80211_hw *hw,
143 struct ieee80211_vif *vif);
144void mt76x02_remove_interface(struct ieee80211_hw *hw,
145 struct ieee80211_vif *vif);
146
147int mt76x02_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
148 struct ieee80211_ampdu_params *params);
149int mt76x02_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
150 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
151 struct ieee80211_key_conf *key);
152int mt76x02_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
153 u16 queue, const struct ieee80211_tx_queue_params *params);
154void mt76x02_sta_rate_tbl_update(struct ieee80211_hw *hw,
155 struct ieee80211_vif *vif,
156 struct ieee80211_sta *sta);
157s8 mt76x02_tx_get_max_txpwr_adj(struct mt76x02_dev *dev,
158 const struct ieee80211_tx_rate *rate);
159s8 mt76x02_tx_get_txpwr_adj(struct mt76x02_dev *dev, s8 txpwr,
160 s8 max_txpwr_adj);
161void mt76x02_wdt_work(struct work_struct *work);
162void mt76x02_tx_set_txpwr_auto(struct mt76x02_dev *dev, s8 txpwr);
163void mt76x02_set_tx_ackto(struct mt76x02_dev *dev);
164void mt76x02_set_coverage_class(struct ieee80211_hw *hw,
165 s16 coverage_class);
166int mt76x02_set_rts_threshold(struct ieee80211_hw *hw, u32 val);
167void mt76x02_remove_hdr_pad(struct sk_buff *skb, int len);
168bool mt76x02_tx_status_data(struct mt76_dev *mdev, u8 *update);
169void mt76x02_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
170 struct sk_buff *skb);
171void mt76x02_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
172irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance);
173void mt76x02_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
174 struct sk_buff *skb);
175int mt76x02_tx_prepare_skb(struct mt76_dev *mdev, void *txwi,
176 enum mt76_txq_id qid, struct mt76_wcid *wcid,
177 struct ieee80211_sta *sta,
178 struct mt76_tx_info *tx_info);
179void mt76x02_sw_scan_complete(struct ieee80211_hw *hw,
180 struct ieee80211_vif *vif);
181void mt76x02_sta_ps(struct mt76_dev *dev, struct ieee80211_sta *sta, bool ps);
182void mt76x02_bss_info_changed(struct ieee80211_hw *hw,
183 struct ieee80211_vif *vif,
184 struct ieee80211_bss_conf *info, u32 changed);
185
186struct beacon_bc_data {
187 struct mt76x02_dev *dev;
188 struct sk_buff_head q;
189 struct sk_buff *tail[8];
190};
191
192void mt76x02_init_beacon_config(struct mt76x02_dev *dev);
193void mt76x02e_init_beacon_config(struct mt76x02_dev *dev);
194void mt76x02_resync_beacon_timer(struct mt76x02_dev *dev);
195void mt76x02_update_beacon_iter(void *priv, u8 *mac, struct ieee80211_vif *vif);
196void mt76x02_enqueue_buffered_bc(struct mt76x02_dev *dev,
197 struct beacon_bc_data *data,
198 int max_nframes);
199
200void mt76x02_mac_start(struct mt76x02_dev *dev);
201
202void mt76x02_init_debugfs(struct mt76x02_dev *dev);
203
204static inline bool is_mt76x0(struct mt76x02_dev *dev)
205{
206 return mt76_chip(&dev->mt76) == 0x7610 ||
207 mt76_chip(&dev->mt76) == 0x7630 ||
208 mt76_chip(&dev->mt76) == 0x7650;
209}
210
211static inline bool is_mt76x2(struct mt76x02_dev *dev)
212{
213 return mt76_chip(&dev->mt76) == 0x7612 ||
214 mt76_chip(&dev->mt76) == 0x7662 ||
215 mt76_chip(&dev->mt76) == 0x7602;
216}
217
218static inline void mt76x02_irq_enable(struct mt76x02_dev *dev, u32 mask)
219{
220 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, 0, mask);
221}
222
223static inline void mt76x02_irq_disable(struct mt76x02_dev *dev, u32 mask)
224{
225 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);
226}
227
228static inline bool
229mt76x02_wait_for_txrx_idle(struct mt76_dev *dev)
230{
231 return __mt76_poll_msec(dev, MT_MAC_STATUS,
232 MT_MAC_STATUS_TX | MT_MAC_STATUS_RX,
233 0, 100);
234}
235
236static inline struct mt76x02_sta *
237mt76x02_rx_get_sta(struct mt76_dev *dev, u8 idx)
238{
239 struct mt76_wcid *wcid;
240
241 if (idx >= ARRAY_SIZE(dev->wcid))
242 return NULL;
243
244 wcid = rcu_dereference(dev->wcid[idx]);
245 if (!wcid)
246 return NULL;
247
248 return container_of(wcid, struct mt76x02_sta, wcid);
249}
250
251static inline struct mt76_wcid *
252mt76x02_rx_get_sta_wcid(struct mt76x02_sta *sta, bool unicast)
253{
254 if (!sta)
255 return NULL;
256
257 if (unicast)
258 return &sta->wcid;
259 else
260 return &sta->vif->group_wcid;
261}
262
263#endif
264