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10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/io.h>
13#include <linux/clk.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/delay.h>
17#include <linux/dma-mapping.h>
18#include <linux/err.h>
19#include <linux/interrupt.h>
20#include <linux/spi/spi.h>
21#include <linux/mutex.h>
22#include <linux/of.h>
23
24#define HSSPI_GLOBAL_CTRL_REG 0x0
25#define GLOBAL_CTRL_CS_POLARITY_SHIFT 0
26#define GLOBAL_CTRL_CS_POLARITY_MASK 0x000000ff
27#define GLOBAL_CTRL_PLL_CLK_CTRL_SHIFT 8
28#define GLOBAL_CTRL_PLL_CLK_CTRL_MASK 0x0000ff00
29#define GLOBAL_CTRL_CLK_GATE_SSOFF BIT(16)
30#define GLOBAL_CTRL_CLK_POLARITY BIT(17)
31#define GLOBAL_CTRL_MOSI_IDLE BIT(18)
32
33#define HSSPI_GLOBAL_EXT_TRIGGER_REG 0x4
34
35#define HSSPI_INT_STATUS_REG 0x8
36#define HSSPI_INT_STATUS_MASKED_REG 0xc
37#define HSSPI_INT_MASK_REG 0x10
38
39#define HSSPI_PINGx_CMD_DONE(i) BIT((i * 8) + 0)
40#define HSSPI_PINGx_RX_OVER(i) BIT((i * 8) + 1)
41#define HSSPI_PINGx_TX_UNDER(i) BIT((i * 8) + 2)
42#define HSSPI_PINGx_POLL_TIMEOUT(i) BIT((i * 8) + 3)
43#define HSSPI_PINGx_CTRL_INVAL(i) BIT((i * 8) + 4)
44
45#define HSSPI_INT_CLEAR_ALL 0xff001f1f
46
47#define HSSPI_PINGPONG_COMMAND_REG(x) (0x80 + (x) * 0x40)
48#define PINGPONG_CMD_COMMAND_MASK 0xf
49#define PINGPONG_COMMAND_NOOP 0
50#define PINGPONG_COMMAND_START_NOW 1
51#define PINGPONG_COMMAND_START_TRIGGER 2
52#define PINGPONG_COMMAND_HALT 3
53#define PINGPONG_COMMAND_FLUSH 4
54#define PINGPONG_CMD_PROFILE_SHIFT 8
55#define PINGPONG_CMD_SS_SHIFT 12
56
57#define HSSPI_PINGPONG_STATUS_REG(x) (0x84 + (x) * 0x40)
58
59#define HSSPI_PROFILE_CLK_CTRL_REG(x) (0x100 + (x) * 0x20)
60#define CLK_CTRL_FREQ_CTRL_MASK 0x0000ffff
61#define CLK_CTRL_SPI_CLK_2X_SEL BIT(14)
62#define CLK_CTRL_ACCUM_RST_ON_LOOP BIT(15)
63
64#define HSSPI_PROFILE_SIGNAL_CTRL_REG(x) (0x104 + (x) * 0x20)
65#define SIGNAL_CTRL_LATCH_RISING BIT(12)
66#define SIGNAL_CTRL_LAUNCH_RISING BIT(13)
67#define SIGNAL_CTRL_ASYNC_INPUT_PATH BIT(16)
68
69#define HSSPI_PROFILE_MODE_CTRL_REG(x) (0x108 + (x) * 0x20)
70#define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT 8
71#define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT 12
72#define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT 16
73#define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT 18
74#define MODE_CTRL_MODE_3WIRE BIT(20)
75#define MODE_CTRL_PREPENDBYTE_CNT_SHIFT 24
76
77#define HSSPI_FIFO_REG(x) (0x200 + (x) * 0x200)
78
79
80#define HSSPI_OP_MULTIBIT BIT(11)
81#define HSSPI_OP_CODE_SHIFT 13
82#define HSSPI_OP_SLEEP (0 << HSSPI_OP_CODE_SHIFT)
83#define HSSPI_OP_READ_WRITE (1 << HSSPI_OP_CODE_SHIFT)
84#define HSSPI_OP_WRITE (2 << HSSPI_OP_CODE_SHIFT)
85#define HSSPI_OP_READ (3 << HSSPI_OP_CODE_SHIFT)
86#define HSSPI_OP_SETIRQ (4 << HSSPI_OP_CODE_SHIFT)
87
88#define HSSPI_BUFFER_LEN 512
89#define HSSPI_OPCODE_LEN 2
90
91#define HSSPI_MAX_PREPEND_LEN 15
92
93#define HSSPI_MAX_SYNC_CLOCK 30000000
94
95#define HSSPI_SPI_MAX_CS 8
96#define HSSPI_BUS_NUM 1
97
98struct bcm63xx_hsspi {
99 struct completion done;
100 struct mutex bus_mutex;
101
102 struct platform_device *pdev;
103 struct clk *clk;
104 void __iomem *regs;
105 u8 __iomem *fifo;
106
107 u32 speed_hz;
108 u8 cs_polarity;
109};
110
111static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned int cs,
112 bool active)
113{
114 u32 reg;
115
116 mutex_lock(&bs->bus_mutex);
117 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
118
119 reg &= ~BIT(cs);
120 if (active == !(bs->cs_polarity & BIT(cs)))
121 reg |= BIT(cs);
122
123 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
124 mutex_unlock(&bs->bus_mutex);
125}
126
127static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
128 struct spi_device *spi, int hz)
129{
130 unsigned int profile = spi->chip_select;
131 u32 reg;
132
133 reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
134 __raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg,
135 bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile));
136
137 reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
138 if (hz > HSSPI_MAX_SYNC_CLOCK)
139 reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH;
140 else
141 reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH;
142 __raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
143
144 mutex_lock(&bs->bus_mutex);
145
146 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
147 reg &= ~GLOBAL_CTRL_CLK_POLARITY;
148 if (spi->mode & SPI_CPOL)
149 reg |= GLOBAL_CTRL_CLK_POLARITY;
150 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
151 mutex_unlock(&bs->bus_mutex);
152}
153
154static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t)
155{
156 struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
157 unsigned int chip_select = spi->chip_select;
158 u16 opcode = 0;
159 int pending = t->len;
160 int step_size = HSSPI_BUFFER_LEN;
161 const u8 *tx = t->tx_buf;
162 u8 *rx = t->rx_buf;
163
164 bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz);
165 bcm63xx_hsspi_set_cs(bs, spi->chip_select, true);
166
167 if (tx && rx)
168 opcode = HSSPI_OP_READ_WRITE;
169 else if (tx)
170 opcode = HSSPI_OP_WRITE;
171 else if (rx)
172 opcode = HSSPI_OP_READ;
173
174 if (opcode != HSSPI_OP_READ)
175 step_size -= HSSPI_OPCODE_LEN;
176
177 if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) ||
178 (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL))
179 opcode |= HSSPI_OP_MULTIBIT;
180
181 __raw_writel(1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT |
182 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT | 0xff,
183 bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
184
185 while (pending > 0) {
186 int curr_step = min_t(int, step_size, pending);
187
188 reinit_completion(&bs->done);
189 if (tx) {
190 memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step);
191 tx += curr_step;
192 }
193
194 __raw_writew(opcode | curr_step, bs->fifo);
195
196
197 __raw_writel(HSSPI_PINGx_CMD_DONE(0),
198 bs->regs + HSSPI_INT_MASK_REG);
199
200
201 __raw_writel(!chip_select << PINGPONG_CMD_SS_SHIFT |
202 chip_select << PINGPONG_CMD_PROFILE_SHIFT |
203 PINGPONG_COMMAND_START_NOW,
204 bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));
205
206 if (wait_for_completion_timeout(&bs->done, HZ) == 0) {
207 dev_err(&bs->pdev->dev, "transfer timed out!\n");
208 return -ETIMEDOUT;
209 }
210
211 if (rx) {
212 memcpy_fromio(rx, bs->fifo, curr_step);
213 rx += curr_step;
214 }
215
216 pending -= curr_step;
217 }
218
219 return 0;
220}
221
222static int bcm63xx_hsspi_setup(struct spi_device *spi)
223{
224 struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
225 u32 reg;
226
227 reg = __raw_readl(bs->regs +
228 HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
229 reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
230 if (spi->mode & SPI_CPHA)
231 reg |= SIGNAL_CTRL_LAUNCH_RISING;
232 else
233 reg |= SIGNAL_CTRL_LATCH_RISING;
234 __raw_writel(reg, bs->regs +
235 HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
236
237 mutex_lock(&bs->bus_mutex);
238 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
239
240
241 if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) {
242 if (spi->mode & SPI_CS_HIGH)
243 reg |= BIT(spi->chip_select);
244 else
245 reg &= ~BIT(spi->chip_select);
246 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
247 }
248
249 if (spi->mode & SPI_CS_HIGH)
250 bs->cs_polarity |= BIT(spi->chip_select);
251 else
252 bs->cs_polarity &= ~BIT(spi->chip_select);
253
254 mutex_unlock(&bs->bus_mutex);
255
256 return 0;
257}
258
259static int bcm63xx_hsspi_transfer_one(struct spi_master *master,
260 struct spi_message *msg)
261{
262 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
263 struct spi_transfer *t;
264 struct spi_device *spi = msg->spi;
265 int status = -EINVAL;
266 int dummy_cs;
267 u32 reg;
268
269
270
271
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273
274
275
276
277
278
279
280
281
282
283 dummy_cs = !spi->chip_select;
284 bcm63xx_hsspi_set_cs(bs, dummy_cs, true);
285
286 list_for_each_entry(t, &msg->transfers, transfer_list) {
287 status = bcm63xx_hsspi_do_txrx(spi, t);
288 if (status)
289 break;
290
291 msg->actual_length += t->len;
292
293 if (t->delay_usecs)
294 udelay(t->delay_usecs);
295
296 if (t->cs_change)
297 bcm63xx_hsspi_set_cs(bs, spi->chip_select, false);
298 }
299
300 mutex_lock(&bs->bus_mutex);
301 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
302 reg &= ~GLOBAL_CTRL_CS_POLARITY_MASK;
303 reg |= bs->cs_polarity;
304 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
305 mutex_unlock(&bs->bus_mutex);
306
307 msg->status = status;
308 spi_finalize_current_message(master);
309
310 return 0;
311}
312
313static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id)
314{
315 struct bcm63xx_hsspi *bs = (struct bcm63xx_hsspi *)dev_id;
316
317 if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0)
318 return IRQ_NONE;
319
320 __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
321 __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
322
323 complete(&bs->done);
324
325 return IRQ_HANDLED;
326}
327
328static int bcm63xx_hsspi_probe(struct platform_device *pdev)
329{
330 struct spi_master *master;
331 struct bcm63xx_hsspi *bs;
332 struct resource *res_mem;
333 void __iomem *regs;
334 struct device *dev = &pdev->dev;
335 struct clk *clk;
336 int irq, ret;
337 u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS;
338
339 irq = platform_get_irq(pdev, 0);
340 if (irq < 0) {
341 dev_err(dev, "no irq: %d\n", irq);
342 return irq;
343 }
344
345 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
346 regs = devm_ioremap_resource(dev, res_mem);
347 if (IS_ERR(regs))
348 return PTR_ERR(regs);
349
350 clk = devm_clk_get(dev, "hsspi");
351
352 if (IS_ERR(clk))
353 return PTR_ERR(clk);
354
355 ret = clk_prepare_enable(clk);
356 if (ret)
357 return ret;
358
359 rate = clk_get_rate(clk);
360 if (!rate) {
361 struct clk *pll_clk = devm_clk_get(dev, "pll");
362
363 if (IS_ERR(pll_clk)) {
364 ret = PTR_ERR(pll_clk);
365 goto out_disable_clk;
366 }
367
368 ret = clk_prepare_enable(pll_clk);
369 if (ret)
370 goto out_disable_clk;
371
372 rate = clk_get_rate(pll_clk);
373 clk_disable_unprepare(pll_clk);
374 if (!rate) {
375 ret = -EINVAL;
376 goto out_disable_clk;
377 }
378 }
379
380 master = spi_alloc_master(&pdev->dev, sizeof(*bs));
381 if (!master) {
382 ret = -ENOMEM;
383 goto out_disable_clk;
384 }
385
386 bs = spi_master_get_devdata(master);
387 bs->pdev = pdev;
388 bs->clk = clk;
389 bs->regs = regs;
390 bs->speed_hz = rate;
391 bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0));
392
393 mutex_init(&bs->bus_mutex);
394 init_completion(&bs->done);
395
396 master->dev.of_node = dev->of_node;
397 if (!dev->of_node)
398 master->bus_num = HSSPI_BUS_NUM;
399
400 of_property_read_u32(dev->of_node, "num-cs", &num_cs);
401 if (num_cs > 8) {
402 dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n",
403 num_cs);
404 num_cs = HSSPI_SPI_MAX_CS;
405 }
406 master->num_chipselect = num_cs;
407 master->setup = bcm63xx_hsspi_setup;
408 master->transfer_one_message = bcm63xx_hsspi_transfer_one;
409 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH |
410 SPI_RX_DUAL | SPI_TX_DUAL;
411 master->bits_per_word_mask = SPI_BPW_MASK(8);
412 master->auto_runtime_pm = true;
413
414 platform_set_drvdata(pdev, master);
415
416
417 __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
418
419
420 __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
421
422
423 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
424 bs->cs_polarity = reg & GLOBAL_CTRL_CS_POLARITY_MASK;
425 __raw_writel(reg | GLOBAL_CTRL_CLK_GATE_SSOFF,
426 bs->regs + HSSPI_GLOBAL_CTRL_REG);
427
428 ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED,
429 pdev->name, bs);
430
431 if (ret)
432 goto out_put_master;
433
434
435 ret = devm_spi_register_master(dev, master);
436 if (ret)
437 goto out_put_master;
438
439 return 0;
440
441out_put_master:
442 spi_master_put(master);
443out_disable_clk:
444 clk_disable_unprepare(clk);
445 return ret;
446}
447
448
449static int bcm63xx_hsspi_remove(struct platform_device *pdev)
450{
451 struct spi_master *master = platform_get_drvdata(pdev);
452 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
453
454
455 __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
456 clk_disable_unprepare(bs->clk);
457
458 return 0;
459}
460
461#ifdef CONFIG_PM_SLEEP
462static int bcm63xx_hsspi_suspend(struct device *dev)
463{
464 struct spi_master *master = dev_get_drvdata(dev);
465 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
466
467 spi_master_suspend(master);
468 clk_disable_unprepare(bs->clk);
469
470 return 0;
471}
472
473static int bcm63xx_hsspi_resume(struct device *dev)
474{
475 struct spi_master *master = dev_get_drvdata(dev);
476 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
477 int ret;
478
479 ret = clk_prepare_enable(bs->clk);
480 if (ret)
481 return ret;
482
483 spi_master_resume(master);
484
485 return 0;
486}
487#endif
488
489static SIMPLE_DEV_PM_OPS(bcm63xx_hsspi_pm_ops, bcm63xx_hsspi_suspend,
490 bcm63xx_hsspi_resume);
491
492static const struct of_device_id bcm63xx_hsspi_of_match[] = {
493 { .compatible = "brcm,bcm6328-hsspi", },
494 { },
495};
496MODULE_DEVICE_TABLE(of, bcm63xx_hsspi_of_match);
497
498static struct platform_driver bcm63xx_hsspi_driver = {
499 .driver = {
500 .name = "bcm63xx-hsspi",
501 .pm = &bcm63xx_hsspi_pm_ops,
502 .of_match_table = bcm63xx_hsspi_of_match,
503 },
504 .probe = bcm63xx_hsspi_probe,
505 .remove = bcm63xx_hsspi_remove,
506};
507
508module_platform_driver(bcm63xx_hsspi_driver);
509
510MODULE_ALIAS("platform:bcm63xx_hsspi");
511MODULE_DESCRIPTION("Broadcom BCM63xx High Speed SPI Controller driver");
512MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
513MODULE_LICENSE("GPL");
514
