LXR linux/drivers/staging/mt7621-pci/pci-mt7621.c

   1/**************************************************************************
   2 *
   3 *  BRIEF MODULE DESCRIPTION
   4 *     PCI init for Ralink RT2880 solution
   5 *
   6 *  Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
   7 *
   8 *  This program is free software; you can redistribute  it and/or modify it
   9 *  under  the terms of  the GNU General  Public License as published by the
  10 *  Free Software Foundation;  either version 2 of the  License, or (at your
  11 *  option) any later version.
  12 *
  13 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  14 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  15 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  16 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  17 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  18 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  19 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  20 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  21 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  22 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23 *
  24 *  You should have received a copy of the  GNU General Public License along
  25 *  with this program; if not, write  to the Free Software Foundation, Inc.,
  26 *  675 Mass Ave, Cambridge, MA 02139, USA.
  27 *
  28 *
  29 **************************************************************************
  30 * May 2007 Bruce Chang
  31 * Initial Release
  32 *
  33 * May 2009 Bruce Chang
  34 * support RT2880/RT3883 PCIe
  35 *
  36 * May 2011 Bruce Chang
  37 * support RT6855/MT7620 PCIe
  38 *
  39 **************************************************************************
  40 */
  41
  42#include <linux/types.h>
  43#include <linux/pci.h>
  44#include <linux/kernel.h>
  45#include <linux/slab.h>
  46#include <linux/version.h>
  47#include <asm/pci.h>
  48#include <asm/io.h>
  49#include <asm/mips-cm.h>
  50#include <linux/init.h>
  51#include <linux/module.h>
  52#include <linux/delay.h>
  53#include <linux/of.h>
  54#include <linux/of_pci.h>
  55#include <linux/platform_device.h>
  56
  57#include <ralink_regs.h>
  58
  59/*
  60 * These functions and structures provide the BIOS scan and mapping of the PCI
  61 * devices.
  62 */
  63
  64#define RALINK_PCIE0_CLK_EN             (1<<24)
  65#define RALINK_PCIE1_CLK_EN             (1<<25)
  66#define RALINK_PCIE2_CLK_EN             (1<<26)
  67
  68#define RALINK_PCI_CONFIG_ADDR          0x20
  69#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG      0x24
  70#define RALINK_PCI_MEMBASE              *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
  71#define RALINK_PCI_IOBASE               *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
  72#define RALINK_PCIE0_RST                (1<<24)
  73#define RALINK_PCIE1_RST                (1<<25)
  74#define RALINK_PCIE2_RST                (1<<26)
  75#define RALINK_SYSCTL_BASE              0xBE000000
  76
  77#define RALINK_PCI_PCICFG_ADDR          *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
  78#define RALINK_PCI_PCIMSK_ADDR          *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
  79#define RALINK_PCI_BASE 0xBE140000
  80
  81#define RALINK_PCIEPHY_P0P1_CTL_OFFSET  (RALINK_PCI_BASE + 0x9000)
  82#define RT6855_PCIE0_OFFSET             0x2000
  83#define RT6855_PCIE1_OFFSET             0x3000
  84#define RT6855_PCIE2_OFFSET             0x4000
  85
  86#define RALINK_PCI0_BAR0SETUP_ADDR      *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
  87#define RALINK_PCI0_IMBASEBAR0_ADDR     *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
  88#define RALINK_PCI0_ID                  *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
  89#define RALINK_PCI0_CLASS               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
  90#define RALINK_PCI0_SUBID               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
  91#define RALINK_PCI0_STATUS              *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
  92#define RALINK_PCI0_DERR                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
  93#define RALINK_PCI0_ECRC                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
  94
  95#define RALINK_PCI1_BAR0SETUP_ADDR      *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
  96#define RALINK_PCI1_IMBASEBAR0_ADDR     *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
  97#define RALINK_PCI1_ID                  *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
  98#define RALINK_PCI1_CLASS               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
  99#define RALINK_PCI1_SUBID               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
 100#define RALINK_PCI1_STATUS              *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
 101#define RALINK_PCI1_DERR                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
 102#define RALINK_PCI1_ECRC                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
 103
 104#define RALINK_PCI2_BAR0SETUP_ADDR      *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
 105#define RALINK_PCI2_IMBASEBAR0_ADDR     *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
 106#define RALINK_PCI2_ID                  *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
 107#define RALINK_PCI2_CLASS               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
 108#define RALINK_PCI2_SUBID               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
 109#define RALINK_PCI2_STATUS              *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
 110#define RALINK_PCI2_DERR                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
 111#define RALINK_PCI2_ECRC                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
 112
 113#define RALINK_PCIEPHY_P0P1_CTL_OFFSET  (RALINK_PCI_BASE + 0x9000)
 114#define RALINK_PCIEPHY_P2_CTL_OFFSET    (RALINK_PCI_BASE + 0xA000)
 115
 116#define MV_WRITE(ofs, data)     \
 117        *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
 118#define MV_READ(ofs, data)      \
 119        *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
 120#define MV_READ_DATA(ofs)       \
 121        le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
 122
 123#define MV_WRITE_16(ofs, data)  \
 124        *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
 125#define MV_READ_16(ofs, data)   \
 126        *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
 127
 128#define MV_WRITE_8(ofs, data)   \
 129        *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
 130#define MV_READ_8(ofs, data)    \
 131        *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
 132
 133#define RALINK_PCI_MM_MAP_BASE          0x60000000
 134#define RALINK_PCI_IO_MAP_BASE          0x1e160000
 135
 136#define RALINK_SYSTEM_CONTROL_BASE      0xbe000000
 137
 138#define ASSERT_SYSRST_PCIE(val)         \
 139        do {                                                            \
 140                if (*(unsigned int *)(0xbe00000c) == 0x00030101)        \
 141                        RALINK_RSTCTRL |= val;                          \
 142                else                                                    \
 143                        RALINK_RSTCTRL &= ~val;                         \
 144        } while(0)
 145#define DEASSERT_SYSRST_PCIE(val)       \
 146        do {                                                            \
 147                if (*(unsigned int *)(0xbe00000c) == 0x00030101)        \
 148                        RALINK_RSTCTRL &= ~val;                         \
 149                else                                                    \
 150                        RALINK_RSTCTRL |= val;                          \
 151        } while(0)
 152#define RALINK_SYSCFG1                  *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x14)
 153#define RALINK_CLKCFG1                  *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x30)
 154#define RALINK_RSTCTRL                  *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x34)
 155#define RALINK_GPIOMODE                 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x60)
 156#define RALINK_PCIE_CLK_GEN             *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x7c)
 157#define RALINK_PCIE_CLK_GEN1            *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x80)
 158#define PPLL_CFG1                       *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x9c)
 159#define PPLL_DRV                        *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0xa0)
 160//RALINK_SYSCFG1 bit
 161#define RALINK_PCI_HOST_MODE_EN         (1<<7)
 162#define RALINK_PCIE_RC_MODE_EN          (1<<8)
 163//RALINK_RSTCTRL bit
 164#define RALINK_PCIE_RST                 (1<<23)
 165#define RALINK_PCI_RST                  (1<<24)
 166//RALINK_CLKCFG1 bit
 167#define RALINK_PCI_CLK_EN               (1<<19)
 168#define RALINK_PCIE_CLK_EN              (1<<21)
 169//RALINK_GPIOMODE bit
 170#define PCI_SLOTx2                      (1<<11)
 171#define PCI_SLOTx1                      (2<<11)
 172//MTK PCIE PLL bit
 173#define PDRV_SW_SET                     (1<<31)
 174#define LC_CKDRVPD_                     (1<<19)
 175
 176#define MEMORY_BASE 0x0
 177static int pcie_link_status = 0;
 178
 179#define PCI_ACCESS_READ_1  0
 180#define PCI_ACCESS_READ_2  1
 181#define PCI_ACCESS_READ_4  2
 182#define PCI_ACCESS_WRITE_1 3
 183#define PCI_ACCESS_WRITE_2 4
 184#define PCI_ACCESS_WRITE_4 5
 185
 186static int config_access(unsigned char access_type, struct pci_bus *bus,
 187                        unsigned int devfn, unsigned int where, u32 * data)
 188{
 189        unsigned int slot = PCI_SLOT(devfn);
 190        u8 func = PCI_FUNC(devfn);
 191        uint32_t address_reg, data_reg;
 192        unsigned int address;
 193
 194        address_reg = RALINK_PCI_CONFIG_ADDR;
 195        data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
 196
 197        address = (((where&0xF00)>>8)<<24) |(bus->number << 16) | (slot << 11) |
 198                                (func << 8) | (where & 0xfc) | 0x80000000;
 199        MV_WRITE(address_reg, address);
 200
 201        switch(access_type) {
 202        case PCI_ACCESS_WRITE_1:
 203                MV_WRITE_8(data_reg+(where&0x3), *data);
 204                break;
 205        case PCI_ACCESS_WRITE_2:
 206                MV_WRITE_16(data_reg+(where&0x3), *data);
 207                break;
 208        case PCI_ACCESS_WRITE_4:
 209                MV_WRITE(data_reg, *data);
 210                break;
 211        case PCI_ACCESS_READ_1:
 212                MV_READ_8( data_reg+(where&0x3), data);
 213                break;
 214        case PCI_ACCESS_READ_2:
 215                MV_READ_16(data_reg+(where&0x3), data);
 216                break;
 217        case PCI_ACCESS_READ_4:
 218                MV_READ(data_reg, data);
 219                break;
 220        default:
 221                printk("no specify access type\n");
 222                break;
 223        }
 224        return 0;
 225}
 226
 227static int
 228read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
 229{
 230        return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned int)where, (u32 *)val);
 231}
 232
 233static int
 234read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
 235{
 236        return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned int)where, (u32 *)val);
 237}
 238
 239static int
 240read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
 241{
 242        return config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned int)where, (u32 *)val);
 243}
 244
 245static int
 246write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
 247{
 248        if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned int)where, (u32 *)&val))
 249                return -1;
 250
 251        return PCIBIOS_SUCCESSFUL;
 252}
 253
 254static int
 255write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
 256{
 257        if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val))
 258                return -1;
 259
 260        return PCIBIOS_SUCCESSFUL;
 261}
 262
 263static int
 264write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
 265{
 266        if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val))
 267                return -1;
 268
 269        return PCIBIOS_SUCCESSFUL;
 270}
 271
 272static int
 273pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
 274{
 275        switch (size) {
 276        case 1:
 277                return read_config_byte(bus, devfn, where, (u8 *) val);
 278        case 2:
 279                return read_config_word(bus, devfn, where, (u16 *) val);
 280        default:
 281                return read_config_dword(bus, devfn, where, val);
 282        }
 283}
 284
 285static int
 286pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
 287{
 288        switch (size) {
 289        case 1:
 290                return write_config_byte(bus, devfn, where, (u8) val);
 291        case 2:
 292                return write_config_word(bus, devfn, where, (u16) val);
 293        default:
 294                return write_config_dword(bus, devfn, where, val);
 295        }
 296}
 297
 298struct pci_ops mt7621_pci_ops= {
 299        .read           = pci_config_read,
 300        .write          = pci_config_write,
 301};
 302
 303static struct resource mt7621_res_pci_mem1;
 304static struct resource mt7621_res_pci_io1;
 305static struct pci_controller mt7621_controller = {
 306        .pci_ops        = &mt7621_pci_ops,
 307        .mem_resource   = &mt7621_res_pci_mem1,
 308        .io_resource    = &mt7621_res_pci_io1,
 309};
 310
 311static void
 312read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val)
 313{
 314        unsigned int address_reg, data_reg, address;
 315
 316        address_reg = RALINK_PCI_CONFIG_ADDR;
 317        data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
 318        address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
 319        MV_WRITE(address_reg, address);
 320        MV_READ(data_reg, val);
 321        return;
 322}
 323
 324static void
 325write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val)
 326{
 327        unsigned int address_reg, data_reg, address;
 328
 329        address_reg = RALINK_PCI_CONFIG_ADDR;
 330        data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
 331        address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
 332        MV_WRITE(address_reg, address);
 333        MV_WRITE(data_reg, val);
 334        return;
 335}
 336
 337int
 338pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 339{
 340        u16 cmd;
 341        u32 val;
 342        int irq;
 343
 344        if (dev->bus->number == 0) {
 345                write_config(0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
 346                read_config(0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
 347                printk("BAR0 at slot %d = %x\n", slot, val);
 348        }
 349
 350        pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);  //configure cache line size 0x14
 351        pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF);  //configure latency timer 0x10
 352        pci_read_config_word(dev, PCI_COMMAND, &cmd);
 353        cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
 354        pci_write_config_word(dev, PCI_COMMAND, cmd);
 355
 356        irq = of_irq_parse_and_map_pci(dev, slot, pin);
 357
 358        pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 359        return irq;
 360}
 361
 362void
 363set_pcie_phy(u32 *addr, int start_b, int bits, int val)
 364{
 365        *(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b);
 366        *(unsigned int *)(addr) |= val << start_b;
 367}
 368
 369void
 370bypass_pipe_rst(void)
 371{
 372        /* PCIe Port 0 */
 373        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01);     // rg_pe1_pipe_rst_b
 374        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c),  4, 1, 0x01);     // rg_pe1_pipe_cmd_frc[4]
 375        /* PCIe Port 1 */
 376        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01);     // rg_pe1_pipe_rst_b
 377        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c),  4, 1, 0x01);     // rg_pe1_pipe_cmd_frc[4]
 378        /* PCIe Port 2 */
 379        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01);       // rg_pe1_pipe_rst_b
 380        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c),  4, 1, 0x01);       // rg_pe1_pipe_cmd_frc[4]
 381}
 382
 383void
 384set_phy_for_ssc(void)
 385{
 386        unsigned long reg = (*(volatile u32 *)(RALINK_SYSCTL_BASE + 0x10));
 387
 388        reg = (reg >> 6) & 0x7;
 389        /* Set PCIe Port0 & Port1 PHY to disable SSC */
 390        /* Debug Xtal Type */
 391        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  8, 1, 0x01);     // rg_pe1_frc_h_xtal_type
 392        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  9, 2, 0x00);     // rg_pe1_h_xtal_type
 393        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x01);     // rg_pe1_frc_phy_en    //Force Port 0 enable control
 394        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x01);     // rg_pe1_frc_phy_en    //Force Port 1 enable control
 395        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x00);     // rg_pe1_phy_en        //Port 0 disable
 396        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x00);     // rg_pe1_phy_en        //Port 1 disable
 397        if(reg <= 5 && reg >= 3) {      // 40MHz Xtal
 398                set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x01);     // RG_PE1_H_PLL_PREDIV  //Pre-divider ratio (for host mode)
 399                printk("***** Xtal 40MHz *****\n");
 400        } else {                        // 25MHz | 20MHz Xtal
 401                set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x00);     // RG_PE1_H_PLL_PREDIV  //Pre-divider ratio (for host mode)
 402                if (reg >= 6) {
 403                        printk("***** Xtal 25MHz *****\n");
 404                        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc),  4, 2, 0x01);     // RG_PE1_H_PLL_FBKSEL  //Feedback clock select
 405                        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c),  0,31, 0x18000000);       // RG_PE1_H_LCDDS_PCW_NCPO      //DDS NCPO PCW (for host mode)
 406                        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4),  0,16, 0x18d);    // RG_PE1_H_LCDDS_SSC_PRD       //DDS SSC dither period control
 407                        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8),  0,12, 0x4a);     // RG_PE1_H_LCDDS_SSC_DELTA     //DDS SSC dither amplitude control
 408                        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16,12, 0x4a);     // RG_PE1_H_LCDDS_SSC_DELTA1    //DDS SSC dither amplitude control for initial
 409                } else {
 410                        printk("***** Xtal 20MHz *****\n");
 411                }
 412        }
 413        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0),  5, 1, 0x01);     // RG_PE1_LCDDS_CLK_PH_INV      //DDS clock inversion
 414        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02);     // RG_PE1_H_PLL_BC
 415        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06);     // RG_PE1_H_PLL_BP
 416        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02);     // RG_PE1_H_PLL_IR
 417        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  8, 4, 0x01);     // RG_PE1_H_PLL_IC
 418        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00);     // RG_PE1_H_PLL_BR
 419        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  1, 3, 0x02);     // RG_PE1_PLL_DIVEN
 420        if(reg <= 5 && reg >= 3) {      // 40MHz Xtal
 421                set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  6, 2, 0x01);     // rg_pe1_mstckdiv              //value of da_pe1_mstckdiv when force mode enable
 422                set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  5, 1, 0x01);     // rg_pe1_frc_mstckdiv  //force mode enable of da_pe1_mstckdiv
 423        }
 424        /* Enable PHY and disable force mode */
 425        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x01);     // rg_pe1_phy_en        //Port 0 enable
 426        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x01);     // rg_pe1_phy_en        //Port 1 enable
 427        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x00);     // rg_pe1_frc_phy_en    //Force Port 0 disable control
 428        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x00);     // rg_pe1_frc_phy_en    //Force Port 1 disable control
 429
 430        /* Set PCIe Port2 PHY to disable SSC */
 431        /* Debug Xtal Type */
 432        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  8, 1, 0x01);       // rg_pe1_frc_h_xtal_type
 433        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  9, 2, 0x00);       // rg_pe1_h_xtal_type
 434        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x01);       // rg_pe1_frc_phy_en    //Force Port 0 enable control
 435        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x00);       // rg_pe1_phy_en        //Port 0 disable
 436        if(reg <= 5 && reg >= 3) {      // 40MHz Xtal
 437                set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x01);       // RG_PE1_H_PLL_PREDIV  //Pre-divider ratio (for host mode)
 438        } else {                        // 25MHz | 20MHz Xtal
 439                set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x00);       // RG_PE1_H_PLL_PREDIV  //Pre-divider ratio (for host mode)
 440                if (reg >= 6) {         // 25MHz Xtal
 441                        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc),  4, 2, 0x01);       // RG_PE1_H_PLL_FBKSEL  //Feedback clock select
 442                        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c),  0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO      //DDS NCPO PCW (for host mode)
 443                        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4),  0,16, 0x18d);      // RG_PE1_H_LCDDS_SSC_PRD       //DDS SSC dither period control
 444                        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8),  0,12, 0x4a);       // RG_PE1_H_LCDDS_SSC_DELTA     //DDS SSC dither amplitude control
 445                        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16,12, 0x4a);       // RG_PE1_H_LCDDS_SSC_DELTA1    //DDS SSC dither amplitude control for initial
 446                }
 447        }
 448        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0),  5, 1, 0x01);       // RG_PE1_LCDDS_CLK_PH_INV      //DDS clock inversion
 449        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02);       // RG_PE1_H_PLL_BC
 450        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06);       // RG_PE1_H_PLL_BP
 451        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02);       // RG_PE1_H_PLL_IR
 452        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  8, 4, 0x01);       // RG_PE1_H_PLL_IC
 453        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00);       // RG_PE1_H_PLL_BR
 454        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  1, 3, 0x02);       // RG_PE1_PLL_DIVEN
 455        if(reg <= 5 && reg >= 3) {      // 40MHz Xtal
 456                set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  6, 2, 0x01);       // rg_pe1_mstckdiv              //value of da_pe1_mstckdiv when force mode enable
 457                set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  5, 1, 0x01);       // rg_pe1_frc_mstckdiv  //force mode enable of da_pe1_mstckdiv
 458        }
 459        /* Enable PHY and disable force mode */
 460        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x01);       // rg_pe1_phy_en        //Port 0 enable
 461        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x00);       // rg_pe1_frc_phy_en    //Force Port 0 disable control
 462}
 463
 464void setup_cm_memory_region(struct resource *mem_resource)
 465{
 466        resource_size_t mask;
 467        if (mips_cps_numiocu(0)) {
 468                /* FIXME: hardware doesn't accept mask values with 1s after
 469                 * 0s (e.g. 0xffef), so it would be great to warn if that's
 470                 * about to happen */
 471                mask = ~(mem_resource->end - mem_resource->start);
 472
 473                write_gcr_reg1_base(mem_resource->start);
 474                write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
 475                printk("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
 476                        (unsigned long long)read_gcr_reg1_base(),
 477                        (unsigned long long)read_gcr_reg1_mask());
 478        }
 479}
 480
 481static int mt7621_pci_probe(struct platform_device *pdev)
 482{
 483        unsigned long val = 0;
 484
 485        iomem_resource.start = 0;
 486        iomem_resource.end= ~0;
 487        ioport_resource.start= 0;
 488        ioport_resource.end = ~0;
 489
 490        val = RALINK_PCIE0_RST;
 491        val |= RALINK_PCIE1_RST;
 492        val |= RALINK_PCIE2_RST;
 493
 494        ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
 495
 496        *(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
 497        *(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
 498        mdelay(100);
 499        *(unsigned int *)(0xbe000600) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
 500        mdelay(100);
 501        *(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7);          // clear DATA
 502
 503        mdelay(100);
 504
 505        val = RALINK_PCIE0_RST;
 506        val |= RALINK_PCIE1_RST;
 507        val |= RALINK_PCIE2_RST;
 508
 509        DEASSERT_SYSRST_PCIE(val);
 510
 511        if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
 512                bypass_pipe_rst();
 513        set_phy_for_ssc();
 514
 515        read_config(0, 0, 0, 0x70c, &val);
 516        printk("Port 0 N_FTS = %x\n", (unsigned int)val);
 517
 518        read_config(0, 1, 0, 0x70c, &val);
 519        printk("Port 1 N_FTS = %x\n", (unsigned int)val);
 520
 521        read_config(0, 2, 0, 0x70c, &val);
 522        printk("Port 2 N_FTS = %x\n", (unsigned int)val);
 523
 524        RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST);
 525        RALINK_SYSCFG1 &= ~(0x30);
 526        RALINK_SYSCFG1 |= (2<<4);
 527        RALINK_PCIE_CLK_GEN &= 0x7fffffff;
 528        RALINK_PCIE_CLK_GEN1 &= 0x80ffffff;
 529        RALINK_PCIE_CLK_GEN1 |= 0xa << 24;
 530        RALINK_PCIE_CLK_GEN |= 0x80000000;
 531        mdelay(50);
 532        RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST);
 533
 534        /* Use GPIO control instead of PERST_N */
 535        *(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7;             // set DATA
 536        mdelay(1000);
 537
 538        if(( RALINK_PCI0_STATUS & 0x1) == 0)
 539        {
 540                printk("PCIE0 no card, disable it(RST&CLK)\n");
 541                ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
 542                RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE0_CLK_EN);
 543                pcie_link_status &= ~(1<<0);
 544        } else {
 545                pcie_link_status |= 1<<0;
 546                RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
 547        }
 548
 549        if(( RALINK_PCI1_STATUS & 0x1) == 0)
 550        {
 551                printk("PCIE1 no card, disable it(RST&CLK)\n");
 552                ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
 553                RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE1_CLK_EN);
 554                pcie_link_status &= ~(1<<1);
 555        } else {
 556                pcie_link_status |= 1<<1;
 557                RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
 558        }
 559
 560        if (( RALINK_PCI2_STATUS & 0x1) == 0) {
 561                printk("PCIE2 no card, disable it(RST&CLK)\n");
 562                ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
 563                RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE2_CLK_EN);
 564                pcie_link_status &= ~(1<<2);
 565        } else {
 566                pcie_link_status |= 1<<2;
 567                RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
 568        }
 569
 570        if (pcie_link_status == 0)
 571                return 0;
 572
 573/*
 574pcie(2/1/0) link status pcie2_num       pcie1_num       pcie0_num
 5753'b000                  x               x               x
 5763'b001                  x               x               0
 5773'b010                  x               0               x
 5783'b011                  x               1               0
 5793'b100                  0               x               x
 5803'b101                  1               x               0
 5813'b110                  1               0               x
 5823'b111                  2               1               0
 583*/
 584        switch(pcie_link_status) {
 585        case 2:
 586                RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000;
 587                RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;    //port0
 588                RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;    //port1
 589                break;
 590        case 4:
 591                RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
 592                RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;    //port0
 593                RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;    //port1
 594                RALINK_PCI_PCICFG_ADDR |= 0x0 << 24;    //port2
 595                break;
 596        case 5:
 597                RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
 598                RALINK_PCI_PCICFG_ADDR |= 0x0 << 16;    //port0
 599                RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;    //port1
 600                RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;    //port2
 601                break;
 602        case 6:
 603                RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
 604                RALINK_PCI_PCICFG_ADDR |= 0x2 << 16;    //port0
 605                RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;    //port1
 606                RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;    //port2
 607                break;
 608        }
 609
 610/*
 611        ioport_resource.start = mt7621_res_pci_io1.start;
 612        ioport_resource.end = mt7621_res_pci_io1.end;
 613*/
 614
 615        RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;
 616        RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE;
 617
 618        //PCIe0
 619        if((pcie_link_status & 0x1) != 0) {
 620                RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001;        //open 7FFF:2G; ENABLE
 621                RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE;
 622                RALINK_PCI0_CLASS = 0x06040001;
 623                printk("PCIE0 enabled\n");
 624        }
 625
 626        //PCIe1
 627        if ((pcie_link_status & 0x2) != 0) {
 628                RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001;        //open 7FFF:2G; ENABLE
 629                RALINK_PCI1_IMBASEBAR0_ADDR = MEMORY_BASE;
 630                RALINK_PCI1_CLASS = 0x06040001;
 631                printk("PCIE1 enabled\n");
 632        }
 633
 634        //PCIe2
 635        if ((pcie_link_status & 0x4) != 0) {
 636                RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001;        //open 7FFF:2G; ENABLE
 637                RALINK_PCI2_IMBASEBAR0_ADDR = MEMORY_BASE;
 638                RALINK_PCI2_CLASS = 0x06040001;
 639                printk("PCIE2 enabled\n");
 640        }
 641
 642        switch(pcie_link_status) {
 643        case 7:
 644                read_config(0, 2, 0, 0x4, &val);
 645                write_config(0, 2, 0, 0x4, val|0x4);
 646                read_config(0, 2, 0, 0x70c, &val);
 647                val &= ~(0xff)<<8;
 648                val |= 0x50<<8;
 649                write_config(0, 2, 0, 0x70c, val);
 650        case 3:
 651        case 5:
 652        case 6:
 653                read_config(0, 1, 0, 0x4, &val);
 654                write_config(0, 1, 0, 0x4, val|0x4);
 655                read_config(0, 1, 0, 0x70c, &val);
 656                val &= ~(0xff)<<8;
 657                val |= 0x50<<8;
 658                write_config(0, 1, 0, 0x70c, val);
 659        default:
 660                read_config(0, 0, 0, 0x4, &val);
 661                write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
 662                read_config(0, 0, 0, 0x70c, &val);
 663                val &= ~(0xff)<<8;
 664                val |= 0x50<<8;
 665                write_config(0, 0, 0, 0x70c, val);
 666        }
 667
 668        pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node);
 669        setup_cm_memory_region(mt7621_controller.mem_resource);
 670        register_pci_controller(&mt7621_controller);
 671        return 0;
 672
 673}
 674
 675int pcibios_plat_dev_init(struct pci_dev *dev)
 676{
 677        return 0;
 678}
 679
 680static const struct of_device_id mt7621_pci_ids[] = {
 681        { .compatible = "mediatek,mt7621-pci" },
 682        {},
 683};
 684MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
 685
 686static struct platform_driver mt7621_pci_driver = {
 687        .probe = mt7621_pci_probe,
 688        .driver = {
 689                .name = "mt7621-pci",
 690                .of_match_table = of_match_ptr(mt7621_pci_ids),
 691        },
 692};
 693
 694static int __init mt7621_pci_init(void)
 695{
 696        return platform_driver_register(&mt7621_pci_driver);
 697}
 698
 699arch_initcall(mt7621_pci_init);
 700