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10#include <linux/module.h>
11#include <linux/mfd/syscon.h>
12#include <linux/delay.h>
13#include <linux/of_gpio.h>
14#include <linux/of_device.h>
15#include <linux/clk.h>
16#include <linux/pm_runtime.h>
17#include <linux/regmap.h>
18#include <sound/pcm_params.h>
19#include <sound/dmaengine_pcm.h>
20
21#include "rockchip_i2s.h"
22#include "rockchip_pcm.h"
23
24#define DRV_NAME "rockchip-i2s"
25
26struct rk_i2s_pins {
27 u32 reg_offset;
28 u32 shift;
29};
30
31struct rk_i2s_dev {
32 struct device *dev;
33
34 struct clk *hclk;
35 struct clk *mclk;
36
37 struct snd_dmaengine_dai_dma_data capture_dma_data;
38 struct snd_dmaengine_dai_dma_data playback_dma_data;
39
40 struct regmap *regmap;
41 struct regmap *grf;
42
43
44
45
46
47
48 bool tx_start;
49 bool rx_start;
50 bool is_master_mode;
51 const struct rk_i2s_pins *pins;
52};
53
54static int i2s_runtime_suspend(struct device *dev)
55{
56 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
57
58 regcache_cache_only(i2s->regmap, true);
59 clk_disable_unprepare(i2s->mclk);
60
61 return 0;
62}
63
64static int i2s_runtime_resume(struct device *dev)
65{
66 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
67 int ret;
68
69 ret = clk_prepare_enable(i2s->mclk);
70 if (ret) {
71 dev_err(i2s->dev, "clock enable failed %d\n", ret);
72 return ret;
73 }
74
75 regcache_cache_only(i2s->regmap, false);
76 regcache_mark_dirty(i2s->regmap);
77
78 ret = regcache_sync(i2s->regmap);
79 if (ret)
80 clk_disable_unprepare(i2s->mclk);
81
82 return ret;
83}
84
85static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
86{
87 return snd_soc_dai_get_drvdata(dai);
88}
89
90static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
91{
92 unsigned int val = 0;
93 int retry = 10;
94
95 if (on) {
96 regmap_update_bits(i2s->regmap, I2S_DMACR,
97 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
98
99 regmap_update_bits(i2s->regmap, I2S_XFER,
100 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
101 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
102
103 i2s->tx_start = true;
104 } else {
105 i2s->tx_start = false;
106
107 regmap_update_bits(i2s->regmap, I2S_DMACR,
108 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
109
110 if (!i2s->rx_start) {
111 regmap_update_bits(i2s->regmap, I2S_XFER,
112 I2S_XFER_TXS_START |
113 I2S_XFER_RXS_START,
114 I2S_XFER_TXS_STOP |
115 I2S_XFER_RXS_STOP);
116
117 udelay(150);
118 regmap_update_bits(i2s->regmap, I2S_CLR,
119 I2S_CLR_TXC | I2S_CLR_RXC,
120 I2S_CLR_TXC | I2S_CLR_RXC);
121
122 regmap_read(i2s->regmap, I2S_CLR, &val);
123
124
125 while (val) {
126 regmap_read(i2s->regmap, I2S_CLR, &val);
127 retry--;
128 if (!retry) {
129 dev_warn(i2s->dev, "fail to clear\n");
130 break;
131 }
132 }
133 }
134 }
135}
136
137static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
138{
139 unsigned int val = 0;
140 int retry = 10;
141
142 if (on) {
143 regmap_update_bits(i2s->regmap, I2S_DMACR,
144 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
145
146 regmap_update_bits(i2s->regmap, I2S_XFER,
147 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
148 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
149
150 i2s->rx_start = true;
151 } else {
152 i2s->rx_start = false;
153
154 regmap_update_bits(i2s->regmap, I2S_DMACR,
155 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
156
157 if (!i2s->tx_start) {
158 regmap_update_bits(i2s->regmap, I2S_XFER,
159 I2S_XFER_TXS_START |
160 I2S_XFER_RXS_START,
161 I2S_XFER_TXS_STOP |
162 I2S_XFER_RXS_STOP);
163
164 udelay(150);
165 regmap_update_bits(i2s->regmap, I2S_CLR,
166 I2S_CLR_TXC | I2S_CLR_RXC,
167 I2S_CLR_TXC | I2S_CLR_RXC);
168
169 regmap_read(i2s->regmap, I2S_CLR, &val);
170
171
172 while (val) {
173 regmap_read(i2s->regmap, I2S_CLR, &val);
174 retry--;
175 if (!retry) {
176 dev_warn(i2s->dev, "fail to clear\n");
177 break;
178 }
179 }
180 }
181 }
182}
183
184static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
185 unsigned int fmt)
186{
187 struct rk_i2s_dev *i2s = to_info(cpu_dai);
188 unsigned int mask = 0, val = 0;
189
190 mask = I2S_CKR_MSS_MASK;
191 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
192 case SND_SOC_DAIFMT_CBS_CFS:
193
194 val = I2S_CKR_MSS_MASTER;
195 i2s->is_master_mode = true;
196 break;
197 case SND_SOC_DAIFMT_CBM_CFM:
198 val = I2S_CKR_MSS_SLAVE;
199 i2s->is_master_mode = false;
200 break;
201 default:
202 return -EINVAL;
203 }
204
205 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
206
207 mask = I2S_CKR_CKP_MASK;
208 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
209 case SND_SOC_DAIFMT_NB_NF:
210 val = I2S_CKR_CKP_NEG;
211 break;
212 case SND_SOC_DAIFMT_IB_NF:
213 val = I2S_CKR_CKP_POS;
214 break;
215 default:
216 return -EINVAL;
217 }
218
219 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
220
221 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
222 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
223 case SND_SOC_DAIFMT_RIGHT_J:
224 val = I2S_TXCR_IBM_RSJM;
225 break;
226 case SND_SOC_DAIFMT_LEFT_J:
227 val = I2S_TXCR_IBM_LSJM;
228 break;
229 case SND_SOC_DAIFMT_I2S:
230 val = I2S_TXCR_IBM_NORMAL;
231 break;
232 case SND_SOC_DAIFMT_DSP_A:
233 val = I2S_TXCR_TFS_PCM;
234 break;
235 case SND_SOC_DAIFMT_DSP_B:
236 val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
237 break;
238 default:
239 return -EINVAL;
240 }
241
242 regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
243
244 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
245 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
246 case SND_SOC_DAIFMT_RIGHT_J:
247 val = I2S_RXCR_IBM_RSJM;
248 break;
249 case SND_SOC_DAIFMT_LEFT_J:
250 val = I2S_RXCR_IBM_LSJM;
251 break;
252 case SND_SOC_DAIFMT_I2S:
253 val = I2S_RXCR_IBM_NORMAL;
254 break;
255 case SND_SOC_DAIFMT_DSP_A:
256 val = I2S_RXCR_TFS_PCM;
257 break;
258 case SND_SOC_DAIFMT_DSP_B:
259 val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
260 break;
261 default:
262 return -EINVAL;
263 }
264
265 regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
266
267 return 0;
268}
269
270static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
271 struct snd_pcm_hw_params *params,
272 struct snd_soc_dai *dai)
273{
274 struct rk_i2s_dev *i2s = to_info(dai);
275 struct snd_soc_pcm_runtime *rtd = substream->private_data;
276 unsigned int val = 0;
277 unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
278
279 if (i2s->is_master_mode) {
280 mclk_rate = clk_get_rate(i2s->mclk);
281 bclk_rate = 2 * 32 * params_rate(params);
282 if (bclk_rate && mclk_rate % bclk_rate)
283 return -EINVAL;
284
285 div_bclk = mclk_rate / bclk_rate;
286 div_lrck = bclk_rate / params_rate(params);
287 regmap_update_bits(i2s->regmap, I2S_CKR,
288 I2S_CKR_MDIV_MASK,
289 I2S_CKR_MDIV(div_bclk));
290
291 regmap_update_bits(i2s->regmap, I2S_CKR,
292 I2S_CKR_TSD_MASK |
293 I2S_CKR_RSD_MASK,
294 I2S_CKR_TSD(div_lrck) |
295 I2S_CKR_RSD(div_lrck));
296 }
297
298 switch (params_format(params)) {
299 case SNDRV_PCM_FORMAT_S8:
300 val |= I2S_TXCR_VDW(8);
301 break;
302 case SNDRV_PCM_FORMAT_S16_LE:
303 val |= I2S_TXCR_VDW(16);
304 break;
305 case SNDRV_PCM_FORMAT_S20_3LE:
306 val |= I2S_TXCR_VDW(20);
307 break;
308 case SNDRV_PCM_FORMAT_S24_LE:
309 val |= I2S_TXCR_VDW(24);
310 break;
311 case SNDRV_PCM_FORMAT_S32_LE:
312 val |= I2S_TXCR_VDW(32);
313 break;
314 default:
315 return -EINVAL;
316 }
317
318 switch (params_channels(params)) {
319 case 8:
320 val |= I2S_CHN_8;
321 break;
322 case 6:
323 val |= I2S_CHN_6;
324 break;
325 case 4:
326 val |= I2S_CHN_4;
327 break;
328 case 2:
329 val |= I2S_CHN_2;
330 break;
331 default:
332 dev_err(i2s->dev, "invalid channel: %d\n",
333 params_channels(params));
334 return -EINVAL;
335 }
336
337 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
338 regmap_update_bits(i2s->regmap, I2S_RXCR,
339 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
340 val);
341 else
342 regmap_update_bits(i2s->regmap, I2S_TXCR,
343 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
344 val);
345
346 if (!IS_ERR(i2s->grf) && i2s->pins) {
347 regmap_read(i2s->regmap, I2S_TXCR, &val);
348 val &= I2S_TXCR_CSR_MASK;
349
350 switch (val) {
351 case I2S_CHN_4:
352 val = I2S_IO_4CH_OUT_6CH_IN;
353 break;
354 case I2S_CHN_6:
355 val = I2S_IO_6CH_OUT_4CH_IN;
356 break;
357 case I2S_CHN_8:
358 val = I2S_IO_8CH_OUT_2CH_IN;
359 break;
360 default:
361 val = I2S_IO_2CH_OUT_8CH_IN;
362 break;
363 }
364
365 val <<= i2s->pins->shift;
366 val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16;
367 regmap_write(i2s->grf, i2s->pins->reg_offset, val);
368 }
369
370 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
371 I2S_DMACR_TDL(16));
372 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
373 I2S_DMACR_RDL(16));
374
375 val = I2S_CKR_TRCM_TXRX;
376 if (dai->driver->symmetric_rates && rtd->dai_link->symmetric_rates)
377 val = I2S_CKR_TRCM_TXONLY;
378
379 regmap_update_bits(i2s->regmap, I2S_CKR,
380 I2S_CKR_TRCM_MASK,
381 val);
382 return 0;
383}
384
385static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
386 int cmd, struct snd_soc_dai *dai)
387{
388 struct rk_i2s_dev *i2s = to_info(dai);
389 int ret = 0;
390
391 switch (cmd) {
392 case SNDRV_PCM_TRIGGER_START:
393 case SNDRV_PCM_TRIGGER_RESUME:
394 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
395 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
396 rockchip_snd_rxctrl(i2s, 1);
397 else
398 rockchip_snd_txctrl(i2s, 1);
399 break;
400 case SNDRV_PCM_TRIGGER_SUSPEND:
401 case SNDRV_PCM_TRIGGER_STOP:
402 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
403 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
404 rockchip_snd_rxctrl(i2s, 0);
405 else
406 rockchip_snd_txctrl(i2s, 0);
407 break;
408 default:
409 ret = -EINVAL;
410 break;
411 }
412
413 return ret;
414}
415
416static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
417 unsigned int freq, int dir)
418{
419 struct rk_i2s_dev *i2s = to_info(cpu_dai);
420 int ret;
421
422 if (freq == 0)
423 return 0;
424
425 ret = clk_set_rate(i2s->mclk, freq);
426 if (ret)
427 dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
428
429 return ret;
430}
431
432static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
433{
434 struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
435
436 dai->capture_dma_data = &i2s->capture_dma_data;
437 dai->playback_dma_data = &i2s->playback_dma_data;
438
439 return 0;
440}
441
442static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
443 .hw_params = rockchip_i2s_hw_params,
444 .set_sysclk = rockchip_i2s_set_sysclk,
445 .set_fmt = rockchip_i2s_set_fmt,
446 .trigger = rockchip_i2s_trigger,
447};
448
449static struct snd_soc_dai_driver rockchip_i2s_dai = {
450 .probe = rockchip_i2s_dai_probe,
451 .playback = {
452 .stream_name = "Playback",
453 .channels_min = 2,
454 .channels_max = 8,
455 .rates = SNDRV_PCM_RATE_8000_192000,
456 .formats = (SNDRV_PCM_FMTBIT_S8 |
457 SNDRV_PCM_FMTBIT_S16_LE |
458 SNDRV_PCM_FMTBIT_S20_3LE |
459 SNDRV_PCM_FMTBIT_S24_LE |
460 SNDRV_PCM_FMTBIT_S32_LE),
461 },
462 .capture = {
463 .stream_name = "Capture",
464 .channels_min = 2,
465 .channels_max = 2,
466 .rates = SNDRV_PCM_RATE_8000_192000,
467 .formats = (SNDRV_PCM_FMTBIT_S8 |
468 SNDRV_PCM_FMTBIT_S16_LE |
469 SNDRV_PCM_FMTBIT_S20_3LE |
470 SNDRV_PCM_FMTBIT_S24_LE |
471 SNDRV_PCM_FMTBIT_S32_LE),
472 },
473 .ops = &rockchip_i2s_dai_ops,
474 .symmetric_rates = 1,
475};
476
477static const struct snd_soc_component_driver rockchip_i2s_component = {
478 .name = DRV_NAME,
479};
480
481static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
482{
483 switch (reg) {
484 case I2S_TXCR:
485 case I2S_RXCR:
486 case I2S_CKR:
487 case I2S_DMACR:
488 case I2S_INTCR:
489 case I2S_XFER:
490 case I2S_CLR:
491 case I2S_TXDR:
492 return true;
493 default:
494 return false;
495 }
496}
497
498static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
499{
500 switch (reg) {
501 case I2S_TXCR:
502 case I2S_RXCR:
503 case I2S_CKR:
504 case I2S_DMACR:
505 case I2S_INTCR:
506 case I2S_XFER:
507 case I2S_CLR:
508 case I2S_TXDR:
509 case I2S_RXDR:
510 case I2S_FIFOLR:
511 case I2S_INTSR:
512 return true;
513 default:
514 return false;
515 }
516}
517
518static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
519{
520 switch (reg) {
521 case I2S_INTSR:
522 case I2S_CLR:
523 case I2S_FIFOLR:
524 case I2S_TXDR:
525 case I2S_RXDR:
526 return true;
527 default:
528 return false;
529 }
530}
531
532static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
533{
534 switch (reg) {
535 case I2S_RXDR:
536 return true;
537 default:
538 return false;
539 }
540}
541
542static const struct reg_default rockchip_i2s_reg_defaults[] = {
543 {0x00, 0x0000000f},
544 {0x04, 0x0000000f},
545 {0x08, 0x00071f1f},
546 {0x10, 0x001f0000},
547 {0x14, 0x01f00000},
548};
549
550static const struct regmap_config rockchip_i2s_regmap_config = {
551 .reg_bits = 32,
552 .reg_stride = 4,
553 .val_bits = 32,
554 .max_register = I2S_RXDR,
555 .reg_defaults = rockchip_i2s_reg_defaults,
556 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
557 .writeable_reg = rockchip_i2s_wr_reg,
558 .readable_reg = rockchip_i2s_rd_reg,
559 .volatile_reg = rockchip_i2s_volatile_reg,
560 .precious_reg = rockchip_i2s_precious_reg,
561 .cache_type = REGCACHE_FLAT,
562};
563
564static const struct rk_i2s_pins rk3399_i2s_pins = {
565 .reg_offset = 0xe220,
566 .shift = 11,
567};
568
569static const struct of_device_id rockchip_i2s_match[] = {
570 { .compatible = "rockchip,rk3066-i2s", },
571 { .compatible = "rockchip,rk3188-i2s", },
572 { .compatible = "rockchip,rk3288-i2s", },
573 { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
574 {},
575};
576
577static int rockchip_i2s_probe(struct platform_device *pdev)
578{
579 struct device_node *node = pdev->dev.of_node;
580 const struct of_device_id *of_id;
581 struct rk_i2s_dev *i2s;
582 struct snd_soc_dai_driver *soc_dai;
583 struct resource *res;
584 void __iomem *regs;
585 int ret;
586 int val;
587
588 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
589 if (!i2s)
590 return -ENOMEM;
591
592 i2s->dev = &pdev->dev;
593
594 i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
595 if (!IS_ERR(i2s->grf)) {
596 of_id = of_match_device(rockchip_i2s_match, &pdev->dev);
597 if (!of_id || !of_id->data)
598 return -EINVAL;
599
600 i2s->pins = of_id->data;
601 }
602
603
604 i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
605 if (IS_ERR(i2s->hclk)) {
606 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
607 return PTR_ERR(i2s->hclk);
608 }
609 ret = clk_prepare_enable(i2s->hclk);
610 if (ret) {
611 dev_err(i2s->dev, "hclock enable failed %d\n", ret);
612 return ret;
613 }
614
615 i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
616 if (IS_ERR(i2s->mclk)) {
617 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
618 return PTR_ERR(i2s->mclk);
619 }
620
621 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
622 regs = devm_ioremap_resource(&pdev->dev, res);
623 if (IS_ERR(regs))
624 return PTR_ERR(regs);
625
626 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
627 &rockchip_i2s_regmap_config);
628 if (IS_ERR(i2s->regmap)) {
629 dev_err(&pdev->dev,
630 "Failed to initialise managed register map\n");
631 return PTR_ERR(i2s->regmap);
632 }
633
634 i2s->playback_dma_data.addr = res->start + I2S_TXDR;
635 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
636 i2s->playback_dma_data.maxburst = 4;
637
638 i2s->capture_dma_data.addr = res->start + I2S_RXDR;
639 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
640 i2s->capture_dma_data.maxburst = 4;
641
642 dev_set_drvdata(&pdev->dev, i2s);
643
644 pm_runtime_enable(&pdev->dev);
645 if (!pm_runtime_enabled(&pdev->dev)) {
646 ret = i2s_runtime_resume(&pdev->dev);
647 if (ret)
648 goto err_pm_disable;
649 }
650
651 soc_dai = devm_kmemdup(&pdev->dev, &rockchip_i2s_dai,
652 sizeof(*soc_dai), GFP_KERNEL);
653 if (!soc_dai) {
654 ret = -ENOMEM;
655 goto err_pm_disable;
656 }
657
658 if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
659 if (val >= 2 && val <= 8)
660 soc_dai->playback.channels_max = val;
661 }
662
663 if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
664 if (val >= 2 && val <= 8)
665 soc_dai->capture.channels_max = val;
666 }
667
668 ret = devm_snd_soc_register_component(&pdev->dev,
669 &rockchip_i2s_component,
670 soc_dai, 1);
671
672 if (ret) {
673 dev_err(&pdev->dev, "Could not register DAI\n");
674 goto err_suspend;
675 }
676
677 ret = rockchip_pcm_platform_register(&pdev->dev);
678 if (ret) {
679 dev_err(&pdev->dev, "Could not register PCM\n");
680 goto err_suspend;
681 }
682
683 return 0;
684
685err_suspend:
686 if (!pm_runtime_status_suspended(&pdev->dev))
687 i2s_runtime_suspend(&pdev->dev);
688err_pm_disable:
689 pm_runtime_disable(&pdev->dev);
690
691 return ret;
692}
693
694static int rockchip_i2s_remove(struct platform_device *pdev)
695{
696 struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
697
698 pm_runtime_disable(&pdev->dev);
699 if (!pm_runtime_status_suspended(&pdev->dev))
700 i2s_runtime_suspend(&pdev->dev);
701
702 clk_disable_unprepare(i2s->hclk);
703
704 return 0;
705}
706
707static const struct dev_pm_ops rockchip_i2s_pm_ops = {
708 SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
709 NULL)
710};
711
712static struct platform_driver rockchip_i2s_driver = {
713 .probe = rockchip_i2s_probe,
714 .remove = rockchip_i2s_remove,
715 .driver = {
716 .name = DRV_NAME,
717 .of_match_table = of_match_ptr(rockchip_i2s_match),
718 .pm = &rockchip_i2s_pm_ops,
719 },
720};
721module_platform_driver(rockchip_i2s_driver);
722
723MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
724MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
725MODULE_LICENSE("GPL v2");
726MODULE_ALIAS("platform:" DRV_NAME);
727MODULE_DEVICE_TABLE(of, rockchip_i2s_match);
728
