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11#ifndef __MIPS_ASM_MIPS_CPS_H__
12# error Please include asm/mips-cps.h rather than asm/mips-cm.h
13#endif
14
15#ifndef __MIPS_ASM_MIPS_CM_H__
16#define __MIPS_ASM_MIPS_CM_H__
17
18#include <linux/bitops.h>
19#include <linux/errno.h>
20
21
22extern void __iomem *mips_gcr_base;
23
24
25extern void __iomem *mips_cm_l2sync_base;
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36
37extern phys_addr_t __mips_cm_phys_base(void);
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50
51extern int mips_cm_is64;
52
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54
55
56#ifdef CONFIG_MIPS_CM
57extern void mips_cm_error_report(void);
58#else
59static inline void mips_cm_error_report(void) {}
60#endif
61
62
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65
66
67
68#ifdef CONFIG_MIPS_CM
69extern int mips_cm_probe(void);
70#else
71static inline int mips_cm_probe(void)
72{
73 return -ENODEV;
74}
75#endif
76
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80
81
82static inline bool mips_cm_present(void)
83{
84#ifdef CONFIG_MIPS_CM
85 return mips_gcr_base != NULL;
86#else
87 return false;
88#endif
89}
90
91
92
93
94
95
96static inline bool mips_cm_has_l2sync(void)
97{
98#ifdef CONFIG_MIPS_CM
99 return mips_cm_l2sync_base != NULL;
100#else
101 return false;
102#endif
103}
104
105
106#define MIPS_CM_GCB_OFS 0x0000
107#define MIPS_CM_CLCB_OFS 0x2000
108#define MIPS_CM_COCB_OFS 0x4000
109#define MIPS_CM_GDB_OFS 0x6000
110
111
112#define MIPS_CM_GCR_SIZE 0x8000
113
114
115#define MIPS_CM_L2SYNC_SIZE 0x1000
116
117#define GCR_ACCESSOR_RO(sz, off, name) \
118 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_GCB_OFS + off, name) \
119 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)
120
121#define GCR_ACCESSOR_RW(sz, off, name) \
122 CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_GCB_OFS + off, name) \
123 CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)
124
125#define GCR_CX_ACCESSOR_RO(sz, off, name) \
126 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name) \
127 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)
128
129#define GCR_CX_ACCESSOR_RW(sz, off, name) \
130 CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name) \
131 CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)
132
133
134GCR_ACCESSOR_RO(64, 0x000, config)
135#define CM_GCR_CONFIG_CLUSTER_COH_CAPABLE BIT_ULL(43)
136#define CM_GCR_CONFIG_CLUSTER_ID GENMASK_ULL(39, 32)
137#define CM_GCR_CONFIG_NUM_CLUSTERS GENMASK(29, 23)
138#define CM_GCR_CONFIG_NUMIOCU GENMASK(15, 8)
139#define CM_GCR_CONFIG_PCORES GENMASK(7, 0)
140
141
142GCR_ACCESSOR_RW(64, 0x008, base)
143#define CM_GCR_BASE_GCRBASE GENMASK_ULL(47, 15)
144#define CM_GCR_BASE_CMDEFTGT GENMASK(1, 0)
145#define CM_GCR_BASE_CMDEFTGT_MEM 0
146#define CM_GCR_BASE_CMDEFTGT_RESERVED 1
147#define CM_GCR_BASE_CMDEFTGT_IOCU0 2
148#define CM_GCR_BASE_CMDEFTGT_IOCU1 3
149
150
151GCR_ACCESSOR_RW(32, 0x020, access)
152#define CM_GCR_ACCESS_ACCESSEN GENMASK(7, 0)
153
154
155GCR_ACCESSOR_RO(32, 0x030, rev)
156#define CM_GCR_REV_MAJOR GENMASK(15, 8)
157#define CM_GCR_REV_MINOR GENMASK(7, 0)
158
159#define CM_ENCODE_REV(major, minor) \
160 (((major) << __ffs(CM_GCR_REV_MAJOR)) | \
161 ((minor) << __ffs(CM_GCR_REV_MINOR)))
162
163#define CM_REV_CM2 CM_ENCODE_REV(6, 0)
164#define CM_REV_CM2_5 CM_ENCODE_REV(7, 0)
165#define CM_REV_CM3 CM_ENCODE_REV(8, 0)
166#define CM_REV_CM3_5 CM_ENCODE_REV(9, 0)
167
168
169GCR_ACCESSOR_RW(32, 0x038, err_control)
170#define CM_GCR_ERR_CONTROL_L2_ECC_EN BIT(1)
171#define CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT BIT(0)
172
173
174GCR_ACCESSOR_RW(64, 0x040, error_mask)
175
176
177GCR_ACCESSOR_RW(64, 0x048, error_cause)
178#define CM_GCR_ERROR_CAUSE_ERRTYPE GENMASK(31, 27)
179#define CM3_GCR_ERROR_CAUSE_ERRTYPE GENMASK_ULL(63, 58)
180#define CM_GCR_ERROR_CAUSE_ERRINFO GENMASK(26, 0)
181
182
183GCR_ACCESSOR_RW(64, 0x050, error_addr)
184
185
186GCR_ACCESSOR_RW(64, 0x058, error_mult)
187#define CM_GCR_ERROR_MULT_ERR2ND GENMASK(4, 0)
188
189
190GCR_ACCESSOR_RW(64, 0x070, l2_only_sync_base)
191#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE GENMASK(31, 12)
192#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN BIT(0)
193
194
195GCR_ACCESSOR_RW(64, 0x080, gic_base)
196#define CM_GCR_GIC_BASE_GICBASE GENMASK(31, 17)
197#define CM_GCR_GIC_BASE_GICEN BIT(0)
198
199
200GCR_ACCESSOR_RW(64, 0x088, cpc_base)
201#define CM_GCR_CPC_BASE_CPCBASE GENMASK(31, 15)
202#define CM_GCR_CPC_BASE_CPCEN BIT(0)
203
204
205GCR_ACCESSOR_RW(64, 0x090, reg0_base)
206GCR_ACCESSOR_RW(64, 0x0a0, reg1_base)
207GCR_ACCESSOR_RW(64, 0x0b0, reg2_base)
208GCR_ACCESSOR_RW(64, 0x0c0, reg3_base)
209#define CM_GCR_REGn_BASE_BASEADDR GENMASK(31, 16)
210
211
212GCR_ACCESSOR_RW(64, 0x098, reg0_mask)
213GCR_ACCESSOR_RW(64, 0x0a8, reg1_mask)
214GCR_ACCESSOR_RW(64, 0x0b8, reg2_mask)
215GCR_ACCESSOR_RW(64, 0x0c8, reg3_mask)
216#define CM_GCR_REGn_MASK_ADDRMASK GENMASK(31, 16)
217#define CM_GCR_REGn_MASK_CCAOVR GENMASK(7, 5)
218#define CM_GCR_REGn_MASK_CCAOVREN BIT(4)
219#define CM_GCR_REGn_MASK_DROPL2 BIT(2)
220#define CM_GCR_REGn_MASK_CMTGT GENMASK(1, 0)
221#define CM_GCR_REGn_MASK_CMTGT_DISABLED 0x0
222#define CM_GCR_REGn_MASK_CMTGT_MEM 0x1
223#define CM_GCR_REGn_MASK_CMTGT_IOCU0 0x2
224#define CM_GCR_REGn_MASK_CMTGT_IOCU1 0x3
225
226
227GCR_ACCESSOR_RO(32, 0x0d0, gic_status)
228#define CM_GCR_GIC_STATUS_EX BIT(0)
229
230
231GCR_ACCESSOR_RO(32, 0x0f0, cpc_status)
232#define CM_GCR_CPC_STATUS_EX BIT(0)
233
234
235GCR_ACCESSOR_RW(32, 0x130, l2_config)
236#define CM_GCR_L2_CONFIG_BYPASS BIT(20)
237#define CM_GCR_L2_CONFIG_SET_SIZE GENMASK(15, 12)
238#define CM_GCR_L2_CONFIG_LINE_SIZE GENMASK(11, 8)
239#define CM_GCR_L2_CONFIG_ASSOC GENMASK(7, 0)
240
241
242GCR_ACCESSOR_RO(32, 0x150, sys_config2)
243#define CM_GCR_SYS_CONFIG2_MAXVPW GENMASK(3, 0)
244
245
246GCR_ACCESSOR_RW(32, 0x300, l2_pft_control)
247#define CM_GCR_L2_PFT_CONTROL_PAGEMASK GENMASK(31, 12)
248#define CM_GCR_L2_PFT_CONTROL_PFTEN BIT(8)
249#define CM_GCR_L2_PFT_CONTROL_NPFT GENMASK(7, 0)
250
251
252GCR_ACCESSOR_RW(32, 0x308, l2_pft_control_b)
253#define CM_GCR_L2_PFT_CONTROL_B_CEN BIT(8)
254#define CM_GCR_L2_PFT_CONTROL_B_PORTID GENMASK(7, 0)
255
256
257GCR_ACCESSOR_RW(32, 0x620, l2sm_cop)
258#define CM_GCR_L2SM_COP_PRESENT BIT(31)
259#define CM_GCR_L2SM_COP_RESULT GENMASK(8, 6)
260#define CM_GCR_L2SM_COP_RESULT_DONTCARE 0
261#define CM_GCR_L2SM_COP_RESULT_DONE_OK 1
262#define CM_GCR_L2SM_COP_RESULT_DONE_ERROR 2
263#define CM_GCR_L2SM_COP_RESULT_ABORT_OK 3
264#define CM_GCR_L2SM_COP_RESULT_ABORT_ERROR 4
265#define CM_GCR_L2SM_COP_RUNNING BIT(5)
266#define CM_GCR_L2SM_COP_TYPE GENMASK(4, 2)
267#define CM_GCR_L2SM_COP_TYPE_IDX_WBINV 0
268#define CM_GCR_L2SM_COP_TYPE_IDX_STORETAG 1
269#define CM_GCR_L2SM_COP_TYPE_IDX_STORETAGDATA 2
270#define CM_GCR_L2SM_COP_TYPE_HIT_INV 4
271#define CM_GCR_L2SM_COP_TYPE_HIT_WBINV 5
272#define CM_GCR_L2SM_COP_TYPE_HIT_WB 6
273#define CM_GCR_L2SM_COP_TYPE_FETCHLOCK 7
274#define CM_GCR_L2SM_COP_CMD GENMASK(1, 0)
275#define CM_GCR_L2SM_COP_CMD_START 1
276#define CM_GCR_L2SM_COP_CMD_ABORT 3
277
278
279GCR_ACCESSOR_RW(64, 0x628, l2sm_tag_addr_cop)
280#define CM_GCR_L2SM_TAG_ADDR_COP_NUM_LINES GENMASK_ULL(63, 48)
281#define CM_GCR_L2SM_TAG_ADDR_COP_START_TAG GENMASK_ULL(47, 6)
282
283
284GCR_ACCESSOR_RW(64, 0x680, bev_base)
285
286
287GCR_CX_ACCESSOR_RW(32, 0x000, reset_release)
288
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290GCR_CX_ACCESSOR_RW(32, 0x008, coherence)
291#define CM_GCR_Cx_COHERENCE_COHDOMAINEN GENMASK(7, 0)
292#define CM3_GCR_Cx_COHERENCE_COHEN BIT(0)
293
294
295GCR_CX_ACCESSOR_RO(32, 0x010, config)
296#define CM_GCR_Cx_CONFIG_IOCUTYPE GENMASK(11, 10)
297#define CM_GCR_Cx_CONFIG_PVPE GENMASK(9, 0)
298
299
300GCR_CX_ACCESSOR_RW(32, 0x018, other)
301#define CM_GCR_Cx_OTHER_CORENUM GENMASK(31, 16)
302#define CM_GCR_Cx_OTHER_CLUSTER_EN BIT(31)
303#define CM_GCR_Cx_OTHER_GIC_EN BIT(30)
304#define CM_GCR_Cx_OTHER_BLOCK GENMASK(25, 24)
305#define CM_GCR_Cx_OTHER_BLOCK_LOCAL 0
306#define CM_GCR_Cx_OTHER_BLOCK_GLOBAL 1
307#define CM_GCR_Cx_OTHER_BLOCK_USER 2
308#define CM_GCR_Cx_OTHER_BLOCK_GLOBAL_HIGH 3
309#define CM_GCR_Cx_OTHER_CLUSTER GENMASK(21, 16)
310#define CM3_GCR_Cx_OTHER_CORE GENMASK(13, 8)
311#define CM_GCR_Cx_OTHER_CORE_CM 32
312#define CM3_GCR_Cx_OTHER_VP GENMASK(2, 0)
313
314
315GCR_CX_ACCESSOR_RW(32, 0x020, reset_base)
316#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE GENMASK(31, 12)
317
318
319GCR_CX_ACCESSOR_RO(32, 0x028, id)
320#define CM_GCR_Cx_ID_CLUSTER GENMASK(15, 8)
321#define CM_GCR_Cx_ID_CORE GENMASK(7, 0)
322
323
324GCR_CX_ACCESSOR_RW(32, 0x030, reset_ext_base)
325#define CM_GCR_Cx_RESET_EXT_BASE_EVARESET BIT(31)
326#define CM_GCR_Cx_RESET_EXT_BASE_UEB BIT(30)
327#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK GENMASK(27, 20)
328#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA GENMASK(7, 1)
329#define CM_GCR_Cx_RESET_EXT_BASE_PRESENT BIT(0)
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336
337static inline int mips_cm_l2sync(void)
338{
339 if (!mips_cm_has_l2sync())
340 return -ENODEV;
341
342 writel(0, mips_cm_l2sync_base);
343 return 0;
344}
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352static inline int mips_cm_revision(void)
353{
354 if (!mips_cm_present())
355 return 0;
356
357 return read_gcr_rev();
358}
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365
366static inline unsigned int mips_cm_max_vp_width(void)
367{
368 extern int smp_num_siblings;
369 uint32_t cfg;
370
371 if (mips_cm_revision() >= CM_REV_CM3)
372 return read_gcr_sys_config2() & CM_GCR_SYS_CONFIG2_MAXVPW;
373
374 if (mips_cm_present()) {
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379
380 cfg = read_gcr_cl_config() & CM_GCR_Cx_CONFIG_PVPE;
381 return (cfg >> __ffs(CM_GCR_Cx_CONFIG_PVPE)) + 1;
382 }
383
384 if (IS_ENABLED(CONFIG_SMP))
385 return smp_num_siblings;
386
387 return 1;
388}
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400static inline unsigned int mips_cm_vp_id(unsigned int cpu)
401{
402 unsigned int core = cpu_core(&cpu_data[cpu]);
403 unsigned int vp = cpu_vpe_id(&cpu_data[cpu]);
404
405 return (core * mips_cm_max_vp_width()) + vp;
406}
407
408#ifdef CONFIG_MIPS_CM
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428extern void mips_cm_lock_other(unsigned int cluster, unsigned int core,
429 unsigned int vp, unsigned int block);
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437extern void mips_cm_unlock_other(void);
438
439#else
440
441static inline void mips_cm_lock_other(unsigned int cluster, unsigned int core,
442 unsigned int vp, unsigned int block) { }
443static inline void mips_cm_unlock_other(void) { }
444
445#endif
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456static inline void mips_cm_lock_other_cpu(unsigned int cpu, unsigned int block)
457{
458 struct cpuinfo_mips *d = &cpu_data[cpu];
459
460 mips_cm_lock_other(cpu_cluster(d), cpu_core(d), cpu_vpe_id(d), block);
461}
462
463#endif
464