1/***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2012 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28#ifndef __CVMX_GPIO_DEFS_H__ 29#define __CVMX_GPIO_DEFS_H__ 30 31#define CVMX_GPIO_BIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8) 32#define CVMX_GPIO_BOOT_ENA (CVMX_ADD_IO_SEG(0x00010700000008A8ull)) 33#define CVMX_GPIO_CLK_GENX(offset) (CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8) 34#define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8) 35#define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull)) 36#define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull)) 37#define CVMX_GPIO_MULTI_CAST (CVMX_ADD_IO_SEG(0x00010700000008B0ull)) 38#define CVMX_GPIO_PIN_ENA (CVMX_ADD_IO_SEG(0x00010700000008B8ull)) 39#define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull)) 40#define CVMX_GPIO_TIM_CTL (CVMX_ADD_IO_SEG(0x00010700000008A0ull)) 41#define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull)) 42#define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull)) 43#define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16) 44 45union cvmx_gpio_bit_cfgx { 46 uint64_t u64; 47 struct cvmx_gpio_bit_cfgx_s { 48#ifdef __BIG_ENDIAN_BITFIELD 49 uint64_t reserved_21_63:42; 50 uint64_t output_sel:5; 51 uint64_t synce_sel:2; 52 uint64_t clk_gen:1; 53 uint64_t clk_sel:2; 54 uint64_t fil_sel:4; 55 uint64_t fil_cnt:4; 56 uint64_t int_type:1; 57 uint64_t int_en:1; 58 uint64_t rx_xor:1; 59 uint64_t tx_oe:1; 60#else 61 uint64_t tx_oe:1; 62 uint64_t rx_xor:1; 63 uint64_t int_en:1; 64 uint64_t int_type:1; 65 uint64_t fil_cnt:4; 66 uint64_t fil_sel:4; 67 uint64_t clk_sel:2; 68 uint64_t clk_gen:1; 69 uint64_t synce_sel:2; 70 uint64_t output_sel:5; 71 uint64_t reserved_21_63:42; 72#endif 73 } s; 74 struct cvmx_gpio_bit_cfgx_cn30xx { 75#ifdef __BIG_ENDIAN_BITFIELD 76 uint64_t reserved_12_63:52; 77 uint64_t fil_sel:4; 78 uint64_t fil_cnt:4; 79 uint64_t int_type:1; 80 uint64_t int_en:1; 81 uint64_t rx_xor:1; 82 uint64_t tx_oe:1; 83#else 84 uint64_t tx_oe:1; 85 uint64_t rx_xor:1; 86 uint64_t int_en:1; 87 uint64_t int_type:1; 88 uint64_t fil_cnt:4; 89 uint64_t fil_sel:4; 90 uint64_t reserved_12_63:52; 91#endif 92 } cn30xx; 93 struct cvmx_gpio_bit_cfgx_cn30xx cn31xx; 94 struct cvmx_gpio_bit_cfgx_cn30xx cn38xx; 95 struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2; 96 struct cvmx_gpio_bit_cfgx_cn30xx cn50xx; 97 struct cvmx_gpio_bit_cfgx_cn52xx { 98#ifdef __BIG_ENDIAN_BITFIELD 99 uint64_t reserved_15_63:49; 100 uint64_t clk_gen:1; 101 uint64_t clk_sel:2; 102 uint64_t fil_sel:4; 103 uint64_t fil_cnt:4; 104 uint64_t int_type:1; 105 uint64_t int_en:1; 106 uint64_t rx_xor:1; 107 uint64_t tx_oe:1; 108#else 109 uint64_t tx_oe:1; 110 uint64_t rx_xor:1; 111 uint64_t int_en:1; 112 uint64_t int_type:1; 113 uint64_t fil_cnt:4; 114 uint64_t fil_sel:4; 115 uint64_t clk_sel:2; 116 uint64_t clk_gen:1; 117 uint64_t reserved_15_63:49; 118#endif 119 } cn52xx; 120 struct cvmx_gpio_bit_cfgx_cn52xx cn52xxp1; 121 struct cvmx_gpio_bit_cfgx_cn52xx cn56xx; 122 struct cvmx_gpio_bit_cfgx_cn52xx cn56xxp1; 123 struct cvmx_gpio_bit_cfgx_cn30xx cn58xx; 124 struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1; 125 struct cvmx_gpio_bit_cfgx_s cn61xx; 126 struct cvmx_gpio_bit_cfgx_s cn63xx; 127 struct cvmx_gpio_bit_cfgx_s cn63xxp1; 128 struct cvmx_gpio_bit_cfgx_s cn66xx; 129 struct cvmx_gpio_bit_cfgx_s cn68xx; 130 struct cvmx_gpio_bit_cfgx_s cn68xxp1; 131 struct cvmx_gpio_bit_cfgx_s cn70xx; 132 struct cvmx_gpio_bit_cfgx_s cn73xx; 133 struct cvmx_gpio_bit_cfgx_s cnf71xx; 134}; 135 136union cvmx_gpio_boot_ena { 137 uint64_t u64; 138 struct cvmx_gpio_boot_ena_s { 139#ifdef __BIG_ENDIAN_BITFIELD 140 uint64_t reserved_12_63:52; 141 uint64_t boot_ena:4; 142 uint64_t reserved_0_7:8; 143#else 144 uint64_t reserved_0_7:8; 145 uint64_t boot_ena:4; 146 uint64_t reserved_12_63:52; 147#endif 148 } s; 149 struct cvmx_gpio_boot_ena_s cn30xx; 150 struct cvmx_gpio_boot_ena_s cn31xx; 151 struct cvmx_gpio_boot_ena_s cn50xx; 152}; 153 154union cvmx_gpio_clk_genx { 155 uint64_t u64; 156 struct cvmx_gpio_clk_genx_s { 157#ifdef __BIG_ENDIAN_BITFIELD 158 uint64_t reserved_32_63:32; 159 uint64_t n:32; 160#else 161 uint64_t n:32; 162 uint64_t reserved_32_63:32; 163#endif 164 } s; 165 struct cvmx_gpio_clk_genx_s cn52xx; 166 struct cvmx_gpio_clk_genx_s cn52xxp1; 167 struct cvmx_gpio_clk_genx_s cn56xx; 168 struct cvmx_gpio_clk_genx_s cn56xxp1; 169 struct cvmx_gpio_clk_genx_s cn61xx; 170 struct cvmx_gpio_clk_genx_s cn63xx; 171 struct cvmx_gpio_clk_genx_s cn63xxp1; 172 struct cvmx_gpio_clk_genx_s cn66xx; 173 struct cvmx_gpio_clk_genx_s cn68xx; 174 struct cvmx_gpio_clk_genx_s cn68xxp1; 175 struct cvmx_gpio_clk_genx_s cnf71xx; 176}; 177 178union cvmx_gpio_clk_qlmx { 179 uint64_t u64; 180 struct cvmx_gpio_clk_qlmx_s { 181#ifdef __BIG_ENDIAN_BITFIELD 182 uint64_t reserved_11_63:53; 183 uint64_t qlm_sel:3; 184 uint64_t reserved_3_7:5; 185 uint64_t div:1; 186 uint64_t lane_sel:2; 187#else 188 uint64_t lane_sel:2; 189 uint64_t div:1; 190 uint64_t reserved_3_7:5; 191 uint64_t qlm_sel:3; 192 uint64_t reserved_11_63:53; 193#endif 194 } s; 195 struct cvmx_gpio_clk_qlmx_cn61xx { 196#ifdef __BIG_ENDIAN_BITFIELD 197 uint64_t reserved_10_63:54; 198 uint64_t qlm_sel:2; 199 uint64_t reserved_3_7:5; 200 uint64_t div:1; 201 uint64_t lane_sel:2; 202#else 203 uint64_t lane_sel:2; 204 uint64_t div:1; 205 uint64_t reserved_3_7:5; 206 uint64_t qlm_sel:2; 207 uint64_t reserved_10_63:54; 208#endif 209 } cn61xx; 210 struct cvmx_gpio_clk_qlmx_cn63xx { 211#ifdef __BIG_ENDIAN_BITFIELD 212 uint64_t reserved_3_63:61; 213 uint64_t div:1; 214 uint64_t lane_sel:2; 215#else 216 uint64_t lane_sel:2; 217 uint64_t div:1; 218 uint64_t reserved_3_63:61; 219#endif 220 } cn63xx; 221 struct cvmx_gpio_clk_qlmx_cn63xx cn63xxp1; 222 struct cvmx_gpio_clk_qlmx_cn61xx cn66xx; 223 struct cvmx_gpio_clk_qlmx_s cn68xx; 224 struct cvmx_gpio_clk_qlmx_s cn68xxp1; 225 struct cvmx_gpio_clk_qlmx_cn61xx cnf71xx; 226}; 227 228union cvmx_gpio_dbg_ena { 229 uint64_t u64; 230 struct cvmx_gpio_dbg_ena_s { 231#ifdef __BIG_ENDIAN_BITFIELD 232 uint64_t reserved_21_63:43; 233 uint64_t dbg_ena:21; 234#else 235 uint64_t dbg_ena:21; 236 uint64_t reserved_21_63:43; 237#endif 238 } s; 239 struct cvmx_gpio_dbg_ena_s cn30xx; 240 struct cvmx_gpio_dbg_ena_s cn31xx; 241 struct cvmx_gpio_dbg_ena_s cn50xx; 242}; 243 244union cvmx_gpio_int_clr { 245 uint64_t u64; 246 struct cvmx_gpio_int_clr_s { 247#ifdef __BIG_ENDIAN_BITFIELD 248 uint64_t reserved_16_63:48; 249 uint64_t type:16; 250#else 251 uint64_t type:16; 252 uint64_t reserved_16_63:48; 253#endif 254 } s; 255 struct cvmx_gpio_int_clr_s cn30xx; 256 struct cvmx_gpio_int_clr_s cn31xx; 257 struct cvmx_gpio_int_clr_s cn38xx; 258 struct cvmx_gpio_int_clr_s cn38xxp2; 259 struct cvmx_gpio_int_clr_s cn50xx; 260 struct cvmx_gpio_int_clr_s cn52xx; 261 struct cvmx_gpio_int_clr_s cn52xxp1; 262 struct cvmx_gpio_int_clr_s cn56xx; 263 struct cvmx_gpio_int_clr_s cn56xxp1; 264 struct cvmx_gpio_int_clr_s cn58xx; 265 struct cvmx_gpio_int_clr_s cn58xxp1; 266 struct cvmx_gpio_int_clr_s cn61xx; 267 struct cvmx_gpio_int_clr_s cn63xx; 268 struct cvmx_gpio_int_clr_s cn63xxp1; 269 struct cvmx_gpio_int_clr_s cn66xx; 270 struct cvmx_gpio_int_clr_s cn68xx; 271 struct cvmx_gpio_int_clr_s cn68xxp1; 272 struct cvmx_gpio_int_clr_s cnf71xx; 273}; 274 275union cvmx_gpio_multi_cast { 276 uint64_t u64; 277 struct cvmx_gpio_multi_cast_s { 278#ifdef __BIG_ENDIAN_BITFIELD 279 uint64_t reserved_1_63:63; 280 uint64_t en:1; 281#else 282 uint64_t en:1; 283 uint64_t reserved_1_63:63; 284#endif 285 } s; 286 struct cvmx_gpio_multi_cast_s cn61xx; 287 struct cvmx_gpio_multi_cast_s cnf71xx; 288}; 289 290union cvmx_gpio_pin_ena { 291 uint64_t u64; 292 struct cvmx_gpio_pin_ena_s { 293#ifdef __BIG_ENDIAN_BITFIELD 294 uint64_t reserved_20_63:44; 295 uint64_t ena19:1; 296 uint64_t ena18:1; 297 uint64_t reserved_0_17:18; 298#else 299 uint64_t reserved_0_17:18; 300 uint64_t ena18:1; 301 uint64_t ena19:1; 302 uint64_t reserved_20_63:44; 303#endif 304 } s; 305 struct cvmx_gpio_pin_ena_s cn66xx; 306}; 307 308union cvmx_gpio_rx_dat { 309 uint64_t u64; 310 struct cvmx_gpio_rx_dat_s { 311#ifdef __BIG_ENDIAN_BITFIELD 312 uint64_t reserved_24_63:40; 313 uint64_t dat:24; 314#else 315 uint64_t dat:24; 316 uint64_t reserved_24_63:40; 317#endif 318 } s; 319 struct cvmx_gpio_rx_dat_s cn30xx; 320 struct cvmx_gpio_rx_dat_s cn31xx; 321 struct cvmx_gpio_rx_dat_cn38xx { 322#ifdef __BIG_ENDIAN_BITFIELD 323 uint64_t reserved_16_63:48; 324 uint64_t dat:16; 325#else 326 uint64_t dat:16; 327 uint64_t reserved_16_63:48; 328#endif 329 } cn38xx; 330 struct cvmx_gpio_rx_dat_cn38xx cn38xxp2; 331 struct cvmx_gpio_rx_dat_s cn50xx; 332 struct cvmx_gpio_rx_dat_cn38xx cn52xx; 333 struct cvmx_gpio_rx_dat_cn38xx cn52xxp1; 334 struct cvmx_gpio_rx_dat_cn38xx cn56xx; 335 struct cvmx_gpio_rx_dat_cn38xx cn56xxp1; 336 struct cvmx_gpio_rx_dat_cn38xx cn58xx; 337 struct cvmx_gpio_rx_dat_cn38xx cn58xxp1; 338 struct cvmx_gpio_rx_dat_cn61xx { 339#ifdef __BIG_ENDIAN_BITFIELD 340 uint64_t reserved_20_63:44; 341 uint64_t dat:20; 342#else 343 uint64_t dat:20; 344 uint64_t reserved_20_63:44; 345#endif 346 } cn61xx; 347 struct cvmx_gpio_rx_dat_cn38xx cn63xx; 348 struct cvmx_gpio_rx_dat_cn38xx cn63xxp1; 349 struct cvmx_gpio_rx_dat_cn61xx cn66xx; 350 struct cvmx_gpio_rx_dat_cn38xx cn68xx; 351 struct cvmx_gpio_rx_dat_cn38xx cn68xxp1; 352 struct cvmx_gpio_rx_dat_cn61xx cnf71xx; 353}; 354 355union cvmx_gpio_tim_ctl { 356 uint64_t u64; 357 struct cvmx_gpio_tim_ctl_s { 358#ifdef __BIG_ENDIAN_BITFIELD 359 uint64_t reserved_4_63:60; 360 uint64_t sel:4; 361#else 362 uint64_t sel:4; 363 uint64_t reserved_4_63:60; 364#endif 365 } s; 366 struct cvmx_gpio_tim_ctl_s cn68xx; 367 struct cvmx_gpio_tim_ctl_s cn68xxp1; 368}; 369 370union cvmx_gpio_tx_clr { 371 uint64_t u64; 372 struct cvmx_gpio_tx_clr_s { 373#ifdef __BIG_ENDIAN_BITFIELD 374 uint64_t reserved_24_63:40; 375 uint64_t clr:24; 376#else 377 uint64_t clr:24; 378 uint64_t reserved_24_63:40; 379#endif 380 } s; 381 struct cvmx_gpio_tx_clr_s cn30xx; 382 struct cvmx_gpio_tx_clr_s cn31xx; 383 struct cvmx_gpio_tx_clr_cn38xx { 384#ifdef __BIG_ENDIAN_BITFIELD 385 uint64_t reserved_16_63:48; 386 uint64_t clr:16; 387#else 388 uint64_t clr:16; 389 uint64_t reserved_16_63:48; 390#endif 391 } cn38xx; 392 struct cvmx_gpio_tx_clr_cn38xx cn38xxp2; 393 struct cvmx_gpio_tx_clr_s cn50xx; 394 struct cvmx_gpio_tx_clr_cn38xx cn52xx; 395 struct cvmx_gpio_tx_clr_cn38xx cn52xxp1; 396 struct cvmx_gpio_tx_clr_cn38xx cn56xx; 397 struct cvmx_gpio_tx_clr_cn38xx cn56xxp1; 398 struct cvmx_gpio_tx_clr_cn38xx cn58xx; 399 struct cvmx_gpio_tx_clr_cn38xx cn58xxp1; 400 struct cvmx_gpio_tx_clr_cn61xx { 401#ifdef __BIG_ENDIAN_BITFIELD 402 uint64_t reserved_20_63:44; 403 uint64_t clr:20; 404#else 405 uint64_t clr:20; 406 uint64_t reserved_20_63:44; 407#endif 408 } cn61xx; 409 struct cvmx_gpio_tx_clr_cn38xx cn63xx; 410 struct cvmx_gpio_tx_clr_cn38xx cn63xxp1; 411 struct cvmx_gpio_tx_clr_cn61xx cn66xx; 412 struct cvmx_gpio_tx_clr_cn38xx cn68xx; 413 struct cvmx_gpio_tx_clr_cn38xx cn68xxp1; 414 struct cvmx_gpio_tx_clr_cn61xx cnf71xx; 415}; 416 417union cvmx_gpio_tx_set { 418 uint64_t u64; 419 struct cvmx_gpio_tx_set_s { 420#ifdef __BIG_ENDIAN_BITFIELD 421 uint64_t reserved_24_63:40; 422 uint64_t set:24; 423#else 424 uint64_t set:24; 425 uint64_t reserved_24_63:40; 426#endif 427 } s; 428 struct cvmx_gpio_tx_set_s cn30xx; 429 struct cvmx_gpio_tx_set_s cn31xx; 430 struct cvmx_gpio_tx_set_cn38xx { 431#ifdef __BIG_ENDIAN_BITFIELD 432 uint64_t reserved_16_63:48; 433 uint64_t set:16; 434#else 435 uint64_t set:16; 436 uint64_t reserved_16_63:48; 437#endif 438 } cn38xx; 439 struct cvmx_gpio_tx_set_cn38xx cn38xxp2; 440 struct cvmx_gpio_tx_set_s cn50xx; 441 struct cvmx_gpio_tx_set_cn38xx cn52xx; 442 struct cvmx_gpio_tx_set_cn38xx cn52xxp1; 443 struct cvmx_gpio_tx_set_cn38xx cn56xx; 444 struct cvmx_gpio_tx_set_cn38xx cn56xxp1; 445 struct cvmx_gpio_tx_set_cn38xx cn58xx; 446 struct cvmx_gpio_tx_set_cn38xx cn58xxp1; 447 struct cvmx_gpio_tx_set_cn61xx { 448#ifdef __BIG_ENDIAN_BITFIELD 449 uint64_t reserved_20_63:44; 450 uint64_t set:20; 451#else 452 uint64_t set:20; 453 uint64_t reserved_20_63:44; 454#endif 455 } cn61xx; 456 struct cvmx_gpio_tx_set_cn38xx cn63xx; 457 struct cvmx_gpio_tx_set_cn38xx cn63xxp1; 458 struct cvmx_gpio_tx_set_cn61xx cn66xx; 459 struct cvmx_gpio_tx_set_cn38xx cn68xx; 460 struct cvmx_gpio_tx_set_cn38xx cn68xxp1; 461 struct cvmx_gpio_tx_set_cn61xx cnf71xx; 462}; 463 464union cvmx_gpio_xbit_cfgx { 465 uint64_t u64; 466 struct cvmx_gpio_xbit_cfgx_s { 467#ifdef __BIG_ENDIAN_BITFIELD 468 uint64_t reserved_17_63:47; 469 uint64_t synce_sel:2; 470 uint64_t clk_gen:1; 471 uint64_t clk_sel:2; 472 uint64_t fil_sel:4; 473 uint64_t fil_cnt:4; 474 uint64_t int_type:1; 475 uint64_t int_en:1; 476 uint64_t rx_xor:1; 477 uint64_t tx_oe:1; 478#else 479 uint64_t tx_oe:1; 480 uint64_t rx_xor:1; 481 uint64_t int_en:1; 482 uint64_t int_type:1; 483 uint64_t fil_cnt:4; 484 uint64_t fil_sel:4; 485 uint64_t clk_sel:2; 486 uint64_t clk_gen:1; 487 uint64_t synce_sel:2; 488 uint64_t reserved_17_63:47; 489#endif 490 } s; 491 struct cvmx_gpio_xbit_cfgx_cn30xx { 492#ifdef __BIG_ENDIAN_BITFIELD 493 uint64_t reserved_12_63:52; 494 uint64_t fil_sel:4; 495 uint64_t fil_cnt:4; 496 uint64_t reserved_2_3:2; 497 uint64_t rx_xor:1; 498 uint64_t tx_oe:1; 499#else 500 uint64_t tx_oe:1; 501 uint64_t rx_xor:1; 502 uint64_t reserved_2_3:2; 503 uint64_t fil_cnt:4; 504 uint64_t fil_sel:4; 505 uint64_t reserved_12_63:52; 506#endif 507 } cn30xx; 508 struct cvmx_gpio_xbit_cfgx_cn30xx cn31xx; 509 struct cvmx_gpio_xbit_cfgx_cn30xx cn50xx; 510 struct cvmx_gpio_xbit_cfgx_s cn61xx; 511 struct cvmx_gpio_xbit_cfgx_s cn66xx; 512 struct cvmx_gpio_xbit_cfgx_s cnf71xx; 513}; 514 515#endif 516