linux/arch/powerpc/mm/book3s64/slb.c
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   1/*
   2 * PowerPC64 SLB support.
   3 *
   4 * Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
   5 * Based on earlier code written by:
   6 * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
   7 *    Copyright (c) 2001 Dave Engebretsen
   8 * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
   9 *
  10 *
  11 *      This program is free software; you can redistribute it and/or
  12 *      modify it under the terms of the GNU General Public License
  13 *      as published by the Free Software Foundation; either version
  14 *      2 of the License, or (at your option) any later version.
  15 */
  16
  17#include <asm/pgtable.h>
  18#include <asm/mmu.h>
  19#include <asm/mmu_context.h>
  20#include <asm/paca.h>
  21#include <asm/cputable.h>
  22#include <asm/cacheflush.h>
  23#include <asm/smp.h>
  24#include <linux/compiler.h>
  25#include <linux/context_tracking.h>
  26#include <linux/mm_types.h>
  27
  28#include <asm/udbg.h>
  29#include <asm/code-patching.h>
  30
  31enum slb_index {
  32        LINEAR_INDEX    = 0, /* Kernel linear map  (0xc000000000000000) */
  33        VMALLOC_INDEX   = 1, /* Kernel virtual map (0xd000000000000000) */
  34        KSTACK_INDEX    = 2, /* Kernel stack map */
  35};
  36
  37extern void slb_allocate(unsigned long ea);
  38
  39#define slb_esid_mask(ssize)    \
  40        (((ssize) == MMU_SEGSIZE_256M)? ESID_MASK: ESID_MASK_1T)
  41
  42static inline unsigned long mk_esid_data(unsigned long ea, int ssize,
  43                                         enum slb_index index)
  44{
  45        return (ea & slb_esid_mask(ssize)) | SLB_ESID_V | index;
  46}
  47
  48static inline unsigned long mk_vsid_data(unsigned long ea, int ssize,
  49                                         unsigned long flags)
  50{
  51        return (get_kernel_vsid(ea, ssize) << slb_vsid_shift(ssize)) | flags |
  52                ((unsigned long) ssize << SLB_VSID_SSIZE_SHIFT);
  53}
  54
  55static inline void slb_shadow_update(unsigned long ea, int ssize,
  56                                     unsigned long flags,
  57                                     enum slb_index index)
  58{
  59        struct slb_shadow *p = get_slb_shadow();
  60
  61        /*
  62         * Clear the ESID first so the entry is not valid while we are
  63         * updating it.  No write barriers are needed here, provided
  64         * we only update the current CPU's SLB shadow buffer.
  65         */
  66        WRITE_ONCE(p->save_area[index].esid, 0);
  67        WRITE_ONCE(p->save_area[index].vsid, cpu_to_be64(mk_vsid_data(ea, ssize, flags)));
  68        WRITE_ONCE(p->save_area[index].esid, cpu_to_be64(mk_esid_data(ea, ssize, index)));
  69}
  70
  71static inline void slb_shadow_clear(enum slb_index index)
  72{
  73        WRITE_ONCE(get_slb_shadow()->save_area[index].esid, cpu_to_be64(index));
  74}
  75
  76static inline void create_shadowed_slbe(unsigned long ea, int ssize,
  77                                        unsigned long flags,
  78                                        enum slb_index index)
  79{
  80        /*
  81         * Updating the shadow buffer before writing the SLB ensures
  82         * we don't get a stale entry here if we get preempted by PHYP
  83         * between these two statements.
  84         */
  85        slb_shadow_update(ea, ssize, flags, index);
  86
  87        asm volatile("slbmte  %0,%1" :
  88                     : "r" (mk_vsid_data(ea, ssize, flags)),
  89                       "r" (mk_esid_data(ea, ssize, index))
  90                     : "memory" );
  91}
  92
  93/*
  94 * Insert bolted entries into SLB (which may not be empty, so don't clear
  95 * slb_cache_ptr).
  96 */
  97void __slb_restore_bolted_realmode(void)
  98{
  99        struct slb_shadow *p = get_slb_shadow();
 100        enum slb_index index;
 101
 102         /* No isync needed because realmode. */
 103        for (index = 0; index < SLB_NUM_BOLTED; index++) {
 104                asm volatile("slbmte  %0,%1" :
 105                     : "r" (be64_to_cpu(p->save_area[index].vsid)),
 106                       "r" (be64_to_cpu(p->save_area[index].esid)));
 107        }
 108}
 109
 110/*
 111 * Insert the bolted entries into an empty SLB.
 112 * This is not the same as rebolt because the bolted segments are not
 113 * changed, just loaded from the shadow area.
 114 */
 115void slb_restore_bolted_realmode(void)
 116{
 117        __slb_restore_bolted_realmode();
 118        get_paca()->slb_cache_ptr = 0;
 119}
 120
 121/*
 122 * This flushes all SLB entries including 0, so it must be realmode.
 123 */
 124void slb_flush_all_realmode(void)
 125{
 126        /*
 127         * This flushes all SLB entries including 0, so it must be realmode.
 128         */
 129        asm volatile("slbmte %0,%0; slbia" : : "r" (0));
 130}
 131
 132static void __slb_flush_and_rebolt(void)
 133{
 134        /* If you change this make sure you change SLB_NUM_BOLTED
 135         * and PR KVM appropriately too. */
 136        unsigned long linear_llp, vmalloc_llp, lflags, vflags;
 137        unsigned long ksp_esid_data, ksp_vsid_data;
 138
 139        linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
 140        vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp;
 141        lflags = SLB_VSID_KERNEL | linear_llp;
 142        vflags = SLB_VSID_KERNEL | vmalloc_llp;
 143
 144        ksp_esid_data = mk_esid_data(get_paca()->kstack, mmu_kernel_ssize, KSTACK_INDEX);
 145        if ((ksp_esid_data & ~0xfffffffUL) <= PAGE_OFFSET) {
 146                ksp_esid_data &= ~SLB_ESID_V;
 147                ksp_vsid_data = 0;
 148                slb_shadow_clear(KSTACK_INDEX);
 149        } else {
 150                /* Update stack entry; others don't change */
 151                slb_shadow_update(get_paca()->kstack, mmu_kernel_ssize, lflags, KSTACK_INDEX);
 152                ksp_vsid_data =
 153                        be64_to_cpu(get_slb_shadow()->save_area[KSTACK_INDEX].vsid);
 154        }
 155
 156        /* We need to do this all in asm, so we're sure we don't touch
 157         * the stack between the slbia and rebolting it. */
 158        asm volatile("isync\n"
 159                     "slbia\n"
 160                     /* Slot 1 - first VMALLOC segment */
 161                     "slbmte    %0,%1\n"
 162                     /* Slot 2 - kernel stack */
 163                     "slbmte    %2,%3\n"
 164                     "isync"
 165                     :: "r"(mk_vsid_data(VMALLOC_START, mmu_kernel_ssize, vflags)),
 166                        "r"(mk_esid_data(VMALLOC_START, mmu_kernel_ssize, VMALLOC_INDEX)),
 167                        "r"(ksp_vsid_data),
 168                        "r"(ksp_esid_data)
 169                     : "memory");
 170}
 171
 172void slb_flush_and_rebolt(void)
 173{
 174
 175        WARN_ON(!irqs_disabled());
 176
 177        /*
 178         * We can't take a PMU exception in the following code, so hard
 179         * disable interrupts.
 180         */
 181        hard_irq_disable();
 182
 183        __slb_flush_and_rebolt();
 184        get_paca()->slb_cache_ptr = 0;
 185}
 186
 187void slb_save_contents(struct slb_entry *slb_ptr)
 188{
 189        int i;
 190        unsigned long e, v;
 191
 192        /* Save slb_cache_ptr value. */
 193        get_paca()->slb_save_cache_ptr = get_paca()->slb_cache_ptr;
 194
 195        if (!slb_ptr)
 196                return;
 197
 198        for (i = 0; i < mmu_slb_size; i++) {
 199                asm volatile("slbmfee  %0,%1" : "=r" (e) : "r" (i));
 200                asm volatile("slbmfev  %0,%1" : "=r" (v) : "r" (i));
 201                slb_ptr->esid = e;
 202                slb_ptr->vsid = v;
 203                slb_ptr++;
 204        }
 205}
 206
 207void slb_dump_contents(struct slb_entry *slb_ptr)
 208{
 209        int i, n;
 210        unsigned long e, v;
 211        unsigned long llp;
 212
 213        if (!slb_ptr)
 214                return;
 215
 216        pr_err("SLB contents of cpu 0x%x\n", smp_processor_id());
 217        pr_err("Last SLB entry inserted at slot %lld\n", get_paca()->stab_rr);
 218
 219        for (i = 0; i < mmu_slb_size; i++) {
 220                e = slb_ptr->esid;
 221                v = slb_ptr->vsid;
 222                slb_ptr++;
 223
 224                if (!e && !v)
 225                        continue;
 226
 227                pr_err("%02d %016lx %016lx\n", i, e, v);
 228
 229                if (!(e & SLB_ESID_V)) {
 230                        pr_err("\n");
 231                        continue;
 232                }
 233                llp = v & SLB_VSID_LLP;
 234                if (v & SLB_VSID_B_1T) {
 235                        pr_err("  1T  ESID=%9lx  VSID=%13lx LLP:%3lx\n",
 236                               GET_ESID_1T(e),
 237                               (v & ~SLB_VSID_B) >> SLB_VSID_SHIFT_1T, llp);
 238                } else {
 239                        pr_err(" 256M ESID=%9lx  VSID=%13lx LLP:%3lx\n",
 240                               GET_ESID(e),
 241                               (v & ~SLB_VSID_B) >> SLB_VSID_SHIFT, llp);
 242                }
 243        }
 244        pr_err("----------------------------------\n");
 245
 246        /* Dump slb cache entires as well. */
 247        pr_err("SLB cache ptr value = %d\n", get_paca()->slb_save_cache_ptr);
 248        pr_err("Valid SLB cache entries:\n");
 249        n = min_t(int, get_paca()->slb_save_cache_ptr, SLB_CACHE_ENTRIES);
 250        for (i = 0; i < n; i++)
 251                pr_err("%02d EA[0-35]=%9x\n", i, get_paca()->slb_cache[i]);
 252        pr_err("Rest of SLB cache entries:\n");
 253        for (i = n; i < SLB_CACHE_ENTRIES; i++)
 254                pr_err("%02d EA[0-35]=%9x\n", i, get_paca()->slb_cache[i]);
 255}
 256
 257void slb_vmalloc_update(void)
 258{
 259        unsigned long vflags;
 260
 261        vflags = SLB_VSID_KERNEL | mmu_psize_defs[mmu_vmalloc_psize].sllp;
 262        slb_shadow_update(VMALLOC_START, mmu_kernel_ssize, vflags, VMALLOC_INDEX);
 263        slb_flush_and_rebolt();
 264}
 265
 266/* Helper function to compare esids.  There are four cases to handle.
 267 * 1. The system is not 1T segment size capable.  Use the GET_ESID compare.
 268 * 2. The system is 1T capable, both addresses are < 1T, use the GET_ESID compare.
 269 * 3. The system is 1T capable, only one of the two addresses is > 1T.  This is not a match.
 270 * 4. The system is 1T capable, both addresses are > 1T, use the GET_ESID_1T macro to compare.
 271 */
 272static inline int esids_match(unsigned long addr1, unsigned long addr2)
 273{
 274        int esid_1t_count;
 275
 276        /* System is not 1T segment size capable. */
 277        if (!mmu_has_feature(MMU_FTR_1T_SEGMENT))
 278                return (GET_ESID(addr1) == GET_ESID(addr2));
 279
 280        esid_1t_count = (((addr1 >> SID_SHIFT_1T) != 0) +
 281                                ((addr2 >> SID_SHIFT_1T) != 0));
 282
 283        /* both addresses are < 1T */
 284        if (esid_1t_count == 0)
 285                return (GET_ESID(addr1) == GET_ESID(addr2));
 286
 287        /* One address < 1T, the other > 1T.  Not a match */
 288        if (esid_1t_count == 1)
 289                return 0;
 290
 291        /* Both addresses are > 1T. */
 292        return (GET_ESID_1T(addr1) == GET_ESID_1T(addr2));
 293}
 294
 295/* Flush all user entries from the segment table of the current processor. */
 296void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
 297{
 298        unsigned long offset;
 299        unsigned long slbie_data = 0;
 300        unsigned long pc = KSTK_EIP(tsk);
 301        unsigned long stack = KSTK_ESP(tsk);
 302        unsigned long exec_base;
 303
 304        /*
 305         * We need interrupts hard-disabled here, not just soft-disabled,
 306         * so that a PMU interrupt can't occur, which might try to access
 307         * user memory (to get a stack trace) and possible cause an SLB miss
 308         * which would update the slb_cache/slb_cache_ptr fields in the PACA.
 309         */
 310        hard_irq_disable();
 311        offset = get_paca()->slb_cache_ptr;
 312        if (!mmu_has_feature(MMU_FTR_NO_SLBIE_B) &&
 313            offset <= SLB_CACHE_ENTRIES) {
 314                int i;
 315                asm volatile("isync" : : : "memory");
 316                for (i = 0; i < offset; i++) {
 317                        slbie_data = (unsigned long)get_paca()->slb_cache[i]
 318                                << SID_SHIFT; /* EA */
 319                        slbie_data |= user_segment_size(slbie_data)
 320                                << SLBIE_SSIZE_SHIFT;
 321                        slbie_data |= SLBIE_C; /* C set for user addresses */
 322                        asm volatile("slbie %0" : : "r" (slbie_data));
 323                }
 324                asm volatile("isync" : : : "memory");
 325        } else {
 326                __slb_flush_and_rebolt();
 327        }
 328
 329        /* Workaround POWER5 < DD2.1 issue */
 330        if (offset == 1 || offset > SLB_CACHE_ENTRIES)
 331                asm volatile("slbie %0" : : "r" (slbie_data));
 332
 333        get_paca()->slb_cache_ptr = 0;
 334        copy_mm_to_paca(mm);
 335
 336        /*
 337         * preload some userspace segments into the SLB.
 338         * Almost all 32 and 64bit PowerPC executables are linked at
 339         * 0x10000000 so it makes sense to preload this segment.
 340         */
 341        exec_base = 0x10000000;
 342
 343        if (is_kernel_addr(pc) || is_kernel_addr(stack) ||
 344            is_kernel_addr(exec_base))
 345                return;
 346
 347        slb_allocate(pc);
 348
 349        if (!esids_match(pc, stack))
 350                slb_allocate(stack);
 351
 352        if (!esids_match(pc, exec_base) &&
 353            !esids_match(stack, exec_base))
 354                slb_allocate(exec_base);
 355}
 356
 357static inline void patch_slb_encoding(unsigned int *insn_addr,
 358                                      unsigned int immed)
 359{
 360
 361        /*
 362         * This function patches either an li or a cmpldi instruction with
 363         * a new immediate value. This relies on the fact that both li
 364         * (which is actually addi) and cmpldi both take a 16-bit immediate
 365         * value, and it is situated in the same location in the instruction,
 366         * ie. bits 16-31 (Big endian bit order) or the lower 16 bits.
 367         * The signedness of the immediate operand differs between the two
 368         * instructions however this code is only ever patching a small value,
 369         * much less than 1 << 15, so we can get away with it.
 370         * To patch the value we read the existing instruction, clear the
 371         * immediate value, and or in our new value, then write the instruction
 372         * back.
 373         */
 374        unsigned int insn = (*insn_addr & 0xffff0000) | immed;
 375        patch_instruction((struct ppc_inst *)insn_addr, ppc_inst(insn));
 376}
 377
 378extern u32 slb_miss_kernel_load_linear[];
 379extern u32 slb_miss_kernel_load_io[];
 380extern u32 slb_compare_rr_to_size[];
 381extern u32 slb_miss_kernel_load_vmemmap[];
 382
 383void slb_set_size(u16 size)
 384{
 385        if (mmu_slb_size == size)
 386                return;
 387
 388        mmu_slb_size = size;
 389        patch_slb_encoding(slb_compare_rr_to_size, mmu_slb_size);
 390}
 391
 392void slb_initialize(void)
 393{
 394        unsigned long linear_llp, vmalloc_llp, io_llp;
 395        unsigned long lflags, vflags;
 396        static int slb_encoding_inited;
 397#ifdef CONFIG_SPARSEMEM_VMEMMAP
 398        unsigned long vmemmap_llp;
 399#endif
 400
 401        /* Prepare our SLB miss handler based on our page size */
 402        linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
 403        io_llp = mmu_psize_defs[mmu_io_psize].sllp;
 404        vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp;
 405        get_paca()->vmalloc_sllp = SLB_VSID_KERNEL | vmalloc_llp;
 406#ifdef CONFIG_SPARSEMEM_VMEMMAP
 407        vmemmap_llp = mmu_psize_defs[mmu_vmemmap_psize].sllp;
 408#endif
 409        if (!slb_encoding_inited) {
 410                slb_encoding_inited = 1;
 411                patch_slb_encoding(slb_miss_kernel_load_linear,
 412                                   SLB_VSID_KERNEL | linear_llp);
 413                patch_slb_encoding(slb_miss_kernel_load_io,
 414                                   SLB_VSID_KERNEL | io_llp);
 415                patch_slb_encoding(slb_compare_rr_to_size,
 416                                   mmu_slb_size);
 417
 418                pr_devel("SLB: linear  LLP = %04lx\n", linear_llp);
 419                pr_devel("SLB: io      LLP = %04lx\n", io_llp);
 420
 421#ifdef CONFIG_SPARSEMEM_VMEMMAP
 422                patch_slb_encoding(slb_miss_kernel_load_vmemmap,
 423                                   SLB_VSID_KERNEL | vmemmap_llp);
 424                pr_devel("SLB: vmemmap LLP = %04lx\n", vmemmap_llp);
 425#endif
 426        }
 427
 428        get_paca()->stab_rr = SLB_NUM_BOLTED;
 429
 430        lflags = SLB_VSID_KERNEL | linear_llp;
 431        vflags = SLB_VSID_KERNEL | vmalloc_llp;
 432
 433        /* Invalidate the entire SLB (even entry 0) & all the ERATS */
 434        asm volatile("isync":::"memory");
 435        asm volatile("slbmte  %0,%0"::"r" (0) : "memory");
 436        asm volatile("isync; slbia; isync":::"memory");
 437        create_shadowed_slbe(PAGE_OFFSET, mmu_kernel_ssize, lflags, LINEAR_INDEX);
 438        create_shadowed_slbe(VMALLOC_START, mmu_kernel_ssize, vflags, VMALLOC_INDEX);
 439
 440        /* 
 441         * For the boot cpu, we're running on the stack in init_thread_union,
 442         * which is in the first segment of the linear mapping, and also
 443         * get_paca()->kstack hasn't been initialized yet.
 444         * For secondary cpus, we need to bolt the kernel stack entry now.
 445         */
 446        slb_shadow_clear(KSTACK_INDEX);
 447        if (raw_smp_processor_id() != boot_cpuid &&
 448            (get_paca()->kstack & slb_esid_mask(mmu_kernel_ssize)) > PAGE_OFFSET)
 449                create_shadowed_slbe(get_paca()->kstack,
 450                                     mmu_kernel_ssize, lflags, KSTACK_INDEX);
 451
 452        asm volatile("isync":::"memory");
 453}
 454
 455static void insert_slb_entry(unsigned long vsid, unsigned long ea,
 456                             int bpsize, int ssize)
 457{
 458        unsigned long flags, vsid_data, esid_data;
 459        enum slb_index index;
 460        int slb_cache_index;
 461
 462        /*
 463         * We are irq disabled, hence should be safe to access PACA.
 464         */
 465        VM_WARN_ON(!irqs_disabled());
 466
 467        /*
 468         * We can't take a PMU exception in the following code, so hard
 469         * disable interrupts.
 470         */
 471        hard_irq_disable();
 472
 473        index = get_paca()->stab_rr;
 474
 475        /*
 476         * simple round-robin replacement of slb starting at SLB_NUM_BOLTED.
 477         */
 478        if (index < (mmu_slb_size - 1))
 479                index++;
 480        else
 481                index = SLB_NUM_BOLTED;
 482
 483        get_paca()->stab_rr = index;
 484
 485        flags = SLB_VSID_USER | mmu_psize_defs[bpsize].sllp;
 486        vsid_data = (vsid << slb_vsid_shift(ssize)) | flags |
 487                    ((unsigned long) ssize << SLB_VSID_SSIZE_SHIFT);
 488        esid_data = mk_esid_data(ea, ssize, index);
 489
 490        /*
 491         * No need for an isync before or after this slbmte. The exception
 492         * we enter with and the rfid we exit with are context synchronizing.
 493         * Also we only handle user segments here.
 494         */
 495        asm volatile("slbmte %0, %1" : : "r" (vsid_data), "r" (esid_data)
 496                     : "memory");
 497
 498        /*
 499         * Now update slb cache entries
 500         */
 501        slb_cache_index = get_paca()->slb_cache_ptr;
 502        if (slb_cache_index < SLB_CACHE_ENTRIES) {
 503                /*
 504                 * We have space in slb cache for optimized switch_slb().
 505                 * Top 36 bits from esid_data as per ISA
 506                 */
 507                get_paca()->slb_cache[slb_cache_index++] = esid_data >> 28;
 508                get_paca()->slb_cache_ptr++;
 509        } else {
 510                /*
 511                 * Our cache is full and the current cache content strictly
 512                 * doesn't indicate the active SLB conents. Bump the ptr
 513                 * so that switch_slb() will ignore the cache.
 514                 */
 515                get_paca()->slb_cache_ptr = SLB_CACHE_ENTRIES + 1;
 516        }
 517}
 518
 519static void handle_multi_context_slb_miss(int context_id, unsigned long ea)
 520{
 521        struct mm_struct *mm = current->mm;
 522        unsigned long vsid;
 523        int bpsize;
 524
 525        /*
 526         * We are always above 1TB, hence use high user segment size.
 527         */
 528        vsid = get_vsid(context_id, ea, mmu_highuser_ssize);
 529        bpsize = get_slice_psize(mm, ea);
 530        insert_slb_entry(vsid, ea, bpsize, mmu_highuser_ssize);
 531}
 532
 533void slb_miss_large_addr(struct pt_regs *regs)
 534{
 535        enum ctx_state prev_state = exception_enter();
 536        unsigned long ea = regs->dar;
 537        int context;
 538
 539        if (REGION_ID(ea) != USER_REGION_ID)
 540                goto slb_bad_addr;
 541
 542        /*
 543         * Are we beyound what the page table layout supports ?
 544         */
 545        if ((ea & ~REGION_MASK) >= H_PGTABLE_RANGE)
 546                goto slb_bad_addr;
 547
 548        /* Lower address should have been handled by asm code */
 549        if (ea < (1UL << MAX_EA_BITS_PER_CONTEXT))
 550                goto slb_bad_addr;
 551
 552        /*
 553         * consider this as bad access if we take a SLB miss
 554         * on an address above addr limit.
 555         */
 556        if (ea >= current->mm->context.slb_addr_limit)
 557                goto slb_bad_addr;
 558
 559        context = get_ea_context(&current->mm->context, ea);
 560        if (!context)
 561                goto slb_bad_addr;
 562
 563        handle_multi_context_slb_miss(context, ea);
 564        exception_exit(prev_state);
 565        return;
 566
 567slb_bad_addr:
 568        if (user_mode(regs))
 569                _exception(SIGSEGV, regs, SEGV_BNDERR, ea);
 570        else
 571                bad_page_fault(regs, ea, SIGSEGV);
 572        exception_exit(prev_state);
 573}
 574