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23#include <linux/err.h>
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/platform_device.h>
27#include <linux/io.h>
28#include <linux/of.h>
29
30#include <soc/tegra/ahb.h>
31
32#define DRV_NAME "tegra-ahb"
33
34#define AHB_ARBITRATION_DISABLE 0x04
35#define AHB_ARBITRATION_PRIORITY_CTRL 0x08
36#define AHB_PRIORITY_WEIGHT(x) (((x) & 0x7) << 29)
37#define PRIORITY_SELECT_USB BIT(6)
38#define PRIORITY_SELECT_USB2 BIT(18)
39#define PRIORITY_SELECT_USB3 BIT(17)
40
41#define AHB_GIZMO_AHB_MEM 0x10
42#define ENB_FAST_REARBITRATE BIT(2)
43#define DONT_SPLIT_AHB_WR BIT(7)
44
45#define AHB_GIZMO_APB_DMA 0x14
46#define AHB_GIZMO_IDE 0x1c
47#define AHB_GIZMO_USB 0x20
48#define AHB_GIZMO_AHB_XBAR_BRIDGE 0x24
49#define AHB_GIZMO_CPU_AHB_BRIDGE 0x28
50#define AHB_GIZMO_COP_AHB_BRIDGE 0x2c
51#define AHB_GIZMO_XBAR_APB_CTLR 0x30
52#define AHB_GIZMO_VCP_AHB_BRIDGE 0x34
53#define AHB_GIZMO_NAND 0x40
54#define AHB_GIZMO_SDMMC4 0x48
55#define AHB_GIZMO_XIO 0x4c
56#define AHB_GIZMO_BSEV 0x64
57#define AHB_GIZMO_BSEA 0x74
58#define AHB_GIZMO_NOR 0x78
59#define AHB_GIZMO_USB2 0x7c
60#define AHB_GIZMO_USB3 0x80
61#define IMMEDIATE BIT(18)
62
63#define AHB_GIZMO_SDMMC1 0x84
64#define AHB_GIZMO_SDMMC2 0x88
65#define AHB_GIZMO_SDMMC3 0x8c
66#define AHB_MEM_PREFETCH_CFG_X 0xdc
67#define AHB_ARBITRATION_XBAR_CTRL 0xe0
68#define AHB_MEM_PREFETCH_CFG3 0xe4
69#define AHB_MEM_PREFETCH_CFG4 0xe8
70#define AHB_MEM_PREFETCH_CFG1 0xf0
71#define AHB_MEM_PREFETCH_CFG2 0xf4
72#define PREFETCH_ENB BIT(31)
73#define MST_ID(x) (((x) & 0x1f) << 26)
74#define AHBDMA_MST_ID MST_ID(5)
75#define USB_MST_ID MST_ID(6)
76#define USB2_MST_ID MST_ID(18)
77#define USB3_MST_ID MST_ID(17)
78#define ADDR_BNDRY(x) (((x) & 0xf) << 21)
79#define INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
80
81#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID 0xfc
82
83#define AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE BIT(17)
84
85
86
87
88
89
90
91
92
93#define INCORRECT_BASE_ADDR_LOW_BYTE 0x4
94
95static struct platform_driver tegra_ahb_driver;
96
97static const u32 tegra_ahb_gizmo[] = {
98 AHB_ARBITRATION_DISABLE,
99 AHB_ARBITRATION_PRIORITY_CTRL,
100 AHB_GIZMO_AHB_MEM,
101 AHB_GIZMO_APB_DMA,
102 AHB_GIZMO_IDE,
103 AHB_GIZMO_USB,
104 AHB_GIZMO_AHB_XBAR_BRIDGE,
105 AHB_GIZMO_CPU_AHB_BRIDGE,
106 AHB_GIZMO_COP_AHB_BRIDGE,
107 AHB_GIZMO_XBAR_APB_CTLR,
108 AHB_GIZMO_VCP_AHB_BRIDGE,
109 AHB_GIZMO_NAND,
110 AHB_GIZMO_SDMMC4,
111 AHB_GIZMO_XIO,
112 AHB_GIZMO_BSEV,
113 AHB_GIZMO_BSEA,
114 AHB_GIZMO_NOR,
115 AHB_GIZMO_USB2,
116 AHB_GIZMO_USB3,
117 AHB_GIZMO_SDMMC1,
118 AHB_GIZMO_SDMMC2,
119 AHB_GIZMO_SDMMC3,
120 AHB_MEM_PREFETCH_CFG_X,
121 AHB_ARBITRATION_XBAR_CTRL,
122 AHB_MEM_PREFETCH_CFG3,
123 AHB_MEM_PREFETCH_CFG4,
124 AHB_MEM_PREFETCH_CFG1,
125 AHB_MEM_PREFETCH_CFG2,
126 AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID,
127};
128
129struct tegra_ahb {
130 void __iomem *regs;
131 struct device *dev;
132 u32 ctx[0];
133};
134
135static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset)
136{
137 return readl(ahb->regs + offset);
138}
139
140static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset)
141{
142 writel(value, ahb->regs + offset);
143}
144
145#ifdef CONFIG_TEGRA_IOMMU_SMMU
146int tegra_ahb_enable_smmu(struct device_node *dn)
147{
148 struct device *dev;
149 u32 val;
150 struct tegra_ahb *ahb;
151
152 dev = driver_find_device_by_of_node(&tegra_ahb_driver.driver, dn);
153 if (!dev)
154 return -EPROBE_DEFER;
155 ahb = dev_get_drvdata(dev);
156 val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL);
157 val |= AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE;
158 gizmo_writel(ahb, val, AHB_ARBITRATION_XBAR_CTRL);
159 return 0;
160}
161EXPORT_SYMBOL(tegra_ahb_enable_smmu);
162#endif
163
164#ifdef CONFIG_PM
165static int tegra_ahb_suspend(struct device *dev)
166{
167 int i;
168 struct tegra_ahb *ahb = dev_get_drvdata(dev);
169
170 for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
171 ahb->ctx[i] = gizmo_readl(ahb, tegra_ahb_gizmo[i]);
172 return 0;
173}
174
175static int tegra_ahb_resume(struct device *dev)
176{
177 int i;
178 struct tegra_ahb *ahb = dev_get_drvdata(dev);
179
180 for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
181 gizmo_writel(ahb, ahb->ctx[i], tegra_ahb_gizmo[i]);
182 return 0;
183}
184#endif
185
186static UNIVERSAL_DEV_PM_OPS(tegra_ahb_pm,
187 tegra_ahb_suspend,
188 tegra_ahb_resume, NULL);
189
190static void tegra_ahb_gizmo_init(struct tegra_ahb *ahb)
191{
192 u32 val;
193
194 val = gizmo_readl(ahb, AHB_GIZMO_AHB_MEM);
195 val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
196 gizmo_writel(ahb, val, AHB_GIZMO_AHB_MEM);
197
198 val = gizmo_readl(ahb, AHB_GIZMO_USB);
199 val |= IMMEDIATE;
200 gizmo_writel(ahb, val, AHB_GIZMO_USB);
201
202 val = gizmo_readl(ahb, AHB_GIZMO_USB2);
203 val |= IMMEDIATE;
204 gizmo_writel(ahb, val, AHB_GIZMO_USB2);
205
206 val = gizmo_readl(ahb, AHB_GIZMO_USB3);
207 val |= IMMEDIATE;
208 gizmo_writel(ahb, val, AHB_GIZMO_USB3);
209
210 val = gizmo_readl(ahb, AHB_ARBITRATION_PRIORITY_CTRL);
211 val |= PRIORITY_SELECT_USB |
212 PRIORITY_SELECT_USB2 |
213 PRIORITY_SELECT_USB3 |
214 AHB_PRIORITY_WEIGHT(7);
215 gizmo_writel(ahb, val, AHB_ARBITRATION_PRIORITY_CTRL);
216
217 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG1);
218 val &= ~MST_ID(~0);
219 val |= PREFETCH_ENB |
220 AHBDMA_MST_ID |
221 ADDR_BNDRY(0xc) |
222 INACTIVITY_TIMEOUT(0x1000);
223 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG1);
224
225 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG2);
226 val &= ~MST_ID(~0);
227 val |= PREFETCH_ENB |
228 USB_MST_ID |
229 ADDR_BNDRY(0xc) |
230 INACTIVITY_TIMEOUT(0x1000);
231 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG2);
232
233 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG3);
234 val &= ~MST_ID(~0);
235 val |= PREFETCH_ENB |
236 USB3_MST_ID |
237 ADDR_BNDRY(0xc) |
238 INACTIVITY_TIMEOUT(0x1000);
239 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG3);
240
241 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG4);
242 val &= ~MST_ID(~0);
243 val |= PREFETCH_ENB |
244 USB2_MST_ID |
245 ADDR_BNDRY(0xc) |
246 INACTIVITY_TIMEOUT(0x1000);
247 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG4);
248}
249
250static int tegra_ahb_probe(struct platform_device *pdev)
251{
252 struct resource *res;
253 struct tegra_ahb *ahb;
254 size_t bytes;
255
256 bytes = sizeof(*ahb) + sizeof(u32) * ARRAY_SIZE(tegra_ahb_gizmo);
257 ahb = devm_kzalloc(&pdev->dev, bytes, GFP_KERNEL);
258 if (!ahb)
259 return -ENOMEM;
260
261 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
262
263
264 if (res &&
265 (res->start & INCORRECT_BASE_ADDR_LOW_BYTE) ==
266 INCORRECT_BASE_ADDR_LOW_BYTE) {
267 dev_warn(&pdev->dev, "incorrect AHB base address in DT data - enabling workaround\n");
268 res->start -= INCORRECT_BASE_ADDR_LOW_BYTE;
269 }
270
271 ahb->regs = devm_ioremap_resource(&pdev->dev, res);
272 if (IS_ERR(ahb->regs))
273 return PTR_ERR(ahb->regs);
274
275 ahb->dev = &pdev->dev;
276 platform_set_drvdata(pdev, ahb);
277 tegra_ahb_gizmo_init(ahb);
278 return 0;
279}
280
281static const struct of_device_id tegra_ahb_of_match[] = {
282 { .compatible = "nvidia,tegra30-ahb", },
283 { .compatible = "nvidia,tegra20-ahb", },
284 {},
285};
286
287static struct platform_driver tegra_ahb_driver = {
288 .probe = tegra_ahb_probe,
289 .driver = {
290 .name = DRV_NAME,
291 .of_match_table = tegra_ahb_of_match,
292 .pm = &tegra_ahb_pm,
293 },
294};
295module_platform_driver(tegra_ahb_driver);
296
297MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
298MODULE_DESCRIPTION("Tegra AHB driver");
299MODULE_LICENSE("GPL v2");
300MODULE_ALIAS("platform:" DRV_NAME);
301
