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17#include <linux/acpi.h>
18#include <linux/dmi.h>
19#include <linux/adxl.h>
20#include <acpi/nfit.h>
21#include <asm/mce.h>
22#include "edac_module.h"
23#include "skx_common.h"
24
25static const char * const component_names[] = {
26 [INDEX_SOCKET] = "ProcessorSocketId",
27 [INDEX_MEMCTRL] = "MemoryControllerId",
28 [INDEX_CHANNEL] = "ChannelId",
29 [INDEX_DIMM] = "DimmSlotId",
30};
31
32static int component_indices[ARRAY_SIZE(component_names)];
33static int adxl_component_count;
34static const char * const *adxl_component_names;
35static u64 *adxl_values;
36static char *adxl_msg;
37
38static char skx_msg[MSG_SIZE];
39static skx_decode_f skx_decode;
40static u64 skx_tolm, skx_tohm;
41static LIST_HEAD(dev_edac_list);
42
43int __init skx_adxl_get(void)
44{
45 const char * const *names;
46 int i, j;
47
48 names = adxl_get_component_names();
49 if (!names) {
50 skx_printk(KERN_NOTICE, "No firmware support for address translation.\n");
51 return -ENODEV;
52 }
53
54 for (i = 0; i < INDEX_MAX; i++) {
55 for (j = 0; names[j]; j++) {
56 if (!strcmp(component_names[i], names[j])) {
57 component_indices[i] = j;
58 break;
59 }
60 }
61
62 if (!names[j])
63 goto err;
64 }
65
66 adxl_component_names = names;
67 while (*names++)
68 adxl_component_count++;
69
70 adxl_values = kcalloc(adxl_component_count, sizeof(*adxl_values),
71 GFP_KERNEL);
72 if (!adxl_values) {
73 adxl_component_count = 0;
74 return -ENOMEM;
75 }
76
77 adxl_msg = kzalloc(MSG_SIZE, GFP_KERNEL);
78 if (!adxl_msg) {
79 adxl_component_count = 0;
80 kfree(adxl_values);
81 return -ENOMEM;
82 }
83
84 return 0;
85err:
86 skx_printk(KERN_ERR, "'%s' is not matched from DSM parameters: ",
87 component_names[i]);
88 for (j = 0; names[j]; j++)
89 skx_printk(KERN_CONT, "%s ", names[j]);
90 skx_printk(KERN_CONT, "\n");
91
92 return -ENODEV;
93}
94
95void __exit skx_adxl_put(void)
96{
97 kfree(adxl_values);
98 kfree(adxl_msg);
99}
100
101static bool skx_adxl_decode(struct decoded_addr *res)
102{
103 int i, len = 0;
104
105 if (res->addr >= skx_tohm || (res->addr >= skx_tolm &&
106 res->addr < BIT_ULL(32))) {
107 edac_dbg(0, "Address 0x%llx out of range\n", res->addr);
108 return false;
109 }
110
111 if (adxl_decode(res->addr, adxl_values)) {
112 edac_dbg(0, "Failed to decode 0x%llx\n", res->addr);
113 return false;
114 }
115
116 res->socket = (int)adxl_values[component_indices[INDEX_SOCKET]];
117 res->imc = (int)adxl_values[component_indices[INDEX_MEMCTRL]];
118 res->channel = (int)adxl_values[component_indices[INDEX_CHANNEL]];
119 res->dimm = (int)adxl_values[component_indices[INDEX_DIMM]];
120
121 for (i = 0; i < adxl_component_count; i++) {
122 if (adxl_values[i] == ~0x0ull)
123 continue;
124
125 len += snprintf(adxl_msg + len, MSG_SIZE - len, " %s:0x%llx",
126 adxl_component_names[i], adxl_values[i]);
127 if (MSG_SIZE - len <= 0)
128 break;
129 }
130
131 return true;
132}
133
134void skx_set_decode(skx_decode_f decode)
135{
136 skx_decode = decode;
137}
138
139int skx_get_src_id(struct skx_dev *d, int off, u8 *id)
140{
141 u32 reg;
142
143 if (pci_read_config_dword(d->util_all, off, ®)) {
144 skx_printk(KERN_ERR, "Failed to read src id\n");
145 return -ENODEV;
146 }
147
148 *id = GET_BITFIELD(reg, 12, 14);
149 return 0;
150}
151
152int skx_get_node_id(struct skx_dev *d, u8 *id)
153{
154 u32 reg;
155
156 if (pci_read_config_dword(d->util_all, 0xf4, ®)) {
157 skx_printk(KERN_ERR, "Failed to read node id\n");
158 return -ENODEV;
159 }
160
161 *id = GET_BITFIELD(reg, 0, 2);
162 return 0;
163}
164
165static int get_width(u32 mtr)
166{
167 switch (GET_BITFIELD(mtr, 8, 9)) {
168 case 0:
169 return DEV_X4;
170 case 1:
171 return DEV_X8;
172 case 2:
173 return DEV_X16;
174 }
175 return DEV_UNKNOWN;
176}
177
178
179
180
181
182
183int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list)
184{
185 struct pci_dev *pdev, *prev;
186 struct skx_dev *d;
187 u32 reg;
188 int ndev = 0;
189
190 prev = NULL;
191 for (;;) {
192 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, cfg->decs_did, prev);
193 if (!pdev)
194 break;
195 ndev++;
196 d = kzalloc(sizeof(*d), GFP_KERNEL);
197 if (!d) {
198 pci_dev_put(pdev);
199 return -ENOMEM;
200 }
201
202 if (pci_read_config_dword(pdev, cfg->busno_cfg_offset, ®)) {
203 kfree(d);
204 pci_dev_put(pdev);
205 skx_printk(KERN_ERR, "Failed to read bus idx\n");
206 return -ENODEV;
207 }
208
209 d->bus[0] = GET_BITFIELD(reg, 0, 7);
210 d->bus[1] = GET_BITFIELD(reg, 8, 15);
211 if (cfg->type == SKX) {
212 d->seg = pci_domain_nr(pdev->bus);
213 d->bus[2] = GET_BITFIELD(reg, 16, 23);
214 d->bus[3] = GET_BITFIELD(reg, 24, 31);
215 } else {
216 d->seg = GET_BITFIELD(reg, 16, 23);
217 }
218
219 edac_dbg(2, "busses: 0x%x, 0x%x, 0x%x, 0x%x\n",
220 d->bus[0], d->bus[1], d->bus[2], d->bus[3]);
221 list_add_tail(&d->list, &dev_edac_list);
222 prev = pdev;
223 }
224
225 if (list)
226 *list = &dev_edac_list;
227 return ndev;
228}
229
230int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm)
231{
232 struct pci_dev *pdev;
233 u32 reg;
234
235 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, did, NULL);
236 if (!pdev) {
237 edac_dbg(2, "Can't get tolm/tohm\n");
238 return -ENODEV;
239 }
240
241 if (pci_read_config_dword(pdev, off[0], ®)) {
242 skx_printk(KERN_ERR, "Failed to read tolm\n");
243 goto fail;
244 }
245 skx_tolm = reg;
246
247 if (pci_read_config_dword(pdev, off[1], ®)) {
248 skx_printk(KERN_ERR, "Failed to read lower tohm\n");
249 goto fail;
250 }
251 skx_tohm = reg;
252
253 if (pci_read_config_dword(pdev, off[2], ®)) {
254 skx_printk(KERN_ERR, "Failed to read upper tohm\n");
255 goto fail;
256 }
257 skx_tohm |= (u64)reg << 32;
258
259 pci_dev_put(pdev);
260 *tolm = skx_tolm;
261 *tohm = skx_tohm;
262 edac_dbg(2, "tolm = 0x%llx tohm = 0x%llx\n", skx_tolm, skx_tohm);
263 return 0;
264fail:
265 pci_dev_put(pdev);
266 return -ENODEV;
267}
268
269static int skx_get_dimm_attr(u32 reg, int lobit, int hibit, int add,
270 int minval, int maxval, const char *name)
271{
272 u32 val = GET_BITFIELD(reg, lobit, hibit);
273
274 if (val < minval || val > maxval) {
275 edac_dbg(2, "bad %s = %d (raw=0x%x)\n", name, val, reg);
276 return -EINVAL;
277 }
278 return val + add;
279}
280
281#define numrank(reg) skx_get_dimm_attr(reg, 12, 13, 0, 0, 2, "ranks")
282#define numrow(reg) skx_get_dimm_attr(reg, 2, 4, 12, 1, 6, "rows")
283#define numcol(reg) skx_get_dimm_attr(reg, 0, 1, 10, 0, 2, "cols")
284
285int skx_get_dimm_info(u32 mtr, u32 amap, struct dimm_info *dimm,
286 struct skx_imc *imc, int chan, int dimmno)
287{
288 int banks = 16, ranks, rows, cols, npages;
289 u64 size;
290
291 ranks = numrank(mtr);
292 rows = numrow(mtr);
293 cols = numcol(mtr);
294
295
296
297
298 size = ((1ull << (rows + cols + ranks)) * banks) >> (20 - 3);
299 npages = MiB_TO_PAGES(size);
300
301 edac_dbg(0, "mc#%d: channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: 0x%x, col: 0x%x\n",
302 imc->mc, chan, dimmno, size, npages,
303 banks, 1 << ranks, rows, cols);
304
305 imc->chan[chan].dimms[dimmno].close_pg = GET_BITFIELD(mtr, 0, 0);
306 imc->chan[chan].dimms[dimmno].bank_xor_enable = GET_BITFIELD(mtr, 9, 9);
307 imc->chan[chan].dimms[dimmno].fine_grain_bank = GET_BITFIELD(amap, 0, 0);
308 imc->chan[chan].dimms[dimmno].rowbits = rows;
309 imc->chan[chan].dimms[dimmno].colbits = cols;
310
311 dimm->nr_pages = npages;
312 dimm->grain = 32;
313 dimm->dtype = get_width(mtr);
314 dimm->mtype = MEM_DDR4;
315 dimm->edac_mode = EDAC_SECDED;
316 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
317 imc->src_id, imc->lmc, chan, dimmno);
318
319 return 1;
320}
321
322int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc,
323 int chan, int dimmno, const char *mod_str)
324{
325 int smbios_handle;
326 u32 dev_handle;
327 u16 flags;
328 u64 size = 0;
329
330 dev_handle = ACPI_NFIT_BUILD_DEVICE_HANDLE(dimmno, chan, imc->lmc,
331 imc->src_id, 0);
332
333 smbios_handle = nfit_get_smbios_id(dev_handle, &flags);
334 if (smbios_handle == -EOPNOTSUPP) {
335 pr_warn_once("%s: Can't find size of NVDIMM. Try enabling CONFIG_ACPI_NFIT\n", mod_str);
336 goto unknown_size;
337 }
338
339 if (smbios_handle < 0) {
340 skx_printk(KERN_ERR, "Can't find handle for NVDIMM ADR=0x%x\n", dev_handle);
341 goto unknown_size;
342 }
343
344 if (flags & ACPI_NFIT_MEM_MAP_FAILED) {
345 skx_printk(KERN_ERR, "NVDIMM ADR=0x%x is not mapped\n", dev_handle);
346 goto unknown_size;
347 }
348
349 size = dmi_memdev_size(smbios_handle);
350 if (size == ~0ull)
351 skx_printk(KERN_ERR, "Can't find size for NVDIMM ADR=0x%x/SMBIOS=0x%x\n",
352 dev_handle, smbios_handle);
353
354unknown_size:
355 dimm->nr_pages = size >> PAGE_SHIFT;
356 dimm->grain = 32;
357 dimm->dtype = DEV_UNKNOWN;
358 dimm->mtype = MEM_NVDIMM;
359 dimm->edac_mode = EDAC_SECDED;
360
361 edac_dbg(0, "mc#%d: channel %d, dimm %d, %llu MiB (%u pages)\n",
362 imc->mc, chan, dimmno, size >> 20, dimm->nr_pages);
363
364 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
365 imc->src_id, imc->lmc, chan, dimmno);
366
367 return (size == 0 || size == ~0ull) ? 0 : 1;
368}
369
370int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev,
371 const char *ctl_name, const char *mod_str,
372 get_dimm_config_f get_dimm_config)
373{
374 struct mem_ctl_info *mci;
375 struct edac_mc_layer layers[2];
376 struct skx_pvt *pvt;
377 int rc;
378
379
380 layers[0].type = EDAC_MC_LAYER_CHANNEL;
381 layers[0].size = NUM_CHANNELS;
382 layers[0].is_virt_csrow = false;
383 layers[1].type = EDAC_MC_LAYER_SLOT;
384 layers[1].size = NUM_DIMMS;
385 layers[1].is_virt_csrow = true;
386 mci = edac_mc_alloc(imc->mc, ARRAY_SIZE(layers), layers,
387 sizeof(struct skx_pvt));
388
389 if (unlikely(!mci))
390 return -ENOMEM;
391
392 edac_dbg(0, "MC#%d: mci = %p\n", imc->mc, mci);
393
394
395 imc->mci = mci;
396 pvt = mci->pvt_info;
397 pvt->imc = imc;
398
399 mci->ctl_name = kasprintf(GFP_KERNEL, "%s#%d IMC#%d", ctl_name,
400 imc->node_id, imc->lmc);
401 if (!mci->ctl_name) {
402 rc = -ENOMEM;
403 goto fail0;
404 }
405
406 mci->mtype_cap = MEM_FLAG_DDR4 | MEM_FLAG_NVDIMM;
407 mci->edac_ctl_cap = EDAC_FLAG_NONE;
408 mci->edac_cap = EDAC_FLAG_NONE;
409 mci->mod_name = mod_str;
410 mci->dev_name = pci_name(pdev);
411 mci->ctl_page_to_phys = NULL;
412
413 rc = get_dimm_config(mci);
414 if (rc < 0)
415 goto fail;
416
417
418 mci->pdev = &pdev->dev;
419
420
421 if (unlikely(edac_mc_add_mc(mci))) {
422 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
423 rc = -EINVAL;
424 goto fail;
425 }
426
427 return 0;
428
429fail:
430 kfree(mci->ctl_name);
431fail0:
432 edac_mc_free(mci);
433 imc->mci = NULL;
434 return rc;
435}
436
437static void skx_unregister_mci(struct skx_imc *imc)
438{
439 struct mem_ctl_info *mci = imc->mci;
440
441 if (!mci)
442 return;
443
444 edac_dbg(0, "MC%d: mci = %p\n", imc->mc, mci);
445
446
447 edac_mc_del_mc(mci->pdev);
448
449 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
450 kfree(mci->ctl_name);
451 edac_mc_free(mci);
452}
453
454static struct mem_ctl_info *get_mci(int src_id, int lmc)
455{
456 struct skx_dev *d;
457
458 if (lmc > NUM_IMC - 1) {
459 skx_printk(KERN_ERR, "Bad lmc %d\n", lmc);
460 return NULL;
461 }
462
463 list_for_each_entry(d, &dev_edac_list, list) {
464 if (d->imc[0].src_id == src_id)
465 return d->imc[lmc].mci;
466 }
467
468 skx_printk(KERN_ERR, "No mci for src_id %d lmc %d\n", src_id, lmc);
469 return NULL;
470}
471
472static void skx_mce_output_error(struct mem_ctl_info *mci,
473 const struct mce *m,
474 struct decoded_addr *res)
475{
476 enum hw_event_mc_err_type tp_event;
477 char *type, *optype;
478 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
479 bool overflow = GET_BITFIELD(m->status, 62, 62);
480 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
481 bool recoverable;
482 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
483 u32 mscod = GET_BITFIELD(m->status, 16, 31);
484 u32 errcode = GET_BITFIELD(m->status, 0, 15);
485 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
486
487 recoverable = GET_BITFIELD(m->status, 56, 56);
488
489 if (uncorrected_error) {
490 core_err_cnt = 1;
491 if (ripv) {
492 type = "FATAL";
493 tp_event = HW_EVENT_ERR_FATAL;
494 } else {
495 type = "NON_FATAL";
496 tp_event = HW_EVENT_ERR_UNCORRECTED;
497 }
498 } else {
499 type = "CORRECTED";
500 tp_event = HW_EVENT_ERR_CORRECTED;
501 }
502
503
504
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507
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511
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513
514
515
516 if (!((errcode & 0xef80) == 0x80 || (errcode & 0xef80) == 0x280)) {
517 optype = "Can't parse: it is not a mem";
518 } else {
519 switch (optypenum) {
520 case 0:
521 optype = "generic undef request error";
522 break;
523 case 1:
524 optype = "memory read error";
525 break;
526 case 2:
527 optype = "memory write error";
528 break;
529 case 3:
530 optype = "addr/cmd error";
531 break;
532 case 4:
533 optype = "memory scrubbing error";
534 break;
535 default:
536 optype = "reserved";
537 break;
538 }
539 }
540 if (adxl_component_count) {
541 snprintf(skx_msg, MSG_SIZE, "%s%s err_code:0x%04x:0x%04x %s",
542 overflow ? " OVERFLOW" : "",
543 (uncorrected_error && recoverable) ? " recoverable" : "",
544 mscod, errcode, adxl_msg);
545 } else {
546 snprintf(skx_msg, MSG_SIZE,
547 "%s%s err_code:0x%04x:0x%04x socket:%d imc:%d rank:%d bg:%d ba:%d row:0x%x col:0x%x",
548 overflow ? " OVERFLOW" : "",
549 (uncorrected_error && recoverable) ? " recoverable" : "",
550 mscod, errcode,
551 res->socket, res->imc, res->rank,
552 res->bank_group, res->bank_address, res->row, res->column);
553 }
554
555 edac_dbg(0, "%s\n", skx_msg);
556
557
558 edac_mc_handle_error(tp_event, mci, core_err_cnt,
559 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
560 res->channel, res->dimm, -1,
561 optype, skx_msg);
562}
563
564int skx_mce_check_error(struct notifier_block *nb, unsigned long val,
565 void *data)
566{
567 struct mce *mce = (struct mce *)data;
568 struct decoded_addr res;
569 struct mem_ctl_info *mci;
570 char *type;
571
572 if (edac_get_report_status() == EDAC_REPORTING_DISABLED)
573 return NOTIFY_DONE;
574
575
576 if ((mce->status & 0xefff) >> 7 != 1 || !(mce->status & MCI_STATUS_ADDRV))
577 return NOTIFY_DONE;
578
579 memset(&res, 0, sizeof(res));
580 res.addr = mce->addr;
581
582 if (adxl_component_count) {
583 if (!skx_adxl_decode(&res))
584 return NOTIFY_DONE;
585
586 mci = get_mci(res.socket, res.imc);
587 } else {
588 if (!skx_decode || !skx_decode(&res))
589 return NOTIFY_DONE;
590
591 mci = res.dev->imc[res.imc].mci;
592 }
593
594 if (!mci)
595 return NOTIFY_DONE;
596
597 if (mce->mcgstatus & MCG_STATUS_MCIP)
598 type = "Exception";
599 else
600 type = "Event";
601
602 skx_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
603
604 skx_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: 0x%llx "
605 "Bank %d: 0x%llx\n", mce->extcpu, type,
606 mce->mcgstatus, mce->bank, mce->status);
607 skx_mc_printk(mci, KERN_DEBUG, "TSC 0x%llx ", mce->tsc);
608 skx_mc_printk(mci, KERN_DEBUG, "ADDR 0x%llx ", mce->addr);
609 skx_mc_printk(mci, KERN_DEBUG, "MISC 0x%llx ", mce->misc);
610
611 skx_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:0x%x TIME %llu SOCKET "
612 "%u APIC 0x%x\n", mce->cpuvendor, mce->cpuid,
613 mce->time, mce->socketid, mce->apicid);
614
615 skx_mce_output_error(mci, mce, &res);
616
617 return NOTIFY_DONE;
618}
619
620void skx_remove(void)
621{
622 int i, j;
623 struct skx_dev *d, *tmp;
624
625 edac_dbg(0, "\n");
626
627 list_for_each_entry_safe(d, tmp, &dev_edac_list, list) {
628 list_del(&d->list);
629 for (i = 0; i < NUM_IMC; i++) {
630 if (d->imc[i].mci)
631 skx_unregister_mci(&d->imc[i]);
632
633 if (d->imc[i].mdev)
634 pci_dev_put(d->imc[i].mdev);
635
636 if (d->imc[i].mbase)
637 iounmap(d->imc[i].mbase);
638
639 for (j = 0; j < NUM_CHANNELS; j++) {
640 if (d->imc[i].chan[j].cdev)
641 pci_dev_put(d->imc[i].chan[j].cdev);
642 }
643 }
644 if (d->util_all)
645 pci_dev_put(d->util_all);
646 if (d->sad_all)
647 pci_dev_put(d->sad_all);
648 if (d->uracu)
649 pci_dev_put(d->uracu);
650
651 kfree(d);
652 }
653}
654
