1
2
3
4
5
6
7
8
9
10#include <linux/acpi.h>
11#include <linux/clk.h>
12#include <linux/err.h>
13#include <linux/gpio/driver.h>
14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/ioport.h>
18#include <linux/irq.h>
19#include <linux/irqdomain.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/of_device.h>
24#include <linux/of_irq.h>
25#include <linux/platform_device.h>
26#include <linux/property.h>
27#include <linux/reset.h>
28#include <linux/spinlock.h>
29#include <linux/platform_data/gpio-dwapb.h>
30#include <linux/slab.h>
31
32#include "gpiolib.h"
33#include "gpiolib-acpi.h"
34
35#define GPIO_SWPORTA_DR 0x00
36#define GPIO_SWPORTA_DDR 0x04
37#define GPIO_SWPORTB_DR 0x0c
38#define GPIO_SWPORTB_DDR 0x10
39#define GPIO_SWPORTC_DR 0x18
40#define GPIO_SWPORTC_DDR 0x1c
41#define GPIO_SWPORTD_DR 0x24
42#define GPIO_SWPORTD_DDR 0x28
43#define GPIO_INTEN 0x30
44#define GPIO_INTMASK 0x34
45#define GPIO_INTTYPE_LEVEL 0x38
46#define GPIO_INT_POLARITY 0x3c
47#define GPIO_INTSTATUS 0x40
48#define GPIO_PORTA_DEBOUNCE 0x48
49#define GPIO_PORTA_EOI 0x4c
50#define GPIO_EXT_PORTA 0x50
51#define GPIO_EXT_PORTB 0x54
52#define GPIO_EXT_PORTC 0x58
53#define GPIO_EXT_PORTD 0x5c
54
55#define DWAPB_MAX_PORTS 4
56#define GPIO_EXT_PORT_STRIDE 0x04
57#define GPIO_SWPORT_DR_STRIDE 0x0c
58#define GPIO_SWPORT_DDR_STRIDE 0x0c
59
60#define GPIO_REG_OFFSET_V2 1
61
62#define GPIO_INTMASK_V2 0x44
63#define GPIO_INTTYPE_LEVEL_V2 0x34
64#define GPIO_INT_POLARITY_V2 0x38
65#define GPIO_INTSTATUS_V2 0x3c
66#define GPIO_PORTA_EOI_V2 0x40
67
68struct dwapb_gpio;
69
70#ifdef CONFIG_PM_SLEEP
71
72struct dwapb_context {
73 u32 data;
74 u32 dir;
75 u32 ext;
76 u32 int_en;
77 u32 int_mask;
78 u32 int_type;
79 u32 int_pol;
80 u32 int_deb;
81 u32 wake_en;
82};
83#endif
84
85struct dwapb_gpio_port {
86 struct gpio_chip gc;
87 bool is_registered;
88 struct dwapb_gpio *gpio;
89#ifdef CONFIG_PM_SLEEP
90 struct dwapb_context *ctx;
91#endif
92 unsigned int idx;
93};
94
95struct dwapb_gpio {
96 struct device *dev;
97 void __iomem *regs;
98 struct dwapb_gpio_port *ports;
99 unsigned int nr_ports;
100 struct irq_domain *domain;
101 unsigned int flags;
102 struct reset_control *rst;
103 struct clk *clk;
104};
105
106static inline u32 gpio_reg_v2_convert(unsigned int offset)
107{
108 switch (offset) {
109 case GPIO_INTMASK:
110 return GPIO_INTMASK_V2;
111 case GPIO_INTTYPE_LEVEL:
112 return GPIO_INTTYPE_LEVEL_V2;
113 case GPIO_INT_POLARITY:
114 return GPIO_INT_POLARITY_V2;
115 case GPIO_INTSTATUS:
116 return GPIO_INTSTATUS_V2;
117 case GPIO_PORTA_EOI:
118 return GPIO_PORTA_EOI_V2;
119 }
120
121 return offset;
122}
123
124static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
125{
126 if (gpio->flags & GPIO_REG_OFFSET_V2)
127 return gpio_reg_v2_convert(offset);
128
129 return offset;
130}
131
132static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
133{
134 struct gpio_chip *gc = &gpio->ports[0].gc;
135 void __iomem *reg_base = gpio->regs;
136
137 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));
138}
139
140static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
141 u32 val)
142{
143 struct gpio_chip *gc = &gpio->ports[0].gc;
144 void __iomem *reg_base = gpio->regs;
145
146 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);
147}
148
149static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
150{
151 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
152 struct dwapb_gpio *gpio = port->gpio;
153
154 return irq_find_mapping(gpio->domain, offset);
155}
156
157static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)
158{
159 struct dwapb_gpio_port *port;
160 int i;
161
162 for (i = 0; i < gpio->nr_ports; i++) {
163 port = &gpio->ports[i];
164 if (port->idx == offs / 32)
165 return port;
166 }
167
168 return NULL;
169}
170
171static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
172{
173 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs);
174 struct gpio_chip *gc;
175 u32 pol;
176 int val;
177
178 if (!port)
179 return;
180 gc = &port->gc;
181
182 pol = dwapb_read(gpio, GPIO_INT_POLARITY);
183
184 val = gc->get(gc, offs % 32);
185 if (val)
186 pol &= ~BIT(offs);
187 else
188 pol |= BIT(offs);
189
190 dwapb_write(gpio, GPIO_INT_POLARITY, pol);
191}
192
193static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
194{
195 u32 irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
196 u32 ret = irq_status;
197
198 while (irq_status) {
199 int hwirq = fls(irq_status) - 1;
200 int gpio_irq = irq_find_mapping(gpio->domain, hwirq);
201
202 generic_handle_irq(gpio_irq);
203 irq_status &= ~BIT(hwirq);
204
205 if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK)
206 == IRQ_TYPE_EDGE_BOTH)
207 dwapb_toggle_trigger(gpio, hwirq);
208 }
209
210 return ret;
211}
212
213static void dwapb_irq_handler(struct irq_desc *desc)
214{
215 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
216 struct irq_chip *chip = irq_desc_get_chip(desc);
217
218 dwapb_do_irq(gpio);
219
220 if (chip->irq_eoi)
221 chip->irq_eoi(irq_desc_get_irq_data(desc));
222}
223
224static void dwapb_irq_enable(struct irq_data *d)
225{
226 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
227 struct dwapb_gpio *gpio = igc->private;
228 struct gpio_chip *gc = &gpio->ports[0].gc;
229 unsigned long flags;
230 u32 val;
231
232 spin_lock_irqsave(&gc->bgpio_lock, flags);
233 val = dwapb_read(gpio, GPIO_INTEN);
234 val |= BIT(d->hwirq);
235 dwapb_write(gpio, GPIO_INTEN, val);
236 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
237}
238
239static void dwapb_irq_disable(struct irq_data *d)
240{
241 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
242 struct dwapb_gpio *gpio = igc->private;
243 struct gpio_chip *gc = &gpio->ports[0].gc;
244 unsigned long flags;
245 u32 val;
246
247 spin_lock_irqsave(&gc->bgpio_lock, flags);
248 val = dwapb_read(gpio, GPIO_INTEN);
249 val &= ~BIT(d->hwirq);
250 dwapb_write(gpio, GPIO_INTEN, val);
251 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
252}
253
254static int dwapb_irq_reqres(struct irq_data *d)
255{
256 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
257 struct dwapb_gpio *gpio = igc->private;
258 struct gpio_chip *gc = &gpio->ports[0].gc;
259
260 if (gpiochip_lock_as_irq(gc, irqd_to_hwirq(d))) {
261 dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n",
262 irqd_to_hwirq(d));
263 return -EINVAL;
264 }
265 return 0;
266}
267
268static void dwapb_irq_relres(struct irq_data *d)
269{
270 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
271 struct dwapb_gpio *gpio = igc->private;
272 struct gpio_chip *gc = &gpio->ports[0].gc;
273
274 gpiochip_unlock_as_irq(gc, irqd_to_hwirq(d));
275}
276
277static int dwapb_irq_set_type(struct irq_data *d, u32 type)
278{
279 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
280 struct dwapb_gpio *gpio = igc->private;
281 struct gpio_chip *gc = &gpio->ports[0].gc;
282 int bit = d->hwirq;
283 unsigned long level, polarity, flags;
284
285 if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
286 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
287 return -EINVAL;
288
289 spin_lock_irqsave(&gc->bgpio_lock, flags);
290 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
291 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
292
293 switch (type) {
294 case IRQ_TYPE_EDGE_BOTH:
295 level |= BIT(bit);
296 dwapb_toggle_trigger(gpio, bit);
297 break;
298 case IRQ_TYPE_EDGE_RISING:
299 level |= BIT(bit);
300 polarity |= BIT(bit);
301 break;
302 case IRQ_TYPE_EDGE_FALLING:
303 level |= BIT(bit);
304 polarity &= ~BIT(bit);
305 break;
306 case IRQ_TYPE_LEVEL_HIGH:
307 level &= ~BIT(bit);
308 polarity |= BIT(bit);
309 break;
310 case IRQ_TYPE_LEVEL_LOW:
311 level &= ~BIT(bit);
312 polarity &= ~BIT(bit);
313 break;
314 }
315
316 irq_setup_alt_chip(d, type);
317
318 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
319 if (type != IRQ_TYPE_EDGE_BOTH)
320 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
321 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
322
323 return 0;
324}
325
326#ifdef CONFIG_PM_SLEEP
327static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)
328{
329 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
330 struct dwapb_gpio *gpio = igc->private;
331 struct dwapb_context *ctx = gpio->ports[0].ctx;
332
333 if (enable)
334 ctx->wake_en |= BIT(d->hwirq);
335 else
336 ctx->wake_en &= ~BIT(d->hwirq);
337
338 return 0;
339}
340#endif
341
342static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
343 unsigned offset, unsigned debounce)
344{
345 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
346 struct dwapb_gpio *gpio = port->gpio;
347 unsigned long flags, val_deb;
348 unsigned long mask = BIT(offset);
349
350 spin_lock_irqsave(&gc->bgpio_lock, flags);
351
352 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
353 if (debounce)
354 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb | mask);
355 else
356 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask);
357
358 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
359
360 return 0;
361}
362
363static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,
364 unsigned long config)
365{
366 u32 debounce;
367
368 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
369 return -ENOTSUPP;
370
371 debounce = pinconf_to_config_argument(config);
372 return dwapb_gpio_set_debounce(gc, offset, debounce);
373}
374
375static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
376{
377 u32 worked;
378 struct dwapb_gpio *gpio = dev_id;
379
380 worked = dwapb_do_irq(gpio);
381
382 return worked ? IRQ_HANDLED : IRQ_NONE;
383}
384
385static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
386 struct dwapb_gpio_port *port,
387 struct dwapb_port_property *pp)
388{
389 struct gpio_chip *gc = &port->gc;
390 struct fwnode_handle *fwnode = pp->fwnode;
391 struct irq_chip_generic *irq_gc = NULL;
392 unsigned int hwirq, ngpio = gc->ngpio;
393 struct irq_chip_type *ct;
394 int err, i;
395
396 gpio->domain = irq_domain_create_linear(fwnode, ngpio,
397 &irq_generic_chip_ops, gpio);
398 if (!gpio->domain)
399 return;
400
401 err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2,
402 "gpio-dwapb", handle_level_irq,
403 IRQ_NOREQUEST, 0,
404 IRQ_GC_INIT_NESTED_LOCK);
405 if (err) {
406 dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n");
407 irq_domain_remove(gpio->domain);
408 gpio->domain = NULL;
409 return;
410 }
411
412 irq_gc = irq_get_domain_generic_chip(gpio->domain, 0);
413 if (!irq_gc) {
414 irq_domain_remove(gpio->domain);
415 gpio->domain = NULL;
416 return;
417 }
418
419 irq_gc->reg_base = gpio->regs;
420 irq_gc->private = gpio;
421
422 for (i = 0; i < 2; i++) {
423 ct = &irq_gc->chip_types[i];
424 ct->chip.irq_ack = irq_gc_ack_set_bit;
425 ct->chip.irq_mask = irq_gc_mask_set_bit;
426 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
427 ct->chip.irq_set_type = dwapb_irq_set_type;
428 ct->chip.irq_enable = dwapb_irq_enable;
429 ct->chip.irq_disable = dwapb_irq_disable;
430 ct->chip.irq_request_resources = dwapb_irq_reqres;
431 ct->chip.irq_release_resources = dwapb_irq_relres;
432#ifdef CONFIG_PM_SLEEP
433 ct->chip.irq_set_wake = dwapb_irq_set_wake;
434#endif
435 ct->regs.ack = gpio_reg_convert(gpio, GPIO_PORTA_EOI);
436 ct->regs.mask = gpio_reg_convert(gpio, GPIO_INTMASK);
437 ct->type = IRQ_TYPE_LEVEL_MASK;
438 }
439
440 irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
441 irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
442 irq_gc->chip_types[1].handler = handle_edge_irq;
443
444 if (!pp->irq_shared) {
445 int i;
446
447 for (i = 0; i < pp->ngpio; i++) {
448 if (pp->irq[i] >= 0)
449 irq_set_chained_handler_and_data(pp->irq[i],
450 dwapb_irq_handler, gpio);
451 }
452 } else {
453
454
455
456
457 err = devm_request_irq(gpio->dev, pp->irq[0],
458 dwapb_irq_handler_mfd,
459 IRQF_SHARED, "gpio-dwapb-mfd", gpio);
460 if (err) {
461 dev_err(gpio->dev, "error requesting IRQ\n");
462 irq_domain_remove(gpio->domain);
463 gpio->domain = NULL;
464 return;
465 }
466 }
467
468 for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
469 irq_create_mapping(gpio->domain, hwirq);
470
471 port->gc.to_irq = dwapb_gpio_to_irq;
472}
473
474static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
475{
476 struct dwapb_gpio_port *port = &gpio->ports[0];
477 struct gpio_chip *gc = &port->gc;
478 unsigned int ngpio = gc->ngpio;
479 irq_hw_number_t hwirq;
480
481 if (!gpio->domain)
482 return;
483
484 for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
485 irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq));
486
487 irq_domain_remove(gpio->domain);
488 gpio->domain = NULL;
489}
490
491static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
492 struct dwapb_port_property *pp,
493 unsigned int offs)
494{
495 struct dwapb_gpio_port *port;
496 void __iomem *dat, *set, *dirout;
497 int err;
498
499 port = &gpio->ports[offs];
500 port->gpio = gpio;
501 port->idx = pp->idx;
502
503#ifdef CONFIG_PM_SLEEP
504 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
505 if (!port->ctx)
506 return -ENOMEM;
507#endif
508
509 dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_STRIDE);
510 set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_STRIDE);
511 dirout = gpio->regs + GPIO_SWPORTA_DDR +
512 (pp->idx * GPIO_SWPORT_DDR_STRIDE);
513
514
515 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
516 NULL, 0);
517 if (err) {
518 dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
519 port->idx);
520 return err;
521 }
522
523#ifdef CONFIG_OF_GPIO
524 port->gc.of_node = to_of_node(pp->fwnode);
525#endif
526 port->gc.ngpio = pp->ngpio;
527 port->gc.base = pp->gpio_base;
528
529
530 if (pp->idx == 0)
531 port->gc.set_config = dwapb_gpio_set_config;
532
533 if (pp->has_irq)
534 dwapb_configure_irqs(gpio, port, pp);
535
536 err = gpiochip_add_data(&port->gc, port);
537 if (err)
538 dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
539 port->idx);
540 else
541 port->is_registered = true;
542
543
544 if (pp->has_irq)
545 acpi_gpiochip_request_interrupts(&port->gc);
546
547 return err;
548}
549
550static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
551{
552 unsigned int m;
553
554 for (m = 0; m < gpio->nr_ports; ++m)
555 if (gpio->ports[m].is_registered)
556 gpiochip_remove(&gpio->ports[m].gc);
557}
558
559static struct dwapb_platform_data *
560dwapb_gpio_get_pdata(struct device *dev)
561{
562 struct fwnode_handle *fwnode;
563 struct dwapb_platform_data *pdata;
564 struct dwapb_port_property *pp;
565 int nports;
566 int i, j;
567
568 nports = device_get_child_node_count(dev);
569 if (nports == 0)
570 return ERR_PTR(-ENODEV);
571
572 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
573 if (!pdata)
574 return ERR_PTR(-ENOMEM);
575
576 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
577 if (!pdata->properties)
578 return ERR_PTR(-ENOMEM);
579
580 pdata->nports = nports;
581
582 i = 0;
583 device_for_each_child_node(dev, fwnode) {
584 struct device_node *np = NULL;
585
586 pp = &pdata->properties[i++];
587 pp->fwnode = fwnode;
588
589 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||
590 pp->idx >= DWAPB_MAX_PORTS) {
591 dev_err(dev,
592 "missing/invalid port index for port%d\n", i);
593 fwnode_handle_put(fwnode);
594 return ERR_PTR(-EINVAL);
595 }
596
597 if (fwnode_property_read_u32(fwnode, "snps,nr-gpios",
598 &pp->ngpio)) {
599 dev_info(dev,
600 "failed to get number of gpios for port%d\n",
601 i);
602 pp->ngpio = 32;
603 }
604
605 pp->irq_shared = false;
606 pp->gpio_base = -1;
607
608
609
610
611
612 if (pp->idx != 0)
613 continue;
614
615 if (dev->of_node && fwnode_property_read_bool(fwnode,
616 "interrupt-controller")) {
617 np = to_of_node(fwnode);
618 }
619
620 for (j = 0; j < pp->ngpio; j++) {
621 pp->irq[j] = -ENXIO;
622
623 if (np)
624 pp->irq[j] = of_irq_get(np, j);
625 else if (has_acpi_companion(dev))
626 pp->irq[j] = platform_get_irq(to_platform_device(dev), j);
627
628 if (pp->irq[j] >= 0)
629 pp->has_irq = true;
630 }
631
632 if (!pp->has_irq)
633 dev_warn(dev, "no irq for port%d\n", pp->idx);
634 }
635
636 return pdata;
637}
638
639static const struct of_device_id dwapb_of_match[] = {
640 { .compatible = "snps,dw-apb-gpio", .data = (void *)0},
641 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
642 { }
643};
644MODULE_DEVICE_TABLE(of, dwapb_of_match);
645
646static const struct acpi_device_id dwapb_acpi_match[] = {
647 {"HISI0181", 0},
648 {"APMC0D07", 0},
649 {"APMC0D81", GPIO_REG_OFFSET_V2},
650 { }
651};
652MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
653
654static int dwapb_gpio_probe(struct platform_device *pdev)
655{
656 unsigned int i;
657 struct resource *res;
658 struct dwapb_gpio *gpio;
659 int err;
660 struct device *dev = &pdev->dev;
661 struct dwapb_platform_data *pdata = dev_get_platdata(dev);
662
663 if (!pdata) {
664 pdata = dwapb_gpio_get_pdata(dev);
665 if (IS_ERR(pdata))
666 return PTR_ERR(pdata);
667 }
668
669 if (!pdata->nports)
670 return -ENODEV;
671
672 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
673 if (!gpio)
674 return -ENOMEM;
675
676 gpio->dev = &pdev->dev;
677 gpio->nr_ports = pdata->nports;
678
679 gpio->rst = devm_reset_control_get_optional_shared(dev, NULL);
680 if (IS_ERR(gpio->rst))
681 return PTR_ERR(gpio->rst);
682
683 reset_control_deassert(gpio->rst);
684
685 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
686 sizeof(*gpio->ports), GFP_KERNEL);
687 if (!gpio->ports)
688 return -ENOMEM;
689
690 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
691 gpio->regs = devm_ioremap_resource(&pdev->dev, res);
692 if (IS_ERR(gpio->regs))
693 return PTR_ERR(gpio->regs);
694
695
696 gpio->clk = devm_clk_get(&pdev->dev, "bus");
697 if (!IS_ERR(gpio->clk)) {
698 err = clk_prepare_enable(gpio->clk);
699 if (err) {
700 dev_info(&pdev->dev, "Cannot enable clock\n");
701 return err;
702 }
703 }
704
705 gpio->flags = 0;
706 if (dev->of_node) {
707 gpio->flags = (uintptr_t)of_device_get_match_data(dev);
708 } else if (has_acpi_companion(dev)) {
709 const struct acpi_device_id *acpi_id;
710
711 acpi_id = acpi_match_device(dwapb_acpi_match, dev);
712 if (acpi_id) {
713 if (acpi_id->driver_data)
714 gpio->flags = acpi_id->driver_data;
715 }
716 }
717
718 for (i = 0; i < gpio->nr_ports; i++) {
719 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
720 if (err)
721 goto out_unregister;
722 }
723 platform_set_drvdata(pdev, gpio);
724
725 return 0;
726
727out_unregister:
728 dwapb_gpio_unregister(gpio);
729 dwapb_irq_teardown(gpio);
730
731 return err;
732}
733
734static int dwapb_gpio_remove(struct platform_device *pdev)
735{
736 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
737
738 dwapb_gpio_unregister(gpio);
739 dwapb_irq_teardown(gpio);
740 reset_control_assert(gpio->rst);
741 clk_disable_unprepare(gpio->clk);
742
743 return 0;
744}
745
746#ifdef CONFIG_PM_SLEEP
747static int dwapb_gpio_suspend(struct device *dev)
748{
749 struct platform_device *pdev = to_platform_device(dev);
750 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
751 struct gpio_chip *gc = &gpio->ports[0].gc;
752 unsigned long flags;
753 int i;
754
755 spin_lock_irqsave(&gc->bgpio_lock, flags);
756 for (i = 0; i < gpio->nr_ports; i++) {
757 unsigned int offset;
758 unsigned int idx = gpio->ports[i].idx;
759 struct dwapb_context *ctx = gpio->ports[i].ctx;
760
761 BUG_ON(!ctx);
762
763 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
764 ctx->dir = dwapb_read(gpio, offset);
765
766 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
767 ctx->data = dwapb_read(gpio, offset);
768
769 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
770 ctx->ext = dwapb_read(gpio, offset);
771
772
773 if (idx == 0) {
774 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
775 ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
776 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
777 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
778 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
779
780
781 dwapb_write(gpio, GPIO_INTMASK,
782 0xffffffff & ~ctx->wake_en);
783 }
784 }
785 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
786
787 clk_disable_unprepare(gpio->clk);
788
789 return 0;
790}
791
792static int dwapb_gpio_resume(struct device *dev)
793{
794 struct platform_device *pdev = to_platform_device(dev);
795 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
796 struct gpio_chip *gc = &gpio->ports[0].gc;
797 unsigned long flags;
798 int i;
799
800 if (!IS_ERR(gpio->clk))
801 clk_prepare_enable(gpio->clk);
802
803 spin_lock_irqsave(&gc->bgpio_lock, flags);
804 for (i = 0; i < gpio->nr_ports; i++) {
805 unsigned int offset;
806 unsigned int idx = gpio->ports[i].idx;
807 struct dwapb_context *ctx = gpio->ports[i].ctx;
808
809 BUG_ON(!ctx);
810
811 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
812 dwapb_write(gpio, offset, ctx->data);
813
814 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
815 dwapb_write(gpio, offset, ctx->dir);
816
817 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
818 dwapb_write(gpio, offset, ctx->ext);
819
820
821 if (idx == 0) {
822 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
823 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
824 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
825 dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
826 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
827
828
829 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
830 }
831 }
832 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
833
834 return 0;
835}
836#endif
837
838static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
839 dwapb_gpio_resume);
840
841static struct platform_driver dwapb_gpio_driver = {
842 .driver = {
843 .name = "gpio-dwapb",
844 .pm = &dwapb_gpio_pm_ops,
845 .of_match_table = of_match_ptr(dwapb_of_match),
846 .acpi_match_table = ACPI_PTR(dwapb_acpi_match),
847 },
848 .probe = dwapb_gpio_probe,
849 .remove = dwapb_gpio_remove,
850};
851
852module_platform_driver(dwapb_gpio_driver);
853
854MODULE_LICENSE("GPL");
855MODULE_AUTHOR("Jamie Iles");
856MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
857
