1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
51
52#include <linux/module.h>
53#include <linux/init.h>
54#include <linux/slab.h>
55#include <linux/jiffies.h>
56#include <linux/platform_device.h>
57#include <linux/hwmon.h>
58#include <linux/hwmon-sysfs.h>
59#include <linux/hwmon-vid.h>
60#include <linux/err.h>
61#include <linux/mutex.h>
62#include <linux/acpi.h>
63#include <linux/bitops.h>
64#include <linux/dmi.h>
65#include <linux/io.h>
66#include <linux/nospec.h>
67#include "lm75.h"
68
69#define USE_ALTERNATE
70
71enum kinds { nct6106, nct6775, nct6776, nct6779, nct6791, nct6792, nct6793,
72 nct6795, nct6796 };
73
74
75static const char * const nct6775_device_names[] = {
76 "nct6106",
77 "nct6775",
78 "nct6776",
79 "nct6779",
80 "nct6791",
81 "nct6792",
82 "nct6793",
83 "nct6795",
84 "nct6796",
85};
86
87static const char * const nct6775_sio_names[] __initconst = {
88 "NCT6106D",
89 "NCT6775F",
90 "NCT6776D/F",
91 "NCT6779D",
92 "NCT6791D",
93 "NCT6792D",
94 "NCT6793D",
95 "NCT6795D",
96 "NCT6796D",
97};
98
99static unsigned short force_id;
100module_param(force_id, ushort, 0);
101MODULE_PARM_DESC(force_id, "Override the detected device ID");
102
103static unsigned short fan_debounce;
104module_param(fan_debounce, ushort, 0);
105MODULE_PARM_DESC(fan_debounce, "Enable debouncing for fan RPM signal");
106
107#define DRVNAME "nct6775"
108
109
110
111
112
113#define NCT6775_LD_ACPI 0x0a
114#define NCT6775_LD_HWM 0x0b
115#define NCT6775_LD_VID 0x0d
116#define NCT6775_LD_12 0x12
117
118#define SIO_REG_LDSEL 0x07
119#define SIO_REG_DEVID 0x20
120#define SIO_REG_ENABLE 0x30
121#define SIO_REG_ADDR 0x60
122
123#define SIO_NCT6106_ID 0xc450
124#define SIO_NCT6775_ID 0xb470
125#define SIO_NCT6776_ID 0xc330
126#define SIO_NCT6779_ID 0xc560
127#define SIO_NCT6791_ID 0xc800
128#define SIO_NCT6792_ID 0xc910
129#define SIO_NCT6793_ID 0xd120
130#define SIO_NCT6795_ID 0xd350
131#define SIO_NCT6796_ID 0xd420
132#define SIO_ID_MASK 0xFFF0
133
134enum pwm_enable { off, manual, thermal_cruise, speed_cruise, sf3, sf4 };
135
136static inline void
137superio_outb(int ioreg, int reg, int val)
138{
139 outb(reg, ioreg);
140 outb(val, ioreg + 1);
141}
142
143static inline int
144superio_inb(int ioreg, int reg)
145{
146 outb(reg, ioreg);
147 return inb(ioreg + 1);
148}
149
150static inline void
151superio_select(int ioreg, int ld)
152{
153 outb(SIO_REG_LDSEL, ioreg);
154 outb(ld, ioreg + 1);
155}
156
157static inline int
158superio_enter(int ioreg)
159{
160
161
162
163 if (!request_muxed_region(ioreg, 2, DRVNAME))
164 return -EBUSY;
165
166 outb(0x87, ioreg);
167 outb(0x87, ioreg);
168
169 return 0;
170}
171
172static inline void
173superio_exit(int ioreg)
174{
175 outb(0xaa, ioreg);
176 outb(0x02, ioreg);
177 outb(0x02, ioreg + 1);
178 release_region(ioreg, 2);
179}
180
181
182
183
184
185#define IOREGION_ALIGNMENT (~7)
186#define IOREGION_OFFSET 5
187#define IOREGION_LENGTH 2
188#define ADDR_REG_OFFSET 0
189#define DATA_REG_OFFSET 1
190
191#define NCT6775_REG_BANK 0x4E
192#define NCT6775_REG_CONFIG 0x40
193
194
195
196
197
198
199
200
201
202#define NUM_TEMP 10
203#define NUM_TEMP_FIXED 6
204
205#define NUM_REG_ALARM 7
206#define NUM_REG_BEEP 5
207
208#define NUM_FAN 7
209
210#define TEMP_SOURCE_VIRTUAL 0x1f
211
212
213
214
215
216static const u16 NCT6775_REG_IN_MAX[] = {
217 0x2b, 0x2d, 0x2f, 0x31, 0x33, 0x35, 0x37, 0x554, 0x556, 0x558, 0x55a,
218 0x55c, 0x55e, 0x560, 0x562 };
219static const u16 NCT6775_REG_IN_MIN[] = {
220 0x2c, 0x2e, 0x30, 0x32, 0x34, 0x36, 0x38, 0x555, 0x557, 0x559, 0x55b,
221 0x55d, 0x55f, 0x561, 0x563 };
222static const u16 NCT6775_REG_IN[] = {
223 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x550, 0x551, 0x552
224};
225
226#define NCT6775_REG_VBAT 0x5D
227#define NCT6775_REG_DIODE 0x5E
228#define NCT6775_DIODE_MASK 0x02
229
230#define NCT6775_REG_FANDIV1 0x506
231#define NCT6775_REG_FANDIV2 0x507
232
233#define NCT6775_REG_CR_FAN_DEBOUNCE 0xf0
234
235static const u16 NCT6775_REG_ALARM[NUM_REG_ALARM] = { 0x459, 0x45A, 0x45B };
236
237
238
239static const s8 NCT6775_ALARM_BITS[] = {
240 0, 1, 2, 3, 8, 21, 20, 16,
241 17, -1, -1, -1, -1, -1, -1,
242 -1,
243 6, 7, 11, -1, -1,
244 -1, -1, -1,
245 4, 5, 13, -1, -1, -1,
246 12, -1 };
247
248#define FAN_ALARM_BASE 16
249#define TEMP_ALARM_BASE 24
250#define INTRUSION_ALARM_BASE 30
251
252static const u16 NCT6775_REG_BEEP[NUM_REG_BEEP] = { 0x56, 0x57, 0x453, 0x4e };
253
254
255
256
257
258static const s8 NCT6775_BEEP_BITS[] = {
259 0, 1, 2, 3, 8, 9, 10, 16,
260 17, -1, -1, -1, -1, -1, -1,
261 21,
262 6, 7, 11, 28, -1,
263 -1, -1, -1,
264 4, 5, 13, -1, -1, -1,
265 12, -1 };
266
267#define BEEP_ENABLE_BASE 15
268
269static const u8 NCT6775_REG_CR_CASEOPEN_CLR[] = { 0xe6, 0xee };
270static const u8 NCT6775_CR_CASEOPEN_CLR_MASK[] = { 0x20, 0x01 };
271
272
273static const u8 NCT6775_REG_PWM_MODE[] = { 0x04, 0x04, 0x12 };
274static const u8 NCT6775_PWM_MODE_MASK[] = { 0x01, 0x02, 0x01 };
275
276
277
278static const u16 NCT6775_REG_TARGET[] = {
279 0x101, 0x201, 0x301, 0x801, 0x901, 0xa01, 0xb01 };
280static const u16 NCT6775_REG_FAN_MODE[] = {
281 0x102, 0x202, 0x302, 0x802, 0x902, 0xa02, 0xb02 };
282static const u16 NCT6775_REG_FAN_STEP_DOWN_TIME[] = {
283 0x103, 0x203, 0x303, 0x803, 0x903, 0xa03, 0xb03 };
284static const u16 NCT6775_REG_FAN_STEP_UP_TIME[] = {
285 0x104, 0x204, 0x304, 0x804, 0x904, 0xa04, 0xb04 };
286static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = {
287 0x105, 0x205, 0x305, 0x805, 0x905, 0xa05, 0xb05 };
288static const u16 NCT6775_REG_FAN_START_OUTPUT[] = {
289 0x106, 0x206, 0x306, 0x806, 0x906, 0xa06, 0xb06 };
290static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a };
291static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b };
292
293static const u16 NCT6775_REG_FAN_STOP_TIME[] = {
294 0x107, 0x207, 0x307, 0x807, 0x907, 0xa07, 0xb07 };
295static const u16 NCT6775_REG_PWM[] = {
296 0x109, 0x209, 0x309, 0x809, 0x909, 0xa09, 0xb09 };
297static const u16 NCT6775_REG_PWM_READ[] = {
298 0x01, 0x03, 0x11, 0x13, 0x15, 0xa09, 0xb09 };
299
300static const u16 NCT6775_REG_FAN[] = { 0x630, 0x632, 0x634, 0x636, 0x638 };
301static const u16 NCT6775_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d };
302static const u16 NCT6775_REG_FAN_PULSES[] = { 0x641, 0x642, 0x643, 0x644, 0 };
303static const u16 NCT6775_FAN_PULSE_SHIFT[] = { 0, 0, 0, 0, 0, 0 };
304
305static const u16 NCT6775_REG_TEMP[] = {
306 0x27, 0x150, 0x250, 0x62b, 0x62c, 0x62d };
307
308static const u16 NCT6775_REG_TEMP_MON[] = { 0x73, 0x75, 0x77 };
309
310static const u16 NCT6775_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
311 0, 0x152, 0x252, 0x628, 0x629, 0x62A };
312static const u16 NCT6775_REG_TEMP_HYST[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
313 0x3a, 0x153, 0x253, 0x673, 0x678, 0x67D };
314static const u16 NCT6775_REG_TEMP_OVER[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
315 0x39, 0x155, 0x255, 0x672, 0x677, 0x67C };
316
317static const u16 NCT6775_REG_TEMP_SOURCE[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
318 0x621, 0x622, 0x623, 0x624, 0x625, 0x626 };
319
320static const u16 NCT6775_REG_TEMP_SEL[] = {
321 0x100, 0x200, 0x300, 0x800, 0x900, 0xa00, 0xb00 };
322
323static const u16 NCT6775_REG_WEIGHT_TEMP_SEL[] = {
324 0x139, 0x239, 0x339, 0x839, 0x939, 0xa39 };
325static const u16 NCT6775_REG_WEIGHT_TEMP_STEP[] = {
326 0x13a, 0x23a, 0x33a, 0x83a, 0x93a, 0xa3a };
327static const u16 NCT6775_REG_WEIGHT_TEMP_STEP_TOL[] = {
328 0x13b, 0x23b, 0x33b, 0x83b, 0x93b, 0xa3b };
329static const u16 NCT6775_REG_WEIGHT_DUTY_STEP[] = {
330 0x13c, 0x23c, 0x33c, 0x83c, 0x93c, 0xa3c };
331static const u16 NCT6775_REG_WEIGHT_TEMP_BASE[] = {
332 0x13d, 0x23d, 0x33d, 0x83d, 0x93d, 0xa3d };
333
334static const u16 NCT6775_REG_TEMP_OFFSET[] = { 0x454, 0x455, 0x456 };
335
336static const u16 NCT6775_REG_AUTO_TEMP[] = {
337 0x121, 0x221, 0x321, 0x821, 0x921, 0xa21, 0xb21 };
338static const u16 NCT6775_REG_AUTO_PWM[] = {
339 0x127, 0x227, 0x327, 0x827, 0x927, 0xa27, 0xb27 };
340
341#define NCT6775_AUTO_TEMP(data, nr, p) ((data)->REG_AUTO_TEMP[nr] + (p))
342#define NCT6775_AUTO_PWM(data, nr, p) ((data)->REG_AUTO_PWM[nr] + (p))
343
344static const u16 NCT6775_REG_CRITICAL_ENAB[] = { 0x134, 0x234, 0x334 };
345
346static const u16 NCT6775_REG_CRITICAL_TEMP[] = {
347 0x135, 0x235, 0x335, 0x835, 0x935, 0xa35, 0xb35 };
348static const u16 NCT6775_REG_CRITICAL_TEMP_TOLERANCE[] = {
349 0x138, 0x238, 0x338, 0x838, 0x938, 0xa38, 0xb38 };
350
351static const char *const nct6775_temp_label[] = {
352 "",
353 "SYSTIN",
354 "CPUTIN",
355 "AUXTIN",
356 "AMD SB-TSI",
357 "PECI Agent 0",
358 "PECI Agent 1",
359 "PECI Agent 2",
360 "PECI Agent 3",
361 "PECI Agent 4",
362 "PECI Agent 5",
363 "PECI Agent 6",
364 "PECI Agent 7",
365 "PCH_CHIP_CPU_MAX_TEMP",
366 "PCH_CHIP_TEMP",
367 "PCH_CPU_TEMP",
368 "PCH_MCH_TEMP",
369 "PCH_DIM0_TEMP",
370 "PCH_DIM1_TEMP",
371 "PCH_DIM2_TEMP",
372 "PCH_DIM3_TEMP"
373};
374
375#define NCT6775_TEMP_MASK 0x001ffffe
376
377static const u16 NCT6775_REG_TEMP_ALTERNATE[32] = {
378 [13] = 0x661,
379 [14] = 0x662,
380 [15] = 0x664,
381};
382
383static const u16 NCT6775_REG_TEMP_CRIT[32] = {
384 [4] = 0xa00,
385 [5] = 0xa01,
386 [6] = 0xa02,
387 [7] = 0xa03,
388 [8] = 0xa04,
389 [9] = 0xa05,
390 [10] = 0xa06,
391 [11] = 0xa07
392};
393
394
395
396
397#define NCT6776_REG_FAN_STEP_UP_TIME NCT6775_REG_FAN_STEP_DOWN_TIME
398#define NCT6776_REG_FAN_STEP_DOWN_TIME NCT6775_REG_FAN_STEP_UP_TIME
399
400static const s8 NCT6776_ALARM_BITS[] = {
401 0, 1, 2, 3, 8, 21, 20, 16,
402 17, -1, -1, -1, -1, -1, -1,
403 -1,
404 6, 7, 11, 10, 23,
405 -1, -1, -1,
406 4, 5, 13, -1, -1, -1,
407 12, 9 };
408
409static const u16 NCT6776_REG_BEEP[NUM_REG_BEEP] = { 0xb2, 0xb3, 0xb4, 0xb5 };
410
411static const s8 NCT6776_BEEP_BITS[] = {
412 0, 1, 2, 3, 4, 5, 6, 7,
413 8, -1, -1, -1, -1, -1, -1,
414 24,
415 25, 26, 27, 28, 29,
416 -1, -1, -1,
417 16, 17, 18, 19, 20, 21,
418 30, 31 };
419
420static const u16 NCT6776_REG_TOLERANCE_H[] = {
421 0x10c, 0x20c, 0x30c, 0x80c, 0x90c, 0xa0c, 0xb0c };
422
423static const u8 NCT6776_REG_PWM_MODE[] = { 0x04, 0, 0, 0, 0, 0 };
424static const u8 NCT6776_PWM_MODE_MASK[] = { 0x01, 0, 0, 0, 0, 0 };
425
426static const u16 NCT6776_REG_FAN_MIN[] = {
427 0x63a, 0x63c, 0x63e, 0x640, 0x642, 0x64a, 0x64c };
428static const u16 NCT6776_REG_FAN_PULSES[] = {
429 0x644, 0x645, 0x646, 0x647, 0x648, 0x649, 0 };
430
431static const u16 NCT6776_REG_WEIGHT_DUTY_BASE[] = {
432 0x13e, 0x23e, 0x33e, 0x83e, 0x93e, 0xa3e };
433
434static const u16 NCT6776_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
435 0x18, 0x152, 0x252, 0x628, 0x629, 0x62A };
436
437static const char *const nct6776_temp_label[] = {
438 "",
439 "SYSTIN",
440 "CPUTIN",
441 "AUXTIN",
442 "SMBUSMASTER 0",
443 "SMBUSMASTER 1",
444 "SMBUSMASTER 2",
445 "SMBUSMASTER 3",
446 "SMBUSMASTER 4",
447 "SMBUSMASTER 5",
448 "SMBUSMASTER 6",
449 "SMBUSMASTER 7",
450 "PECI Agent 0",
451 "PECI Agent 1",
452 "PCH_CHIP_CPU_MAX_TEMP",
453 "PCH_CHIP_TEMP",
454 "PCH_CPU_TEMP",
455 "PCH_MCH_TEMP",
456 "PCH_DIM0_TEMP",
457 "PCH_DIM1_TEMP",
458 "PCH_DIM2_TEMP",
459 "PCH_DIM3_TEMP",
460 "BYTE_TEMP"
461};
462
463#define NCT6776_TEMP_MASK 0x007ffffe
464
465static const u16 NCT6776_REG_TEMP_ALTERNATE[32] = {
466 [14] = 0x401,
467 [15] = 0x402,
468 [16] = 0x404,
469};
470
471static const u16 NCT6776_REG_TEMP_CRIT[32] = {
472 [11] = 0x709,
473 [12] = 0x70a,
474};
475
476
477
478static const u16 NCT6779_REG_IN[] = {
479 0x480, 0x481, 0x482, 0x483, 0x484, 0x485, 0x486, 0x487,
480 0x488, 0x489, 0x48a, 0x48b, 0x48c, 0x48d, 0x48e };
481
482static const u16 NCT6779_REG_ALARM[NUM_REG_ALARM] = {
483 0x459, 0x45A, 0x45B, 0x568 };
484
485static const s8 NCT6779_ALARM_BITS[] = {
486 0, 1, 2, 3, 8, 21, 20, 16,
487 17, 24, 25, 26, 27, 28, 29,
488 -1,
489 6, 7, 11, 10, 23,
490 -1, -1, -1,
491 4, 5, 13, -1, -1, -1,
492 12, 9 };
493
494static const s8 NCT6779_BEEP_BITS[] = {
495 0, 1, 2, 3, 4, 5, 6, 7,
496 8, 9, 10, 11, 12, 13, 14,
497 24,
498 25, 26, 27, 28, 29,
499 -1, -1, -1,
500 16, 17, -1, -1, -1, -1,
501 30, 31 };
502
503static const u16 NCT6779_REG_FAN[] = {
504 0x4b0, 0x4b2, 0x4b4, 0x4b6, 0x4b8, 0x4ba, 0x660 };
505static const u16 NCT6779_REG_FAN_PULSES[] = {
506 0x644, 0x645, 0x646, 0x647, 0x648, 0x649, 0 };
507
508static const u16 NCT6779_REG_CRITICAL_PWM_ENABLE[] = {
509 0x136, 0x236, 0x336, 0x836, 0x936, 0xa36, 0xb36 };
510#define NCT6779_CRITICAL_PWM_ENABLE_MASK 0x01
511static const u16 NCT6779_REG_CRITICAL_PWM[] = {
512 0x137, 0x237, 0x337, 0x837, 0x937, 0xa37, 0xb37 };
513
514static const u16 NCT6779_REG_TEMP[] = { 0x27, 0x150 };
515static const u16 NCT6779_REG_TEMP_MON[] = { 0x73, 0x75, 0x77, 0x79, 0x7b };
516static const u16 NCT6779_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
517 0x18, 0x152 };
518static const u16 NCT6779_REG_TEMP_HYST[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
519 0x3a, 0x153 };
520static const u16 NCT6779_REG_TEMP_OVER[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
521 0x39, 0x155 };
522
523static const u16 NCT6779_REG_TEMP_OFFSET[] = {
524 0x454, 0x455, 0x456, 0x44a, 0x44b, 0x44c };
525
526static const char *const nct6779_temp_label[] = {
527 "",
528 "SYSTIN",
529 "CPUTIN",
530 "AUXTIN0",
531 "AUXTIN1",
532 "AUXTIN2",
533 "AUXTIN3",
534 "",
535 "SMBUSMASTER 0",
536 "SMBUSMASTER 1",
537 "SMBUSMASTER 2",
538 "SMBUSMASTER 3",
539 "SMBUSMASTER 4",
540 "SMBUSMASTER 5",
541 "SMBUSMASTER 6",
542 "SMBUSMASTER 7",
543 "PECI Agent 0",
544 "PECI Agent 1",
545 "PCH_CHIP_CPU_MAX_TEMP",
546 "PCH_CHIP_TEMP",
547 "PCH_CPU_TEMP",
548 "PCH_MCH_TEMP",
549 "PCH_DIM0_TEMP",
550 "PCH_DIM1_TEMP",
551 "PCH_DIM2_TEMP",
552 "PCH_DIM3_TEMP",
553 "BYTE_TEMP",
554 "",
555 "",
556 "",
557 "",
558 "Virtual_TEMP"
559};
560
561#define NCT6779_TEMP_MASK 0x07ffff7e
562#define NCT6791_TEMP_MASK 0x87ffff7e
563
564static const u16 NCT6779_REG_TEMP_ALTERNATE[32]
565 = { 0x490, 0x491, 0x492, 0x493, 0x494, 0x495, 0, 0,
566 0, 0, 0, 0, 0, 0, 0, 0,
567 0, 0x400, 0x401, 0x402, 0x404, 0x405, 0x406, 0x407,
568 0x408, 0 };
569
570static const u16 NCT6779_REG_TEMP_CRIT[32] = {
571 [15] = 0x709,
572 [16] = 0x70a,
573};
574
575
576
577#define NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE 0x28
578
579static const u16 NCT6791_REG_WEIGHT_TEMP_SEL[NUM_FAN] = { 0, 0x239 };
580static const u16 NCT6791_REG_WEIGHT_TEMP_STEP[NUM_FAN] = { 0, 0x23a };
581static const u16 NCT6791_REG_WEIGHT_TEMP_STEP_TOL[NUM_FAN] = { 0, 0x23b };
582static const u16 NCT6791_REG_WEIGHT_DUTY_STEP[NUM_FAN] = { 0, 0x23c };
583static const u16 NCT6791_REG_WEIGHT_TEMP_BASE[NUM_FAN] = { 0, 0x23d };
584static const u16 NCT6791_REG_WEIGHT_DUTY_BASE[NUM_FAN] = { 0, 0x23e };
585
586static const u16 NCT6791_REG_ALARM[NUM_REG_ALARM] = {
587 0x459, 0x45A, 0x45B, 0x568, 0x45D };
588
589static const s8 NCT6791_ALARM_BITS[] = {
590 0, 1, 2, 3, 8, 21, 20, 16,
591 17, 24, 25, 26, 27, 28, 29,
592 -1,
593 6, 7, 11, 10, 23, 33,
594 -1, -1,
595 4, 5, 13, -1, -1, -1,
596 12, 9 };
597
598
599
600static const u16 NCT6792_REG_TEMP_MON[] = {
601 0x73, 0x75, 0x77, 0x79, 0x7b, 0x7d };
602static const u16 NCT6792_REG_BEEP[NUM_REG_BEEP] = {
603 0xb2, 0xb3, 0xb4, 0xb5, 0xbf };
604
605static const char *const nct6792_temp_label[] = {
606 "",
607 "SYSTIN",
608 "CPUTIN",
609 "AUXTIN0",
610 "AUXTIN1",
611 "AUXTIN2",
612 "AUXTIN3",
613 "",
614 "SMBUSMASTER 0",
615 "SMBUSMASTER 1",
616 "SMBUSMASTER 2",
617 "SMBUSMASTER 3",
618 "SMBUSMASTER 4",
619 "SMBUSMASTER 5",
620 "SMBUSMASTER 6",
621 "SMBUSMASTER 7",
622 "PECI Agent 0",
623 "PECI Agent 1",
624 "PCH_CHIP_CPU_MAX_TEMP",
625 "PCH_CHIP_TEMP",
626 "PCH_CPU_TEMP",
627 "PCH_MCH_TEMP",
628 "PCH_DIM0_TEMP",
629 "PCH_DIM1_TEMP",
630 "PCH_DIM2_TEMP",
631 "PCH_DIM3_TEMP",
632 "BYTE_TEMP",
633 "PECI Agent 0 Calibration",
634 "PECI Agent 1 Calibration",
635 "",
636 "",
637 "Virtual_TEMP"
638};
639
640#define NCT6792_TEMP_MASK 0x9fffff7e
641
642static const char *const nct6793_temp_label[] = {
643 "",
644 "SYSTIN",
645 "CPUTIN",
646 "AUXTIN0",
647 "AUXTIN1",
648 "AUXTIN2",
649 "AUXTIN3",
650 "",
651 "SMBUSMASTER 0",
652 "SMBUSMASTER 1",
653 "",
654 "",
655 "",
656 "",
657 "",
658 "",
659 "PECI Agent 0",
660 "PECI Agent 1",
661 "PCH_CHIP_CPU_MAX_TEMP",
662 "PCH_CHIP_TEMP",
663 "PCH_CPU_TEMP",
664 "PCH_MCH_TEMP",
665 "Agent0 Dimm0 ",
666 "Agent0 Dimm1",
667 "Agent1 Dimm0",
668 "Agent1 Dimm1",
669 "BYTE_TEMP0",
670 "BYTE_TEMP1",
671 "PECI Agent 0 Calibration",
672 "PECI Agent 1 Calibration",
673 "",
674 "Virtual_TEMP"
675};
676
677#define NCT6793_TEMP_MASK 0xbfff037e
678
679static const char *const nct6795_temp_label[] = {
680 "",
681 "SYSTIN",
682 "CPUTIN",
683 "AUXTIN0",
684 "AUXTIN1",
685 "AUXTIN2",
686 "AUXTIN3",
687 "",
688 "SMBUSMASTER 0",
689 "SMBUSMASTER 1",
690 "SMBUSMASTER 2",
691 "SMBUSMASTER 3",
692 "SMBUSMASTER 4",
693 "SMBUSMASTER 5",
694 "SMBUSMASTER 6",
695 "SMBUSMASTER 7",
696 "PECI Agent 0",
697 "PECI Agent 1",
698 "PCH_CHIP_CPU_MAX_TEMP",
699 "PCH_CHIP_TEMP",
700 "PCH_CPU_TEMP",
701 "PCH_MCH_TEMP",
702 "PCH_DIM0_TEMP",
703 "PCH_DIM1_TEMP",
704 "PCH_DIM2_TEMP",
705 "PCH_DIM3_TEMP",
706 "BYTE_TEMP0",
707 "BYTE_TEMP1",
708 "PECI Agent 0 Calibration",
709 "PECI Agent 1 Calibration",
710 "",
711 "Virtual_TEMP"
712};
713
714#define NCT6795_TEMP_MASK 0xbfffff7e
715
716static const char *const nct6796_temp_label[] = {
717 "",
718 "SYSTIN",
719 "CPUTIN",
720 "AUXTIN0",
721 "AUXTIN1",
722 "AUXTIN2",
723 "AUXTIN3",
724 "AUXTIN4",
725 "SMBUSMASTER 0",
726 "SMBUSMASTER 1",
727 "",
728 "",
729 "",
730 "",
731 "",
732 "",
733 "PECI Agent 0",
734 "PECI Agent 1",
735 "PCH_CHIP_CPU_MAX_TEMP",
736 "PCH_CHIP_TEMP",
737 "PCH_CPU_TEMP",
738 "PCH_MCH_TEMP",
739 "PCH_DIM0_TEMP",
740 "PCH_DIM1_TEMP",
741 "PCH_DIM2_TEMP",
742 "PCH_DIM3_TEMP",
743 "BYTE_TEMP0",
744 "BYTE_TEMP1",
745 "PECI Agent 0 Calibration",
746 "PECI Agent 1 Calibration",
747 "",
748 "Virtual_TEMP"
749};
750
751#define NCT6796_TEMP_MASK 0xbfff03fe
752
753
754
755#define NCT6106_REG_VBAT 0x318
756#define NCT6106_REG_DIODE 0x319
757#define NCT6106_DIODE_MASK 0x01
758
759static const u16 NCT6106_REG_IN_MAX[] = {
760 0x90, 0x92, 0x94, 0x96, 0x98, 0x9a, 0x9e, 0xa0, 0xa2 };
761static const u16 NCT6106_REG_IN_MIN[] = {
762 0x91, 0x93, 0x95, 0x97, 0x99, 0x9b, 0x9f, 0xa1, 0xa3 };
763static const u16 NCT6106_REG_IN[] = {
764 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x07, 0x08, 0x09 };
765
766static const u16 NCT6106_REG_TEMP[] = { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15 };
767static const u16 NCT6106_REG_TEMP_MON[] = { 0x18, 0x19, 0x1a };
768static const u16 NCT6106_REG_TEMP_HYST[] = {
769 0xc3, 0xc7, 0xcb, 0xcf, 0xd3, 0xd7 };
770static const u16 NCT6106_REG_TEMP_OVER[] = {
771 0xc2, 0xc6, 0xca, 0xce, 0xd2, 0xd6 };
772static const u16 NCT6106_REG_TEMP_CRIT_L[] = {
773 0xc0, 0xc4, 0xc8, 0xcc, 0xd0, 0xd4 };
774static const u16 NCT6106_REG_TEMP_CRIT_H[] = {
775 0xc1, 0xc5, 0xc9, 0xcf, 0xd1, 0xd5 };
776static const u16 NCT6106_REG_TEMP_OFFSET[] = { 0x311, 0x312, 0x313 };
777static const u16 NCT6106_REG_TEMP_CONFIG[] = {
778 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc };
779
780static const u16 NCT6106_REG_FAN[] = { 0x20, 0x22, 0x24 };
781static const u16 NCT6106_REG_FAN_MIN[] = { 0xe0, 0xe2, 0xe4 };
782static const u16 NCT6106_REG_FAN_PULSES[] = { 0xf6, 0xf6, 0xf6, 0, 0 };
783static const u16 NCT6106_FAN_PULSE_SHIFT[] = { 0, 2, 4, 0, 0 };
784
785static const u8 NCT6106_REG_PWM_MODE[] = { 0xf3, 0xf3, 0xf3 };
786static const u8 NCT6106_PWM_MODE_MASK[] = { 0x01, 0x02, 0x04 };
787static const u16 NCT6106_REG_PWM[] = { 0x119, 0x129, 0x139 };
788static const u16 NCT6106_REG_PWM_READ[] = { 0x4a, 0x4b, 0x4c };
789static const u16 NCT6106_REG_FAN_MODE[] = { 0x113, 0x123, 0x133 };
790static const u16 NCT6106_REG_TEMP_SEL[] = { 0x110, 0x120, 0x130 };
791static const u16 NCT6106_REG_TEMP_SOURCE[] = {
792 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5 };
793
794static const u16 NCT6106_REG_CRITICAL_TEMP[] = { 0x11a, 0x12a, 0x13a };
795static const u16 NCT6106_REG_CRITICAL_TEMP_TOLERANCE[] = {
796 0x11b, 0x12b, 0x13b };
797
798static const u16 NCT6106_REG_CRITICAL_PWM_ENABLE[] = { 0x11c, 0x12c, 0x13c };
799#define NCT6106_CRITICAL_PWM_ENABLE_MASK 0x10
800static const u16 NCT6106_REG_CRITICAL_PWM[] = { 0x11d, 0x12d, 0x13d };
801
802static const u16 NCT6106_REG_FAN_STEP_UP_TIME[] = { 0x114, 0x124, 0x134 };
803static const u16 NCT6106_REG_FAN_STEP_DOWN_TIME[] = { 0x115, 0x125, 0x135 };
804static const u16 NCT6106_REG_FAN_STOP_OUTPUT[] = { 0x116, 0x126, 0x136 };
805static const u16 NCT6106_REG_FAN_START_OUTPUT[] = { 0x117, 0x127, 0x137 };
806static const u16 NCT6106_REG_FAN_STOP_TIME[] = { 0x118, 0x128, 0x138 };
807static const u16 NCT6106_REG_TOLERANCE_H[] = { 0x112, 0x122, 0x132 };
808
809static const u16 NCT6106_REG_TARGET[] = { 0x111, 0x121, 0x131 };
810
811static const u16 NCT6106_REG_WEIGHT_TEMP_SEL[] = { 0x168, 0x178, 0x188 };
812static const u16 NCT6106_REG_WEIGHT_TEMP_STEP[] = { 0x169, 0x179, 0x189 };
813static const u16 NCT6106_REG_WEIGHT_TEMP_STEP_TOL[] = { 0x16a, 0x17a, 0x18a };
814static const u16 NCT6106_REG_WEIGHT_DUTY_STEP[] = { 0x16b, 0x17b, 0x17c };
815static const u16 NCT6106_REG_WEIGHT_TEMP_BASE[] = { 0x16c, 0x17c, 0x18c };
816static const u16 NCT6106_REG_WEIGHT_DUTY_BASE[] = { 0x16d, 0x17d, 0x18d };
817
818static const u16 NCT6106_REG_AUTO_TEMP[] = { 0x160, 0x170, 0x180 };
819static const u16 NCT6106_REG_AUTO_PWM[] = { 0x164, 0x174, 0x184 };
820
821static const u16 NCT6106_REG_ALARM[NUM_REG_ALARM] = {
822 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d };
823
824static const s8 NCT6106_ALARM_BITS[] = {
825 0, 1, 2, 3, 4, 5, 7, 8,
826 9, -1, -1, -1, -1, -1, -1,
827 -1,
828 32, 33, 34, -1, -1,
829 -1, -1, -1,
830 16, 17, 18, 19, 20, 21,
831 48, -1
832};
833
834static const u16 NCT6106_REG_BEEP[NUM_REG_BEEP] = {
835 0x3c0, 0x3c1, 0x3c2, 0x3c3, 0x3c4 };
836
837static const s8 NCT6106_BEEP_BITS[] = {
838 0, 1, 2, 3, 4, 5, 7, 8,
839 9, 10, 11, 12, -1, -1, -1,
840 32,
841 24, 25, 26, 27, 28,
842 -1, -1, -1,
843 16, 17, 18, 19, 20, 21,
844 34, -1
845};
846
847static const u16 NCT6106_REG_TEMP_ALTERNATE[32] = {
848 [14] = 0x51,
849 [15] = 0x52,
850 [16] = 0x54,
851};
852
853static const u16 NCT6106_REG_TEMP_CRIT[32] = {
854 [11] = 0x204,
855 [12] = 0x205,
856};
857
858static enum pwm_enable reg_to_pwm_enable(int pwm, int mode)
859{
860 if (mode == 0 && pwm == 255)
861 return off;
862 return mode + 1;
863}
864
865static int pwm_enable_to_reg(enum pwm_enable mode)
866{
867 if (mode == off)
868 return 0;
869 return mode - 1;
870}
871
872
873
874
875
876
877static unsigned int step_time_from_reg(u8 reg, u8 mode)
878{
879 return mode ? 400 * reg : 100 * reg;
880}
881
882static u8 step_time_to_reg(unsigned int msec, u8 mode)
883{
884 return clamp_val((mode ? (msec + 200) / 400 :
885 (msec + 50) / 100), 1, 255);
886}
887
888static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
889{
890 if (reg == 0 || reg == 255)
891 return 0;
892 return 1350000U / (reg << divreg);
893}
894
895static unsigned int fan_from_reg13(u16 reg, unsigned int divreg)
896{
897 if ((reg & 0xff1f) == 0xff1f)
898 return 0;
899
900 reg = (reg & 0x1f) | ((reg & 0xff00) >> 3);
901
902 if (reg == 0)
903 return 0;
904
905 return 1350000U / reg;
906}
907
908static unsigned int fan_from_reg16(u16 reg, unsigned int divreg)
909{
910 if (reg == 0 || reg == 0xffff)
911 return 0;
912
913
914
915
916
917 return 1350000U / (reg << divreg);
918}
919
920static u16 fan_to_reg(u32 fan, unsigned int divreg)
921{
922 if (!fan)
923 return 0;
924
925 return (1350000U / fan) >> divreg;
926}
927
928static inline unsigned int
929div_from_reg(u8 reg)
930{
931 return BIT(reg);
932}
933
934
935
936
937
938static const u16 scale_in[15] = {
939 800, 800, 1600, 1600, 800, 800, 800, 1600, 1600, 800, 800, 800, 800,
940 800, 800
941};
942
943static inline long in_from_reg(u8 reg, u8 nr)
944{
945 return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100);
946}
947
948static inline u8 in_to_reg(u32 val, u8 nr)
949{
950 return clamp_val(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0, 255);
951}
952
953
954
955
956
957struct nct6775_data {
958 int addr;
959 int sioreg;
960 enum kinds kind;
961 const char *name;
962
963 const struct attribute_group *groups[6];
964
965 u16 reg_temp[5][NUM_TEMP];
966
967
968 u8 temp_src[NUM_TEMP];
969 u16 reg_temp_config[NUM_TEMP];
970 const char * const *temp_label;
971 u32 temp_mask;
972
973 u16 REG_CONFIG;
974 u16 REG_VBAT;
975 u16 REG_DIODE;
976 u8 DIODE_MASK;
977
978 const s8 *ALARM_BITS;
979 const s8 *BEEP_BITS;
980
981 const u16 *REG_VIN;
982 const u16 *REG_IN_MINMAX[2];
983
984 const u16 *REG_TARGET;
985 const u16 *REG_FAN;
986 const u16 *REG_FAN_MODE;
987 const u16 *REG_FAN_MIN;
988 const u16 *REG_FAN_PULSES;
989 const u16 *FAN_PULSE_SHIFT;
990 const u16 *REG_FAN_TIME[3];
991
992 const u16 *REG_TOLERANCE_H;
993
994 const u8 *REG_PWM_MODE;
995 const u8 *PWM_MODE_MASK;
996
997 const u16 *REG_PWM[7];
998
999
1000
1001 const u16 *REG_PWM_READ;
1002
1003 const u16 *REG_CRITICAL_PWM_ENABLE;
1004 u8 CRITICAL_PWM_ENABLE_MASK;
1005 const u16 *REG_CRITICAL_PWM;
1006
1007 const u16 *REG_AUTO_TEMP;
1008 const u16 *REG_AUTO_PWM;
1009
1010 const u16 *REG_CRITICAL_TEMP;
1011 const u16 *REG_CRITICAL_TEMP_TOLERANCE;
1012
1013 const u16 *REG_TEMP_SOURCE;
1014 const u16 *REG_TEMP_SEL;
1015 const u16 *REG_WEIGHT_TEMP_SEL;
1016 const u16 *REG_WEIGHT_TEMP[3];
1017
1018 const u16 *REG_TEMP_OFFSET;
1019
1020 const u16 *REG_ALARM;
1021 const u16 *REG_BEEP;
1022
1023 unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg);
1024 unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg);
1025
1026 struct mutex update_lock;
1027 bool valid;
1028 unsigned long last_updated;
1029
1030
1031 u8 bank;
1032 u8 in_num;
1033 u8 in[15][3];
1034 unsigned int rpm[NUM_FAN];
1035 u16 fan_min[NUM_FAN];
1036 u8 fan_pulses[NUM_FAN];
1037 u8 fan_div[NUM_FAN];
1038 u8 has_pwm;
1039 u8 has_fan;
1040 u8 has_fan_min;
1041 bool has_fan_div;
1042
1043 u8 num_temp_alarms;
1044 u8 num_temp_beeps;
1045 u8 temp_fixed_num;
1046 u8 temp_type[NUM_TEMP_FIXED];
1047 s8 temp_offset[NUM_TEMP_FIXED];
1048 s16 temp[5][NUM_TEMP];
1049
1050 u64 alarms;
1051 u64 beeps;
1052
1053 u8 pwm_num;
1054 u8 pwm_mode[NUM_FAN];
1055
1056
1057 enum pwm_enable pwm_enable[NUM_FAN];
1058
1059
1060
1061
1062
1063
1064
1065 u8 pwm[7][NUM_FAN];
1066
1067
1068
1069
1070 u8 target_temp[NUM_FAN];
1071 u8 target_temp_mask;
1072 u32 target_speed[NUM_FAN];
1073 u32 target_speed_tolerance[NUM_FAN];
1074 u8 speed_tolerance_limit;
1075
1076 u8 temp_tolerance[2][NUM_FAN];
1077 u8 tolerance_mask;
1078
1079 u8 fan_time[3][NUM_FAN];
1080
1081
1082 int auto_pwm_num;
1083 u8 auto_pwm[NUM_FAN][7];
1084 u8 auto_temp[NUM_FAN][7];
1085 u8 pwm_temp_sel[NUM_FAN];
1086 u8 pwm_weight_temp_sel[NUM_FAN];
1087 u8 weight_temp[3][NUM_FAN];
1088
1089
1090
1091 u8 vid;
1092 u8 vrm;
1093
1094 bool have_vid;
1095
1096 u16 have_temp;
1097 u16 have_temp_fixed;
1098 u16 have_in;
1099
1100
1101 u8 vbat;
1102 u8 fandiv1;
1103 u8 fandiv2;
1104 u8 sio_reg_enable;
1105};
1106
1107struct nct6775_sio_data {
1108 int sioreg;
1109 enum kinds kind;
1110};
1111
1112struct sensor_device_template {
1113 struct device_attribute dev_attr;
1114 union {
1115 struct {
1116 u8 nr;
1117 u8 index;
1118 } s;
1119 int index;
1120 } u;
1121 bool s2;
1122};
1123
1124struct sensor_device_attr_u {
1125 union {
1126 struct sensor_device_attribute a1;
1127 struct sensor_device_attribute_2 a2;
1128 } u;
1129 char name[32];
1130};
1131
1132#define __TEMPLATE_ATTR(_template, _mode, _show, _store) { \
1133 .attr = {.name = _template, .mode = _mode }, \
1134 .show = _show, \
1135 .store = _store, \
1136}
1137
1138#define SENSOR_DEVICE_TEMPLATE(_template, _mode, _show, _store, _index) \
1139 { .dev_attr = __TEMPLATE_ATTR(_template, _mode, _show, _store), \
1140 .u.index = _index, \
1141 .s2 = false }
1142
1143#define SENSOR_DEVICE_TEMPLATE_2(_template, _mode, _show, _store, \
1144 _nr, _index) \
1145 { .dev_attr = __TEMPLATE_ATTR(_template, _mode, _show, _store), \
1146 .u.s.index = _index, \
1147 .u.s.nr = _nr, \
1148 .s2 = true }
1149
1150#define SENSOR_TEMPLATE(_name, _template, _mode, _show, _store, _index) \
1151static struct sensor_device_template sensor_dev_template_##_name \
1152 = SENSOR_DEVICE_TEMPLATE(_template, _mode, _show, _store, \
1153 _index)
1154
1155#define SENSOR_TEMPLATE_2(_name, _template, _mode, _show, _store, \
1156 _nr, _index) \
1157static struct sensor_device_template sensor_dev_template_##_name \
1158 = SENSOR_DEVICE_TEMPLATE_2(_template, _mode, _show, _store, \
1159 _nr, _index)
1160
1161struct sensor_template_group {
1162 struct sensor_device_template **templates;
1163 umode_t (*is_visible)(struct kobject *, struct attribute *, int);
1164 int base;
1165};
1166
1167static struct attribute_group *
1168nct6775_create_attr_group(struct device *dev,
1169 const struct sensor_template_group *tg,
1170 int repeat)
1171{
1172 struct attribute_group *group;
1173 struct sensor_device_attr_u *su;
1174 struct sensor_device_attribute *a;
1175 struct sensor_device_attribute_2 *a2;
1176 struct attribute **attrs;
1177 struct sensor_device_template **t;
1178 int i, count;
1179
1180 if (repeat <= 0)
1181 return ERR_PTR(-EINVAL);
1182
1183 t = tg->templates;
1184 for (count = 0; *t; t++, count++)
1185 ;
1186
1187 if (count == 0)
1188 return ERR_PTR(-EINVAL);
1189
1190 group = devm_kzalloc(dev, sizeof(*group), GFP_KERNEL);
1191 if (group == NULL)
1192 return ERR_PTR(-ENOMEM);
1193
1194 attrs = devm_kcalloc(dev, repeat * count + 1, sizeof(*attrs),
1195 GFP_KERNEL);
1196 if (attrs == NULL)
1197 return ERR_PTR(-ENOMEM);
1198
1199 su = devm_kzalloc(dev, array3_size(repeat, count, sizeof(*su)),
1200 GFP_KERNEL);
1201 if (su == NULL)
1202 return ERR_PTR(-ENOMEM);
1203
1204 group->attrs = attrs;
1205 group->is_visible = tg->is_visible;
1206
1207 for (i = 0; i < repeat; i++) {
1208 t = tg->templates;
1209 while (*t != NULL) {
1210 snprintf(su->name, sizeof(su->name),
1211 (*t)->dev_attr.attr.name, tg->base + i);
1212 if ((*t)->s2) {
1213 a2 = &su->u.a2;
1214 sysfs_attr_init(&a2->dev_attr.attr);
1215 a2->dev_attr.attr.name = su->name;
1216 a2->nr = (*t)->u.s.nr + i;
1217 a2->index = (*t)->u.s.index;
1218 a2->dev_attr.attr.mode =
1219 (*t)->dev_attr.attr.mode;
1220 a2->dev_attr.show = (*t)->dev_attr.show;
1221 a2->dev_attr.store = (*t)->dev_attr.store;
1222 *attrs = &a2->dev_attr.attr;
1223 } else {
1224 a = &su->u.a1;
1225 sysfs_attr_init(&a->dev_attr.attr);
1226 a->dev_attr.attr.name = su->name;
1227 a->index = (*t)->u.index + i;
1228 a->dev_attr.attr.mode =
1229 (*t)->dev_attr.attr.mode;
1230 a->dev_attr.show = (*t)->dev_attr.show;
1231 a->dev_attr.store = (*t)->dev_attr.store;
1232 *attrs = &a->dev_attr.attr;
1233 }
1234 attrs++;
1235 su++;
1236 t++;
1237 }
1238 }
1239
1240 return group;
1241}
1242
1243static bool is_word_sized(struct nct6775_data *data, u16 reg)
1244{
1245 switch (data->kind) {
1246 case nct6106:
1247 return reg == 0x20 || reg == 0x22 || reg == 0x24 ||
1248 reg == 0xe0 || reg == 0xe2 || reg == 0xe4 ||
1249 reg == 0x111 || reg == 0x121 || reg == 0x131;
1250 case nct6775:
1251 return (((reg & 0xff00) == 0x100 ||
1252 (reg & 0xff00) == 0x200) &&
1253 ((reg & 0x00ff) == 0x50 ||
1254 (reg & 0x00ff) == 0x53 ||
1255 (reg & 0x00ff) == 0x55)) ||
1256 (reg & 0xfff0) == 0x630 ||
1257 reg == 0x640 || reg == 0x642 ||
1258 reg == 0x662 ||
1259 ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) ||
1260 reg == 0x73 || reg == 0x75 || reg == 0x77;
1261 case nct6776:
1262 return (((reg & 0xff00) == 0x100 ||
1263 (reg & 0xff00) == 0x200) &&
1264 ((reg & 0x00ff) == 0x50 ||
1265 (reg & 0x00ff) == 0x53 ||
1266 (reg & 0x00ff) == 0x55)) ||
1267 (reg & 0xfff0) == 0x630 ||
1268 reg == 0x402 ||
1269 reg == 0x640 || reg == 0x642 ||
1270 ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) ||
1271 reg == 0x73 || reg == 0x75 || reg == 0x77;
1272 case nct6779:
1273 case nct6791:
1274 case nct6792:
1275 case nct6793:
1276 case nct6795:
1277 case nct6796:
1278 return reg == 0x150 || reg == 0x153 || reg == 0x155 ||
1279 ((reg & 0xfff0) == 0x4b0 && (reg & 0x000f) < 0x0b) ||
1280 reg == 0x402 ||
1281 reg == 0x63a || reg == 0x63c || reg == 0x63e ||
1282 reg == 0x640 || reg == 0x642 || reg == 0x64a ||
1283 reg == 0x64c || reg == 0x660 ||
1284 reg == 0x73 || reg == 0x75 || reg == 0x77 || reg == 0x79 ||
1285 reg == 0x7b || reg == 0x7d;
1286 }
1287 return false;
1288}
1289
1290
1291
1292
1293
1294
1295
1296static inline void nct6775_set_bank(struct nct6775_data *data, u16 reg)
1297{
1298 u8 bank = reg >> 8;
1299
1300 if (data->bank != bank) {
1301 outb_p(NCT6775_REG_BANK, data->addr + ADDR_REG_OFFSET);
1302 outb_p(bank, data->addr + DATA_REG_OFFSET);
1303 data->bank = bank;
1304 }
1305}
1306
1307static u16 nct6775_read_value(struct nct6775_data *data, u16 reg)
1308{
1309 int res, word_sized = is_word_sized(data, reg);
1310
1311 nct6775_set_bank(data, reg);
1312 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
1313 res = inb_p(data->addr + DATA_REG_OFFSET);
1314 if (word_sized) {
1315 outb_p((reg & 0xff) + 1,
1316 data->addr + ADDR_REG_OFFSET);
1317 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
1318 }
1319 return res;
1320}
1321
1322static int nct6775_write_value(struct nct6775_data *data, u16 reg, u16 value)
1323{
1324 int word_sized = is_word_sized(data, reg);
1325
1326 nct6775_set_bank(data, reg);
1327 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
1328 if (word_sized) {
1329 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
1330 outb_p((reg & 0xff) + 1,
1331 data->addr + ADDR_REG_OFFSET);
1332 }
1333 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
1334 return 0;
1335}
1336
1337
1338static u16 nct6775_read_temp(struct nct6775_data *data, u16 reg)
1339{
1340 u16 res;
1341
1342 res = nct6775_read_value(data, reg);
1343 if (!is_word_sized(data, reg))
1344 res <<= 8;
1345
1346 return res;
1347}
1348
1349static int nct6775_write_temp(struct nct6775_data *data, u16 reg, u16 value)
1350{
1351 if (!is_word_sized(data, reg))
1352 value >>= 8;
1353 return nct6775_write_value(data, reg, value);
1354}
1355
1356
1357static void nct6775_write_fan_div(struct nct6775_data *data, int nr)
1358{
1359 u8 reg;
1360
1361 switch (nr) {
1362 case 0:
1363 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x70)
1364 | (data->fan_div[0] & 0x7);
1365 nct6775_write_value(data, NCT6775_REG_FANDIV1, reg);
1366 break;
1367 case 1:
1368 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x7)
1369 | ((data->fan_div[1] << 4) & 0x70);
1370 nct6775_write_value(data, NCT6775_REG_FANDIV1, reg);
1371 break;
1372 case 2:
1373 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x70)
1374 | (data->fan_div[2] & 0x7);
1375 nct6775_write_value(data, NCT6775_REG_FANDIV2, reg);
1376 break;
1377 case 3:
1378 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x7)
1379 | ((data->fan_div[3] << 4) & 0x70);
1380 nct6775_write_value(data, NCT6775_REG_FANDIV2, reg);
1381 break;
1382 }
1383}
1384
1385static void nct6775_write_fan_div_common(struct nct6775_data *data, int nr)
1386{
1387 if (data->kind == nct6775)
1388 nct6775_write_fan_div(data, nr);
1389}
1390
1391static void nct6775_update_fan_div(struct nct6775_data *data)
1392{
1393 u8 i;
1394
1395 i = nct6775_read_value(data, NCT6775_REG_FANDIV1);
1396 data->fan_div[0] = i & 0x7;
1397 data->fan_div[1] = (i & 0x70) >> 4;
1398 i = nct6775_read_value(data, NCT6775_REG_FANDIV2);
1399 data->fan_div[2] = i & 0x7;
1400 if (data->has_fan & BIT(3))
1401 data->fan_div[3] = (i & 0x70) >> 4;
1402}
1403
1404static void nct6775_update_fan_div_common(struct nct6775_data *data)
1405{
1406 if (data->kind == nct6775)
1407 nct6775_update_fan_div(data);
1408}
1409
1410static void nct6775_init_fan_div(struct nct6775_data *data)
1411{
1412 int i;
1413
1414 nct6775_update_fan_div_common(data);
1415
1416
1417
1418
1419
1420
1421 for (i = 0; i < ARRAY_SIZE(data->fan_div); i++) {
1422 if (!(data->has_fan & BIT(i)))
1423 continue;
1424 if (data->fan_div[i] == 0) {
1425 data->fan_div[i] = 7;
1426 nct6775_write_fan_div_common(data, i);
1427 }
1428 }
1429}
1430
1431static void nct6775_init_fan_common(struct device *dev,
1432 struct nct6775_data *data)
1433{
1434 int i;
1435 u8 reg;
1436
1437 if (data->has_fan_div)
1438 nct6775_init_fan_div(data);
1439
1440
1441
1442
1443
1444 for (i = 0; i < ARRAY_SIZE(data->fan_min); i++) {
1445 if (data->has_fan_min & BIT(i)) {
1446 reg = nct6775_read_value(data, data->REG_FAN_MIN[i]);
1447 if (!reg)
1448 nct6775_write_value(data, data->REG_FAN_MIN[i],
1449 data->has_fan_div ? 0xff
1450 : 0xff1f);
1451 }
1452 }
1453}
1454
1455static void nct6775_select_fan_div(struct device *dev,
1456 struct nct6775_data *data, int nr, u16 reg)
1457{
1458 u8 fan_div = data->fan_div[nr];
1459 u16 fan_min;
1460
1461 if (!data->has_fan_div)
1462 return;
1463
1464
1465
1466
1467
1468
1469 if (reg == 0x00 && fan_div < 0x07)
1470 fan_div++;
1471 else if (reg != 0x00 && reg < 0x30 && fan_div > 0)
1472 fan_div--;
1473
1474 if (fan_div != data->fan_div[nr]) {
1475 dev_dbg(dev, "Modifying fan%d clock divider from %u to %u\n",
1476 nr + 1, div_from_reg(data->fan_div[nr]),
1477 div_from_reg(fan_div));
1478
1479
1480 if (data->has_fan_min & BIT(nr)) {
1481 fan_min = data->fan_min[nr];
1482 if (fan_div > data->fan_div[nr]) {
1483 if (fan_min != 255 && fan_min > 1)
1484 fan_min >>= 1;
1485 } else {
1486 if (fan_min != 255) {
1487 fan_min <<= 1;
1488 if (fan_min > 254)
1489 fan_min = 254;
1490 }
1491 }
1492 if (fan_min != data->fan_min[nr]) {
1493 data->fan_min[nr] = fan_min;
1494 nct6775_write_value(data, data->REG_FAN_MIN[nr],
1495 fan_min);
1496 }
1497 }
1498 data->fan_div[nr] = fan_div;
1499 nct6775_write_fan_div_common(data, nr);
1500 }
1501}
1502
1503static void nct6775_update_pwm(struct device *dev)
1504{
1505 struct nct6775_data *data = dev_get_drvdata(dev);
1506 int i, j;
1507 int fanmodecfg, reg;
1508 bool duty_is_dc;
1509
1510 for (i = 0; i < data->pwm_num; i++) {
1511 if (!(data->has_pwm & BIT(i)))
1512 continue;
1513
1514 duty_is_dc = data->REG_PWM_MODE[i] &&
1515 (nct6775_read_value(data, data->REG_PWM_MODE[i])
1516 & data->PWM_MODE_MASK[i]);
1517 data->pwm_mode[i] = !duty_is_dc;
1518
1519 fanmodecfg = nct6775_read_value(data, data->REG_FAN_MODE[i]);
1520 for (j = 0; j < ARRAY_SIZE(data->REG_PWM); j++) {
1521 if (data->REG_PWM[j] && data->REG_PWM[j][i]) {
1522 data->pwm[j][i]
1523 = nct6775_read_value(data,
1524 data->REG_PWM[j][i]);
1525 }
1526 }
1527
1528 data->pwm_enable[i] = reg_to_pwm_enable(data->pwm[0][i],
1529 (fanmodecfg >> 4) & 7);
1530
1531 if (!data->temp_tolerance[0][i] ||
1532 data->pwm_enable[i] != speed_cruise)
1533 data->temp_tolerance[0][i] = fanmodecfg & 0x0f;
1534 if (!data->target_speed_tolerance[i] ||
1535 data->pwm_enable[i] == speed_cruise) {
1536 u8 t = fanmodecfg & 0x0f;
1537
1538 if (data->REG_TOLERANCE_H) {
1539 t |= (nct6775_read_value(data,
1540 data->REG_TOLERANCE_H[i]) & 0x70) >> 1;
1541 }
1542 data->target_speed_tolerance[i] = t;
1543 }
1544
1545 data->temp_tolerance[1][i] =
1546 nct6775_read_value(data,
1547 data->REG_CRITICAL_TEMP_TOLERANCE[i]);
1548
1549 reg = nct6775_read_value(data, data->REG_TEMP_SEL[i]);
1550 data->pwm_temp_sel[i] = reg & 0x1f;
1551
1552 if (reg & 0x80)
1553 data->pwm[2][i] = 0;
1554
1555 if (!data->REG_WEIGHT_TEMP_SEL[i])
1556 continue;
1557
1558 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[i]);
1559 data->pwm_weight_temp_sel[i] = reg & 0x1f;
1560
1561 if (j == 1 && !(reg & 0x80))
1562 data->pwm_weight_temp_sel[i] = 0;
1563
1564
1565 for (j = 0; j < ARRAY_SIZE(data->weight_temp); j++) {
1566 data->weight_temp[j][i]
1567 = nct6775_read_value(data,
1568 data->REG_WEIGHT_TEMP[j][i]);
1569 }
1570 }
1571}
1572
1573static void nct6775_update_pwm_limits(struct device *dev)
1574{
1575 struct nct6775_data *data = dev_get_drvdata(dev);
1576 int i, j;
1577 u8 reg;
1578 u16 reg_t;
1579
1580 for (i = 0; i < data->pwm_num; i++) {
1581 if (!(data->has_pwm & BIT(i)))
1582 continue;
1583
1584 for (j = 0; j < ARRAY_SIZE(data->fan_time); j++) {
1585 data->fan_time[j][i] =
1586 nct6775_read_value(data, data->REG_FAN_TIME[j][i]);
1587 }
1588
1589 reg_t = nct6775_read_value(data, data->REG_TARGET[i]);
1590
1591 if (!data->target_temp[i] ||
1592 data->pwm_enable[i] == thermal_cruise)
1593 data->target_temp[i] = reg_t & data->target_temp_mask;
1594 if (!data->target_speed[i] ||
1595 data->pwm_enable[i] == speed_cruise) {
1596 if (data->REG_TOLERANCE_H) {
1597 reg_t |= (nct6775_read_value(data,
1598 data->REG_TOLERANCE_H[i]) & 0x0f) << 8;
1599 }
1600 data->target_speed[i] = reg_t;
1601 }
1602
1603 for (j = 0; j < data->auto_pwm_num; j++) {
1604 data->auto_pwm[i][j] =
1605 nct6775_read_value(data,
1606 NCT6775_AUTO_PWM(data, i, j));
1607 data->auto_temp[i][j] =
1608 nct6775_read_value(data,
1609 NCT6775_AUTO_TEMP(data, i, j));
1610 }
1611
1612
1613 data->auto_temp[i][data->auto_pwm_num] =
1614 nct6775_read_value(data, data->REG_CRITICAL_TEMP[i]);
1615
1616 switch (data->kind) {
1617 case nct6775:
1618 reg = nct6775_read_value(data,
1619 NCT6775_REG_CRITICAL_ENAB[i]);
1620 data->auto_pwm[i][data->auto_pwm_num] =
1621 (reg & 0x02) ? 0xff : 0x00;
1622 break;
1623 case nct6776:
1624 data->auto_pwm[i][data->auto_pwm_num] = 0xff;
1625 break;
1626 case nct6106:
1627 case nct6779:
1628 case nct6791:
1629 case nct6792:
1630 case nct6793:
1631 case nct6795:
1632 case nct6796:
1633 reg = nct6775_read_value(data,
1634 data->REG_CRITICAL_PWM_ENABLE[i]);
1635 if (reg & data->CRITICAL_PWM_ENABLE_MASK)
1636 reg = nct6775_read_value(data,
1637 data->REG_CRITICAL_PWM[i]);
1638 else
1639 reg = 0xff;
1640 data->auto_pwm[i][data->auto_pwm_num] = reg;
1641 break;
1642 }
1643 }
1644}
1645
1646static struct nct6775_data *nct6775_update_device(struct device *dev)
1647{
1648 struct nct6775_data *data = dev_get_drvdata(dev);
1649 int i, j;
1650
1651 mutex_lock(&data->update_lock);
1652
1653 if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
1654 || !data->valid) {
1655
1656 nct6775_update_fan_div_common(data);
1657
1658
1659 for (i = 0; i < data->in_num; i++) {
1660 if (!(data->have_in & BIT(i)))
1661 continue;
1662
1663 data->in[i][0] = nct6775_read_value(data,
1664 data->REG_VIN[i]);
1665 data->in[i][1] = nct6775_read_value(data,
1666 data->REG_IN_MINMAX[0][i]);
1667 data->in[i][2] = nct6775_read_value(data,
1668 data->REG_IN_MINMAX[1][i]);
1669 }
1670
1671
1672 for (i = 0; i < ARRAY_SIZE(data->rpm); i++) {
1673 u16 reg;
1674
1675 if (!(data->has_fan & BIT(i)))
1676 continue;
1677
1678 reg = nct6775_read_value(data, data->REG_FAN[i]);
1679 data->rpm[i] = data->fan_from_reg(reg,
1680 data->fan_div[i]);
1681
1682 if (data->has_fan_min & BIT(i))
1683 data->fan_min[i] = nct6775_read_value(data,
1684 data->REG_FAN_MIN[i]);
1685 data->fan_pulses[i] =
1686 (nct6775_read_value(data, data->REG_FAN_PULSES[i])
1687 >> data->FAN_PULSE_SHIFT[i]) & 0x03;
1688
1689 nct6775_select_fan_div(dev, data, i, reg);
1690 }
1691
1692 nct6775_update_pwm(dev);
1693 nct6775_update_pwm_limits(dev);
1694
1695
1696 for (i = 0; i < NUM_TEMP; i++) {
1697 if (!(data->have_temp & BIT(i)))
1698 continue;
1699 for (j = 0; j < ARRAY_SIZE(data->reg_temp); j++) {
1700 if (data->reg_temp[j][i])
1701 data->temp[j][i]
1702 = nct6775_read_temp(data,
1703 data->reg_temp[j][i]);
1704 }
1705 if (i >= NUM_TEMP_FIXED ||
1706 !(data->have_temp_fixed & BIT(i)))
1707 continue;
1708 data->temp_offset[i]
1709 = nct6775_read_value(data, data->REG_TEMP_OFFSET[i]);
1710 }
1711
1712 data->alarms = 0;
1713 for (i = 0; i < NUM_REG_ALARM; i++) {
1714 u8 alarm;
1715
1716 if (!data->REG_ALARM[i])
1717 continue;
1718 alarm = nct6775_read_value(data, data->REG_ALARM[i]);
1719 data->alarms |= ((u64)alarm) << (i << 3);
1720 }
1721
1722 data->beeps = 0;
1723 for (i = 0; i < NUM_REG_BEEP; i++) {
1724 u8 beep;
1725
1726 if (!data->REG_BEEP[i])
1727 continue;
1728 beep = nct6775_read_value(data, data->REG_BEEP[i]);
1729 data->beeps |= ((u64)beep) << (i << 3);
1730 }
1731
1732 data->last_updated = jiffies;
1733 data->valid = true;
1734 }
1735
1736 mutex_unlock(&data->update_lock);
1737 return data;
1738}
1739
1740
1741
1742
1743static ssize_t
1744show_in_reg(struct device *dev, struct device_attribute *attr, char *buf)
1745{
1746 struct nct6775_data *data = nct6775_update_device(dev);
1747 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1748 int index = sattr->index;
1749 int nr = sattr->nr;
1750
1751 return sprintf(buf, "%ld\n", in_from_reg(data->in[nr][index], nr));
1752}
1753
1754static ssize_t
1755store_in_reg(struct device *dev, struct device_attribute *attr, const char *buf,
1756 size_t count)
1757{
1758 struct nct6775_data *data = dev_get_drvdata(dev);
1759 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1760 int index = sattr->index;
1761 int nr = sattr->nr;
1762 unsigned long val;
1763 int err;
1764
1765 err = kstrtoul(buf, 10, &val);
1766 if (err < 0)
1767 return err;
1768 mutex_lock(&data->update_lock);
1769 data->in[nr][index] = in_to_reg(val, nr);
1770 nct6775_write_value(data, data->REG_IN_MINMAX[index - 1][nr],
1771 data->in[nr][index]);
1772 mutex_unlock(&data->update_lock);
1773 return count;
1774}
1775
1776static ssize_t
1777show_alarm(struct device *dev, struct device_attribute *attr, char *buf)
1778{
1779 struct nct6775_data *data = nct6775_update_device(dev);
1780 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1781 int nr = data->ALARM_BITS[sattr->index];
1782
1783 return sprintf(buf, "%u\n",
1784 (unsigned int)((data->alarms >> nr) & 0x01));
1785}
1786
1787static int find_temp_source(struct nct6775_data *data, int index, int count)
1788{
1789 int source = data->temp_src[index];
1790 int nr;
1791
1792 for (nr = 0; nr < count; nr++) {
1793 int src;
1794
1795 src = nct6775_read_value(data,
1796 data->REG_TEMP_SOURCE[nr]) & 0x1f;
1797 if (src == source)
1798 return nr;
1799 }
1800 return -ENODEV;
1801}
1802
1803static ssize_t
1804show_temp_alarm(struct device *dev, struct device_attribute *attr, char *buf)
1805{
1806 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1807 struct nct6775_data *data = nct6775_update_device(dev);
1808 unsigned int alarm = 0;
1809 int nr;
1810
1811
1812
1813
1814
1815 nr = find_temp_source(data, sattr->index, data->num_temp_alarms);
1816 if (nr >= 0) {
1817 int bit = data->ALARM_BITS[nr + TEMP_ALARM_BASE];
1818
1819 alarm = (data->alarms >> bit) & 0x01;
1820 }
1821 return sprintf(buf, "%u\n", alarm);
1822}
1823
1824static ssize_t
1825show_beep(struct device *dev, struct device_attribute *attr, char *buf)
1826{
1827 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1828 struct nct6775_data *data = nct6775_update_device(dev);
1829 int nr = data->BEEP_BITS[sattr->index];
1830
1831 return sprintf(buf, "%u\n",
1832 (unsigned int)((data->beeps >> nr) & 0x01));
1833}
1834
1835static ssize_t
1836store_beep(struct device *dev, struct device_attribute *attr, const char *buf,
1837 size_t count)
1838{
1839 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1840 struct nct6775_data *data = dev_get_drvdata(dev);
1841 int nr = data->BEEP_BITS[sattr->index];
1842 int regindex = nr >> 3;
1843 unsigned long val;
1844 int err;
1845
1846 err = kstrtoul(buf, 10, &val);
1847 if (err < 0)
1848 return err;
1849 if (val > 1)
1850 return -EINVAL;
1851
1852 mutex_lock(&data->update_lock);
1853 if (val)
1854 data->beeps |= (1ULL << nr);
1855 else
1856 data->beeps &= ~(1ULL << nr);
1857 nct6775_write_value(data, data->REG_BEEP[regindex],
1858 (data->beeps >> (regindex << 3)) & 0xff);
1859 mutex_unlock(&data->update_lock);
1860 return count;
1861}
1862
1863static ssize_t
1864show_temp_beep(struct device *dev, struct device_attribute *attr, char *buf)
1865{
1866 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1867 struct nct6775_data *data = nct6775_update_device(dev);
1868 unsigned int beep = 0;
1869 int nr;
1870
1871
1872
1873
1874
1875
1876 nr = find_temp_source(data, sattr->index, data->num_temp_beeps);
1877 if (nr >= 0) {
1878 int bit = data->BEEP_BITS[nr + TEMP_ALARM_BASE];
1879
1880 beep = (data->beeps >> bit) & 0x01;
1881 }
1882 return sprintf(buf, "%u\n", beep);
1883}
1884
1885static ssize_t
1886store_temp_beep(struct device *dev, struct device_attribute *attr,
1887 const char *buf, size_t count)
1888{
1889 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1890 struct nct6775_data *data = dev_get_drvdata(dev);
1891 int nr, bit, regindex;
1892 unsigned long val;
1893 int err;
1894
1895 err = kstrtoul(buf, 10, &val);
1896 if (err < 0)
1897 return err;
1898 if (val > 1)
1899 return -EINVAL;
1900
1901 nr = find_temp_source(data, sattr->index, data->num_temp_beeps);
1902 if (nr < 0)
1903 return nr;
1904
1905 bit = data->BEEP_BITS[nr + TEMP_ALARM_BASE];
1906 regindex = bit >> 3;
1907
1908 mutex_lock(&data->update_lock);
1909 if (val)
1910 data->beeps |= (1ULL << bit);
1911 else
1912 data->beeps &= ~(1ULL << bit);
1913 nct6775_write_value(data, data->REG_BEEP[regindex],
1914 (data->beeps >> (regindex << 3)) & 0xff);
1915 mutex_unlock(&data->update_lock);
1916
1917 return count;
1918}
1919
1920static umode_t nct6775_in_is_visible(struct kobject *kobj,
1921 struct attribute *attr, int index)
1922{
1923 struct device *dev = container_of(kobj, struct device, kobj);
1924 struct nct6775_data *data = dev_get_drvdata(dev);
1925 int in = index / 5;
1926
1927 if (!(data->have_in & BIT(in)))
1928 return 0;
1929
1930 return attr->mode;
1931}
1932
1933SENSOR_TEMPLATE_2(in_input, "in%d_input", S_IRUGO, show_in_reg, NULL, 0, 0);
1934SENSOR_TEMPLATE(in_alarm, "in%d_alarm", S_IRUGO, show_alarm, NULL, 0);
1935SENSOR_TEMPLATE(in_beep, "in%d_beep", S_IWUSR | S_IRUGO, show_beep, store_beep,
1936 0);
1937SENSOR_TEMPLATE_2(in_min, "in%d_min", S_IWUSR | S_IRUGO, show_in_reg,
1938 store_in_reg, 0, 1);
1939SENSOR_TEMPLATE_2(in_max, "in%d_max", S_IWUSR | S_IRUGO, show_in_reg,
1940 store_in_reg, 0, 2);
1941
1942
1943
1944
1945
1946
1947static struct sensor_device_template *nct6775_attributes_in_template[] = {
1948 &sensor_dev_template_in_input,
1949 &sensor_dev_template_in_alarm,
1950 &sensor_dev_template_in_beep,
1951 &sensor_dev_template_in_min,
1952 &sensor_dev_template_in_max,
1953 NULL
1954};
1955
1956static const struct sensor_template_group nct6775_in_template_group = {
1957 .templates = nct6775_attributes_in_template,
1958 .is_visible = nct6775_in_is_visible,
1959};
1960
1961static ssize_t
1962show_fan(struct device *dev, struct device_attribute *attr, char *buf)
1963{
1964 struct nct6775_data *data = nct6775_update_device(dev);
1965 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1966 int nr = sattr->index;
1967
1968 return sprintf(buf, "%d\n", data->rpm[nr]);
1969}
1970
1971static ssize_t
1972show_fan_min(struct device *dev, struct device_attribute *attr, char *buf)
1973{
1974 struct nct6775_data *data = nct6775_update_device(dev);
1975 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1976 int nr = sattr->index;
1977
1978 return sprintf(buf, "%d\n",
1979 data->fan_from_reg_min(data->fan_min[nr],
1980 data->fan_div[nr]));
1981}
1982
1983static ssize_t
1984show_fan_div(struct device *dev, struct device_attribute *attr, char *buf)
1985{
1986 struct nct6775_data *data = nct6775_update_device(dev);
1987 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1988 int nr = sattr->index;
1989
1990 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
1991}
1992
1993static ssize_t
1994store_fan_min(struct device *dev, struct device_attribute *attr,
1995 const char *buf, size_t count)
1996{
1997 struct nct6775_data *data = dev_get_drvdata(dev);
1998 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1999 int nr = sattr->index;
2000 unsigned long val;
2001 unsigned int reg;
2002 u8 new_div;
2003 int err;
2004
2005 err = kstrtoul(buf, 10, &val);
2006 if (err < 0)
2007 return err;
2008
2009 mutex_lock(&data->update_lock);
2010 if (!data->has_fan_div) {
2011
2012 if (!val) {
2013 val = 0xff1f;
2014 } else {
2015 if (val > 1350000U)
2016 val = 135000U;
2017 val = 1350000U / val;
2018 val = (val & 0x1f) | ((val << 3) & 0xff00);
2019 }
2020 data->fan_min[nr] = val;
2021 goto write_min;
2022 }
2023 if (!val) {
2024
2025 data->fan_min[nr] = 255;
2026 new_div = data->fan_div[nr];
2027 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
2028 goto write_div;
2029 }
2030 reg = 1350000U / val;
2031 if (reg >= 128 * 255) {
2032
2033
2034
2035
2036 data->fan_min[nr] = 254;
2037 new_div = 7;
2038 dev_warn(dev,
2039 "fan%u low limit %lu below minimum %u, set to minimum\n",
2040 nr + 1, val, data->fan_from_reg_min(254, 7));
2041 } else if (!reg) {
2042
2043
2044
2045
2046 data->fan_min[nr] = 1;
2047 new_div = 0;
2048 dev_warn(dev,
2049 "fan%u low limit %lu above maximum %u, set to maximum\n",
2050 nr + 1, val, data->fan_from_reg_min(1, 0));
2051 } else {
2052
2053
2054
2055
2056
2057 new_div = 0;
2058 while (reg > 192 && new_div < 7) {
2059 reg >>= 1;
2060 new_div++;
2061 }
2062 data->fan_min[nr] = reg;
2063 }
2064
2065write_div:
2066
2067
2068
2069
2070 if (new_div != data->fan_div[nr]) {
2071 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
2072 nr + 1, div_from_reg(data->fan_div[nr]),
2073 div_from_reg(new_div));
2074 data->fan_div[nr] = new_div;
2075 nct6775_write_fan_div_common(data, nr);
2076
2077 data->last_updated = jiffies;
2078 }
2079
2080write_min:
2081 nct6775_write_value(data, data->REG_FAN_MIN[nr], data->fan_min[nr]);
2082 mutex_unlock(&data->update_lock);
2083
2084 return count;
2085}
2086
2087static ssize_t
2088show_fan_pulses(struct device *dev, struct device_attribute *attr, char *buf)
2089{
2090 struct nct6775_data *data = nct6775_update_device(dev);
2091 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2092 int p = data->fan_pulses[sattr->index];
2093
2094 return sprintf(buf, "%d\n", p ? : 4);
2095}
2096
2097static ssize_t
2098store_fan_pulses(struct device *dev, struct device_attribute *attr,
2099 const char *buf, size_t count)
2100{
2101 struct nct6775_data *data = dev_get_drvdata(dev);
2102 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2103 int nr = sattr->index;
2104 unsigned long val;
2105 int err;
2106 u8 reg;
2107
2108 err = kstrtoul(buf, 10, &val);
2109 if (err < 0)
2110 return err;
2111
2112 if (val > 4)
2113 return -EINVAL;
2114
2115 mutex_lock(&data->update_lock);
2116 data->fan_pulses[nr] = val & 3;
2117 reg = nct6775_read_value(data, data->REG_FAN_PULSES[nr]);
2118 reg &= ~(0x03 << data->FAN_PULSE_SHIFT[nr]);
2119 reg |= (val & 3) << data->FAN_PULSE_SHIFT[nr];
2120 nct6775_write_value(data, data->REG_FAN_PULSES[nr], reg);
2121 mutex_unlock(&data->update_lock);
2122
2123 return count;
2124}
2125
2126static umode_t nct6775_fan_is_visible(struct kobject *kobj,
2127 struct attribute *attr, int index)
2128{
2129 struct device *dev = container_of(kobj, struct device, kobj);
2130 struct nct6775_data *data = dev_get_drvdata(dev);
2131 int fan = index / 6;
2132 int nr = index % 6;
2133
2134 if (!(data->has_fan & BIT(fan)))
2135 return 0;
2136
2137 if (nr == 1 && data->ALARM_BITS[FAN_ALARM_BASE + fan] == -1)
2138 return 0;
2139 if (nr == 2 && data->BEEP_BITS[FAN_ALARM_BASE + fan] == -1)
2140 return 0;
2141 if (nr == 3 && !data->REG_FAN_PULSES[fan])
2142 return 0;
2143 if (nr == 4 && !(data->has_fan_min & BIT(fan)))
2144 return 0;
2145 if (nr == 5 && data->kind != nct6775)
2146 return 0;
2147
2148 return attr->mode;
2149}
2150
2151SENSOR_TEMPLATE(fan_input, "fan%d_input", S_IRUGO, show_fan, NULL, 0);
2152SENSOR_TEMPLATE(fan_alarm, "fan%d_alarm", S_IRUGO, show_alarm, NULL,
2153 FAN_ALARM_BASE);
2154SENSOR_TEMPLATE(fan_beep, "fan%d_beep", S_IWUSR | S_IRUGO, show_beep,
2155 store_beep, FAN_ALARM_BASE);
2156SENSOR_TEMPLATE(fan_pulses, "fan%d_pulses", S_IWUSR | S_IRUGO, show_fan_pulses,
2157 store_fan_pulses, 0);
2158SENSOR_TEMPLATE(fan_min, "fan%d_min", S_IWUSR | S_IRUGO, show_fan_min,
2159 store_fan_min, 0);
2160SENSOR_TEMPLATE(fan_div, "fan%d_div", S_IRUGO, show_fan_div, NULL, 0);
2161
2162
2163
2164
2165
2166
2167static struct sensor_device_template *nct6775_attributes_fan_template[] = {
2168 &sensor_dev_template_fan_input,
2169 &sensor_dev_template_fan_alarm,
2170 &sensor_dev_template_fan_beep,
2171 &sensor_dev_template_fan_pulses,
2172 &sensor_dev_template_fan_min,
2173 &sensor_dev_template_fan_div,
2174 NULL
2175};
2176
2177static const struct sensor_template_group nct6775_fan_template_group = {
2178 .templates = nct6775_attributes_fan_template,
2179 .is_visible = nct6775_fan_is_visible,
2180 .base = 1,
2181};
2182
2183static ssize_t
2184show_temp_label(struct device *dev, struct device_attribute *attr, char *buf)
2185{
2186 struct nct6775_data *data = nct6775_update_device(dev);
2187 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2188 int nr = sattr->index;
2189
2190 return sprintf(buf, "%s\n", data->temp_label[data->temp_src[nr]]);
2191}
2192
2193static ssize_t
2194show_temp(struct device *dev, struct device_attribute *attr, char *buf)
2195{
2196 struct nct6775_data *data = nct6775_update_device(dev);
2197 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2198 int nr = sattr->nr;
2199 int index = sattr->index;
2200
2201 return sprintf(buf, "%d\n", LM75_TEMP_FROM_REG(data->temp[index][nr]));
2202}
2203
2204static ssize_t
2205store_temp(struct device *dev, struct device_attribute *attr, const char *buf,
2206 size_t count)
2207{
2208 struct nct6775_data *data = dev_get_drvdata(dev);
2209 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2210 int nr = sattr->nr;
2211 int index = sattr->index;
2212 int err;
2213 long val;
2214
2215 err = kstrtol(buf, 10, &val);
2216 if (err < 0)
2217 return err;
2218
2219 mutex_lock(&data->update_lock);
2220 data->temp[index][nr] = LM75_TEMP_TO_REG(val);
2221 nct6775_write_temp(data, data->reg_temp[index][nr],
2222 data->temp[index][nr]);
2223 mutex_unlock(&data->update_lock);
2224 return count;
2225}
2226
2227static ssize_t
2228show_temp_offset(struct device *dev, struct device_attribute *attr, char *buf)
2229{
2230 struct nct6775_data *data = nct6775_update_device(dev);
2231 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2232
2233 return sprintf(buf, "%d\n", data->temp_offset[sattr->index] * 1000);
2234}
2235
2236static ssize_t
2237store_temp_offset(struct device *dev, struct device_attribute *attr,
2238 const char *buf, size_t count)
2239{
2240 struct nct6775_data *data = dev_get_drvdata(dev);
2241 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2242 int nr = sattr->index;
2243 long val;
2244 int err;
2245
2246 err = kstrtol(buf, 10, &val);
2247 if (err < 0)
2248 return err;
2249
2250 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127);
2251
2252 mutex_lock(&data->update_lock);
2253 data->temp_offset[nr] = val;
2254 nct6775_write_value(data, data->REG_TEMP_OFFSET[nr], val);
2255 mutex_unlock(&data->update_lock);
2256
2257 return count;
2258}
2259
2260static ssize_t
2261show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
2262{
2263 struct nct6775_data *data = nct6775_update_device(dev);
2264 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2265 int nr = sattr->index;
2266
2267 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
2268}
2269
2270static ssize_t
2271store_temp_type(struct device *dev, struct device_attribute *attr,
2272 const char *buf, size_t count)
2273{
2274 struct nct6775_data *data = nct6775_update_device(dev);
2275 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2276 int nr = sattr->index;
2277 unsigned long val;
2278 int err;
2279 u8 vbat, diode, vbit, dbit;
2280
2281 err = kstrtoul(buf, 10, &val);
2282 if (err < 0)
2283 return err;
2284
2285 if (val != 1 && val != 3 && val != 4)
2286 return -EINVAL;
2287
2288 mutex_lock(&data->update_lock);
2289
2290 data->temp_type[nr] = val;
2291 vbit = 0x02 << nr;
2292 dbit = data->DIODE_MASK << nr;
2293 vbat = nct6775_read_value(data, data->REG_VBAT) & ~vbit;
2294 diode = nct6775_read_value(data, data->REG_DIODE) & ~dbit;
2295 switch (val) {
2296 case 1:
2297 vbat |= vbit;
2298 diode |= dbit;
2299 break;
2300 case 3:
2301 vbat |= dbit;
2302 break;
2303 case 4:
2304 break;
2305 }
2306 nct6775_write_value(data, data->REG_VBAT, vbat);
2307 nct6775_write_value(data, data->REG_DIODE, diode);
2308
2309 mutex_unlock(&data->update_lock);
2310 return count;
2311}
2312
2313static umode_t nct6775_temp_is_visible(struct kobject *kobj,
2314 struct attribute *attr, int index)
2315{
2316 struct device *dev = container_of(kobj, struct device, kobj);
2317 struct nct6775_data *data = dev_get_drvdata(dev);
2318 int temp = index / 10;
2319 int nr = index % 10;
2320
2321 if (!(data->have_temp & BIT(temp)))
2322 return 0;
2323
2324 if (nr == 1 && !data->temp_label)
2325 return 0;
2326
2327 if (nr == 2 && find_temp_source(data, temp, data->num_temp_alarms) < 0)
2328 return 0;
2329
2330 if (nr == 3 && find_temp_source(data, temp, data->num_temp_beeps) < 0)
2331 return 0;
2332
2333 if (nr == 4 && !data->reg_temp[1][temp])
2334 return 0;
2335
2336 if (nr == 5 && !data->reg_temp[2][temp])
2337 return 0;
2338
2339 if (nr == 6 && !data->reg_temp[3][temp])
2340 return 0;
2341
2342 if (nr == 7 && !data->reg_temp[4][temp])
2343 return 0;
2344
2345
2346 if (nr > 7 && !(data->have_temp_fixed & BIT(temp)))
2347 return 0;
2348
2349 return attr->mode;
2350}
2351
2352SENSOR_TEMPLATE_2(temp_input, "temp%d_input", S_IRUGO, show_temp, NULL, 0, 0);
2353SENSOR_TEMPLATE(temp_label, "temp%d_label", S_IRUGO, show_temp_label, NULL, 0);
2354SENSOR_TEMPLATE_2(temp_max, "temp%d_max", S_IRUGO | S_IWUSR, show_temp,
2355 store_temp, 0, 1);
2356SENSOR_TEMPLATE_2(temp_max_hyst, "temp%d_max_hyst", S_IRUGO | S_IWUSR,
2357 show_temp, store_temp, 0, 2);
2358SENSOR_TEMPLATE_2(temp_crit, "temp%d_crit", S_IRUGO | S_IWUSR, show_temp,
2359 store_temp, 0, 3);
2360SENSOR_TEMPLATE_2(temp_lcrit, "temp%d_lcrit", S_IRUGO | S_IWUSR, show_temp,
2361 store_temp, 0, 4);
2362SENSOR_TEMPLATE(temp_offset, "temp%d_offset", S_IRUGO | S_IWUSR,
2363 show_temp_offset, store_temp_offset, 0);
2364SENSOR_TEMPLATE(temp_type, "temp%d_type", S_IRUGO | S_IWUSR, show_temp_type,
2365 store_temp_type, 0);
2366SENSOR_TEMPLATE(temp_alarm, "temp%d_alarm", S_IRUGO, show_temp_alarm, NULL, 0);
2367SENSOR_TEMPLATE(temp_beep, "temp%d_beep", S_IRUGO | S_IWUSR, show_temp_beep,
2368 store_temp_beep, 0);
2369
2370
2371
2372
2373
2374
2375static struct sensor_device_template *nct6775_attributes_temp_template[] = {
2376 &sensor_dev_template_temp_input,
2377 &sensor_dev_template_temp_label,
2378 &sensor_dev_template_temp_alarm,
2379 &sensor_dev_template_temp_beep,
2380 &sensor_dev_template_temp_max,
2381 &sensor_dev_template_temp_max_hyst,
2382 &sensor_dev_template_temp_crit,
2383 &sensor_dev_template_temp_lcrit,
2384 &sensor_dev_template_temp_offset,
2385 &sensor_dev_template_temp_type,
2386 NULL
2387};
2388
2389static const struct sensor_template_group nct6775_temp_template_group = {
2390 .templates = nct6775_attributes_temp_template,
2391 .is_visible = nct6775_temp_is_visible,
2392 .base = 1,
2393};
2394
2395static ssize_t
2396show_pwm_mode(struct device *dev, struct device_attribute *attr, char *buf)
2397{
2398 struct nct6775_data *data = nct6775_update_device(dev);
2399 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2400
2401 return sprintf(buf, "%d\n", data->pwm_mode[sattr->index]);
2402}
2403
2404static ssize_t
2405store_pwm_mode(struct device *dev, struct device_attribute *attr,
2406 const char *buf, size_t count)
2407{
2408 struct nct6775_data *data = dev_get_drvdata(dev);
2409 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2410 int nr = sattr->index;
2411 unsigned long val;
2412 int err;
2413 u8 reg;
2414
2415 err = kstrtoul(buf, 10, &val);
2416 if (err < 0)
2417 return err;
2418
2419 if (val > 1)
2420 return -EINVAL;
2421
2422
2423 if (data->REG_PWM_MODE[nr] == 0) {
2424 if (!val)
2425 return -EINVAL;
2426 return count;
2427 }
2428
2429 mutex_lock(&data->update_lock);
2430 data->pwm_mode[nr] = val;
2431 reg = nct6775_read_value(data, data->REG_PWM_MODE[nr]);
2432 reg &= ~data->PWM_MODE_MASK[nr];
2433 if (!val)
2434 reg |= data->PWM_MODE_MASK[nr];
2435 nct6775_write_value(data, data->REG_PWM_MODE[nr], reg);
2436 mutex_unlock(&data->update_lock);
2437 return count;
2438}
2439
2440static ssize_t
2441show_pwm(struct device *dev, struct device_attribute *attr, char *buf)
2442{
2443 struct nct6775_data *data = nct6775_update_device(dev);
2444 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2445 int nr = sattr->nr;
2446 int index = sattr->index;
2447 int pwm;
2448
2449
2450
2451
2452
2453 if (index == 0 && data->pwm_enable[nr] > manual)
2454 pwm = nct6775_read_value(data, data->REG_PWM_READ[nr]);
2455 else
2456 pwm = data->pwm[index][nr];
2457
2458 return sprintf(buf, "%d\n", pwm);
2459}
2460
2461static ssize_t
2462store_pwm(struct device *dev, struct device_attribute *attr, const char *buf,
2463 size_t count)
2464{
2465 struct nct6775_data *data = dev_get_drvdata(dev);
2466 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2467 int nr = sattr->nr;
2468 int index = sattr->index;
2469 unsigned long val;
2470 int minval[7] = { 0, 1, 1, data->pwm[2][nr], 0, 0, 0 };
2471 int maxval[7]
2472 = { 255, 255, data->pwm[3][nr] ? : 255, 255, 255, 255, 255 };
2473 int err;
2474 u8 reg;
2475
2476 err = kstrtoul(buf, 10, &val);
2477 if (err < 0)
2478 return err;
2479 val = clamp_val(val, minval[index], maxval[index]);
2480
2481 mutex_lock(&data->update_lock);
2482 data->pwm[index][nr] = val;
2483 nct6775_write_value(data, data->REG_PWM[index][nr], val);
2484 if (index == 2) {
2485 reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]);
2486 reg &= 0x7f;
2487 if (val)
2488 reg |= 0x80;
2489 nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg);
2490 }
2491 mutex_unlock(&data->update_lock);
2492 return count;
2493}
2494
2495
2496static int check_trip_points(struct nct6775_data *data, int nr)
2497{
2498 int i;
2499
2500 for (i = 0; i < data->auto_pwm_num - 1; i++) {
2501 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
2502 return -EINVAL;
2503 }
2504 for (i = 0; i < data->auto_pwm_num - 1; i++) {
2505 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
2506 return -EINVAL;
2507 }
2508
2509 if (data->auto_pwm[nr][data->auto_pwm_num]) {
2510 if (data->auto_temp[nr][data->auto_pwm_num - 1] >
2511 data->auto_temp[nr][data->auto_pwm_num] ||
2512 data->auto_pwm[nr][data->auto_pwm_num - 1] >
2513 data->auto_pwm[nr][data->auto_pwm_num])
2514 return -EINVAL;
2515 }
2516 return 0;
2517}
2518
2519static void pwm_update_registers(struct nct6775_data *data, int nr)
2520{
2521 u8 reg;
2522
2523 switch (data->pwm_enable[nr]) {
2524 case off:
2525 case manual:
2526 break;
2527 case speed_cruise:
2528 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2529 reg = (reg & ~data->tolerance_mask) |
2530 (data->target_speed_tolerance[nr] & data->tolerance_mask);
2531 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2532 nct6775_write_value(data, data->REG_TARGET[nr],
2533 data->target_speed[nr] & 0xff);
2534 if (data->REG_TOLERANCE_H) {
2535 reg = (data->target_speed[nr] >> 8) & 0x0f;
2536 reg |= (data->target_speed_tolerance[nr] & 0x38) << 1;
2537 nct6775_write_value(data,
2538 data->REG_TOLERANCE_H[nr],
2539 reg);
2540 }
2541 break;
2542 case thermal_cruise:
2543 nct6775_write_value(data, data->REG_TARGET[nr],
2544 data->target_temp[nr]);
2545
2546 default:
2547 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2548 reg = (reg & ~data->tolerance_mask) |
2549 data->temp_tolerance[0][nr];
2550 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2551 break;
2552 }
2553}
2554
2555static ssize_t
2556show_pwm_enable(struct device *dev, struct device_attribute *attr, char *buf)
2557{
2558 struct nct6775_data *data = nct6775_update_device(dev);
2559 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2560
2561 return sprintf(buf, "%d\n", data->pwm_enable[sattr->index]);
2562}
2563
2564static ssize_t
2565store_pwm_enable(struct device *dev, struct device_attribute *attr,
2566 const char *buf, size_t count)
2567{
2568 struct nct6775_data *data = dev_get_drvdata(dev);
2569 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2570 int nr = sattr->index;
2571 unsigned long val;
2572 int err;
2573 u16 reg;
2574
2575 err = kstrtoul(buf, 10, &val);
2576 if (err < 0)
2577 return err;
2578
2579 if (val > sf4)
2580 return -EINVAL;
2581
2582 if (val == sf3 && data->kind != nct6775)
2583 return -EINVAL;
2584
2585 if (val == sf4 && check_trip_points(data, nr)) {
2586 dev_err(dev, "Inconsistent trip points, not switching to SmartFan IV mode\n");
2587 dev_err(dev, "Adjust trip points and try again\n");
2588 return -EINVAL;
2589 }
2590
2591 mutex_lock(&data->update_lock);
2592 data->pwm_enable[nr] = val;
2593 if (val == off) {
2594
2595
2596
2597 data->pwm[0][nr] = 255;
2598 nct6775_write_value(data, data->REG_PWM[0][nr], 255);
2599 }
2600 pwm_update_registers(data, nr);
2601 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2602 reg &= 0x0f;
2603 reg |= pwm_enable_to_reg(val) << 4;
2604 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2605 mutex_unlock(&data->update_lock);
2606 return count;
2607}
2608
2609static ssize_t
2610show_pwm_temp_sel_common(struct nct6775_data *data, char *buf, int src)
2611{
2612 int i, sel = 0;
2613
2614 for (i = 0; i < NUM_TEMP; i++) {
2615 if (!(data->have_temp & BIT(i)))
2616 continue;
2617 if (src == data->temp_src[i]) {
2618 sel = i + 1;
2619 break;
2620 }
2621 }
2622
2623 return sprintf(buf, "%d\n", sel);
2624}
2625
2626static ssize_t
2627show_pwm_temp_sel(struct device *dev, struct device_attribute *attr, char *buf)
2628{
2629 struct nct6775_data *data = nct6775_update_device(dev);
2630 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2631 int index = sattr->index;
2632
2633 return show_pwm_temp_sel_common(data, buf, data->pwm_temp_sel[index]);
2634}
2635
2636static ssize_t
2637store_pwm_temp_sel(struct device *dev, struct device_attribute *attr,
2638 const char *buf, size_t count)
2639{
2640 struct nct6775_data *data = nct6775_update_device(dev);
2641 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2642 int nr = sattr->index;
2643 unsigned long val;
2644 int err, reg, src;
2645
2646 err = kstrtoul(buf, 10, &val);
2647 if (err < 0)
2648 return err;
2649 if (val == 0 || val > NUM_TEMP)
2650 return -EINVAL;
2651 if (!(data->have_temp & BIT(val - 1)) || !data->temp_src[val - 1])
2652 return -EINVAL;
2653
2654 mutex_lock(&data->update_lock);
2655 src = data->temp_src[val - 1];
2656 data->pwm_temp_sel[nr] = src;
2657 reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]);
2658 reg &= 0xe0;
2659 reg |= src;
2660 nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg);
2661 mutex_unlock(&data->update_lock);
2662
2663 return count;
2664}
2665
2666static ssize_t
2667show_pwm_weight_temp_sel(struct device *dev, struct device_attribute *attr,
2668 char *buf)
2669{
2670 struct nct6775_data *data = nct6775_update_device(dev);
2671 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2672 int index = sattr->index;
2673
2674 return show_pwm_temp_sel_common(data, buf,
2675 data->pwm_weight_temp_sel[index]);
2676}
2677
2678static ssize_t
2679store_pwm_weight_temp_sel(struct device *dev, struct device_attribute *attr,
2680 const char *buf, size_t count)
2681{
2682 struct nct6775_data *data = nct6775_update_device(dev);
2683 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2684 int nr = sattr->index;
2685 unsigned long val;
2686 int err, reg, src;
2687
2688 err = kstrtoul(buf, 10, &val);
2689 if (err < 0)
2690 return err;
2691 if (val > NUM_TEMP)
2692 return -EINVAL;
2693 val = array_index_nospec(val, NUM_TEMP + 1);
2694 if (val && (!(data->have_temp & BIT(val - 1)) ||
2695 !data->temp_src[val - 1]))
2696 return -EINVAL;
2697
2698 mutex_lock(&data->update_lock);
2699 if (val) {
2700 src = data->temp_src[val - 1];
2701 data->pwm_weight_temp_sel[nr] = src;
2702 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]);
2703 reg &= 0xe0;
2704 reg |= (src | 0x80);
2705 nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg);
2706 } else {
2707 data->pwm_weight_temp_sel[nr] = 0;
2708 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]);
2709 reg &= 0x7f;
2710 nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg);
2711 }
2712 mutex_unlock(&data->update_lock);
2713
2714 return count;
2715}
2716
2717static ssize_t
2718show_target_temp(struct device *dev, struct device_attribute *attr, char *buf)
2719{
2720 struct nct6775_data *data = nct6775_update_device(dev);
2721 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2722
2723 return sprintf(buf, "%d\n", data->target_temp[sattr->index] * 1000);
2724}
2725
2726static ssize_t
2727store_target_temp(struct device *dev, struct device_attribute *attr,
2728 const char *buf, size_t count)
2729{
2730 struct nct6775_data *data = dev_get_drvdata(dev);
2731 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2732 int nr = sattr->index;
2733 unsigned long val;
2734 int err;
2735
2736 err = kstrtoul(buf, 10, &val);
2737 if (err < 0)
2738 return err;
2739
2740 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0,
2741 data->target_temp_mask);
2742
2743 mutex_lock(&data->update_lock);
2744 data->target_temp[nr] = val;
2745 pwm_update_registers(data, nr);
2746 mutex_unlock(&data->update_lock);
2747 return count;
2748}
2749
2750static ssize_t
2751show_target_speed(struct device *dev, struct device_attribute *attr, char *buf)
2752{
2753 struct nct6775_data *data = nct6775_update_device(dev);
2754 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2755 int nr = sattr->index;
2756
2757 return sprintf(buf, "%d\n",
2758 fan_from_reg16(data->target_speed[nr],
2759 data->fan_div[nr]));
2760}
2761
2762static ssize_t
2763store_target_speed(struct device *dev, struct device_attribute *attr,
2764 const char *buf, size_t count)
2765{
2766 struct nct6775_data *data = dev_get_drvdata(dev);
2767 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2768 int nr = sattr->index;
2769 unsigned long val;
2770 int err;
2771 u16 speed;
2772
2773 err = kstrtoul(buf, 10, &val);
2774 if (err < 0)
2775 return err;
2776
2777 val = clamp_val(val, 0, 1350000U);
2778 speed = fan_to_reg(val, data->fan_div[nr]);
2779
2780 mutex_lock(&data->update_lock);
2781 data->target_speed[nr] = speed;
2782 pwm_update_registers(data, nr);
2783 mutex_unlock(&data->update_lock);
2784 return count;
2785}
2786
2787static ssize_t
2788show_temp_tolerance(struct device *dev, struct device_attribute *attr,
2789 char *buf)
2790{
2791 struct nct6775_data *data = nct6775_update_device(dev);
2792 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2793 int nr = sattr->nr;
2794 int index = sattr->index;
2795
2796 return sprintf(buf, "%d\n", data->temp_tolerance[index][nr] * 1000);
2797}
2798
2799static ssize_t
2800store_temp_tolerance(struct device *dev, struct device_attribute *attr,
2801 const char *buf, size_t count)
2802{
2803 struct nct6775_data *data = dev_get_drvdata(dev);
2804 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2805 int nr = sattr->nr;
2806 int index = sattr->index;
2807 unsigned long val;
2808 int err;
2809
2810 err = kstrtoul(buf, 10, &val);
2811 if (err < 0)
2812 return err;
2813
2814
2815 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, data->tolerance_mask);
2816
2817 mutex_lock(&data->update_lock);
2818 data->temp_tolerance[index][nr] = val;
2819 if (index)
2820 pwm_update_registers(data, nr);
2821 else
2822 nct6775_write_value(data,
2823 data->REG_CRITICAL_TEMP_TOLERANCE[nr],
2824 val);
2825 mutex_unlock(&data->update_lock);
2826 return count;
2827}
2828
2829
2830
2831
2832
2833
2834static ssize_t
2835show_speed_tolerance(struct device *dev, struct device_attribute *attr,
2836 char *buf)
2837{
2838 struct nct6775_data *data = nct6775_update_device(dev);
2839 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2840 int nr = sattr->index;
2841 int low = data->target_speed[nr] - data->target_speed_tolerance[nr];
2842 int high = data->target_speed[nr] + data->target_speed_tolerance[nr];
2843 int tolerance;
2844
2845 if (low <= 0)
2846 low = 1;
2847 if (high > 0xffff)
2848 high = 0xffff;
2849 if (high < low)
2850 high = low;
2851
2852 tolerance = (fan_from_reg16(low, data->fan_div[nr])
2853 - fan_from_reg16(high, data->fan_div[nr])) / 2;
2854
2855 return sprintf(buf, "%d\n", tolerance);
2856}
2857
2858static ssize_t
2859store_speed_tolerance(struct device *dev, struct device_attribute *attr,
2860 const char *buf, size_t count)
2861{
2862 struct nct6775_data *data = dev_get_drvdata(dev);
2863 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2864 int nr = sattr->index;
2865 unsigned long val;
2866 int err;
2867 int low, high;
2868
2869 err = kstrtoul(buf, 10, &val);
2870 if (err < 0)
2871 return err;
2872
2873 high = fan_from_reg16(data->target_speed[nr],
2874 data->fan_div[nr]) + val;
2875 low = fan_from_reg16(data->target_speed[nr],
2876 data->fan_div[nr]) - val;
2877 if (low <= 0)
2878 low = 1;
2879 if (high < low)
2880 high = low;
2881
2882 val = (fan_to_reg(low, data->fan_div[nr]) -
2883 fan_to_reg(high, data->fan_div[nr])) / 2;
2884
2885
2886 val = clamp_val(val, 0, data->speed_tolerance_limit);
2887
2888 mutex_lock(&data->update_lock);
2889 data->target_speed_tolerance[nr] = val;
2890 pwm_update_registers(data, nr);
2891 mutex_unlock(&data->update_lock);
2892 return count;
2893}
2894
2895SENSOR_TEMPLATE_2(pwm, "pwm%d", S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 0);
2896SENSOR_TEMPLATE(pwm_mode, "pwm%d_mode", S_IWUSR | S_IRUGO, show_pwm_mode,
2897 store_pwm_mode, 0);
2898SENSOR_TEMPLATE(pwm_enable, "pwm%d_enable", S_IWUSR | S_IRUGO, show_pwm_enable,
2899 store_pwm_enable, 0);
2900SENSOR_TEMPLATE(pwm_temp_sel, "pwm%d_temp_sel", S_IWUSR | S_IRUGO,
2901 show_pwm_temp_sel, store_pwm_temp_sel, 0);
2902SENSOR_TEMPLATE(pwm_target_temp, "pwm%d_target_temp", S_IWUSR | S_IRUGO,
2903 show_target_temp, store_target_temp, 0);
2904SENSOR_TEMPLATE(fan_target, "fan%d_target", S_IWUSR | S_IRUGO,
2905 show_target_speed, store_target_speed, 0);
2906SENSOR_TEMPLATE(fan_tolerance, "fan%d_tolerance", S_IWUSR | S_IRUGO,
2907 show_speed_tolerance, store_speed_tolerance, 0);
2908
2909
2910
2911static ssize_t
2912show_weight_temp(struct device *dev, struct device_attribute *attr, char *buf)
2913{
2914 struct nct6775_data *data = nct6775_update_device(dev);
2915 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2916 int nr = sattr->nr;
2917 int index = sattr->index;
2918
2919 return sprintf(buf, "%d\n", data->weight_temp[index][nr] * 1000);
2920}
2921
2922static ssize_t
2923store_weight_temp(struct device *dev, struct device_attribute *attr,
2924 const char *buf, size_t count)
2925{
2926 struct nct6775_data *data = dev_get_drvdata(dev);
2927 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2928 int nr = sattr->nr;
2929 int index = sattr->index;
2930 unsigned long val;
2931 int err;
2932
2933 err = kstrtoul(buf, 10, &val);
2934 if (err < 0)
2935 return err;
2936
2937 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 255);
2938
2939 mutex_lock(&data->update_lock);
2940 data->weight_temp[index][nr] = val;
2941 nct6775_write_value(data, data->REG_WEIGHT_TEMP[index][nr], val);
2942 mutex_unlock(&data->update_lock);
2943 return count;
2944}
2945
2946SENSOR_TEMPLATE(pwm_weight_temp_sel, "pwm%d_weight_temp_sel", S_IWUSR | S_IRUGO,
2947 show_pwm_weight_temp_sel, store_pwm_weight_temp_sel, 0);
2948SENSOR_TEMPLATE_2(pwm_weight_temp_step, "pwm%d_weight_temp_step",
2949 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 0);
2950SENSOR_TEMPLATE_2(pwm_weight_temp_step_tol, "pwm%d_weight_temp_step_tol",
2951 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 1);
2952SENSOR_TEMPLATE_2(pwm_weight_temp_step_base, "pwm%d_weight_temp_step_base",
2953 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 2);
2954SENSOR_TEMPLATE_2(pwm_weight_duty_step, "pwm%d_weight_duty_step",
2955 S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 5);
2956SENSOR_TEMPLATE_2(pwm_weight_duty_base, "pwm%d_weight_duty_base",
2957 S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 6);
2958
2959static ssize_t
2960show_fan_time(struct device *dev, struct device_attribute *attr, char *buf)
2961{
2962 struct nct6775_data *data = nct6775_update_device(dev);
2963 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2964 int nr = sattr->nr;
2965 int index = sattr->index;
2966
2967 return sprintf(buf, "%d\n",
2968 step_time_from_reg(data->fan_time[index][nr],
2969 data->pwm_mode[nr]));
2970}
2971
2972static ssize_t
2973store_fan_time(struct device *dev, struct device_attribute *attr,
2974 const char *buf, size_t count)
2975{
2976 struct nct6775_data *data = dev_get_drvdata(dev);
2977 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2978 int nr = sattr->nr;
2979 int index = sattr->index;
2980 unsigned long val;
2981 int err;
2982
2983 err = kstrtoul(buf, 10, &val);
2984 if (err < 0)
2985 return err;
2986
2987 val = step_time_to_reg(val, data->pwm_mode[nr]);
2988 mutex_lock(&data->update_lock);
2989 data->fan_time[index][nr] = val;
2990 nct6775_write_value(data, data->REG_FAN_TIME[index][nr], val);
2991 mutex_unlock(&data->update_lock);
2992 return count;
2993}
2994
2995static ssize_t
2996show_auto_pwm(struct device *dev, struct device_attribute *attr, char *buf)
2997{
2998 struct nct6775_data *data = nct6775_update_device(dev);
2999 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3000
3001 return sprintf(buf, "%d\n", data->auto_pwm[sattr->nr][sattr->index]);
3002}
3003
3004static ssize_t
3005store_auto_pwm(struct device *dev, struct device_attribute *attr,
3006 const char *buf, size_t count)
3007{
3008 struct nct6775_data *data = dev_get_drvdata(dev);
3009 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3010 int nr = sattr->nr;
3011 int point = sattr->index;
3012 unsigned long val;
3013 int err;
3014 u8 reg;
3015
3016 err = kstrtoul(buf, 10, &val);
3017 if (err < 0)
3018 return err;
3019 if (val > 255)
3020 return -EINVAL;
3021
3022 if (point == data->auto_pwm_num) {
3023 if (data->kind != nct6775 && !val)
3024 return -EINVAL;
3025 if (data->kind != nct6779 && val)
3026 val = 0xff;
3027 }
3028
3029 mutex_lock(&data->update_lock);
3030 data->auto_pwm[nr][point] = val;
3031 if (point < data->auto_pwm_num) {
3032 nct6775_write_value(data,
3033 NCT6775_AUTO_PWM(data, nr, point),
3034 data->auto_pwm[nr][point]);
3035 } else {
3036 switch (data->kind) {
3037 case nct6775:
3038
3039 reg = nct6775_read_value(data,
3040 NCT6775_REG_CRITICAL_ENAB[nr]);
3041 if (val)
3042 reg |= 0x02;
3043 else
3044 reg &= ~0x02;
3045 nct6775_write_value(data, NCT6775_REG_CRITICAL_ENAB[nr],
3046 reg);
3047 break;
3048 case nct6776:
3049 break;
3050 case nct6106:
3051 case nct6779:
3052 case nct6791:
3053 case nct6792:
3054 case nct6793:
3055 case nct6795:
3056 case nct6796:
3057 nct6775_write_value(data, data->REG_CRITICAL_PWM[nr],
3058 val);
3059 reg = nct6775_read_value(data,
3060 data->REG_CRITICAL_PWM_ENABLE[nr]);
3061 if (val == 255)
3062 reg &= ~data->CRITICAL_PWM_ENABLE_MASK;
3063 else
3064 reg |= data->CRITICAL_PWM_ENABLE_MASK;
3065 nct6775_write_value(data,
3066 data->REG_CRITICAL_PWM_ENABLE[nr],
3067 reg);
3068 break;
3069 }
3070 }
3071 mutex_unlock(&data->update_lock);
3072 return count;
3073}
3074
3075static ssize_t
3076show_auto_temp(struct device *dev, struct device_attribute *attr, char *buf)
3077{
3078 struct nct6775_data *data = nct6775_update_device(dev);
3079 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3080 int nr = sattr->nr;
3081 int point = sattr->index;
3082
3083
3084
3085
3086
3087 return sprintf(buf, "%d\n", data->auto_temp[nr][point] * 1000);
3088}
3089
3090static ssize_t
3091store_auto_temp(struct device *dev, struct device_attribute *attr,
3092 const char *buf, size_t count)
3093{
3094 struct nct6775_data *data = dev_get_drvdata(dev);
3095 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3096 int nr = sattr->nr;
3097 int point = sattr->index;
3098 unsigned long val;
3099 int err;
3100
3101 err = kstrtoul(buf, 10, &val);
3102 if (err)
3103 return err;
3104 if (val > 255000)
3105 return -EINVAL;
3106
3107 mutex_lock(&data->update_lock);
3108 data->auto_temp[nr][point] = DIV_ROUND_CLOSEST(val, 1000);
3109 if (point < data->auto_pwm_num) {
3110 nct6775_write_value(data,
3111 NCT6775_AUTO_TEMP(data, nr, point),
3112 data->auto_temp[nr][point]);
3113 } else {
3114 nct6775_write_value(data, data->REG_CRITICAL_TEMP[nr],
3115 data->auto_temp[nr][point]);
3116 }
3117 mutex_unlock(&data->update_lock);
3118 return count;
3119}
3120
3121static umode_t nct6775_pwm_is_visible(struct kobject *kobj,
3122 struct attribute *attr, int index)
3123{
3124 struct device *dev = container_of(kobj, struct device, kobj);
3125 struct nct6775_data *data = dev_get_drvdata(dev);
3126 int pwm = index / 36;
3127 int nr = index % 36;
3128
3129 if (!(data->has_pwm & BIT(pwm)))
3130 return 0;
3131
3132 if ((nr >= 14 && nr <= 18) || nr == 21)
3133 if (!data->REG_WEIGHT_TEMP_SEL[pwm])
3134 return 0;
3135 if (nr == 19 && data->REG_PWM[3] == NULL)
3136 return 0;
3137 if (nr == 20 && data->REG_PWM[4] == NULL)
3138 return 0;
3139 if (nr == 21 && data->REG_PWM[6] == NULL)
3140 return 0;
3141
3142 if (nr >= 22 && nr <= 35) {
3143 int api = (nr - 22) / 2;
3144
3145 if (api > data->auto_pwm_num)
3146 return 0;
3147 }
3148 return attr->mode;
3149}
3150
3151SENSOR_TEMPLATE_2(pwm_stop_time, "pwm%d_stop_time", S_IWUSR | S_IRUGO,
3152 show_fan_time, store_fan_time, 0, 0);
3153SENSOR_TEMPLATE_2(pwm_step_up_time, "pwm%d_step_up_time", S_IWUSR | S_IRUGO,
3154 show_fan_time, store_fan_time, 0, 1);
3155SENSOR_TEMPLATE_2(pwm_step_down_time, "pwm%d_step_down_time", S_IWUSR | S_IRUGO,
3156 show_fan_time, store_fan_time, 0, 2);
3157SENSOR_TEMPLATE_2(pwm_start, "pwm%d_start", S_IWUSR | S_IRUGO, show_pwm,
3158 store_pwm, 0, 1);
3159SENSOR_TEMPLATE_2(pwm_floor, "pwm%d_floor", S_IWUSR | S_IRUGO, show_pwm,
3160 store_pwm, 0, 2);
3161SENSOR_TEMPLATE_2(pwm_temp_tolerance, "pwm%d_temp_tolerance", S_IWUSR | S_IRUGO,
3162 show_temp_tolerance, store_temp_tolerance, 0, 0);
3163SENSOR_TEMPLATE_2(pwm_crit_temp_tolerance, "pwm%d_crit_temp_tolerance",
3164 S_IWUSR | S_IRUGO, show_temp_tolerance, store_temp_tolerance,
3165 0, 1);
3166
3167SENSOR_TEMPLATE_2(pwm_max, "pwm%d_max", S_IWUSR | S_IRUGO, show_pwm, store_pwm,
3168 0, 3);
3169
3170SENSOR_TEMPLATE_2(pwm_step, "pwm%d_step", S_IWUSR | S_IRUGO, show_pwm,
3171 store_pwm, 0, 4);
3172
3173SENSOR_TEMPLATE_2(pwm_auto_point1_pwm, "pwm%d_auto_point1_pwm",
3174 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 0);
3175SENSOR_TEMPLATE_2(pwm_auto_point1_temp, "pwm%d_auto_point1_temp",
3176 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 0);
3177
3178SENSOR_TEMPLATE_2(pwm_auto_point2_pwm, "pwm%d_auto_point2_pwm",
3179 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 1);
3180SENSOR_TEMPLATE_2(pwm_auto_point2_temp, "pwm%d_auto_point2_temp",
3181 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 1);
3182
3183SENSOR_TEMPLATE_2(pwm_auto_point3_pwm, "pwm%d_auto_point3_pwm",
3184 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 2);
3185SENSOR_TEMPLATE_2(pwm_auto_point3_temp, "pwm%d_auto_point3_temp",
3186 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 2);
3187
3188SENSOR_TEMPLATE_2(pwm_auto_point4_pwm, "pwm%d_auto_point4_pwm",
3189 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 3);
3190SENSOR_TEMPLATE_2(pwm_auto_point4_temp, "pwm%d_auto_point4_temp",
3191 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 3);
3192
3193SENSOR_TEMPLATE_2(pwm_auto_point5_pwm, "pwm%d_auto_point5_pwm",
3194 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 4);
3195SENSOR_TEMPLATE_2(pwm_auto_point5_temp, "pwm%d_auto_point5_temp",
3196 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 4);
3197
3198SENSOR_TEMPLATE_2(pwm_auto_point6_pwm, "pwm%d_auto_point6_pwm",
3199 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 5);
3200SENSOR_TEMPLATE_2(pwm_auto_point6_temp, "pwm%d_auto_point6_temp",
3201 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 5);
3202
3203SENSOR_TEMPLATE_2(pwm_auto_point7_pwm, "pwm%d_auto_point7_pwm",
3204 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 6);
3205SENSOR_TEMPLATE_2(pwm_auto_point7_temp, "pwm%d_auto_point7_temp",
3206 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 6);
3207
3208
3209
3210
3211
3212
3213static struct sensor_device_template *nct6775_attributes_pwm_template[] = {
3214 &sensor_dev_template_pwm,
3215 &sensor_dev_template_pwm_mode,
3216 &sensor_dev_template_pwm_enable,
3217 &sensor_dev_template_pwm_temp_sel,
3218 &sensor_dev_template_pwm_temp_tolerance,
3219 &sensor_dev_template_pwm_crit_temp_tolerance,
3220 &sensor_dev_template_pwm_target_temp,
3221 &sensor_dev_template_fan_target,
3222 &sensor_dev_template_fan_tolerance,
3223 &sensor_dev_template_pwm_stop_time,
3224 &sensor_dev_template_pwm_step_up_time,
3225 &sensor_dev_template_pwm_step_down_time,
3226 &sensor_dev_template_pwm_start,
3227 &sensor_dev_template_pwm_floor,
3228 &sensor_dev_template_pwm_weight_temp_sel,
3229 &sensor_dev_template_pwm_weight_temp_step,
3230 &sensor_dev_template_pwm_weight_temp_step_tol,
3231 &sensor_dev_template_pwm_weight_temp_step_base,
3232 &sensor_dev_template_pwm_weight_duty_step,
3233 &sensor_dev_template_pwm_max,
3234 &sensor_dev_template_pwm_step,
3235 &sensor_dev_template_pwm_weight_duty_base,
3236 &sensor_dev_template_pwm_auto_point1_pwm,
3237 &sensor_dev_template_pwm_auto_point1_temp,
3238 &sensor_dev_template_pwm_auto_point2_pwm,
3239 &sensor_dev_template_pwm_auto_point2_temp,
3240 &sensor_dev_template_pwm_auto_point3_pwm,
3241 &sensor_dev_template_pwm_auto_point3_temp,
3242 &sensor_dev_template_pwm_auto_point4_pwm,
3243 &sensor_dev_template_pwm_auto_point4_temp,
3244 &sensor_dev_template_pwm_auto_point5_pwm,
3245 &sensor_dev_template_pwm_auto_point5_temp,
3246 &sensor_dev_template_pwm_auto_point6_pwm,
3247 &sensor_dev_template_pwm_auto_point6_temp,
3248 &sensor_dev_template_pwm_auto_point7_pwm,
3249 &sensor_dev_template_pwm_auto_point7_temp,
3250
3251 NULL
3252};
3253
3254static const struct sensor_template_group nct6775_pwm_template_group = {
3255 .templates = nct6775_attributes_pwm_template,
3256 .is_visible = nct6775_pwm_is_visible,
3257 .base = 1,
3258};
3259
3260static ssize_t
3261cpu0_vid_show(struct device *dev, struct device_attribute *attr, char *buf)
3262{
3263 struct nct6775_data *data = dev_get_drvdata(dev);
3264
3265 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
3266}
3267
3268static DEVICE_ATTR_RO(cpu0_vid);
3269
3270
3271
3272static ssize_t
3273clear_caseopen(struct device *dev, struct device_attribute *attr,
3274 const char *buf, size_t count)
3275{
3276 struct nct6775_data *data = dev_get_drvdata(dev);
3277 int nr = to_sensor_dev_attr(attr)->index - INTRUSION_ALARM_BASE;
3278 unsigned long val;
3279 u8 reg;
3280 int ret;
3281
3282 if (kstrtoul(buf, 10, &val) || val != 0)
3283 return -EINVAL;
3284
3285 mutex_lock(&data->update_lock);
3286
3287
3288
3289
3290
3291
3292 ret = superio_enter(data->sioreg);
3293 if (ret) {
3294 count = ret;
3295 goto error;
3296 }
3297
3298 superio_select(data->sioreg, NCT6775_LD_ACPI);
3299 reg = superio_inb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr]);
3300 reg |= NCT6775_CR_CASEOPEN_CLR_MASK[nr];
3301 superio_outb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg);
3302 reg &= ~NCT6775_CR_CASEOPEN_CLR_MASK[nr];
3303 superio_outb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg);
3304 superio_exit(data->sioreg);
3305
3306 data->valid = false;
3307error:
3308 mutex_unlock(&data->update_lock);
3309 return count;
3310}
3311
3312static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IWUSR | S_IRUGO, show_alarm,
3313 clear_caseopen, INTRUSION_ALARM_BASE);
3314static SENSOR_DEVICE_ATTR(intrusion1_alarm, S_IWUSR | S_IRUGO, show_alarm,
3315 clear_caseopen, INTRUSION_ALARM_BASE + 1);
3316static SENSOR_DEVICE_ATTR(intrusion0_beep, S_IWUSR | S_IRUGO, show_beep,
3317 store_beep, INTRUSION_ALARM_BASE);
3318static SENSOR_DEVICE_ATTR(intrusion1_beep, S_IWUSR | S_IRUGO, show_beep,
3319 store_beep, INTRUSION_ALARM_BASE + 1);
3320static SENSOR_DEVICE_ATTR(beep_enable, S_IWUSR | S_IRUGO, show_beep,
3321 store_beep, BEEP_ENABLE_BASE);
3322
3323static umode_t nct6775_other_is_visible(struct kobject *kobj,
3324 struct attribute *attr, int index)
3325{
3326 struct device *dev = container_of(kobj, struct device, kobj);
3327 struct nct6775_data *data = dev_get_drvdata(dev);
3328
3329 if (index == 0 && !data->have_vid)
3330 return 0;
3331
3332 if (index == 1 || index == 2) {
3333 if (data->ALARM_BITS[INTRUSION_ALARM_BASE + index - 1] < 0)
3334 return 0;
3335 }
3336
3337 if (index == 3 || index == 4) {
3338 if (data->BEEP_BITS[INTRUSION_ALARM_BASE + index - 3] < 0)
3339 return 0;
3340 }
3341
3342 return attr->mode;
3343}
3344
3345
3346
3347
3348
3349
3350static struct attribute *nct6775_attributes_other[] = {
3351 &dev_attr_cpu0_vid.attr,
3352 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
3353 &sensor_dev_attr_intrusion1_alarm.dev_attr.attr,
3354 &sensor_dev_attr_intrusion0_beep.dev_attr.attr,
3355 &sensor_dev_attr_intrusion1_beep.dev_attr.attr,
3356 &sensor_dev_attr_beep_enable.dev_attr.attr,
3357
3358 NULL
3359};
3360
3361static const struct attribute_group nct6775_group_other = {
3362 .attrs = nct6775_attributes_other,
3363 .is_visible = nct6775_other_is_visible,
3364};
3365
3366static inline void nct6775_init_device(struct nct6775_data *data)
3367{
3368 int i;
3369 u8 tmp, diode;
3370
3371
3372 if (data->REG_CONFIG) {
3373 tmp = nct6775_read_value(data, data->REG_CONFIG);
3374 if (!(tmp & 0x01))
3375 nct6775_write_value(data, data->REG_CONFIG, tmp | 0x01);
3376 }
3377
3378
3379 for (i = 0; i < NUM_TEMP; i++) {
3380 if (!(data->have_temp & BIT(i)))
3381 continue;
3382 if (!data->reg_temp_config[i])
3383 continue;
3384 tmp = nct6775_read_value(data, data->reg_temp_config[i]);
3385 if (tmp & 0x01)
3386 nct6775_write_value(data, data->reg_temp_config[i],
3387 tmp & 0xfe);
3388 }
3389
3390
3391 tmp = nct6775_read_value(data, data->REG_VBAT);
3392 if (!(tmp & 0x01))
3393 nct6775_write_value(data, data->REG_VBAT, tmp | 0x01);
3394
3395 diode = nct6775_read_value(data, data->REG_DIODE);
3396
3397 for (i = 0; i < data->temp_fixed_num; i++) {
3398 if (!(data->have_temp_fixed & BIT(i)))
3399 continue;
3400 if ((tmp & (data->DIODE_MASK << i)))
3401 data->temp_type[i]
3402 = 3 - ((diode >> i) & data->DIODE_MASK);
3403 else
3404 data->temp_type[i] = 4;
3405 }
3406}
3407
3408static void
3409nct6775_check_fan_inputs(struct nct6775_data *data)
3410{
3411 bool fan3pin = false, fan4pin = false, fan4min = false;
3412 bool fan5pin = false, fan6pin = false, fan7pin = false;
3413 bool pwm3pin = false, pwm4pin = false, pwm5pin = false;
3414 bool pwm6pin = false, pwm7pin = false;
3415 int sioreg = data->sioreg;
3416 int regval;
3417
3418
3419 superio_select(sioreg, NCT6775_LD_HWM);
3420 data->sio_reg_enable = superio_inb(sioreg, SIO_REG_ENABLE);
3421
3422
3423 if (data->kind == nct6775) {
3424 regval = superio_inb(sioreg, 0x2c);
3425
3426 fan3pin = regval & BIT(6);
3427 pwm3pin = regval & BIT(7);
3428
3429
3430 fan4pin = !(superio_inb(sioreg, 0x2A) & 0x80);
3431 } else if (data->kind == nct6776) {
3432 bool gpok = superio_inb(sioreg, 0x27) & 0x80;
3433 const char *board_vendor, *board_name;
3434
3435 board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
3436 board_name = dmi_get_system_info(DMI_BOARD_NAME);
3437
3438 if (board_name && board_vendor &&
3439 !strcmp(board_vendor, "ASRock")) {
3440
3441
3442
3443
3444
3445 if (!strcmp(board_name, "Z77 Pro4-M")) {
3446 if ((data->sio_reg_enable & 0xe0) != 0xe0) {
3447 data->sio_reg_enable |= 0xe0;
3448 superio_outb(sioreg, SIO_REG_ENABLE,
3449 data->sio_reg_enable);
3450 }
3451 }
3452 }
3453
3454 if (data->sio_reg_enable & 0x80)
3455 fan3pin = gpok;
3456 else
3457 fan3pin = !(superio_inb(sioreg, 0x24) & 0x40);
3458
3459 if (data->sio_reg_enable & 0x40)
3460 fan4pin = gpok;
3461 else
3462 fan4pin = superio_inb(sioreg, 0x1C) & 0x01;
3463
3464 if (data->sio_reg_enable & 0x20)
3465 fan5pin = gpok;
3466 else
3467 fan5pin = superio_inb(sioreg, 0x1C) & 0x02;
3468
3469 fan4min = fan4pin;
3470 pwm3pin = fan3pin;
3471 } else if (data->kind == nct6106) {
3472 regval = superio_inb(sioreg, 0x24);
3473 fan3pin = !(regval & 0x80);
3474 pwm3pin = regval & 0x08;
3475 } else {
3476
3477 int regval_1b, regval_2a, regval_2f;
3478 bool dsw_en;
3479
3480 regval = superio_inb(sioreg, 0x1c);
3481
3482 fan3pin = !(regval & BIT(5));
3483 fan4pin = !(regval & BIT(6));
3484 fan5pin = !(regval & BIT(7));
3485
3486 pwm3pin = !(regval & BIT(0));
3487 pwm4pin = !(regval & BIT(1));
3488 pwm5pin = !(regval & BIT(2));
3489
3490 regval = superio_inb(sioreg, 0x2d);
3491 switch (data->kind) {
3492 case nct6791:
3493 case nct6792:
3494 fan6pin = regval & BIT(1);
3495 pwm6pin = regval & BIT(0);
3496 break;
3497 case nct6793:
3498 case nct6795:
3499 case nct6796:
3500 regval_1b = superio_inb(sioreg, 0x1b);
3501 regval_2a = superio_inb(sioreg, 0x2a);
3502 regval_2f = superio_inb(sioreg, 0x2f);
3503 dsw_en = regval_2f & BIT(3);
3504
3505 if (!pwm5pin)
3506 pwm5pin = regval & BIT(7);
3507
3508 if (!fan5pin)
3509 fan5pin = regval_1b & BIT(5);
3510
3511 superio_select(sioreg, NCT6775_LD_12);
3512 if (data->kind != nct6796) {
3513 int regval_eb = superio_inb(sioreg, 0xeb);
3514
3515 if (!dsw_en) {
3516 fan6pin = regval & BIT(1);
3517 pwm6pin = regval & BIT(0);
3518 }
3519
3520 if (!fan5pin)
3521 fan5pin = regval_eb & BIT(5);
3522 if (!pwm5pin)
3523 pwm5pin = (regval_eb & BIT(4)) &&
3524 !(regval_2a & BIT(0));
3525 if (!fan6pin)
3526 fan6pin = regval_eb & BIT(3);
3527 if (!pwm6pin)
3528 pwm6pin = regval_eb & BIT(2);
3529 }
3530
3531 if (data->kind == nct6795 || data->kind == nct6796) {
3532 int regval_ed = superio_inb(sioreg, 0xed);
3533
3534 if (!fan6pin)
3535 fan6pin = (regval_2a & BIT(4)) &&
3536 (!dsw_en ||
3537 (dsw_en && (regval_ed & BIT(4))));
3538 if (!pwm6pin)
3539 pwm6pin = (regval_2a & BIT(3)) &&
3540 (regval_ed & BIT(2));
3541 }
3542
3543 if (data->kind == nct6796) {
3544 int regval_1d = superio_inb(sioreg, 0x1d);
3545 int regval_2b = superio_inb(sioreg, 0x2b);
3546
3547 fan7pin = !(regval_2b & BIT(2));
3548 pwm7pin = !(regval_1d & (BIT(2) | BIT(3)));
3549 }
3550
3551 break;
3552 default:
3553 break;
3554 }
3555
3556 fan4min = fan4pin;
3557 }
3558
3559
3560 data->has_fan = 0x03 | (fan3pin << 2) | (fan4pin << 3) |
3561 (fan5pin << 4) | (fan6pin << 5) | (fan7pin << 6);
3562 data->has_fan_min = 0x03 | (fan3pin << 2) | (fan4min << 3) |
3563 (fan5pin << 4) | (fan6pin << 5) | (fan7pin << 6);
3564 data->has_pwm = 0x03 | (pwm3pin << 2) | (pwm4pin << 3) |
3565 (pwm5pin << 4) | (pwm6pin << 5) | (pwm7pin << 6);
3566}
3567
3568static void add_temp_sensors(struct nct6775_data *data, const u16 *regp,
3569 int *available, int *mask)
3570{
3571 int i;
3572 u8 src;
3573
3574 for (i = 0; i < data->pwm_num && *available; i++) {
3575 int index;
3576
3577 if (!regp[i])
3578 continue;
3579 src = nct6775_read_value(data, regp[i]);
3580 src &= 0x1f;
3581 if (!src || (*mask & BIT(src)))
3582 continue;
3583 if (!(data->temp_mask & BIT(src)))
3584 continue;
3585
3586 index = __ffs(*available);
3587 nct6775_write_value(data, data->REG_TEMP_SOURCE[index], src);
3588 *available &= ~BIT(index);
3589 *mask |= BIT(src);
3590 }
3591}
3592
3593static int nct6775_probe(struct platform_device *pdev)
3594{
3595 struct device *dev = &pdev->dev;
3596 struct nct6775_sio_data *sio_data = dev_get_platdata(dev);
3597 struct nct6775_data *data;
3598 struct resource *res;
3599 int i, s, err = 0;
3600 int src, mask, available;
3601 const u16 *reg_temp, *reg_temp_over, *reg_temp_hyst, *reg_temp_config;
3602 const u16 *reg_temp_mon, *reg_temp_alternate, *reg_temp_crit;
3603 const u16 *reg_temp_crit_l = NULL, *reg_temp_crit_h = NULL;
3604 int num_reg_temp, num_reg_temp_mon;
3605 u8 cr2a;
3606 struct attribute_group *group;
3607 struct device *hwmon_dev;
3608 int num_attr_groups = 0;
3609
3610 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3611 if (!devm_request_region(&pdev->dev, res->start, IOREGION_LENGTH,
3612 DRVNAME))
3613 return -EBUSY;
3614
3615 data = devm_kzalloc(&pdev->dev, sizeof(struct nct6775_data),
3616 GFP_KERNEL);
3617 if (!data)
3618 return -ENOMEM;
3619
3620 data->kind = sio_data->kind;
3621 data->sioreg = sio_data->sioreg;
3622 data->addr = res->start;
3623 mutex_init(&data->update_lock);
3624 data->name = nct6775_device_names[data->kind];
3625 data->bank = 0xff;
3626 platform_set_drvdata(pdev, data);
3627
3628 switch (data->kind) {
3629 case nct6106:
3630 data->in_num = 9;
3631 data->pwm_num = 3;
3632 data->auto_pwm_num = 4;
3633 data->temp_fixed_num = 3;
3634 data->num_temp_alarms = 6;
3635 data->num_temp_beeps = 6;
3636
3637 data->fan_from_reg = fan_from_reg13;
3638 data->fan_from_reg_min = fan_from_reg13;
3639
3640 data->temp_label = nct6776_temp_label;
3641 data->temp_mask = NCT6776_TEMP_MASK;
3642
3643 data->REG_VBAT = NCT6106_REG_VBAT;
3644 data->REG_DIODE = NCT6106_REG_DIODE;
3645 data->DIODE_MASK = NCT6106_DIODE_MASK;
3646 data->REG_VIN = NCT6106_REG_IN;
3647 data->REG_IN_MINMAX[0] = NCT6106_REG_IN_MIN;
3648 data->REG_IN_MINMAX[1] = NCT6106_REG_IN_MAX;
3649 data->REG_TARGET = NCT6106_REG_TARGET;
3650 data->REG_FAN = NCT6106_REG_FAN;
3651 data->REG_FAN_MODE = NCT6106_REG_FAN_MODE;
3652 data->REG_FAN_MIN = NCT6106_REG_FAN_MIN;
3653 data->REG_FAN_PULSES = NCT6106_REG_FAN_PULSES;
3654 data->FAN_PULSE_SHIFT = NCT6106_FAN_PULSE_SHIFT;
3655 data->REG_FAN_TIME[0] = NCT6106_REG_FAN_STOP_TIME;
3656 data->REG_FAN_TIME[1] = NCT6106_REG_FAN_STEP_UP_TIME;
3657 data->REG_FAN_TIME[2] = NCT6106_REG_FAN_STEP_DOWN_TIME;
3658 data->REG_PWM[0] = NCT6106_REG_PWM;
3659 data->REG_PWM[1] = NCT6106_REG_FAN_START_OUTPUT;
3660 data->REG_PWM[2] = NCT6106_REG_FAN_STOP_OUTPUT;
3661 data->REG_PWM[5] = NCT6106_REG_WEIGHT_DUTY_STEP;
3662 data->REG_PWM[6] = NCT6106_REG_WEIGHT_DUTY_BASE;
3663 data->REG_PWM_READ = NCT6106_REG_PWM_READ;
3664 data->REG_PWM_MODE = NCT6106_REG_PWM_MODE;
3665 data->PWM_MODE_MASK = NCT6106_PWM_MODE_MASK;
3666 data->REG_AUTO_TEMP = NCT6106_REG_AUTO_TEMP;
3667 data->REG_AUTO_PWM = NCT6106_REG_AUTO_PWM;
3668 data->REG_CRITICAL_TEMP = NCT6106_REG_CRITICAL_TEMP;
3669 data->REG_CRITICAL_TEMP_TOLERANCE
3670 = NCT6106_REG_CRITICAL_TEMP_TOLERANCE;
3671 data->REG_CRITICAL_PWM_ENABLE = NCT6106_REG_CRITICAL_PWM_ENABLE;
3672 data->CRITICAL_PWM_ENABLE_MASK
3673 = NCT6106_CRITICAL_PWM_ENABLE_MASK;
3674 data->REG_CRITICAL_PWM = NCT6106_REG_CRITICAL_PWM;
3675 data->REG_TEMP_OFFSET = NCT6106_REG_TEMP_OFFSET;
3676 data->REG_TEMP_SOURCE = NCT6106_REG_TEMP_SOURCE;
3677 data->REG_TEMP_SEL = NCT6106_REG_TEMP_SEL;
3678 data->REG_WEIGHT_TEMP_SEL = NCT6106_REG_WEIGHT_TEMP_SEL;
3679 data->REG_WEIGHT_TEMP[0] = NCT6106_REG_WEIGHT_TEMP_STEP;
3680 data->REG_WEIGHT_TEMP[1] = NCT6106_REG_WEIGHT_TEMP_STEP_TOL;
3681 data->REG_WEIGHT_TEMP[2] = NCT6106_REG_WEIGHT_TEMP_BASE;
3682 data->REG_ALARM = NCT6106_REG_ALARM;
3683 data->ALARM_BITS = NCT6106_ALARM_BITS;
3684 data->REG_BEEP = NCT6106_REG_BEEP;
3685 data->BEEP_BITS = NCT6106_BEEP_BITS;
3686
3687 reg_temp = NCT6106_REG_TEMP;
3688 reg_temp_mon = NCT6106_REG_TEMP_MON;
3689 num_reg_temp = ARRAY_SIZE(NCT6106_REG_TEMP);
3690 num_reg_temp_mon = ARRAY_SIZE(NCT6106_REG_TEMP_MON);
3691 reg_temp_over = NCT6106_REG_TEMP_OVER;
3692 reg_temp_hyst = NCT6106_REG_TEMP_HYST;
3693 reg_temp_config = NCT6106_REG_TEMP_CONFIG;
3694 reg_temp_alternate = NCT6106_REG_TEMP_ALTERNATE;
3695 reg_temp_crit = NCT6106_REG_TEMP_CRIT;
3696 reg_temp_crit_l = NCT6106_REG_TEMP_CRIT_L;
3697 reg_temp_crit_h = NCT6106_REG_TEMP_CRIT_H;
3698
3699 break;
3700 case nct6775:
3701 data->in_num = 9;
3702 data->pwm_num = 3;
3703 data->auto_pwm_num = 6;
3704 data->has_fan_div = true;
3705 data->temp_fixed_num = 3;
3706 data->num_temp_alarms = 3;
3707 data->num_temp_beeps = 3;
3708
3709 data->ALARM_BITS = NCT6775_ALARM_BITS;
3710 data->BEEP_BITS = NCT6775_BEEP_BITS;
3711
3712 data->fan_from_reg = fan_from_reg16;
3713 data->fan_from_reg_min = fan_from_reg8;
3714 data->target_temp_mask = 0x7f;
3715 data->tolerance_mask = 0x0f;
3716 data->speed_tolerance_limit = 15;
3717
3718 data->temp_label = nct6775_temp_label;
3719 data->temp_mask = NCT6775_TEMP_MASK;
3720
3721 data->REG_CONFIG = NCT6775_REG_CONFIG;
3722 data->REG_VBAT = NCT6775_REG_VBAT;
3723 data->REG_DIODE = NCT6775_REG_DIODE;
3724 data->DIODE_MASK = NCT6775_DIODE_MASK;
3725 data->REG_VIN = NCT6775_REG_IN;
3726 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3727 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3728 data->REG_TARGET = NCT6775_REG_TARGET;
3729 data->REG_FAN = NCT6775_REG_FAN;
3730 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3731 data->REG_FAN_MIN = NCT6775_REG_FAN_MIN;
3732 data->REG_FAN_PULSES = NCT6775_REG_FAN_PULSES;
3733 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3734 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3735 data->REG_FAN_TIME[1] = NCT6775_REG_FAN_STEP_UP_TIME;
3736 data->REG_FAN_TIME[2] = NCT6775_REG_FAN_STEP_DOWN_TIME;
3737 data->REG_PWM[0] = NCT6775_REG_PWM;
3738 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3739 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3740 data->REG_PWM[3] = NCT6775_REG_FAN_MAX_OUTPUT;
3741 data->REG_PWM[4] = NCT6775_REG_FAN_STEP_OUTPUT;
3742 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3743 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3744 data->REG_PWM_MODE = NCT6775_REG_PWM_MODE;
3745 data->PWM_MODE_MASK = NCT6775_PWM_MODE_MASK;
3746 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3747 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3748 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3749 data->REG_CRITICAL_TEMP_TOLERANCE
3750 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3751 data->REG_TEMP_OFFSET = NCT6775_REG_TEMP_OFFSET;
3752 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3753 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
3754 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3755 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3756 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3757 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
3758 data->REG_ALARM = NCT6775_REG_ALARM;
3759 data->REG_BEEP = NCT6775_REG_BEEP;
3760
3761 reg_temp = NCT6775_REG_TEMP;
3762 reg_temp_mon = NCT6775_REG_TEMP_MON;
3763 num_reg_temp = ARRAY_SIZE(NCT6775_REG_TEMP);
3764 num_reg_temp_mon = ARRAY_SIZE(NCT6775_REG_TEMP_MON);
3765 reg_temp_over = NCT6775_REG_TEMP_OVER;
3766 reg_temp_hyst = NCT6775_REG_TEMP_HYST;
3767 reg_temp_config = NCT6775_REG_TEMP_CONFIG;
3768 reg_temp_alternate = NCT6775_REG_TEMP_ALTERNATE;
3769 reg_temp_crit = NCT6775_REG_TEMP_CRIT;
3770
3771 break;
3772 case nct6776:
3773 data->in_num = 9;
3774 data->pwm_num = 3;
3775 data->auto_pwm_num = 4;
3776 data->has_fan_div = false;
3777 data->temp_fixed_num = 3;
3778 data->num_temp_alarms = 3;
3779 data->num_temp_beeps = 6;
3780
3781 data->ALARM_BITS = NCT6776_ALARM_BITS;
3782 data->BEEP_BITS = NCT6776_BEEP_BITS;
3783
3784 data->fan_from_reg = fan_from_reg13;
3785 data->fan_from_reg_min = fan_from_reg13;
3786 data->target_temp_mask = 0xff;
3787 data->tolerance_mask = 0x07;
3788 data->speed_tolerance_limit = 63;
3789
3790 data->temp_label = nct6776_temp_label;
3791 data->temp_mask = NCT6776_TEMP_MASK;
3792
3793 data->REG_CONFIG = NCT6775_REG_CONFIG;
3794 data->REG_VBAT = NCT6775_REG_VBAT;
3795 data->REG_DIODE = NCT6775_REG_DIODE;
3796 data->DIODE_MASK = NCT6775_DIODE_MASK;
3797 data->REG_VIN = NCT6775_REG_IN;
3798 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3799 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3800 data->REG_TARGET = NCT6775_REG_TARGET;
3801 data->REG_FAN = NCT6775_REG_FAN;
3802 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3803 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
3804 data->REG_FAN_PULSES = NCT6776_REG_FAN_PULSES;
3805 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3806 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3807 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
3808 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
3809 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
3810 data->REG_PWM[0] = NCT6775_REG_PWM;
3811 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3812 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3813 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3814 data->REG_PWM[6] = NCT6776_REG_WEIGHT_DUTY_BASE;
3815 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3816 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
3817 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
3818 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3819 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3820 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3821 data->REG_CRITICAL_TEMP_TOLERANCE
3822 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3823 data->REG_TEMP_OFFSET = NCT6775_REG_TEMP_OFFSET;
3824 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3825 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
3826 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3827 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3828 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3829 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
3830 data->REG_ALARM = NCT6775_REG_ALARM;
3831 data->REG_BEEP = NCT6776_REG_BEEP;
3832
3833 reg_temp = NCT6775_REG_TEMP;
3834 reg_temp_mon = NCT6775_REG_TEMP_MON;
3835 num_reg_temp = ARRAY_SIZE(NCT6775_REG_TEMP);
3836 num_reg_temp_mon = ARRAY_SIZE(NCT6775_REG_TEMP_MON);
3837 reg_temp_over = NCT6775_REG_TEMP_OVER;
3838 reg_temp_hyst = NCT6775_REG_TEMP_HYST;
3839 reg_temp_config = NCT6776_REG_TEMP_CONFIG;
3840 reg_temp_alternate = NCT6776_REG_TEMP_ALTERNATE;
3841 reg_temp_crit = NCT6776_REG_TEMP_CRIT;
3842
3843 break;
3844 case nct6779:
3845 data->in_num = 15;
3846 data->pwm_num = 5;
3847 data->auto_pwm_num = 4;
3848 data->has_fan_div = false;
3849 data->temp_fixed_num = 6;
3850 data->num_temp_alarms = 2;
3851 data->num_temp_beeps = 2;
3852
3853 data->ALARM_BITS = NCT6779_ALARM_BITS;
3854 data->BEEP_BITS = NCT6779_BEEP_BITS;
3855
3856 data->fan_from_reg = fan_from_reg13;
3857 data->fan_from_reg_min = fan_from_reg13;
3858 data->target_temp_mask = 0xff;
3859 data->tolerance_mask = 0x07;
3860 data->speed_tolerance_limit = 63;
3861
3862 data->temp_label = nct6779_temp_label;
3863 data->temp_mask = NCT6779_TEMP_MASK;
3864
3865 data->REG_CONFIG = NCT6775_REG_CONFIG;
3866 data->REG_VBAT = NCT6775_REG_VBAT;
3867 data->REG_DIODE = NCT6775_REG_DIODE;
3868 data->DIODE_MASK = NCT6775_DIODE_MASK;
3869 data->REG_VIN = NCT6779_REG_IN;
3870 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3871 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3872 data->REG_TARGET = NCT6775_REG_TARGET;
3873 data->REG_FAN = NCT6779_REG_FAN;
3874 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3875 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
3876 data->REG_FAN_PULSES = NCT6779_REG_FAN_PULSES;
3877 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3878 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3879 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
3880 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
3881 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
3882 data->REG_PWM[0] = NCT6775_REG_PWM;
3883 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3884 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3885 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3886 data->REG_PWM[6] = NCT6776_REG_WEIGHT_DUTY_BASE;
3887 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3888 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
3889 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
3890 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3891 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3892 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3893 data->REG_CRITICAL_TEMP_TOLERANCE
3894 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3895 data->REG_CRITICAL_PWM_ENABLE = NCT6779_REG_CRITICAL_PWM_ENABLE;
3896 data->CRITICAL_PWM_ENABLE_MASK
3897 = NCT6779_CRITICAL_PWM_ENABLE_MASK;
3898 data->REG_CRITICAL_PWM = NCT6779_REG_CRITICAL_PWM;
3899 data->REG_TEMP_OFFSET = NCT6779_REG_TEMP_OFFSET;
3900 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3901 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
3902 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3903 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3904 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3905 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
3906 data->REG_ALARM = NCT6779_REG_ALARM;
3907 data->REG_BEEP = NCT6776_REG_BEEP;
3908
3909 reg_temp = NCT6779_REG_TEMP;
3910 reg_temp_mon = NCT6779_REG_TEMP_MON;
3911 num_reg_temp = ARRAY_SIZE(NCT6779_REG_TEMP);
3912 num_reg_temp_mon = ARRAY_SIZE(NCT6779_REG_TEMP_MON);
3913 reg_temp_over = NCT6779_REG_TEMP_OVER;
3914 reg_temp_hyst = NCT6779_REG_TEMP_HYST;
3915 reg_temp_config = NCT6779_REG_TEMP_CONFIG;
3916 reg_temp_alternate = NCT6779_REG_TEMP_ALTERNATE;
3917 reg_temp_crit = NCT6779_REG_TEMP_CRIT;
3918
3919 break;
3920 case nct6791:
3921 case nct6792:
3922 case nct6793:
3923 case nct6795:
3924 case nct6796:
3925 data->in_num = 15;
3926 data->pwm_num = (data->kind == nct6796) ? 7 : 6;
3927 data->auto_pwm_num = 4;
3928 data->has_fan_div = false;
3929 data->temp_fixed_num = 6;
3930 data->num_temp_alarms = 2;
3931 data->num_temp_beeps = 2;
3932
3933 data->ALARM_BITS = NCT6791_ALARM_BITS;
3934 data->BEEP_BITS = NCT6779_BEEP_BITS;
3935
3936 data->fan_from_reg = fan_from_reg13;
3937 data->fan_from_reg_min = fan_from_reg13;
3938 data->target_temp_mask = 0xff;
3939 data->tolerance_mask = 0x07;
3940 data->speed_tolerance_limit = 63;
3941
3942 switch (data->kind) {
3943 default:
3944 case nct6791:
3945 data->temp_label = nct6779_temp_label;
3946 data->temp_mask = NCT6791_TEMP_MASK;
3947 break;
3948 case nct6792:
3949 data->temp_label = nct6792_temp_label;
3950 data->temp_mask = NCT6792_TEMP_MASK;
3951 break;
3952 case nct6793:
3953 data->temp_label = nct6793_temp_label;
3954 data->temp_mask = NCT6793_TEMP_MASK;
3955 break;
3956 case nct6795:
3957 data->temp_label = nct6795_temp_label;
3958 data->temp_mask = NCT6795_TEMP_MASK;
3959 break;
3960 case nct6796:
3961 data->temp_label = nct6796_temp_label;
3962 data->temp_mask = NCT6796_TEMP_MASK;
3963 break;
3964 }
3965
3966 data->REG_CONFIG = NCT6775_REG_CONFIG;
3967 data->REG_VBAT = NCT6775_REG_VBAT;
3968 data->REG_DIODE = NCT6775_REG_DIODE;
3969 data->DIODE_MASK = NCT6775_DIODE_MASK;
3970 data->REG_VIN = NCT6779_REG_IN;
3971 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3972 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3973 data->REG_TARGET = NCT6775_REG_TARGET;
3974 data->REG_FAN = NCT6779_REG_FAN;
3975 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3976 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
3977 data->REG_FAN_PULSES = NCT6779_REG_FAN_PULSES;
3978 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3979 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3980 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
3981 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
3982 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
3983 data->REG_PWM[0] = NCT6775_REG_PWM;
3984 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3985 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3986 data->REG_PWM[5] = NCT6791_REG_WEIGHT_DUTY_STEP;
3987 data->REG_PWM[6] = NCT6791_REG_WEIGHT_DUTY_BASE;
3988 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3989 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
3990 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
3991 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3992 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3993 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3994 data->REG_CRITICAL_TEMP_TOLERANCE
3995 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3996 data->REG_CRITICAL_PWM_ENABLE = NCT6779_REG_CRITICAL_PWM_ENABLE;
3997 data->CRITICAL_PWM_ENABLE_MASK
3998 = NCT6779_CRITICAL_PWM_ENABLE_MASK;
3999 data->REG_CRITICAL_PWM = NCT6779_REG_CRITICAL_PWM;
4000 data->REG_TEMP_OFFSET = NCT6779_REG_TEMP_OFFSET;
4001 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
4002 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
4003 data->REG_WEIGHT_TEMP_SEL = NCT6791_REG_WEIGHT_TEMP_SEL;
4004 data->REG_WEIGHT_TEMP[0] = NCT6791_REG_WEIGHT_TEMP_STEP;
4005 data->REG_WEIGHT_TEMP[1] = NCT6791_REG_WEIGHT_TEMP_STEP_TOL;
4006 data->REG_WEIGHT_TEMP[2] = NCT6791_REG_WEIGHT_TEMP_BASE;
4007 data->REG_ALARM = NCT6791_REG_ALARM;
4008 if (data->kind == nct6791)
4009 data->REG_BEEP = NCT6776_REG_BEEP;
4010 else
4011 data->REG_BEEP = NCT6792_REG_BEEP;
4012
4013 reg_temp = NCT6779_REG_TEMP;
4014 num_reg_temp = ARRAY_SIZE(NCT6779_REG_TEMP);
4015 if (data->kind == nct6791) {
4016 reg_temp_mon = NCT6779_REG_TEMP_MON;
4017 num_reg_temp_mon = ARRAY_SIZE(NCT6779_REG_TEMP_MON);
4018 } else {
4019 reg_temp_mon = NCT6792_REG_TEMP_MON;
4020 num_reg_temp_mon = ARRAY_SIZE(NCT6792_REG_TEMP_MON);
4021 }
4022 reg_temp_over = NCT6779_REG_TEMP_OVER;
4023 reg_temp_hyst = NCT6779_REG_TEMP_HYST;
4024 reg_temp_config = NCT6779_REG_TEMP_CONFIG;
4025 reg_temp_alternate = NCT6779_REG_TEMP_ALTERNATE;
4026 reg_temp_crit = NCT6779_REG_TEMP_CRIT;
4027
4028 break;
4029 default:
4030 return -ENODEV;
4031 }
4032 data->have_in = BIT(data->in_num) - 1;
4033 data->have_temp = 0;
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043 mask = 0;
4044 available = 0;
4045 for (i = 0; i < num_reg_temp; i++) {
4046 if (reg_temp[i] == 0)
4047 continue;
4048
4049 src = nct6775_read_value(data, data->REG_TEMP_SOURCE[i]) & 0x1f;
4050 if (!src || (mask & BIT(src)))
4051 available |= BIT(i);
4052
4053 mask |= BIT(src);
4054 }
4055
4056
4057
4058
4059
4060 add_temp_sensors(data, data->REG_TEMP_SEL, &available, &mask);
4061 add_temp_sensors(data, data->REG_WEIGHT_TEMP_SEL, &available, &mask);
4062
4063 mask = 0;
4064 s = NUM_TEMP_FIXED;
4065 for (i = 0; i < num_reg_temp; i++) {
4066 if (reg_temp[i] == 0)
4067 continue;
4068
4069 src = nct6775_read_value(data, data->REG_TEMP_SOURCE[i]) & 0x1f;
4070 if (!src || (mask & BIT(src)))
4071 continue;
4072
4073 if (!(data->temp_mask & BIT(src))) {
4074 dev_info(dev,
4075 "Invalid temperature source %d at index %d, source register 0x%x, temp register 0x%x\n",
4076 src, i, data->REG_TEMP_SOURCE[i], reg_temp[i]);
4077 continue;
4078 }
4079
4080 mask |= BIT(src);
4081
4082
4083 if (src <= data->temp_fixed_num) {
4084 data->have_temp |= BIT(src - 1);
4085 data->have_temp_fixed |= BIT(src - 1);
4086 data->reg_temp[0][src - 1] = reg_temp[i];
4087 data->reg_temp[1][src - 1] = reg_temp_over[i];
4088 data->reg_temp[2][src - 1] = reg_temp_hyst[i];
4089 if (reg_temp_crit_h && reg_temp_crit_h[i])
4090 data->reg_temp[3][src - 1] = reg_temp_crit_h[i];
4091 else if (reg_temp_crit[src - 1])
4092 data->reg_temp[3][src - 1]
4093 = reg_temp_crit[src - 1];
4094 if (reg_temp_crit_l && reg_temp_crit_l[i])
4095 data->reg_temp[4][src - 1] = reg_temp_crit_l[i];
4096 data->reg_temp_config[src - 1] = reg_temp_config[i];
4097 data->temp_src[src - 1] = src;
4098 continue;
4099 }
4100
4101 if (s >= NUM_TEMP)
4102 continue;
4103
4104
4105 data->have_temp |= BIT(s);
4106 data->reg_temp[0][s] = reg_temp[i];
4107 data->reg_temp[1][s] = reg_temp_over[i];
4108 data->reg_temp[2][s] = reg_temp_hyst[i];
4109 data->reg_temp_config[s] = reg_temp_config[i];
4110 if (reg_temp_crit_h && reg_temp_crit_h[i])
4111 data->reg_temp[3][s] = reg_temp_crit_h[i];
4112 else if (reg_temp_crit[src - 1])
4113 data->reg_temp[3][s] = reg_temp_crit[src - 1];
4114 if (reg_temp_crit_l && reg_temp_crit_l[i])
4115 data->reg_temp[4][s] = reg_temp_crit_l[i];
4116
4117 data->temp_src[s] = src;
4118 s++;
4119 }
4120
4121
4122
4123
4124
4125 for (i = 0; i < num_reg_temp_mon; i++) {
4126 if (reg_temp_mon[i] == 0)
4127 continue;
4128
4129 src = nct6775_read_value(data, data->REG_TEMP_SEL[i]) & 0x1f;
4130 if (!src)
4131 continue;
4132
4133 if (!(data->temp_mask & BIT(src))) {
4134 dev_info(dev,
4135 "Invalid temperature source %d at index %d, source register 0x%x, temp register 0x%x\n",
4136 src, i, data->REG_TEMP_SEL[i],
4137 reg_temp_mon[i]);
4138 continue;
4139 }
4140
4141
4142
4143
4144
4145
4146 if (src != TEMP_SOURCE_VIRTUAL) {
4147 if (mask & BIT(src))
4148 continue;
4149 mask |= BIT(src);
4150 }
4151
4152
4153 if (src <= data->temp_fixed_num) {
4154 if (data->have_temp & BIT(src - 1))
4155 continue;
4156 data->have_temp |= BIT(src - 1);
4157 data->have_temp_fixed |= BIT(src - 1);
4158 data->reg_temp[0][src - 1] = reg_temp_mon[i];
4159 data->temp_src[src - 1] = src;
4160 continue;
4161 }
4162
4163 if (s >= NUM_TEMP)
4164 continue;
4165
4166
4167 data->have_temp |= BIT(s);
4168 data->reg_temp[0][s] = reg_temp_mon[i];
4169 data->temp_src[s] = src;
4170 s++;
4171 }
4172
4173#ifdef USE_ALTERNATE
4174
4175
4176
4177
4178
4179
4180 for (i = 0; i < 31; i++) {
4181 if (!(data->temp_mask & BIT(i + 1)))
4182 continue;
4183 if (!reg_temp_alternate[i])
4184 continue;
4185 if (mask & BIT(i + 1))
4186 continue;
4187 if (i < data->temp_fixed_num) {
4188 if (data->have_temp & BIT(i))
4189 continue;
4190 data->have_temp |= BIT(i);
4191 data->have_temp_fixed |= BIT(i);
4192 data->reg_temp[0][i] = reg_temp_alternate[i];
4193 if (i < num_reg_temp) {
4194 data->reg_temp[1][i] = reg_temp_over[i];
4195 data->reg_temp[2][i] = reg_temp_hyst[i];
4196 }
4197 data->temp_src[i] = i + 1;
4198 continue;
4199 }
4200
4201 if (s >= NUM_TEMP)
4202 break;
4203
4204 data->have_temp |= BIT(s);
4205 data->reg_temp[0][s] = reg_temp_alternate[i];
4206 data->temp_src[s] = i + 1;
4207 s++;
4208 }
4209#endif
4210
4211
4212 nct6775_init_device(data);
4213
4214 err = superio_enter(sio_data->sioreg);
4215 if (err)
4216 return err;
4217
4218 cr2a = superio_inb(sio_data->sioreg, 0x2a);
4219 switch (data->kind) {
4220 case nct6775:
4221 data->have_vid = (cr2a & 0x40);
4222 break;
4223 case nct6776:
4224 data->have_vid = (cr2a & 0x60) == 0x40;
4225 break;
4226 case nct6106:
4227 case nct6779:
4228 case nct6791:
4229 case nct6792:
4230 case nct6793:
4231 case nct6795:
4232 case nct6796:
4233 break;
4234 }
4235
4236
4237
4238
4239
4240 if (data->have_vid) {
4241 superio_select(sio_data->sioreg, NCT6775_LD_VID);
4242 data->vid = superio_inb(sio_data->sioreg, 0xe3);
4243 data->vrm = vid_which_vrm();
4244 }
4245
4246 if (fan_debounce) {
4247 u8 tmp;
4248
4249 superio_select(sio_data->sioreg, NCT6775_LD_HWM);
4250 tmp = superio_inb(sio_data->sioreg,
4251 NCT6775_REG_CR_FAN_DEBOUNCE);
4252 switch (data->kind) {
4253 case nct6106:
4254 tmp |= 0xe0;
4255 break;
4256 case nct6775:
4257 tmp |= 0x1e;
4258 break;
4259 case nct6776:
4260 case nct6779:
4261 tmp |= 0x3e;
4262 break;
4263 case nct6791:
4264 case nct6792:
4265 case nct6793:
4266 case nct6795:
4267 case nct6796:
4268 tmp |= 0x7e;
4269 break;
4270 }
4271 superio_outb(sio_data->sioreg, NCT6775_REG_CR_FAN_DEBOUNCE,
4272 tmp);
4273 dev_info(&pdev->dev, "Enabled fan debounce for chip %s\n",
4274 data->name);
4275 }
4276
4277 nct6775_check_fan_inputs(data);
4278
4279 superio_exit(sio_data->sioreg);
4280
4281
4282 nct6775_init_fan_common(dev, data);
4283
4284
4285 group = nct6775_create_attr_group(dev, &nct6775_pwm_template_group,
4286 data->pwm_num);
4287 if (IS_ERR(group))
4288 return PTR_ERR(group);
4289
4290 data->groups[num_attr_groups++] = group;
4291
4292 group = nct6775_create_attr_group(dev, &nct6775_in_template_group,
4293 fls(data->have_in));
4294 if (IS_ERR(group))
4295 return PTR_ERR(group);
4296
4297 data->groups[num_attr_groups++] = group;
4298
4299 group = nct6775_create_attr_group(dev, &nct6775_fan_template_group,
4300 fls(data->has_fan));
4301 if (IS_ERR(group))
4302 return PTR_ERR(group);
4303
4304 data->groups[num_attr_groups++] = group;
4305
4306 group = nct6775_create_attr_group(dev, &nct6775_temp_template_group,
4307 fls(data->have_temp));
4308 if (IS_ERR(group))
4309 return PTR_ERR(group);
4310
4311 data->groups[num_attr_groups++] = group;
4312 data->groups[num_attr_groups++] = &nct6775_group_other;
4313
4314 hwmon_dev = devm_hwmon_device_register_with_groups(dev, data->name,
4315 data, data->groups);
4316 return PTR_ERR_OR_ZERO(hwmon_dev);
4317}
4318
4319static void nct6791_enable_io_mapping(int sioaddr)
4320{
4321 int val;
4322
4323 val = superio_inb(sioaddr, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE);
4324 if (val & 0x10) {
4325 pr_info("Enabling hardware monitor logical device mappings.\n");
4326 superio_outb(sioaddr, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE,
4327 val & ~0x10);
4328 }
4329}
4330
4331static int __maybe_unused nct6775_suspend(struct device *dev)
4332{
4333 struct nct6775_data *data = nct6775_update_device(dev);
4334
4335 mutex_lock(&data->update_lock);
4336 data->vbat = nct6775_read_value(data, data->REG_VBAT);
4337 if (data->kind == nct6775) {
4338 data->fandiv1 = nct6775_read_value(data, NCT6775_REG_FANDIV1);
4339 data->fandiv2 = nct6775_read_value(data, NCT6775_REG_FANDIV2);
4340 }
4341 mutex_unlock(&data->update_lock);
4342
4343 return 0;
4344}
4345
4346static int __maybe_unused nct6775_resume(struct device *dev)
4347{
4348 struct nct6775_data *data = dev_get_drvdata(dev);
4349 int sioreg = data->sioreg;
4350 int i, j, err = 0;
4351 u8 reg;
4352
4353 mutex_lock(&data->update_lock);
4354 data->bank = 0xff;
4355
4356 err = superio_enter(sioreg);
4357 if (err)
4358 goto abort;
4359
4360 superio_select(sioreg, NCT6775_LD_HWM);
4361 reg = superio_inb(sioreg, SIO_REG_ENABLE);
4362 if (reg != data->sio_reg_enable)
4363 superio_outb(sioreg, SIO_REG_ENABLE, data->sio_reg_enable);
4364
4365 if (data->kind == nct6791 || data->kind == nct6792 ||
4366 data->kind == nct6793 || data->kind == nct6795 ||
4367 data->kind == nct6796)
4368 nct6791_enable_io_mapping(sioreg);
4369
4370 superio_exit(sioreg);
4371
4372
4373 for (i = 0; i < data->in_num; i++) {
4374 if (!(data->have_in & BIT(i)))
4375 continue;
4376
4377 nct6775_write_value(data, data->REG_IN_MINMAX[0][i],
4378 data->in[i][1]);
4379 nct6775_write_value(data, data->REG_IN_MINMAX[1][i],
4380 data->in[i][2]);
4381 }
4382
4383 for (i = 0; i < ARRAY_SIZE(data->fan_min); i++) {
4384 if (!(data->has_fan_min & BIT(i)))
4385 continue;
4386
4387 nct6775_write_value(data, data->REG_FAN_MIN[i],
4388 data->fan_min[i]);
4389 }
4390
4391 for (i = 0; i < NUM_TEMP; i++) {
4392 if (!(data->have_temp & BIT(i)))
4393 continue;
4394
4395 for (j = 1; j < ARRAY_SIZE(data->reg_temp); j++)
4396 if (data->reg_temp[j][i])
4397 nct6775_write_temp(data, data->reg_temp[j][i],
4398 data->temp[j][i]);
4399 }
4400
4401
4402 nct6775_write_value(data, data->REG_VBAT, data->vbat);
4403 if (data->kind == nct6775) {
4404 nct6775_write_value(data, NCT6775_REG_FANDIV1, data->fandiv1);
4405 nct6775_write_value(data, NCT6775_REG_FANDIV2, data->fandiv2);
4406 }
4407
4408abort:
4409
4410 data->valid = false;
4411 mutex_unlock(&data->update_lock);
4412
4413 return err;
4414}
4415
4416static SIMPLE_DEV_PM_OPS(nct6775_dev_pm_ops, nct6775_suspend, nct6775_resume);
4417
4418static struct platform_driver nct6775_driver = {
4419 .driver = {
4420 .name = DRVNAME,
4421 .pm = &nct6775_dev_pm_ops,
4422 },
4423 .probe = nct6775_probe,
4424};
4425
4426
4427static int __init nct6775_find(int sioaddr, struct nct6775_sio_data *sio_data)
4428{
4429 u16 val;
4430 int err;
4431 int addr;
4432
4433 err = superio_enter(sioaddr);
4434 if (err)
4435 return err;
4436
4437 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8) |
4438 superio_inb(sioaddr, SIO_REG_DEVID + 1);
4439 if (force_id && val != 0xffff)
4440 val = force_id;
4441
4442 switch (val & SIO_ID_MASK) {
4443 case SIO_NCT6106_ID:
4444 sio_data->kind = nct6106;
4445 break;
4446 case SIO_NCT6775_ID:
4447 sio_data->kind = nct6775;
4448 break;
4449 case SIO_NCT6776_ID:
4450 sio_data->kind = nct6776;
4451 break;
4452 case SIO_NCT6779_ID:
4453 sio_data->kind = nct6779;
4454 break;
4455 case SIO_NCT6791_ID:
4456 sio_data->kind = nct6791;
4457 break;
4458 case SIO_NCT6792_ID:
4459 sio_data->kind = nct6792;
4460 break;
4461 case SIO_NCT6793_ID:
4462 sio_data->kind = nct6793;
4463 break;
4464 case SIO_NCT6795_ID:
4465 sio_data->kind = nct6795;
4466 break;
4467 case SIO_NCT6796_ID:
4468 sio_data->kind = nct6796;
4469 break;
4470 default:
4471 if (val != 0xffff)
4472 pr_debug("unsupported chip ID: 0x%04x\n", val);
4473 superio_exit(sioaddr);
4474 return -ENODEV;
4475 }
4476
4477
4478 superio_select(sioaddr, NCT6775_LD_HWM);
4479 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
4480 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
4481 addr = val & IOREGION_ALIGNMENT;
4482 if (addr == 0) {
4483 pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
4484 superio_exit(sioaddr);
4485 return -ENODEV;
4486 }
4487
4488
4489 val = superio_inb(sioaddr, SIO_REG_ENABLE);
4490 if (!(val & 0x01)) {
4491 pr_warn("Forcibly enabling Super-I/O. Sensor is probably unusable.\n");
4492 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
4493 }
4494
4495 if (sio_data->kind == nct6791 || sio_data->kind == nct6792 ||
4496 sio_data->kind == nct6793 || sio_data->kind == nct6795 ||
4497 sio_data->kind == nct6796)
4498 nct6791_enable_io_mapping(sioaddr);
4499
4500 superio_exit(sioaddr);
4501 pr_info("Found %s or compatible chip at %#x:%#x\n",
4502 nct6775_sio_names[sio_data->kind], sioaddr, addr);
4503 sio_data->sioreg = sioaddr;
4504
4505 return addr;
4506}
4507
4508
4509
4510
4511
4512
4513
4514static struct platform_device *pdev[2];
4515
4516static int __init sensors_nct6775_init(void)
4517{
4518 int i, err;
4519 bool found = false;
4520 int address;
4521 struct resource res;
4522 struct nct6775_sio_data sio_data;
4523 int sioaddr[2] = { 0x2e, 0x4e };
4524
4525 err = platform_driver_register(&nct6775_driver);
4526 if (err)
4527 return err;
4528
4529
4530
4531
4532
4533
4534
4535
4536 for (i = 0; i < ARRAY_SIZE(pdev); i++) {
4537 address = nct6775_find(sioaddr[i], &sio_data);
4538 if (address <= 0)
4539 continue;
4540
4541 found = true;
4542
4543 pdev[i] = platform_device_alloc(DRVNAME, address);
4544 if (!pdev[i]) {
4545 err = -ENOMEM;
4546 goto exit_device_unregister;
4547 }
4548
4549 err = platform_device_add_data(pdev[i], &sio_data,
4550 sizeof(struct nct6775_sio_data));
4551 if (err)
4552 goto exit_device_put;
4553
4554 memset(&res, 0, sizeof(res));
4555 res.name = DRVNAME;
4556 res.start = address + IOREGION_OFFSET;
4557 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
4558 res.flags = IORESOURCE_IO;
4559
4560 err = acpi_check_resource_conflict(&res);
4561 if (err) {
4562 platform_device_put(pdev[i]);
4563 pdev[i] = NULL;
4564 continue;
4565 }
4566
4567 err = platform_device_add_resources(pdev[i], &res, 1);
4568 if (err)
4569 goto exit_device_put;
4570
4571
4572 err = platform_device_add(pdev[i]);
4573 if (err)
4574 goto exit_device_put;
4575 }
4576 if (!found) {
4577 err = -ENODEV;
4578 goto exit_unregister;
4579 }
4580
4581 return 0;
4582
4583exit_device_put:
4584 platform_device_put(pdev[i]);
4585exit_device_unregister:
4586 while (--i >= 0) {
4587 if (pdev[i])
4588 platform_device_unregister(pdev[i]);
4589 }
4590exit_unregister:
4591 platform_driver_unregister(&nct6775_driver);
4592 return err;
4593}
4594
4595static void __exit sensors_nct6775_exit(void)
4596{
4597 int i;
4598
4599 for (i = 0; i < ARRAY_SIZE(pdev); i++) {
4600 if (pdev[i])
4601 platform_device_unregister(pdev[i]);
4602 }
4603 platform_driver_unregister(&nct6775_driver);
4604}
4605
4606MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
4607MODULE_DESCRIPTION("Driver for NCT6775F and compatible chips");
4608MODULE_LICENSE("GPL");
4609
4610module_init(sensors_nct6775_init);
4611module_exit(sensors_nct6775_exit);
4612