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12#include <linux/kernel.h>
13#include <linux/slab.h>
14#include <linux/module.h>
15#include <linux/spinlock.h>
16#include <linux/i2c.h>
17#include <linux/interrupt.h>
18#include <linux/mv643xx_i2c.h>
19#include <linux/platform_device.h>
20#include <linux/reset.h>
21#include <linux/io.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/of_irq.h>
25#include <linux/clk.h>
26#include <linux/err.h>
27#include <linux/delay.h>
28
29#define MV64XXX_I2C_ADDR_ADDR(val) ((val & 0x7f) << 1)
30#define MV64XXX_I2C_BAUD_DIV_N(val) (val & 0x7)
31#define MV64XXX_I2C_BAUD_DIV_M(val) ((val & 0xf) << 3)
32
33#define MV64XXX_I2C_REG_CONTROL_ACK BIT(2)
34#define MV64XXX_I2C_REG_CONTROL_IFLG BIT(3)
35#define MV64XXX_I2C_REG_CONTROL_STOP BIT(4)
36#define MV64XXX_I2C_REG_CONTROL_START BIT(5)
37#define MV64XXX_I2C_REG_CONTROL_TWSIEN BIT(6)
38#define MV64XXX_I2C_REG_CONTROL_INTEN BIT(7)
39
40
41#define MV64XXX_I2C_STATUS_BUS_ERR 0x00
42#define MV64XXX_I2C_STATUS_MAST_START 0x08
43#define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10
44#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
45#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
46#define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28
47#define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30
48#define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38
49#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
50#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
51#define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50
52#define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
53#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
54#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
55#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
56#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
57#define MV64XXX_I2C_STATUS_NO_STATUS 0xf8
58
59
60#define MV64XXX_I2C_REG_TX_DATA_LO 0xc0
61#define MV64XXX_I2C_REG_TX_DATA_HI 0xc4
62#define MV64XXX_I2C_REG_RX_DATA_LO 0xc8
63#define MV64XXX_I2C_REG_RX_DATA_HI 0xcc
64#define MV64XXX_I2C_REG_BRIDGE_CONTROL 0xd0
65#define MV64XXX_I2C_REG_BRIDGE_STATUS 0xd4
66#define MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE 0xd8
67#define MV64XXX_I2C_REG_BRIDGE_INTR_MASK 0xdC
68#define MV64XXX_I2C_REG_BRIDGE_TIMING 0xe0
69
70
71#define MV64XXX_I2C_BRIDGE_CONTROL_WR BIT(0)
72#define MV64XXX_I2C_BRIDGE_CONTROL_RD BIT(1)
73#define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT 2
74#define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT BIT(12)
75#define MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT 13
76#define MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT 16
77#define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE BIT(19)
78#define MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START BIT(20)
79
80
81#define MV64XXX_I2C_BRIDGE_STATUS_ERROR BIT(0)
82
83
84enum {
85 MV64XXX_I2C_STATE_INVALID,
86 MV64XXX_I2C_STATE_IDLE,
87 MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
88 MV64XXX_I2C_STATE_WAITING_FOR_RESTART,
89 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
90 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
91 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK,
92 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA,
93};
94
95
96enum {
97 MV64XXX_I2C_ACTION_INVALID,
98 MV64XXX_I2C_ACTION_CONTINUE,
99 MV64XXX_I2C_ACTION_SEND_RESTART,
100 MV64XXX_I2C_ACTION_SEND_ADDR_1,
101 MV64XXX_I2C_ACTION_SEND_ADDR_2,
102 MV64XXX_I2C_ACTION_SEND_DATA,
103 MV64XXX_I2C_ACTION_RCV_DATA,
104 MV64XXX_I2C_ACTION_RCV_DATA_STOP,
105 MV64XXX_I2C_ACTION_SEND_STOP,
106};
107
108struct mv64xxx_i2c_regs {
109 u8 addr;
110 u8 ext_addr;
111 u8 data;
112 u8 control;
113 u8 status;
114 u8 clock;
115 u8 soft_reset;
116};
117
118struct mv64xxx_i2c_data {
119 struct i2c_msg *msgs;
120 int num_msgs;
121 int irq;
122 u32 state;
123 u32 action;
124 u32 aborting;
125 u32 cntl_bits;
126 void __iomem *reg_base;
127 struct mv64xxx_i2c_regs reg_offsets;
128 u32 addr1;
129 u32 addr2;
130 u32 bytes_left;
131 u32 byte_posn;
132 u32 send_stop;
133 u32 block;
134 int rc;
135 u32 freq_m;
136 u32 freq_n;
137 struct clk *clk;
138 struct clk *reg_clk;
139 wait_queue_head_t waitq;
140 spinlock_t lock;
141 struct i2c_msg *msg;
142 struct i2c_adapter adapter;
143 bool offload_enabled;
144
145 bool errata_delay;
146 struct reset_control *rstc;
147 bool irq_clear_inverted;
148
149 bool clk_n_base_0;
150};
151
152static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = {
153 .addr = 0x00,
154 .ext_addr = 0x10,
155 .data = 0x04,
156 .control = 0x08,
157 .status = 0x0c,
158 .clock = 0x0c,
159 .soft_reset = 0x1c,
160};
161
162static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_sun4i = {
163 .addr = 0x00,
164 .ext_addr = 0x04,
165 .data = 0x08,
166 .control = 0x0c,
167 .status = 0x10,
168 .clock = 0x14,
169 .soft_reset = 0x18,
170};
171
172static void
173mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
174 struct i2c_msg *msg)
175{
176 u32 dir = 0;
177
178 drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
179 MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN;
180
181 if (msg->flags & I2C_M_RD)
182 dir = 1;
183
184 if (msg->flags & I2C_M_TEN) {
185 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
186 drv_data->addr2 = (u32)msg->addr & 0xff;
187 } else {
188 drv_data->addr1 = MV64XXX_I2C_ADDR_ADDR((u32)msg->addr) | dir;
189 drv_data->addr2 = 0;
190 }
191}
192
193
194
195
196
197
198
199
200
201
202static void
203mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
204{
205 if (drv_data->offload_enabled) {
206 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
207 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING);
208 writel(0, drv_data->reg_base +
209 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
210 writel(0, drv_data->reg_base +
211 MV64XXX_I2C_REG_BRIDGE_INTR_MASK);
212 }
213
214 writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset);
215 writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n),
216 drv_data->reg_base + drv_data->reg_offsets.clock);
217 writel(0, drv_data->reg_base + drv_data->reg_offsets.addr);
218 writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr);
219 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
220 drv_data->reg_base + drv_data->reg_offsets.control);
221 drv_data->state = MV64XXX_I2C_STATE_IDLE;
222}
223
224static void
225mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
226{
227
228
229
230
231
232 if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
233 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
234 return;
235 }
236
237
238 switch (status) {
239
240 case MV64XXX_I2C_STATUS_MAST_START:
241 case MV64XXX_I2C_STATUS_MAST_REPEAT_START:
242 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
243 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
244 break;
245
246
247 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK:
248 if (drv_data->msg->flags & I2C_M_TEN) {
249 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
250 drv_data->state =
251 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
252 break;
253 }
254
255 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK:
256 case MV64XXX_I2C_STATUS_MAST_WR_ACK:
257 if ((drv_data->bytes_left == 0)
258 || (drv_data->aborting
259 && (drv_data->byte_posn != 0))) {
260 if (drv_data->send_stop || drv_data->aborting) {
261 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
262 drv_data->state = MV64XXX_I2C_STATE_IDLE;
263 } else {
264 drv_data->action =
265 MV64XXX_I2C_ACTION_SEND_RESTART;
266 drv_data->state =
267 MV64XXX_I2C_STATE_WAITING_FOR_RESTART;
268 }
269 } else {
270 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
271 drv_data->state =
272 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
273 drv_data->bytes_left--;
274 }
275 break;
276
277
278 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK:
279 if (drv_data->msg->flags & I2C_M_TEN) {
280 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
281 drv_data->state =
282 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
283 break;
284 }
285
286 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK:
287 if (drv_data->bytes_left == 0) {
288 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
289 drv_data->state = MV64XXX_I2C_STATE_IDLE;
290 break;
291 }
292
293 case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK:
294 if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK)
295 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
296 else {
297 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
298 drv_data->bytes_left--;
299 }
300 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
301
302 if ((drv_data->bytes_left == 1) || drv_data->aborting)
303 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
304 break;
305
306 case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK:
307 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
308 drv_data->state = MV64XXX_I2C_STATE_IDLE;
309 break;
310
311 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK:
312 case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK:
313 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK:
314
315 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
316 drv_data->state = MV64XXX_I2C_STATE_IDLE;
317 drv_data->rc = -ENXIO;
318 break;
319
320 default:
321 dev_err(&drv_data->adapter.dev,
322 "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
323 "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
324 drv_data->state, status, drv_data->msg->addr,
325 drv_data->msg->flags);
326 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
327 mv64xxx_i2c_hw_init(drv_data);
328 drv_data->rc = -EIO;
329 }
330}
331
332static void mv64xxx_i2c_send_start(struct mv64xxx_i2c_data *drv_data)
333{
334 drv_data->msg = drv_data->msgs;
335 drv_data->byte_posn = 0;
336 drv_data->bytes_left = drv_data->msg->len;
337 drv_data->aborting = 0;
338 drv_data->rc = 0;
339
340 mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
341 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
342 drv_data->reg_base + drv_data->reg_offsets.control);
343}
344
345static void
346mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
347{
348 switch(drv_data->action) {
349 case MV64XXX_I2C_ACTION_SEND_RESTART:
350
351 BUG_ON(drv_data->num_msgs == 0);
352
353 drv_data->msgs++;
354 drv_data->num_msgs--;
355 mv64xxx_i2c_send_start(drv_data);
356
357 if (drv_data->errata_delay)
358 udelay(5);
359
360
361
362
363
364
365 drv_data->send_stop = drv_data->num_msgs == 1;
366 break;
367
368 case MV64XXX_I2C_ACTION_CONTINUE:
369 writel(drv_data->cntl_bits,
370 drv_data->reg_base + drv_data->reg_offsets.control);
371 break;
372
373 case MV64XXX_I2C_ACTION_SEND_ADDR_1:
374 writel(drv_data->addr1,
375 drv_data->reg_base + drv_data->reg_offsets.data);
376 writel(drv_data->cntl_bits,
377 drv_data->reg_base + drv_data->reg_offsets.control);
378 break;
379
380 case MV64XXX_I2C_ACTION_SEND_ADDR_2:
381 writel(drv_data->addr2,
382 drv_data->reg_base + drv_data->reg_offsets.data);
383 writel(drv_data->cntl_bits,
384 drv_data->reg_base + drv_data->reg_offsets.control);
385 break;
386
387 case MV64XXX_I2C_ACTION_SEND_DATA:
388 writel(drv_data->msg->buf[drv_data->byte_posn++],
389 drv_data->reg_base + drv_data->reg_offsets.data);
390 writel(drv_data->cntl_bits,
391 drv_data->reg_base + drv_data->reg_offsets.control);
392 break;
393
394 case MV64XXX_I2C_ACTION_RCV_DATA:
395 drv_data->msg->buf[drv_data->byte_posn++] =
396 readl(drv_data->reg_base + drv_data->reg_offsets.data);
397 writel(drv_data->cntl_bits,
398 drv_data->reg_base + drv_data->reg_offsets.control);
399 break;
400
401 case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
402 drv_data->msg->buf[drv_data->byte_posn++] =
403 readl(drv_data->reg_base + drv_data->reg_offsets.data);
404 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
405 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
406 drv_data->reg_base + drv_data->reg_offsets.control);
407 drv_data->block = 0;
408 if (drv_data->errata_delay)
409 udelay(5);
410
411 wake_up(&drv_data->waitq);
412 break;
413
414 case MV64XXX_I2C_ACTION_INVALID:
415 default:
416 dev_err(&drv_data->adapter.dev,
417 "mv64xxx_i2c_do_action: Invalid action: %d\n",
418 drv_data->action);
419 drv_data->rc = -EIO;
420
421
422 case MV64XXX_I2C_ACTION_SEND_STOP:
423 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
424 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
425 drv_data->reg_base + drv_data->reg_offsets.control);
426 drv_data->block = 0;
427 wake_up(&drv_data->waitq);
428 break;
429 }
430}
431
432static void
433mv64xxx_i2c_read_offload_rx_data(struct mv64xxx_i2c_data *drv_data,
434 struct i2c_msg *msg)
435{
436 u32 buf[2];
437
438 buf[0] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_LO);
439 buf[1] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_HI);
440
441 memcpy(msg->buf, buf, msg->len);
442}
443
444static int
445mv64xxx_i2c_intr_offload(struct mv64xxx_i2c_data *drv_data)
446{
447 u32 cause, status;
448
449 cause = readl(drv_data->reg_base +
450 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
451 if (!cause)
452 return IRQ_NONE;
453
454 status = readl(drv_data->reg_base +
455 MV64XXX_I2C_REG_BRIDGE_STATUS);
456
457 if (status & MV64XXX_I2C_BRIDGE_STATUS_ERROR) {
458 drv_data->rc = -EIO;
459 goto out;
460 }
461
462 drv_data->rc = 0;
463
464
465
466
467
468 if (drv_data->num_msgs == 1 && drv_data->msgs[0].flags & I2C_M_RD) {
469 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs);
470 drv_data->msgs++;
471 drv_data->num_msgs--;
472 }
473
474
475
476
477 else if (drv_data->num_msgs == 2 &&
478 !(drv_data->msgs[0].flags & I2C_M_RD) &&
479 drv_data->msgs[1].flags & I2C_M_RD) {
480 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs + 1);
481 drv_data->msgs += 2;
482 drv_data->num_msgs -= 2;
483 }
484
485out:
486 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
487 writel(0, drv_data->reg_base +
488 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
489 drv_data->block = 0;
490
491 wake_up(&drv_data->waitq);
492
493 return IRQ_HANDLED;
494}
495
496static irqreturn_t
497mv64xxx_i2c_intr(int irq, void *dev_id)
498{
499 struct mv64xxx_i2c_data *drv_data = dev_id;
500 unsigned long flags;
501 u32 status;
502 irqreturn_t rc = IRQ_NONE;
503
504 spin_lock_irqsave(&drv_data->lock, flags);
505
506 if (drv_data->offload_enabled)
507 rc = mv64xxx_i2c_intr_offload(drv_data);
508
509 while (readl(drv_data->reg_base + drv_data->reg_offsets.control) &
510 MV64XXX_I2C_REG_CONTROL_IFLG) {
511 status = readl(drv_data->reg_base + drv_data->reg_offsets.status);
512 mv64xxx_i2c_fsm(drv_data, status);
513 mv64xxx_i2c_do_action(drv_data);
514
515 if (drv_data->irq_clear_inverted)
516 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_IFLG,
517 drv_data->reg_base + drv_data->reg_offsets.control);
518
519 rc = IRQ_HANDLED;
520 }
521 spin_unlock_irqrestore(&drv_data->lock, flags);
522
523 return rc;
524}
525
526
527
528
529
530
531
532
533static void
534mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
535{
536 long time_left;
537 unsigned long flags;
538 char abort = 0;
539
540 time_left = wait_event_timeout(drv_data->waitq,
541 !drv_data->block, drv_data->adapter.timeout);
542
543 spin_lock_irqsave(&drv_data->lock, flags);
544 if (!time_left) {
545 drv_data->rc = -ETIMEDOUT;
546 abort = 1;
547 } else if (time_left < 0) {
548 drv_data->rc = time_left;
549 abort = 1;
550 }
551
552 if (abort && drv_data->block) {
553 drv_data->aborting = 1;
554 spin_unlock_irqrestore(&drv_data->lock, flags);
555
556 time_left = wait_event_timeout(drv_data->waitq,
557 !drv_data->block, drv_data->adapter.timeout);
558
559 if ((time_left <= 0) && drv_data->block) {
560 drv_data->state = MV64XXX_I2C_STATE_IDLE;
561 dev_err(&drv_data->adapter.dev,
562 "mv64xxx: I2C bus locked, block: %d, "
563 "time_left: %d\n", drv_data->block,
564 (int)time_left);
565 mv64xxx_i2c_hw_init(drv_data);
566 }
567 } else
568 spin_unlock_irqrestore(&drv_data->lock, flags);
569}
570
571static int
572mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
573 int is_last)
574{
575 unsigned long flags;
576
577 spin_lock_irqsave(&drv_data->lock, flags);
578
579 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
580
581 drv_data->send_stop = is_last;
582 drv_data->block = 1;
583 mv64xxx_i2c_send_start(drv_data);
584 spin_unlock_irqrestore(&drv_data->lock, flags);
585
586 mv64xxx_i2c_wait_for_completion(drv_data);
587 return drv_data->rc;
588}
589
590static void
591mv64xxx_i2c_prepare_tx(struct mv64xxx_i2c_data *drv_data)
592{
593 struct i2c_msg *msg = drv_data->msgs;
594 u32 buf[2];
595
596 memcpy(buf, msg->buf, msg->len);
597
598 writel(buf[0], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO);
599 writel(buf[1], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI);
600}
601
602static int
603mv64xxx_i2c_offload_xfer(struct mv64xxx_i2c_data *drv_data)
604{
605 struct i2c_msg *msgs = drv_data->msgs;
606 int num = drv_data->num_msgs;
607 unsigned long ctrl_reg;
608 unsigned long flags;
609
610 spin_lock_irqsave(&drv_data->lock, flags);
611
612
613 ctrl_reg = MV64XXX_I2C_BRIDGE_CONTROL_ENABLE |
614 (msgs[0].addr << MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT);
615
616 if (msgs[0].flags & I2C_M_TEN)
617 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT;
618
619
620 if (num == 1 && !(msgs[0].flags & I2C_M_RD)) {
621 size_t len = msgs[0].len - 1;
622
623 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR |
624 (len << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT);
625 mv64xxx_i2c_prepare_tx(drv_data);
626 }
627
628 else if (num == 1 && msgs[0].flags & I2C_M_RD) {
629 size_t len = msgs[0].len - 1;
630
631 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_RD |
632 (len << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT);
633 }
634
635
636
637
638 else if (num == 2) {
639 size_t lentx = msgs[0].len - 1;
640 size_t lenrx = msgs[1].len - 1;
641
642 ctrl_reg |=
643 MV64XXX_I2C_BRIDGE_CONTROL_RD |
644 MV64XXX_I2C_BRIDGE_CONTROL_WR |
645 (lentx << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT) |
646 (lenrx << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT) |
647 MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START;
648 mv64xxx_i2c_prepare_tx(drv_data);
649 }
650
651
652 drv_data->block = 1;
653 writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
654 spin_unlock_irqrestore(&drv_data->lock, flags);
655
656 mv64xxx_i2c_wait_for_completion(drv_data);
657
658 return drv_data->rc;
659}
660
661static bool
662mv64xxx_i2c_valid_offload_sz(struct i2c_msg *msg)
663{
664 return msg->len <= 8 && msg->len >= 1;
665}
666
667static bool
668mv64xxx_i2c_can_offload(struct mv64xxx_i2c_data *drv_data)
669{
670 struct i2c_msg *msgs = drv_data->msgs;
671 int num = drv_data->num_msgs;
672
673 if (!drv_data->offload_enabled)
674 return false;
675
676
677
678
679
680
681 if (num == 1 && mv64xxx_i2c_valid_offload_sz(msgs))
682 return true;
683
684
685
686
687
688
689 if (num == 2 &&
690 mv64xxx_i2c_valid_offload_sz(msgs) &&
691 mv64xxx_i2c_valid_offload_sz(msgs + 1) &&
692 !(msgs[0].flags & I2C_M_RD) &&
693 msgs[1].flags & I2C_M_RD)
694 return true;
695
696 return false;
697}
698
699
700
701
702
703
704
705
706static u32
707mv64xxx_i2c_functionality(struct i2c_adapter *adap)
708{
709 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
710}
711
712static int
713mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
714{
715 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
716 int rc, ret = num;
717
718 BUG_ON(drv_data->msgs != NULL);
719 drv_data->msgs = msgs;
720 drv_data->num_msgs = num;
721
722 if (mv64xxx_i2c_can_offload(drv_data))
723 rc = mv64xxx_i2c_offload_xfer(drv_data);
724 else
725 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
726
727 if (rc < 0)
728 ret = rc;
729
730 drv_data->num_msgs = 0;
731 drv_data->msgs = NULL;
732
733 return ret;
734}
735
736static const struct i2c_algorithm mv64xxx_i2c_algo = {
737 .master_xfer = mv64xxx_i2c_xfer,
738 .functionality = mv64xxx_i2c_functionality,
739};
740
741
742
743
744
745
746
747
748static const struct of_device_id mv64xxx_i2c_of_match_table[] = {
749 { .compatible = "allwinner,sun4i-a10-i2c", .data = &mv64xxx_i2c_regs_sun4i},
750 { .compatible = "allwinner,sun6i-a31-i2c", .data = &mv64xxx_i2c_regs_sun4i},
751 { .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
752 { .compatible = "marvell,mv78230-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
753 { .compatible = "marvell,mv78230-a0-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
754 {}
755};
756MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
757
758#ifdef CONFIG_OF
759static int
760mv64xxx_calc_freq(struct mv64xxx_i2c_data *drv_data,
761 const int tclk, const int n, const int m)
762{
763 if (drv_data->clk_n_base_0)
764 return tclk / (10 * (m + 1) * (1 << n));
765 else
766 return tclk / (10 * (m + 1) * (2 << n));
767}
768
769static bool
770mv64xxx_find_baud_factors(struct mv64xxx_i2c_data *drv_data,
771 const u32 req_freq, const u32 tclk)
772{
773 int freq, delta, best_delta = INT_MAX;
774 int m, n;
775
776 for (n = 0; n <= 7; n++)
777 for (m = 0; m <= 15; m++) {
778 freq = mv64xxx_calc_freq(drv_data, tclk, n, m);
779 delta = req_freq - freq;
780 if (delta >= 0 && delta < best_delta) {
781 drv_data->freq_m = m;
782 drv_data->freq_n = n;
783 best_delta = delta;
784 }
785 if (best_delta == 0)
786 return true;
787 }
788 if (best_delta == INT_MAX)
789 return false;
790 return true;
791}
792
793static int
794mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
795 struct device *dev)
796{
797 const struct of_device_id *device;
798 struct device_node *np = dev->of_node;
799 u32 bus_freq, tclk;
800 int rc = 0;
801
802
803
804
805
806 if (IS_ERR(drv_data->clk)) {
807 rc = -ENODEV;
808 goto out;
809 }
810 tclk = clk_get_rate(drv_data->clk);
811
812 if (of_property_read_u32(np, "clock-frequency", &bus_freq))
813 bus_freq = 100000;
814
815 if (of_device_is_compatible(np, "allwinner,sun4i-a10-i2c") ||
816 of_device_is_compatible(np, "allwinner,sun6i-a31-i2c"))
817 drv_data->clk_n_base_0 = true;
818
819 if (!mv64xxx_find_baud_factors(drv_data, bus_freq, tclk)) {
820 rc = -EINVAL;
821 goto out;
822 }
823
824 drv_data->rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
825 if (IS_ERR(drv_data->rstc)) {
826 rc = PTR_ERR(drv_data->rstc);
827 goto out;
828 }
829 reset_control_deassert(drv_data->rstc);
830
831
832
833
834 drv_data->adapter.timeout = HZ;
835
836 device = of_match_device(mv64xxx_i2c_of_match_table, dev);
837 if (!device)
838 return -ENODEV;
839
840 memcpy(&drv_data->reg_offsets, device->data, sizeof(drv_data->reg_offsets));
841
842
843
844
845
846 if (of_device_is_compatible(np, "marvell,mv78230-i2c")) {
847 drv_data->offload_enabled = true;
848
849 if (bus_freq <= 100000)
850 drv_data->errata_delay = true;
851 }
852
853 if (of_device_is_compatible(np, "marvell,mv78230-a0-i2c")) {
854 drv_data->offload_enabled = false;
855
856 if (bus_freq <= 100000)
857 drv_data->errata_delay = true;
858 }
859
860 if (of_device_is_compatible(np, "allwinner,sun6i-a31-i2c"))
861 drv_data->irq_clear_inverted = true;
862
863out:
864 return rc;
865}
866#else
867static int
868mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
869 struct device *dev)
870{
871 return -ENODEV;
872}
873#endif
874
875static int
876mv64xxx_i2c_probe(struct platform_device *pd)
877{
878 struct mv64xxx_i2c_data *drv_data;
879 struct mv64xxx_i2c_pdata *pdata = dev_get_platdata(&pd->dev);
880 struct resource *r;
881 int rc;
882
883 if ((!pdata && !pd->dev.of_node))
884 return -ENODEV;
885
886 drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data),
887 GFP_KERNEL);
888 if (!drv_data)
889 return -ENOMEM;
890
891 r = platform_get_resource(pd, IORESOURCE_MEM, 0);
892 drv_data->reg_base = devm_ioremap_resource(&pd->dev, r);
893 if (IS_ERR(drv_data->reg_base))
894 return PTR_ERR(drv_data->reg_base);
895
896 strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
897 sizeof(drv_data->adapter.name));
898
899 init_waitqueue_head(&drv_data->waitq);
900 spin_lock_init(&drv_data->lock);
901
902
903 drv_data->clk = devm_clk_get(&pd->dev, NULL);
904 if (PTR_ERR(drv_data->clk) == -EPROBE_DEFER)
905 return -EPROBE_DEFER;
906 if (!IS_ERR(drv_data->clk))
907 clk_prepare_enable(drv_data->clk);
908
909 drv_data->reg_clk = devm_clk_get(&pd->dev, "reg");
910 if (PTR_ERR(drv_data->reg_clk) == -EPROBE_DEFER)
911 return -EPROBE_DEFER;
912 if (!IS_ERR(drv_data->reg_clk))
913 clk_prepare_enable(drv_data->reg_clk);
914
915 drv_data->irq = platform_get_irq(pd, 0);
916
917 if (pdata) {
918 drv_data->freq_m = pdata->freq_m;
919 drv_data->freq_n = pdata->freq_n;
920 drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout);
921 drv_data->offload_enabled = false;
922 memcpy(&drv_data->reg_offsets, &mv64xxx_i2c_regs_mv64xxx, sizeof(drv_data->reg_offsets));
923 } else if (pd->dev.of_node) {
924 rc = mv64xxx_of_config(drv_data, &pd->dev);
925 if (rc)
926 goto exit_clk;
927 }
928 if (drv_data->irq < 0) {
929 rc = drv_data->irq;
930 goto exit_reset;
931 }
932
933 drv_data->adapter.dev.parent = &pd->dev;
934 drv_data->adapter.algo = &mv64xxx_i2c_algo;
935 drv_data->adapter.owner = THIS_MODULE;
936 drv_data->adapter.class = I2C_CLASS_DEPRECATED;
937 drv_data->adapter.nr = pd->id;
938 drv_data->adapter.dev.of_node = pd->dev.of_node;
939 platform_set_drvdata(pd, drv_data);
940 i2c_set_adapdata(&drv_data->adapter, drv_data);
941
942 mv64xxx_i2c_hw_init(drv_data);
943
944 rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
945 MV64XXX_I2C_CTLR_NAME, drv_data);
946 if (rc) {
947 dev_err(&drv_data->adapter.dev,
948 "mv64xxx: Can't register intr handler irq%d: %d\n",
949 drv_data->irq, rc);
950 goto exit_reset;
951 } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
952 dev_err(&drv_data->adapter.dev,
953 "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
954 goto exit_free_irq;
955 }
956
957 return 0;
958
959exit_free_irq:
960 free_irq(drv_data->irq, drv_data);
961exit_reset:
962 reset_control_assert(drv_data->rstc);
963exit_clk:
964 clk_disable_unprepare(drv_data->reg_clk);
965 clk_disable_unprepare(drv_data->clk);
966
967 return rc;
968}
969
970static int
971mv64xxx_i2c_remove(struct platform_device *dev)
972{
973 struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(dev);
974
975 i2c_del_adapter(&drv_data->adapter);
976 free_irq(drv_data->irq, drv_data);
977 reset_control_assert(drv_data->rstc);
978 clk_disable_unprepare(drv_data->reg_clk);
979 clk_disable_unprepare(drv_data->clk);
980
981 return 0;
982}
983
984#ifdef CONFIG_PM
985static int mv64xxx_i2c_resume(struct device *dev)
986{
987 struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev);
988
989 mv64xxx_i2c_hw_init(drv_data);
990
991 return 0;
992}
993
994static const struct dev_pm_ops mv64xxx_i2c_pm = {
995 .resume = mv64xxx_i2c_resume,
996};
997
998#define mv64xxx_i2c_pm_ops (&mv64xxx_i2c_pm)
999#else
1000#define mv64xxx_i2c_pm_ops NULL
1001#endif
1002
1003static struct platform_driver mv64xxx_i2c_driver = {
1004 .probe = mv64xxx_i2c_probe,
1005 .remove = mv64xxx_i2c_remove,
1006 .driver = {
1007 .name = MV64XXX_I2C_CTLR_NAME,
1008 .pm = mv64xxx_i2c_pm_ops,
1009 .of_match_table = mv64xxx_i2c_of_match_table,
1010 },
1011};
1012
1013module_platform_driver(mv64xxx_i2c_driver);
1014
1015MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
1016MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
1017MODULE_LICENSE("GPL");
1018
