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17#include <linux/module.h>
18#include <linux/stringify.h>
19#include <linux/delay.h>
20#include <linux/kthread.h>
21#include <linux/slab.h>
22#include <media/v4l2-dev.h>
23#include <media/v4l2-ioctl.h>
24#include <media/v4l2-common.h>
25#include <media/videobuf2-dma-contig.h>
26
27#include "dt3155.h"
28
29#define DT3155_DEVICE_ID 0x1223
30
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41
42
43
44static int read_i2c_reg(void __iomem *addr, u8 index, u8 *data)
45{
46 u32 tmp = index;
47
48 iowrite32((tmp << 17) | IIC_READ, addr + IIC_CSR2);
49 udelay(45);
50 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
51 return -EIO;
52 tmp = ioread32(addr + IIC_CSR1);
53 if (tmp & DIRECT_ABORT) {
54
55 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
56 return -EIO;
57 }
58 *data = tmp >> 24;
59 return 0;
60}
61
62
63
64
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71
72
73
74static int write_i2c_reg(void __iomem *addr, u8 index, u8 data)
75{
76 u32 tmp = index;
77
78 iowrite32((tmp << 17) | IIC_WRITE | data, addr + IIC_CSR2);
79 udelay(65);
80 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
81 return -EIO;
82 if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
83
84 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
85 return -EIO;
86 }
87 return 0;
88}
89
90
91
92
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94
95
96
97
98
99
100static void write_i2c_reg_nowait(void __iomem *addr, u8 index, u8 data)
101{
102 u32 tmp = index;
103
104 iowrite32((tmp << 17) | IIC_WRITE | data, addr + IIC_CSR2);
105}
106
107
108
109
110
111
112
113
114
115
116static int wait_i2c_reg(void __iomem *addr)
117{
118 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
119 udelay(65);
120 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
121 return -EIO;
122 if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
123
124 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
125 return -EIO;
126 }
127 return 0;
128}
129
130static int
131dt3155_queue_setup(struct vb2_queue *vq,
132 unsigned int *nbuffers, unsigned int *num_planes,
133 unsigned int sizes[], struct device *alloc_devs[])
134
135{
136 struct dt3155_priv *pd = vb2_get_drv_priv(vq);
137 unsigned size = pd->width * pd->height;
138
139 if (vq->num_buffers + *nbuffers < 2)
140 *nbuffers = 2 - vq->num_buffers;
141 if (*num_planes)
142 return sizes[0] < size ? -EINVAL : 0;
143 *num_planes = 1;
144 sizes[0] = size;
145 return 0;
146}
147
148static int dt3155_buf_prepare(struct vb2_buffer *vb)
149{
150 struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue);
151
152 vb2_set_plane_payload(vb, 0, pd->width * pd->height);
153 return 0;
154}
155
156static int dt3155_start_streaming(struct vb2_queue *q, unsigned count)
157{
158 struct dt3155_priv *pd = vb2_get_drv_priv(q);
159 struct vb2_buffer *vb = &pd->curr_buf->vb2_buf;
160 dma_addr_t dma_addr;
161
162 pd->sequence = 0;
163 dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
164 iowrite32(dma_addr, pd->regs + EVEN_DMA_START);
165 iowrite32(dma_addr + pd->width, pd->regs + ODD_DMA_START);
166 iowrite32(pd->width, pd->regs + EVEN_DMA_STRIDE);
167 iowrite32(pd->width, pd->regs + ODD_DMA_STRIDE);
168
169 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
170 FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
171 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
172 FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD,
173 pd->regs + CSR1);
174 wait_i2c_reg(pd->regs);
175 write_i2c_reg(pd->regs, CONFIG, pd->config);
176 write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE);
177 write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE);
178
179
180 write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD);
181 return 0;
182}
183
184static void dt3155_stop_streaming(struct vb2_queue *q)
185{
186 struct dt3155_priv *pd = vb2_get_drv_priv(q);
187 struct vb2_buffer *vb;
188
189 spin_lock_irq(&pd->lock);
190
191 write_i2c_reg_nowait(pd->regs, CSR2, pd->csr2);
192 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
193 FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1);
194
195 iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
196 spin_unlock_irq(&pd->lock);
197
198
199
200
201
202
203 msleep(45);
204
205 spin_lock_irq(&pd->lock);
206 if (pd->curr_buf) {
207 vb2_buffer_done(&pd->curr_buf->vb2_buf, VB2_BUF_STATE_ERROR);
208 pd->curr_buf = NULL;
209 }
210
211 while (!list_empty(&pd->dmaq)) {
212 vb = list_first_entry(&pd->dmaq, typeof(*vb), done_entry);
213 list_del(&vb->done_entry);
214 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
215 }
216 spin_unlock_irq(&pd->lock);
217}
218
219static void dt3155_buf_queue(struct vb2_buffer *vb)
220{
221 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
222 struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue);
223
224
225 spin_lock_irq(&pd->lock);
226 if (pd->curr_buf)
227 list_add_tail(&vb->done_entry, &pd->dmaq);
228 else
229 pd->curr_buf = vbuf;
230 spin_unlock_irq(&pd->lock);
231}
232
233static const struct vb2_ops q_ops = {
234 .queue_setup = dt3155_queue_setup,
235 .wait_prepare = vb2_ops_wait_prepare,
236 .wait_finish = vb2_ops_wait_finish,
237 .buf_prepare = dt3155_buf_prepare,
238 .start_streaming = dt3155_start_streaming,
239 .stop_streaming = dt3155_stop_streaming,
240 .buf_queue = dt3155_buf_queue,
241};
242
243static irqreturn_t dt3155_irq_handler_even(int irq, void *dev_id)
244{
245 struct dt3155_priv *ipd = dev_id;
246 struct vb2_buffer *ivb;
247 dma_addr_t dma_addr;
248 u32 tmp;
249
250 tmp = ioread32(ipd->regs + INT_CSR) & (FLD_START | FLD_END_ODD);
251 if (!tmp)
252 return IRQ_NONE;
253 if ((tmp & FLD_START) && !(tmp & FLD_END_ODD)) {
254 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START,
255 ipd->regs + INT_CSR);
256 return IRQ_HANDLED;
257 }
258 tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD);
259 if (tmp) {
260 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
261 FLD_DN_ODD | FLD_DN_EVEN |
262 CAP_CONT_EVEN | CAP_CONT_ODD,
263 ipd->regs + CSR1);
264 }
265
266 spin_lock(&ipd->lock);
267 if (ipd->curr_buf && !list_empty(&ipd->dmaq)) {
268 ipd->curr_buf->vb2_buf.timestamp = ktime_get_ns();
269 ipd->curr_buf->sequence = ipd->sequence++;
270 ipd->curr_buf->field = V4L2_FIELD_NONE;
271 vb2_buffer_done(&ipd->curr_buf->vb2_buf, VB2_BUF_STATE_DONE);
272
273 ivb = list_first_entry(&ipd->dmaq, typeof(*ivb), done_entry);
274 list_del(&ivb->done_entry);
275 ipd->curr_buf = to_vb2_v4l2_buffer(ivb);
276 dma_addr = vb2_dma_contig_plane_dma_addr(ivb, 0);
277 iowrite32(dma_addr, ipd->regs + EVEN_DMA_START);
278 iowrite32(dma_addr + ipd->width, ipd->regs + ODD_DMA_START);
279 iowrite32(ipd->width, ipd->regs + EVEN_DMA_STRIDE);
280 iowrite32(ipd->width, ipd->regs + ODD_DMA_STRIDE);
281 }
282
283
284 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
285 FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR);
286 spin_unlock(&ipd->lock);
287 return IRQ_HANDLED;
288}
289
290static const struct v4l2_file_operations dt3155_fops = {
291 .owner = THIS_MODULE,
292 .open = v4l2_fh_open,
293 .release = vb2_fop_release,
294 .unlocked_ioctl = video_ioctl2,
295 .read = vb2_fop_read,
296 .mmap = vb2_fop_mmap,
297 .poll = vb2_fop_poll
298};
299
300static int dt3155_querycap(struct file *filp, void *p,
301 struct v4l2_capability *cap)
302{
303 struct dt3155_priv *pd = video_drvdata(filp);
304
305 strcpy(cap->driver, DT3155_NAME);
306 strcpy(cap->card, DT3155_NAME " frame grabber");
307 sprintf(cap->bus_info, "PCI:%s", pci_name(pd->pdev));
308 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE |
309 V4L2_CAP_STREAMING | V4L2_CAP_READWRITE;
310 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
311 return 0;
312}
313
314static int dt3155_enum_fmt_vid_cap(struct file *filp,
315 void *p, struct v4l2_fmtdesc *f)
316{
317 if (f->index)
318 return -EINVAL;
319 f->pixelformat = V4L2_PIX_FMT_GREY;
320 strcpy(f->description, "8-bit Greyscale");
321 return 0;
322}
323
324static int dt3155_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
325{
326 struct dt3155_priv *pd = video_drvdata(filp);
327
328 f->fmt.pix.width = pd->width;
329 f->fmt.pix.height = pd->height;
330 f->fmt.pix.pixelformat = V4L2_PIX_FMT_GREY;
331 f->fmt.pix.field = V4L2_FIELD_NONE;
332 f->fmt.pix.bytesperline = f->fmt.pix.width;
333 f->fmt.pix.sizeimage = f->fmt.pix.width * f->fmt.pix.height;
334 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
335 return 0;
336}
337
338static int dt3155_g_std(struct file *filp, void *p, v4l2_std_id *norm)
339{
340 struct dt3155_priv *pd = video_drvdata(filp);
341
342 *norm = pd->std;
343 return 0;
344}
345
346static int dt3155_s_std(struct file *filp, void *p, v4l2_std_id norm)
347{
348 struct dt3155_priv *pd = video_drvdata(filp);
349
350 if (pd->std == norm)
351 return 0;
352 if (vb2_is_busy(&pd->vidq))
353 return -EBUSY;
354 pd->std = norm;
355 if (pd->std & V4L2_STD_525_60) {
356 pd->csr2 = VT_60HZ;
357 pd->width = 640;
358 pd->height = 480;
359 } else {
360 pd->csr2 = VT_50HZ;
361 pd->width = 768;
362 pd->height = 576;
363 }
364 return 0;
365}
366
367static int dt3155_enum_input(struct file *filp, void *p,
368 struct v4l2_input *input)
369{
370 if (input->index > 3)
371 return -EINVAL;
372 if (input->index)
373 snprintf(input->name, sizeof(input->name), "VID%d",
374 input->index);
375 else
376 strscpy(input->name, "J2/VID0", sizeof(input->name));
377 input->type = V4L2_INPUT_TYPE_CAMERA;
378 input->std = V4L2_STD_ALL;
379 input->status = 0;
380 return 0;
381}
382
383static int dt3155_g_input(struct file *filp, void *p, unsigned int *i)
384{
385 struct dt3155_priv *pd = video_drvdata(filp);
386
387 *i = pd->input;
388 return 0;
389}
390
391static int dt3155_s_input(struct file *filp, void *p, unsigned int i)
392{
393 struct dt3155_priv *pd = video_drvdata(filp);
394
395 if (i > 3)
396 return -EINVAL;
397 pd->input = i;
398 write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
399 write_i2c_reg(pd->regs, AD_CMD, (i << 6) | (i << 4) | SYNC_LVL_3);
400 return 0;
401}
402
403static const struct v4l2_ioctl_ops dt3155_ioctl_ops = {
404 .vidioc_querycap = dt3155_querycap,
405 .vidioc_enum_fmt_vid_cap = dt3155_enum_fmt_vid_cap,
406 .vidioc_try_fmt_vid_cap = dt3155_fmt_vid_cap,
407 .vidioc_g_fmt_vid_cap = dt3155_fmt_vid_cap,
408 .vidioc_s_fmt_vid_cap = dt3155_fmt_vid_cap,
409 .vidioc_reqbufs = vb2_ioctl_reqbufs,
410 .vidioc_create_bufs = vb2_ioctl_create_bufs,
411 .vidioc_querybuf = vb2_ioctl_querybuf,
412 .vidioc_expbuf = vb2_ioctl_expbuf,
413 .vidioc_qbuf = vb2_ioctl_qbuf,
414 .vidioc_dqbuf = vb2_ioctl_dqbuf,
415 .vidioc_streamon = vb2_ioctl_streamon,
416 .vidioc_streamoff = vb2_ioctl_streamoff,
417 .vidioc_g_std = dt3155_g_std,
418 .vidioc_s_std = dt3155_s_std,
419 .vidioc_enum_input = dt3155_enum_input,
420 .vidioc_g_input = dt3155_g_input,
421 .vidioc_s_input = dt3155_s_input,
422};
423
424static int dt3155_init_board(struct dt3155_priv *pd)
425{
426 struct pci_dev *pdev = pd->pdev;
427 int i;
428 u8 tmp = 0;
429
430 pci_set_master(pdev);
431
432
433 iowrite32(ADDR_ERR_ODD | ADDR_ERR_EVEN | FLD_CRPT_ODD | FLD_CRPT_EVEN |
434 FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1);
435 msleep(20);
436
437
438 iowrite32(FIFO_EN | SRST, pd->regs + CSR1);
439 iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT);
440 iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT);
441 iowrite32(0x00000020, pd->regs + FIFO_TRIGER);
442 iowrite32(0x00000103, pd->regs + XFER_MODE);
443 iowrite32(0, pd->regs + RETRY_WAIT_CNT);
444 iowrite32(0, pd->regs + INT_CSR);
445 iowrite32(1, pd->regs + EVEN_FLD_MASK);
446 iowrite32(1, pd->regs + ODD_FLD_MASK);
447 iowrite32(0, pd->regs + MASK_LENGTH);
448 iowrite32(0x0005007C, pd->regs + FIFO_FLAG_CNT);
449 iowrite32(0x01010101, pd->regs + IIC_CLK_DUR);
450
451
452 read_i2c_reg(pd->regs, DT_ID, &tmp);
453 if (tmp != DT3155_ID)
454 return -ENODEV;
455
456
457 write_i2c_reg(pd->regs, AD_ADDR, 0);
458 for (i = 0; i < 256; i++)
459 write_i2c_reg(pd->regs, AD_LUT, i);
460
461
462
463 write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
464 write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
465 write_i2c_reg(pd->regs, AD_ADDR, AD_POS_REF);
466 write_i2c_reg(pd->regs, AD_CMD, 34);
467 write_i2c_reg(pd->regs, AD_ADDR, AD_NEG_REF);
468 write_i2c_reg(pd->regs, AD_CMD, 0);
469
470
471 write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM);
472 for (i = 0; i < 256; i++) {
473 write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
474 write_i2c_reg(pd->regs, PM_LUT_DATA, i);
475 }
476 write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM | PM_LUT_SEL);
477 for (i = 0; i < 256; i++) {
478 write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
479 write_i2c_reg(pd->regs, PM_LUT_DATA, i);
480 }
481 write_i2c_reg(pd->regs, CONFIG, pd->config);
482
483
484 write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
485 write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
486
487
488 iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD,
489 pd->regs + INT_CSR);
490
491 return 0;
492}
493
494static const struct video_device dt3155_vdev = {
495 .name = DT3155_NAME,
496 .fops = &dt3155_fops,
497 .ioctl_ops = &dt3155_ioctl_ops,
498 .minor = -1,
499 .release = video_device_release_empty,
500 .tvnorms = V4L2_STD_ALL,
501};
502
503static int dt3155_probe(struct pci_dev *pdev, const struct pci_device_id *id)
504{
505 int err;
506 struct dt3155_priv *pd;
507
508 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
509 if (err)
510 return -ENODEV;
511 pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
512 if (!pd)
513 return -ENOMEM;
514
515 err = v4l2_device_register(&pdev->dev, &pd->v4l2_dev);
516 if (err)
517 return err;
518 pd->vdev = dt3155_vdev;
519 pd->vdev.v4l2_dev = &pd->v4l2_dev;
520 video_set_drvdata(&pd->vdev, pd);
521 pd->pdev = pdev;
522 pd->std = V4L2_STD_625_50;
523 pd->csr2 = VT_50HZ;
524 pd->width = 768;
525 pd->height = 576;
526 INIT_LIST_HEAD(&pd->dmaq);
527 mutex_init(&pd->mux);
528 pd->vdev.lock = &pd->mux;
529 pd->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
530 pd->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
531 pd->vidq.io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
532 pd->vidq.ops = &q_ops;
533 pd->vidq.mem_ops = &vb2_dma_contig_memops;
534 pd->vidq.drv_priv = pd;
535 pd->vidq.min_buffers_needed = 2;
536 pd->vidq.gfp_flags = GFP_DMA32;
537 pd->vidq.lock = &pd->mux;
538 pd->vidq.dev = &pdev->dev;
539 pd->vdev.queue = &pd->vidq;
540 err = vb2_queue_init(&pd->vidq);
541 if (err < 0)
542 goto err_v4l2_dev_unreg;
543 spin_lock_init(&pd->lock);
544 pd->config = ACQ_MODE_EVEN;
545 err = pci_enable_device(pdev);
546 if (err)
547 goto err_v4l2_dev_unreg;
548 err = pci_request_region(pdev, 0, pci_name(pdev));
549 if (err)
550 goto err_pci_disable;
551 pd->regs = pci_iomap(pdev, 0, pci_resource_len(pd->pdev, 0));
552 if (!pd->regs) {
553 err = -ENOMEM;
554 goto err_free_reg;
555 }
556 err = dt3155_init_board(pd);
557 if (err)
558 goto err_iounmap;
559 err = request_irq(pd->pdev->irq, dt3155_irq_handler_even,
560 IRQF_SHARED, DT3155_NAME, pd);
561 if (err)
562 goto err_iounmap;
563 err = video_register_device(&pd->vdev, VFL_TYPE_GRABBER, -1);
564 if (err)
565 goto err_free_irq;
566 dev_info(&pdev->dev, "/dev/video%i is ready\n", pd->vdev.minor);
567 return 0;
568
569err_free_irq:
570 free_irq(pd->pdev->irq, pd);
571err_iounmap:
572 pci_iounmap(pdev, pd->regs);
573err_free_reg:
574 pci_release_region(pdev, 0);
575err_pci_disable:
576 pci_disable_device(pdev);
577err_v4l2_dev_unreg:
578 v4l2_device_unregister(&pd->v4l2_dev);
579 return err;
580}
581
582static void dt3155_remove(struct pci_dev *pdev)
583{
584 struct v4l2_device *v4l2_dev = pci_get_drvdata(pdev);
585 struct dt3155_priv *pd = container_of(v4l2_dev, struct dt3155_priv,
586 v4l2_dev);
587
588 video_unregister_device(&pd->vdev);
589 free_irq(pd->pdev->irq, pd);
590 vb2_queue_release(&pd->vidq);
591 v4l2_device_unregister(&pd->v4l2_dev);
592 pci_iounmap(pdev, pd->regs);
593 pci_release_region(pdev, 0);
594 pci_disable_device(pdev);
595}
596
597static const struct pci_device_id pci_ids[] = {
598 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, DT3155_DEVICE_ID) },
599 { 0, },
600};
601MODULE_DEVICE_TABLE(pci, pci_ids);
602
603static struct pci_driver pci_driver = {
604 .name = DT3155_NAME,
605 .id_table = pci_ids,
606 .probe = dt3155_probe,
607 .remove = dt3155_remove,
608};
609
610module_pci_driver(pci_driver);
611
612MODULE_DESCRIPTION("video4linux pci-driver for dt3155 frame grabber");
613MODULE_AUTHOR("Marin Mitov <mitov@issp.bas.bg>");
614MODULE_VERSION(DT3155_VERSION);
615MODULE_LICENSE("GPL");
616