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7#include "qede_ptp.h"
8#define QEDE_PTP_TX_TIMEOUT (2 * HZ)
9
10struct qede_ptp {
11 const struct qed_eth_ptp_ops *ops;
12 struct ptp_clock_info clock_info;
13 struct cyclecounter cc;
14 struct timecounter tc;
15 struct ptp_clock *clock;
16 struct work_struct work;
17 unsigned long ptp_tx_start;
18 struct qede_dev *edev;
19 struct sk_buff *tx_skb;
20
21
22
23
24 spinlock_t lock;
25 bool hw_ts_ioctl_called;
26 u16 tx_type;
27 u16 rx_filter;
28};
29
30
31
32
33
34
35
36
37
38static int qede_ptp_adjfreq(struct ptp_clock_info *info, s32 ppb)
39{
40 struct qede_ptp *ptp = container_of(info, struct qede_ptp, clock_info);
41 struct qede_dev *edev = ptp->edev;
42 int rc;
43
44 __qede_lock(edev);
45 if (edev->state == QEDE_STATE_OPEN) {
46 spin_lock_bh(&ptp->lock);
47 rc = ptp->ops->adjfreq(edev->cdev, ppb);
48 spin_unlock_bh(&ptp->lock);
49 } else {
50 DP_ERR(edev, "PTP adjfreq called while interface is down\n");
51 rc = -EFAULT;
52 }
53 __qede_unlock(edev);
54
55 return rc;
56}
57
58static int qede_ptp_adjtime(struct ptp_clock_info *info, s64 delta)
59{
60 struct qede_dev *edev;
61 struct qede_ptp *ptp;
62
63 ptp = container_of(info, struct qede_ptp, clock_info);
64 edev = ptp->edev;
65
66 DP_VERBOSE(edev, QED_MSG_DEBUG, "PTP adjtime called, delta = %llx\n",
67 delta);
68
69 spin_lock_bh(&ptp->lock);
70 timecounter_adjtime(&ptp->tc, delta);
71 spin_unlock_bh(&ptp->lock);
72
73 return 0;
74}
75
76static int qede_ptp_gettime(struct ptp_clock_info *info, struct timespec64 *ts)
77{
78 struct qede_dev *edev;
79 struct qede_ptp *ptp;
80 u64 ns;
81
82 ptp = container_of(info, struct qede_ptp, clock_info);
83 edev = ptp->edev;
84
85 spin_lock_bh(&ptp->lock);
86 ns = timecounter_read(&ptp->tc);
87 spin_unlock_bh(&ptp->lock);
88
89 DP_VERBOSE(edev, QED_MSG_DEBUG, "PTP gettime called, ns = %llu\n", ns);
90
91 *ts = ns_to_timespec64(ns);
92
93 return 0;
94}
95
96static int qede_ptp_settime(struct ptp_clock_info *info,
97 const struct timespec64 *ts)
98{
99 struct qede_dev *edev;
100 struct qede_ptp *ptp;
101 u64 ns;
102
103 ptp = container_of(info, struct qede_ptp, clock_info);
104 edev = ptp->edev;
105
106 ns = timespec64_to_ns(ts);
107
108 DP_VERBOSE(edev, QED_MSG_DEBUG, "PTP settime called, ns = %llu\n", ns);
109
110
111 spin_lock_bh(&ptp->lock);
112 timecounter_init(&ptp->tc, &ptp->cc, ns);
113 spin_unlock_bh(&ptp->lock);
114
115 return 0;
116}
117
118
119static int qede_ptp_ancillary_feature_enable(struct ptp_clock_info *info,
120 struct ptp_clock_request *rq,
121 int on)
122{
123 struct qede_dev *edev;
124 struct qede_ptp *ptp;
125
126 ptp = container_of(info, struct qede_ptp, clock_info);
127 edev = ptp->edev;
128
129 DP_ERR(edev, "PHC ancillary features are not supported\n");
130
131 return -ENOTSUPP;
132}
133
134static void qede_ptp_task(struct work_struct *work)
135{
136 struct skb_shared_hwtstamps shhwtstamps;
137 struct qede_dev *edev;
138 struct qede_ptp *ptp;
139 u64 timestamp, ns;
140 bool timedout;
141 int rc;
142
143 ptp = container_of(work, struct qede_ptp, work);
144 edev = ptp->edev;
145 timedout = time_is_before_jiffies(ptp->ptp_tx_start +
146 QEDE_PTP_TX_TIMEOUT);
147
148
149 spin_lock_bh(&ptp->lock);
150 rc = ptp->ops->read_tx_ts(edev->cdev, ×tamp);
151 spin_unlock_bh(&ptp->lock);
152 if (rc) {
153 if (unlikely(timedout)) {
154 DP_INFO(edev, "Tx timestamp is not recorded\n");
155 dev_kfree_skb_any(ptp->tx_skb);
156 ptp->tx_skb = NULL;
157 clear_bit_unlock(QEDE_FLAGS_PTP_TX_IN_PRORGESS,
158 &edev->flags);
159 edev->ptp_skip_txts++;
160 } else {
161
162 schedule_work(&ptp->work);
163 }
164 return;
165 }
166
167 ns = timecounter_cyc2time(&ptp->tc, timestamp);
168 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
169 shhwtstamps.hwtstamp = ns_to_ktime(ns);
170 skb_tstamp_tx(ptp->tx_skb, &shhwtstamps);
171 dev_kfree_skb_any(ptp->tx_skb);
172 ptp->tx_skb = NULL;
173 clear_bit_unlock(QEDE_FLAGS_PTP_TX_IN_PRORGESS, &edev->flags);
174
175 DP_VERBOSE(edev, QED_MSG_DEBUG,
176 "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
177 timestamp, ns);
178}
179
180
181static u64 qede_ptp_read_cc(const struct cyclecounter *cc)
182{
183 struct qede_dev *edev;
184 struct qede_ptp *ptp;
185 u64 phc_cycles;
186 int rc;
187
188 ptp = container_of(cc, struct qede_ptp, cc);
189 edev = ptp->edev;
190 rc = ptp->ops->read_cc(edev->cdev, &phc_cycles);
191 if (rc)
192 WARN_ONCE(1, "PHC read err %d\n", rc);
193
194 DP_VERBOSE(edev, QED_MSG_DEBUG, "PHC read cycles = %llu\n", phc_cycles);
195
196 return phc_cycles;
197}
198
199static int qede_ptp_cfg_filters(struct qede_dev *edev)
200{
201 enum qed_ptp_hwtstamp_tx_type tx_type = QED_PTP_HWTSTAMP_TX_ON;
202 enum qed_ptp_filter_type rx_filter = QED_PTP_FILTER_NONE;
203 struct qede_ptp *ptp = edev->ptp;
204
205 if (!ptp)
206 return -EIO;
207
208 if (!ptp->hw_ts_ioctl_called) {
209 DP_INFO(edev, "TS IOCTL not called\n");
210 return 0;
211 }
212
213 switch (ptp->tx_type) {
214 case HWTSTAMP_TX_ON:
215 set_bit(QEDE_FLAGS_TX_TIMESTAMPING_EN, &edev->flags);
216 tx_type = QED_PTP_HWTSTAMP_TX_ON;
217 break;
218
219 case HWTSTAMP_TX_OFF:
220 clear_bit(QEDE_FLAGS_TX_TIMESTAMPING_EN, &edev->flags);
221 tx_type = QED_PTP_HWTSTAMP_TX_OFF;
222 break;
223
224 case HWTSTAMP_TX_ONESTEP_SYNC:
225 DP_ERR(edev, "One-step timestamping is not supported\n");
226 return -ERANGE;
227 }
228
229 spin_lock_bh(&ptp->lock);
230 switch (ptp->rx_filter) {
231 case HWTSTAMP_FILTER_NONE:
232 rx_filter = QED_PTP_FILTER_NONE;
233 break;
234 case HWTSTAMP_FILTER_ALL:
235 case HWTSTAMP_FILTER_SOME:
236 case HWTSTAMP_FILTER_NTP_ALL:
237 ptp->rx_filter = HWTSTAMP_FILTER_NONE;
238 rx_filter = QED_PTP_FILTER_ALL;
239 break;
240 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
241 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
242 rx_filter = QED_PTP_FILTER_V1_L4_EVENT;
243 break;
244 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
245 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
246 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
247
248 rx_filter = QED_PTP_FILTER_V1_L4_GEN;
249 break;
250 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
251 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
252 rx_filter = QED_PTP_FILTER_V2_L4_EVENT;
253 break;
254 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
255 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
256 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
257
258 rx_filter = QED_PTP_FILTER_V2_L4_GEN;
259 break;
260 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
261 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
262 rx_filter = QED_PTP_FILTER_V2_L2_EVENT;
263 break;
264 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
265 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
266 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
267
268 rx_filter = QED_PTP_FILTER_V2_L2_GEN;
269 break;
270 case HWTSTAMP_FILTER_PTP_V2_EVENT:
271 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
272 rx_filter = QED_PTP_FILTER_V2_EVENT;
273 break;
274 case HWTSTAMP_FILTER_PTP_V2_SYNC:
275 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
276 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
277
278 rx_filter = QED_PTP_FILTER_V2_GEN;
279 break;
280 }
281
282 ptp->ops->cfg_filters(edev->cdev, rx_filter, tx_type);
283
284 spin_unlock_bh(&ptp->lock);
285
286 return 0;
287}
288
289int qede_ptp_hw_ts(struct qede_dev *edev, struct ifreq *ifr)
290{
291 struct hwtstamp_config config;
292 struct qede_ptp *ptp;
293 int rc;
294
295 ptp = edev->ptp;
296 if (!ptp)
297 return -EIO;
298
299 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
300 return -EFAULT;
301
302 DP_VERBOSE(edev, QED_MSG_DEBUG,
303 "HWTSTAMP IOCTL: Requested tx_type = %d, requested rx_filters = %d\n",
304 config.tx_type, config.rx_filter);
305
306 if (config.flags) {
307 DP_ERR(edev, "config.flags is reserved for future use\n");
308 return -EINVAL;
309 }
310
311 ptp->hw_ts_ioctl_called = 1;
312 ptp->tx_type = config.tx_type;
313 ptp->rx_filter = config.rx_filter;
314
315 rc = qede_ptp_cfg_filters(edev);
316 if (rc)
317 return rc;
318
319 config.rx_filter = ptp->rx_filter;
320
321 return copy_to_user(ifr->ifr_data, &config,
322 sizeof(config)) ? -EFAULT : 0;
323}
324
325int qede_ptp_get_ts_info(struct qede_dev *edev, struct ethtool_ts_info *info)
326{
327 struct qede_ptp *ptp = edev->ptp;
328
329 if (!ptp) {
330 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
331 SOF_TIMESTAMPING_RX_SOFTWARE |
332 SOF_TIMESTAMPING_SOFTWARE;
333 info->phc_index = -1;
334
335 return 0;
336 }
337
338 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
339 SOF_TIMESTAMPING_RX_SOFTWARE |
340 SOF_TIMESTAMPING_SOFTWARE |
341 SOF_TIMESTAMPING_TX_HARDWARE |
342 SOF_TIMESTAMPING_RX_HARDWARE |
343 SOF_TIMESTAMPING_RAW_HARDWARE;
344
345 if (ptp->clock)
346 info->phc_index = ptp_clock_index(ptp->clock);
347 else
348 info->phc_index = -1;
349
350 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
351 BIT(HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
352 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
353 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
354 BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
355 BIT(HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
356 BIT(HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
357 BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
358 BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
359 BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
360 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) |
361 BIT(HWTSTAMP_FILTER_PTP_V2_SYNC) |
362 BIT(HWTSTAMP_FILTER_PTP_V2_DELAY_REQ);
363
364 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON);
365
366 return 0;
367}
368
369void qede_ptp_disable(struct qede_dev *edev)
370{
371 struct qede_ptp *ptp;
372
373 ptp = edev->ptp;
374 if (!ptp)
375 return;
376
377 if (ptp->clock) {
378 ptp_clock_unregister(ptp->clock);
379 ptp->clock = NULL;
380 }
381
382
383
384
385 cancel_work_sync(&ptp->work);
386 if (ptp->tx_skb) {
387 dev_kfree_skb_any(ptp->tx_skb);
388 ptp->tx_skb = NULL;
389 clear_bit_unlock(QEDE_FLAGS_PTP_TX_IN_PRORGESS, &edev->flags);
390 }
391
392
393 spin_lock_bh(&ptp->lock);
394 ptp->ops->disable(edev->cdev);
395 spin_unlock_bh(&ptp->lock);
396
397 kfree(ptp);
398 edev->ptp = NULL;
399}
400
401static int qede_ptp_init(struct qede_dev *edev)
402{
403 struct qede_ptp *ptp;
404 int rc;
405
406 ptp = edev->ptp;
407 if (!ptp)
408 return -EINVAL;
409
410 spin_lock_init(&ptp->lock);
411
412
413 rc = ptp->ops->enable(edev->cdev);
414 if (rc) {
415 DP_INFO(edev, "PTP HW enable failed\n");
416 return rc;
417 }
418
419
420 INIT_WORK(&ptp->work, qede_ptp_task);
421
422
423 memset(&ptp->cc, 0, sizeof(ptp->cc));
424 ptp->cc.read = qede_ptp_read_cc;
425 ptp->cc.mask = CYCLECOUNTER_MASK(64);
426 ptp->cc.shift = 0;
427 ptp->cc.mult = 1;
428
429 timecounter_init(&ptp->tc, &ptp->cc, ktime_to_ns(ktime_get_real()));
430
431 return 0;
432}
433
434int qede_ptp_enable(struct qede_dev *edev)
435{
436 struct qede_ptp *ptp;
437 int rc;
438
439 ptp = kzalloc(sizeof(*ptp), GFP_KERNEL);
440 if (!ptp) {
441 DP_INFO(edev, "Failed to allocate struct for PTP\n");
442 return -ENOMEM;
443 }
444
445 ptp->edev = edev;
446 ptp->ops = edev->ops->ptp;
447 if (!ptp->ops) {
448 DP_INFO(edev, "PTP enable failed\n");
449 rc = -EIO;
450 goto err1;
451 }
452
453 edev->ptp = ptp;
454
455 rc = qede_ptp_init(edev);
456 if (rc)
457 goto err1;
458
459 qede_ptp_cfg_filters(edev);
460
461
462 ptp->clock_info.owner = THIS_MODULE;
463 snprintf(ptp->clock_info.name, 16, "%s", edev->ndev->name);
464 ptp->clock_info.max_adj = QED_MAX_PHC_DRIFT_PPB;
465 ptp->clock_info.n_alarm = 0;
466 ptp->clock_info.n_ext_ts = 0;
467 ptp->clock_info.n_per_out = 0;
468 ptp->clock_info.pps = 0;
469 ptp->clock_info.adjfreq = qede_ptp_adjfreq;
470 ptp->clock_info.adjtime = qede_ptp_adjtime;
471 ptp->clock_info.gettime64 = qede_ptp_gettime;
472 ptp->clock_info.settime64 = qede_ptp_settime;
473 ptp->clock_info.enable = qede_ptp_ancillary_feature_enable;
474
475 ptp->clock = ptp_clock_register(&ptp->clock_info, &edev->pdev->dev);
476 if (IS_ERR(ptp->clock)) {
477 DP_ERR(edev, "PTP clock registration failed\n");
478 qede_ptp_disable(edev);
479 rc = -EINVAL;
480 goto err2;
481 }
482
483 return 0;
484
485err1:
486 kfree(ptp);
487err2:
488 edev->ptp = NULL;
489
490 return rc;
491}
492
493void qede_ptp_tx_ts(struct qede_dev *edev, struct sk_buff *skb)
494{
495 struct qede_ptp *ptp;
496
497 ptp = edev->ptp;
498 if (!ptp)
499 return;
500
501 if (test_and_set_bit_lock(QEDE_FLAGS_PTP_TX_IN_PRORGESS,
502 &edev->flags)) {
503 DP_ERR(edev, "Timestamping in progress\n");
504 edev->ptp_skip_txts++;
505 return;
506 }
507
508 if (unlikely(!test_bit(QEDE_FLAGS_TX_TIMESTAMPING_EN, &edev->flags))) {
509 DP_ERR(edev,
510 "Tx timestamping was not enabled, this packet will not be timestamped\n");
511 clear_bit_unlock(QEDE_FLAGS_PTP_TX_IN_PRORGESS, &edev->flags);
512 edev->ptp_skip_txts++;
513 } else if (unlikely(ptp->tx_skb)) {
514 DP_ERR(edev,
515 "The device supports only a single outstanding packet to timestamp, this packet will not be timestamped\n");
516 clear_bit_unlock(QEDE_FLAGS_PTP_TX_IN_PRORGESS, &edev->flags);
517 edev->ptp_skip_txts++;
518 } else {
519 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
520
521 ptp->tx_skb = skb_get(skb);
522 ptp->ptp_tx_start = jiffies;
523 schedule_work(&ptp->work);
524 }
525}
526
527void qede_ptp_rx_ts(struct qede_dev *edev, struct sk_buff *skb)
528{
529 struct qede_ptp *ptp;
530 u64 timestamp, ns;
531 int rc;
532
533 ptp = edev->ptp;
534 if (!ptp)
535 return;
536
537 spin_lock_bh(&ptp->lock);
538 rc = ptp->ops->read_rx_ts(edev->cdev, ×tamp);
539 if (rc) {
540 spin_unlock_bh(&ptp->lock);
541 DP_INFO(edev, "Invalid Rx timestamp\n");
542 return;
543 }
544
545 ns = timecounter_cyc2time(&ptp->tc, timestamp);
546 spin_unlock_bh(&ptp->lock);
547 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
548 DP_VERBOSE(edev, QED_MSG_DEBUG,
549 "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
550 timestamp, ns);
551}
552
