1
2
3
4
5
6#include <linux/delay.h>
7#include <linux/ethtool.h>
8#include <linux/ethtool_netlink.h>
9#include <linux/kernel.h>
10#include <linux/mdio.h>
11#include <linux/mii.h>
12#include <linux/module.h>
13#include <linux/phy.h>
14#include <linux/hwmon.h>
15#include <linux/bitfield.h>
16#include <linux/of_mdio.h>
17#include <linux/of_irq.h>
18
19#define PHY_ID_MASK 0xfffffff0
20#define PHY_ID_TJA1100 0x0180dc40
21#define PHY_ID_TJA1101 0x0180dd00
22#define PHY_ID_TJA1102 0x0180dc80
23
24#define MII_ECTRL 17
25#define MII_ECTRL_LINK_CONTROL BIT(15)
26#define MII_ECTRL_POWER_MODE_MASK GENMASK(14, 11)
27#define MII_ECTRL_POWER_MODE_NO_CHANGE (0x0 << 11)
28#define MII_ECTRL_POWER_MODE_NORMAL (0x3 << 11)
29#define MII_ECTRL_POWER_MODE_STANDBY (0xc << 11)
30#define MII_ECTRL_CABLE_TEST BIT(5)
31#define MII_ECTRL_CONFIG_EN BIT(2)
32#define MII_ECTRL_WAKE_REQUEST BIT(0)
33
34#define MII_CFG1 18
35#define MII_CFG1_MASTER_SLAVE BIT(15)
36#define MII_CFG1_AUTO_OP BIT(14)
37#define MII_CFG1_SLEEP_CONFIRM BIT(6)
38#define MII_CFG1_LED_MODE_MASK GENMASK(5, 4)
39#define MII_CFG1_LED_MODE_LINKUP 0
40#define MII_CFG1_LED_ENABLE BIT(3)
41
42#define MII_CFG2 19
43#define MII_CFG2_SLEEP_REQUEST_TO GENMASK(1, 0)
44#define MII_CFG2_SLEEP_REQUEST_TO_16MS 0x3
45
46#define MII_INTSRC 21
47#define MII_INTSRC_TEMP_ERR BIT(1)
48#define MII_INTSRC_UV_ERR BIT(3)
49
50#define MII_INTEN 22
51#define MII_INTEN_LINK_FAIL BIT(10)
52#define MII_INTEN_LINK_UP BIT(9)
53
54#define MII_COMMSTAT 23
55#define MII_COMMSTAT_LINK_UP BIT(15)
56#define MII_COMMSTAT_SQI_STATE GENMASK(7, 5)
57#define MII_COMMSTAT_SQI_MAX 7
58
59#define MII_GENSTAT 24
60#define MII_GENSTAT_PLL_LOCKED BIT(14)
61
62#define MII_EXTSTAT 25
63#define MII_EXTSTAT_SHORT_DETECT BIT(8)
64#define MII_EXTSTAT_OPEN_DETECT BIT(7)
65#define MII_EXTSTAT_POLARITY_DETECT BIT(6)
66
67#define MII_COMMCFG 27
68#define MII_COMMCFG_AUTO_OP BIT(15)
69
70struct tja11xx_priv {
71 char *hwmon_name;
72 struct device *hwmon_dev;
73 struct phy_device *phydev;
74 struct work_struct phy_register_work;
75};
76
77struct tja11xx_phy_stats {
78 const char *string;
79 u8 reg;
80 u8 off;
81 u16 mask;
82};
83
84static struct tja11xx_phy_stats tja11xx_hw_stats[] = {
85 { "phy_symbol_error_count", 20, 0, GENMASK(15, 0) },
86 { "phy_polarity_detect", 25, 6, BIT(6) },
87 { "phy_open_detect", 25, 7, BIT(7) },
88 { "phy_short_detect", 25, 8, BIT(8) },
89 { "phy_rem_rcvr_count", 26, 0, GENMASK(7, 0) },
90 { "phy_loc_rcvr_count", 26, 8, GENMASK(15, 8) },
91};
92
93static int tja11xx_check(struct phy_device *phydev, u8 reg, u16 mask, u16 set)
94{
95 int val;
96
97 return phy_read_poll_timeout(phydev, reg, val, (val & mask) == set,
98 150, 30000, false);
99}
100
101static int phy_modify_check(struct phy_device *phydev, u8 reg,
102 u16 mask, u16 set)
103{
104 int ret;
105
106 ret = phy_modify(phydev, reg, mask, set);
107 if (ret)
108 return ret;
109
110 return tja11xx_check(phydev, reg, mask, set);
111}
112
113static int tja11xx_enable_reg_write(struct phy_device *phydev)
114{
115 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CONFIG_EN);
116}
117
118static int tja11xx_enable_link_control(struct phy_device *phydev)
119{
120 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL);
121}
122
123static int tja11xx_disable_link_control(struct phy_device *phydev)
124{
125 return phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL);
126}
127
128static int tja11xx_wakeup(struct phy_device *phydev)
129{
130 int ret;
131
132 ret = phy_read(phydev, MII_ECTRL);
133 if (ret < 0)
134 return ret;
135
136 switch (ret & MII_ECTRL_POWER_MODE_MASK) {
137 case MII_ECTRL_POWER_MODE_NO_CHANGE:
138 break;
139 case MII_ECTRL_POWER_MODE_NORMAL:
140 ret = phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);
141 if (ret)
142 return ret;
143
144 ret = phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);
145 if (ret)
146 return ret;
147 break;
148 case MII_ECTRL_POWER_MODE_STANDBY:
149 ret = phy_modify_check(phydev, MII_ECTRL,
150 MII_ECTRL_POWER_MODE_MASK,
151 MII_ECTRL_POWER_MODE_STANDBY);
152 if (ret)
153 return ret;
154
155 ret = phy_modify(phydev, MII_ECTRL, MII_ECTRL_POWER_MODE_MASK,
156 MII_ECTRL_POWER_MODE_NORMAL);
157 if (ret)
158 return ret;
159
160 ret = phy_modify_check(phydev, MII_GENSTAT,
161 MII_GENSTAT_PLL_LOCKED,
162 MII_GENSTAT_PLL_LOCKED);
163 if (ret)
164 return ret;
165
166 return tja11xx_enable_link_control(phydev);
167 default:
168 break;
169 }
170
171 return 0;
172}
173
174static int tja11xx_soft_reset(struct phy_device *phydev)
175{
176 int ret;
177
178 ret = tja11xx_enable_reg_write(phydev);
179 if (ret)
180 return ret;
181
182 return genphy_soft_reset(phydev);
183}
184
185static int tja11xx_config_aneg_cable_test(struct phy_device *phydev)
186{
187 bool finished = false;
188 int ret;
189
190 if (phydev->link)
191 return 0;
192
193 if (!phydev->drv->cable_test_start ||
194 !phydev->drv->cable_test_get_status)
195 return 0;
196
197 ret = ethnl_cable_test_alloc(phydev, ETHTOOL_MSG_CABLE_TEST_NTF);
198 if (ret)
199 return ret;
200
201 ret = phydev->drv->cable_test_start(phydev);
202 if (ret)
203 return ret;
204
205
206 usleep_range(100, 200);
207
208 ret = phydev->drv->cable_test_get_status(phydev, &finished);
209 if (ret)
210 return ret;
211
212 if (finished)
213 ethnl_cable_test_finished(phydev);
214
215 return 0;
216}
217
218static int tja11xx_config_aneg(struct phy_device *phydev)
219{
220 int ret, changed = 0;
221 u16 ctl = 0;
222
223 switch (phydev->master_slave_set) {
224 case MASTER_SLAVE_CFG_MASTER_FORCE:
225 ctl |= MII_CFG1_MASTER_SLAVE;
226 break;
227 case MASTER_SLAVE_CFG_SLAVE_FORCE:
228 break;
229 case MASTER_SLAVE_CFG_UNKNOWN:
230 case MASTER_SLAVE_CFG_UNSUPPORTED:
231 goto do_test;
232 default:
233 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
234 return -ENOTSUPP;
235 }
236
237 changed = phy_modify_changed(phydev, MII_CFG1, MII_CFG1_MASTER_SLAVE, ctl);
238 if (changed < 0)
239 return changed;
240
241do_test:
242 ret = tja11xx_config_aneg_cable_test(phydev);
243 if (ret)
244 return ret;
245
246 return __genphy_config_aneg(phydev, changed);
247}
248
249static int tja11xx_config_init(struct phy_device *phydev)
250{
251 int ret;
252
253 ret = tja11xx_enable_reg_write(phydev);
254 if (ret)
255 return ret;
256
257 phydev->autoneg = AUTONEG_DISABLE;
258 phydev->speed = SPEED_100;
259 phydev->duplex = DUPLEX_FULL;
260
261 switch (phydev->phy_id & PHY_ID_MASK) {
262 case PHY_ID_TJA1100:
263 ret = phy_modify(phydev, MII_CFG1,
264 MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_MASK |
265 MII_CFG1_LED_ENABLE,
266 MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_LINKUP |
267 MII_CFG1_LED_ENABLE);
268 if (ret)
269 return ret;
270 break;
271 case PHY_ID_TJA1101:
272 case PHY_ID_TJA1102:
273 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
274 if (ret)
275 return ret;
276 break;
277 default:
278 return -EINVAL;
279 }
280
281 ret = phy_clear_bits(phydev, MII_CFG1, MII_CFG1_SLEEP_CONFIRM);
282 if (ret)
283 return ret;
284
285 ret = phy_modify(phydev, MII_CFG2, MII_CFG2_SLEEP_REQUEST_TO,
286 MII_CFG2_SLEEP_REQUEST_TO_16MS);
287 if (ret)
288 return ret;
289
290 ret = tja11xx_wakeup(phydev);
291 if (ret < 0)
292 return ret;
293
294
295 ret = phy_read(phydev, MII_INTSRC);
296 if (ret < 0)
297 return ret;
298
299 return 0;
300}
301
302static int tja11xx_read_status(struct phy_device *phydev)
303{
304 int ret;
305
306 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
307 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
308
309 ret = genphy_update_link(phydev);
310 if (ret)
311 return ret;
312
313 ret = phy_read(phydev, MII_CFG1);
314 if (ret < 0)
315 return ret;
316
317 if (ret & MII_CFG1_MASTER_SLAVE)
318 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
319 else
320 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
321
322 if (phydev->link) {
323 ret = phy_read(phydev, MII_COMMSTAT);
324 if (ret < 0)
325 return ret;
326
327 if (!(ret & MII_COMMSTAT_LINK_UP))
328 phydev->link = 0;
329 }
330
331 return 0;
332}
333
334static int tja11xx_get_sqi(struct phy_device *phydev)
335{
336 int ret;
337
338 ret = phy_read(phydev, MII_COMMSTAT);
339 if (ret < 0)
340 return ret;
341
342 return FIELD_GET(MII_COMMSTAT_SQI_STATE, ret);
343}
344
345static int tja11xx_get_sqi_max(struct phy_device *phydev)
346{
347 return MII_COMMSTAT_SQI_MAX;
348}
349
350static int tja11xx_get_sset_count(struct phy_device *phydev)
351{
352 return ARRAY_SIZE(tja11xx_hw_stats);
353}
354
355static void tja11xx_get_strings(struct phy_device *phydev, u8 *data)
356{
357 int i;
358
359 for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) {
360 strncpy(data + i * ETH_GSTRING_LEN,
361 tja11xx_hw_stats[i].string, ETH_GSTRING_LEN);
362 }
363}
364
365static void tja11xx_get_stats(struct phy_device *phydev,
366 struct ethtool_stats *stats, u64 *data)
367{
368 int i, ret;
369
370 for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) {
371 ret = phy_read(phydev, tja11xx_hw_stats[i].reg);
372 if (ret < 0)
373 data[i] = U64_MAX;
374 else {
375 data[i] = ret & tja11xx_hw_stats[i].mask;
376 data[i] >>= tja11xx_hw_stats[i].off;
377 }
378 }
379}
380
381static int tja11xx_hwmon_read(struct device *dev,
382 enum hwmon_sensor_types type,
383 u32 attr, int channel, long *value)
384{
385 struct phy_device *phydev = dev_get_drvdata(dev);
386 int ret;
387
388 if (type == hwmon_in && attr == hwmon_in_lcrit_alarm) {
389 ret = phy_read(phydev, MII_INTSRC);
390 if (ret < 0)
391 return ret;
392
393 *value = !!(ret & MII_INTSRC_TEMP_ERR);
394 return 0;
395 }
396
397 if (type == hwmon_temp && attr == hwmon_temp_crit_alarm) {
398 ret = phy_read(phydev, MII_INTSRC);
399 if (ret < 0)
400 return ret;
401
402 *value = !!(ret & MII_INTSRC_UV_ERR);
403 return 0;
404 }
405
406 return -EOPNOTSUPP;
407}
408
409static umode_t tja11xx_hwmon_is_visible(const void *data,
410 enum hwmon_sensor_types type,
411 u32 attr, int channel)
412{
413 if (type == hwmon_in && attr == hwmon_in_lcrit_alarm)
414 return 0444;
415
416 if (type == hwmon_temp && attr == hwmon_temp_crit_alarm)
417 return 0444;
418
419 return 0;
420}
421
422static const struct hwmon_channel_info *tja11xx_hwmon_info[] = {
423 HWMON_CHANNEL_INFO(in, HWMON_I_LCRIT_ALARM),
424 HWMON_CHANNEL_INFO(temp, HWMON_T_CRIT_ALARM),
425 NULL
426};
427
428static const struct hwmon_ops tja11xx_hwmon_hwmon_ops = {
429 .is_visible = tja11xx_hwmon_is_visible,
430 .read = tja11xx_hwmon_read,
431};
432
433static const struct hwmon_chip_info tja11xx_hwmon_chip_info = {
434 .ops = &tja11xx_hwmon_hwmon_ops,
435 .info = tja11xx_hwmon_info,
436};
437
438static int tja11xx_hwmon_register(struct phy_device *phydev,
439 struct tja11xx_priv *priv)
440{
441 struct device *dev = &phydev->mdio.dev;
442 int i;
443
444 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
445 if (!priv->hwmon_name)
446 return -ENOMEM;
447
448 for (i = 0; priv->hwmon_name[i]; i++)
449 if (hwmon_is_bad_char(priv->hwmon_name[i]))
450 priv->hwmon_name[i] = '_';
451
452 priv->hwmon_dev =
453 devm_hwmon_device_register_with_info(dev, priv->hwmon_name,
454 phydev,
455 &tja11xx_hwmon_chip_info,
456 NULL);
457
458 return PTR_ERR_OR_ZERO(priv->hwmon_dev);
459}
460
461static int tja11xx_probe(struct phy_device *phydev)
462{
463 struct device *dev = &phydev->mdio.dev;
464 struct tja11xx_priv *priv;
465
466 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
467 if (!priv)
468 return -ENOMEM;
469
470 priv->phydev = phydev;
471
472 return tja11xx_hwmon_register(phydev, priv);
473}
474
475static void tja1102_p1_register(struct work_struct *work)
476{
477 struct tja11xx_priv *priv = container_of(work, struct tja11xx_priv,
478 phy_register_work);
479 struct phy_device *phydev_phy0 = priv->phydev;
480 struct mii_bus *bus = phydev_phy0->mdio.bus;
481 struct device *dev = &phydev_phy0->mdio.dev;
482 struct device_node *np = dev->of_node;
483 struct device_node *child;
484 int ret;
485
486 for_each_available_child_of_node(np, child) {
487 struct phy_device *phy;
488 int addr;
489
490 addr = of_mdio_parse_addr(dev, child);
491 if (addr < 0) {
492 dev_err(dev, "Can't parse addr\n");
493 continue;
494 } else if (addr != phydev_phy0->mdio.addr + 1) {
495
496
497
498
499 dev_err(dev, "Unexpected address. Should be: %i\n",
500 phydev_phy0->mdio.addr + 1);
501 continue;
502 }
503
504 if (mdiobus_is_registered_device(bus, addr)) {
505 dev_err(dev, "device is already registered\n");
506 continue;
507 }
508
509
510 phy = phy_device_create(bus, addr, PHY_ID_TJA1102, false, NULL);
511 if (IS_ERR(phy)) {
512 dev_err(dev, "Can't create PHY device for Port 1: %i\n",
513 addr);
514 continue;
515 }
516
517
518
519
520 phy->mdio.dev.parent = dev;
521
522 ret = of_mdiobus_phy_device_register(bus, phy, child, addr);
523 if (ret) {
524
525
526
527
528
529 dev_err(dev, "Can't register Port 1. Unexpected error: %i\n",
530 ret);
531 phy_device_free(phy);
532 }
533 }
534}
535
536static int tja1102_p0_probe(struct phy_device *phydev)
537{
538 struct device *dev = &phydev->mdio.dev;
539 struct tja11xx_priv *priv;
540 int ret;
541
542 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
543 if (!priv)
544 return -ENOMEM;
545
546 priv->phydev = phydev;
547 INIT_WORK(&priv->phy_register_work, tja1102_p1_register);
548
549 ret = tja11xx_hwmon_register(phydev, priv);
550 if (ret)
551 return ret;
552
553 schedule_work(&priv->phy_register_work);
554
555 return 0;
556}
557
558static int tja1102_match_phy_device(struct phy_device *phydev, bool port0)
559{
560 int ret;
561
562 if ((phydev->phy_id & PHY_ID_MASK) != PHY_ID_TJA1102)
563 return 0;
564
565 ret = phy_read(phydev, MII_PHYSID2);
566 if (ret < 0)
567 return ret;
568
569
570
571
572 if (port0)
573 return ret ? 1 : 0;
574
575 return !ret;
576}
577
578static int tja1102_p0_match_phy_device(struct phy_device *phydev)
579{
580 return tja1102_match_phy_device(phydev, true);
581}
582
583static int tja1102_p1_match_phy_device(struct phy_device *phydev)
584{
585 return tja1102_match_phy_device(phydev, false);
586}
587
588static int tja11xx_ack_interrupt(struct phy_device *phydev)
589{
590 int ret;
591
592 ret = phy_read(phydev, MII_INTSRC);
593
594 return (ret < 0) ? ret : 0;
595}
596
597static int tja11xx_config_intr(struct phy_device *phydev)
598{
599 int value = 0;
600
601 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
602 value = MII_INTEN_LINK_FAIL | MII_INTEN_LINK_UP;
603
604 return phy_write(phydev, MII_INTEN, value);
605}
606
607static int tja11xx_cable_test_start(struct phy_device *phydev)
608{
609 int ret;
610
611 ret = phy_clear_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
612 if (ret)
613 return ret;
614
615 ret = tja11xx_wakeup(phydev);
616 if (ret < 0)
617 return ret;
618
619 ret = tja11xx_disable_link_control(phydev);
620 if (ret < 0)
621 return ret;
622
623 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CABLE_TEST);
624}
625
626
627
628
629
630
631
632
633
634
635
636
637
638static int tja11xx_cable_test_report_trans(u32 result)
639{
640 u32 mask = MII_EXTSTAT_SHORT_DETECT | MII_EXTSTAT_OPEN_DETECT;
641
642 if ((result & mask) == mask) {
643
644 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
645 } else if ((result & mask) == 0) {
646 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
647 } else if (result & MII_EXTSTAT_SHORT_DETECT) {
648 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
649 } else if (result & MII_EXTSTAT_OPEN_DETECT) {
650 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
651 } else {
652 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
653 }
654}
655
656static int tja11xx_cable_test_report(struct phy_device *phydev)
657{
658 int ret;
659
660 ret = phy_read(phydev, MII_EXTSTAT);
661 if (ret < 0)
662 return ret;
663
664 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
665 tja11xx_cable_test_report_trans(ret));
666
667 return 0;
668}
669
670static int tja11xx_cable_test_get_status(struct phy_device *phydev,
671 bool *finished)
672{
673 int ret;
674
675 *finished = false;
676
677 ret = phy_read(phydev, MII_ECTRL);
678 if (ret < 0)
679 return ret;
680
681 if (!(ret & MII_ECTRL_CABLE_TEST)) {
682 *finished = true;
683
684 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
685 if (ret)
686 return ret;
687
688 return tja11xx_cable_test_report(phydev);
689 }
690
691 return 0;
692}
693
694static struct phy_driver tja11xx_driver[] = {
695 {
696 PHY_ID_MATCH_MODEL(PHY_ID_TJA1100),
697 .name = "NXP TJA1100",
698 .features = PHY_BASIC_T1_FEATURES,
699 .probe = tja11xx_probe,
700 .soft_reset = tja11xx_soft_reset,
701 .config_aneg = tja11xx_config_aneg,
702 .config_init = tja11xx_config_init,
703 .read_status = tja11xx_read_status,
704 .get_sqi = tja11xx_get_sqi,
705 .get_sqi_max = tja11xx_get_sqi_max,
706 .suspend = genphy_suspend,
707 .resume = genphy_resume,
708 .set_loopback = genphy_loopback,
709
710 .get_sset_count = tja11xx_get_sset_count,
711 .get_strings = tja11xx_get_strings,
712 .get_stats = tja11xx_get_stats,
713 }, {
714 PHY_ID_MATCH_MODEL(PHY_ID_TJA1101),
715 .name = "NXP TJA1101",
716 .features = PHY_BASIC_T1_FEATURES,
717 .probe = tja11xx_probe,
718 .soft_reset = tja11xx_soft_reset,
719 .config_aneg = tja11xx_config_aneg,
720 .config_init = tja11xx_config_init,
721 .read_status = tja11xx_read_status,
722 .get_sqi = tja11xx_get_sqi,
723 .get_sqi_max = tja11xx_get_sqi_max,
724 .suspend = genphy_suspend,
725 .resume = genphy_resume,
726 .set_loopback = genphy_loopback,
727
728 .get_sset_count = tja11xx_get_sset_count,
729 .get_strings = tja11xx_get_strings,
730 .get_stats = tja11xx_get_stats,
731 }, {
732 .name = "NXP TJA1102 Port 0",
733 .features = PHY_BASIC_T1_FEATURES,
734 .flags = PHY_POLL_CABLE_TEST,
735 .probe = tja1102_p0_probe,
736 .soft_reset = tja11xx_soft_reset,
737 .config_aneg = tja11xx_config_aneg,
738 .config_init = tja11xx_config_init,
739 .read_status = tja11xx_read_status,
740 .get_sqi = tja11xx_get_sqi,
741 .get_sqi_max = tja11xx_get_sqi_max,
742 .match_phy_device = tja1102_p0_match_phy_device,
743 .suspend = genphy_suspend,
744 .resume = genphy_resume,
745 .set_loopback = genphy_loopback,
746
747 .get_sset_count = tja11xx_get_sset_count,
748 .get_strings = tja11xx_get_strings,
749 .get_stats = tja11xx_get_stats,
750 .ack_interrupt = tja11xx_ack_interrupt,
751 .config_intr = tja11xx_config_intr,
752 .cable_test_start = tja11xx_cable_test_start,
753 .cable_test_get_status = tja11xx_cable_test_get_status,
754 }, {
755 .name = "NXP TJA1102 Port 1",
756 .features = PHY_BASIC_T1_FEATURES,
757 .flags = PHY_POLL_CABLE_TEST,
758
759 .soft_reset = tja11xx_soft_reset,
760 .config_aneg = tja11xx_config_aneg,
761 .config_init = tja11xx_config_init,
762 .read_status = tja11xx_read_status,
763 .get_sqi = tja11xx_get_sqi,
764 .get_sqi_max = tja11xx_get_sqi_max,
765 .match_phy_device = tja1102_p1_match_phy_device,
766 .suspend = genphy_suspend,
767 .resume = genphy_resume,
768 .set_loopback = genphy_loopback,
769
770 .get_sset_count = tja11xx_get_sset_count,
771 .get_strings = tja11xx_get_strings,
772 .get_stats = tja11xx_get_stats,
773 .ack_interrupt = tja11xx_ack_interrupt,
774 .config_intr = tja11xx_config_intr,
775 .cable_test_start = tja11xx_cable_test_start,
776 .cable_test_get_status = tja11xx_cable_test_get_status,
777 }
778};
779
780module_phy_driver(tja11xx_driver);
781
782static struct mdio_device_id __maybe_unused tja11xx_tbl[] = {
783 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1100) },
784 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1101) },
785 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1102) },
786 { }
787};
788
789MODULE_DEVICE_TABLE(mdio, tja11xx_tbl);
790
791MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
792MODULE_DESCRIPTION("NXP TJA11xx BoardR-Reach PHY driver");
793MODULE_LICENSE("GPL");
794
