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24#include <linux/gfp.h>
25#include <linux/sched.h>
26
27#include "wlcore.h"
28#include "debug.h"
29#include "acx.h"
30#include "rx.h"
31#include "tx.h"
32#include "io.h"
33#include "hw_ops.h"
34
35
36
37
38
39#include "../wl12xx/reg.h"
40
41static u32 wlcore_rx_get_buf_size(struct wl1271 *wl,
42 u32 rx_pkt_desc)
43{
44 if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN)
45 return (rx_pkt_desc & ALIGNED_RX_BUF_SIZE_MASK) >>
46 ALIGNED_RX_BUF_SIZE_SHIFT;
47
48 return (rx_pkt_desc & RX_BUF_SIZE_MASK) >> RX_BUF_SIZE_SHIFT_DIV;
49}
50
51static u32 wlcore_rx_get_align_buf_size(struct wl1271 *wl, u32 pkt_len)
52{
53 if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN)
54 return ALIGN(pkt_len, WL12XX_BUS_BLOCK_SIZE);
55
56 return pkt_len;
57}
58
59static void wl1271_rx_status(struct wl1271 *wl,
60 struct wl1271_rx_descriptor *desc,
61 struct ieee80211_rx_status *status,
62 u8 beacon)
63{
64 memset(status, 0, sizeof(struct ieee80211_rx_status));
65
66 if ((desc->flags & WL1271_RX_DESC_BAND_MASK) == WL1271_RX_DESC_BAND_BG)
67 status->band = NL80211_BAND_2GHZ;
68 else
69 status->band = NL80211_BAND_5GHZ;
70
71 status->rate_idx = wlcore_rate_to_idx(wl, desc->rate, status->band);
72
73
74 if (desc->rate <= wl->hw_min_ht_rate)
75 status->encoding = RX_ENC_HT;
76
77
78
79
80
81
82
83 status->signal = ((desc->rssi & RSSI_LEVEL_BITMASK) | BIT(7));
84 status->antenna = ((desc->rssi & ANT_DIVERSITY_BITMASK) >> 7);
85
86
87
88
89
90
91 wl->noise = desc->rssi - (desc->snr >> 1);
92
93 status->freq = ieee80211_channel_to_frequency(desc->channel,
94 status->band);
95
96 if (desc->flags & WL1271_RX_DESC_ENCRYPT_MASK) {
97 u8 desc_err_code = desc->status & WL1271_RX_DESC_STATUS_MASK;
98
99 status->flag |= RX_FLAG_IV_STRIPPED | RX_FLAG_MMIC_STRIPPED |
100 RX_FLAG_DECRYPTED;
101
102 if (unlikely(desc_err_code & WL1271_RX_DESC_MIC_FAIL)) {
103 status->flag |= RX_FLAG_MMIC_ERROR;
104 wl1271_warning("Michael MIC error. Desc: 0x%x",
105 desc_err_code);
106 }
107 }
108
109 if (beacon)
110 wlcore_set_pending_regdomain_ch(wl, (u16)desc->channel,
111 status->band);
112}
113
114static int wl1271_rx_handle_data(struct wl1271 *wl, u8 *data, u32 length,
115 enum wl_rx_buf_align rx_align, u8 *hlid)
116{
117 struct wl1271_rx_descriptor *desc;
118 struct sk_buff *skb;
119 struct ieee80211_hdr *hdr;
120 u8 beacon = 0;
121 u8 is_data = 0;
122 u8 reserved = 0, offset_to_data = 0;
123 u16 seq_num;
124 u32 pkt_data_len;
125
126
127
128
129
130 if (unlikely(wl->plt))
131 return -EINVAL;
132
133 pkt_data_len = wlcore_hw_get_rx_packet_len(wl, data, length);
134 if (!pkt_data_len) {
135 wl1271_error("Invalid packet arrived from HW. length %d",
136 length);
137 return -EINVAL;
138 }
139
140 if (rx_align == WLCORE_RX_BUF_UNALIGNED)
141 reserved = RX_BUF_ALIGN;
142 else if (rx_align == WLCORE_RX_BUF_PADDED)
143 offset_to_data = RX_BUF_ALIGN;
144
145
146 desc = (struct wl1271_rx_descriptor *) data;
147
148 if (desc->packet_class == WL12XX_RX_CLASS_LOGGER) {
149 size_t len = length - sizeof(*desc);
150 wl12xx_copy_fwlog(wl, data + sizeof(*desc), len);
151 return 0;
152 }
153
154
155 if (desc->status & WL1271_RX_DESC_DECRYPT_FAIL) {
156 hdr = (void *)(data + sizeof(*desc) + offset_to_data);
157 wl1271_warning("corrupted packet in RX: status: 0x%x len: %d",
158 desc->status & WL1271_RX_DESC_STATUS_MASK,
159 pkt_data_len);
160 wl1271_dump((DEBUG_RX|DEBUG_CMD), "PKT: ", data + sizeof(*desc),
161 min(pkt_data_len,
162 ieee80211_hdrlen(hdr->frame_control)));
163 return -EINVAL;
164 }
165
166
167 skb = __dev_alloc_skb(pkt_data_len + reserved, GFP_KERNEL);
168 if (!skb) {
169 wl1271_error("Couldn't allocate RX frame");
170 return -ENOMEM;
171 }
172
173
174 skb_reserve(skb, reserved);
175
176
177
178
179
180
181
182 skb_put_data(skb, data + sizeof(*desc), pkt_data_len);
183 if (rx_align == WLCORE_RX_BUF_PADDED)
184 skb_pull(skb, RX_BUF_ALIGN);
185
186 *hlid = desc->hlid;
187
188 hdr = (struct ieee80211_hdr *)skb->data;
189 if (ieee80211_is_beacon(hdr->frame_control))
190 beacon = 1;
191 if (ieee80211_is_data_present(hdr->frame_control))
192 is_data = 1;
193
194 wl1271_rx_status(wl, desc, IEEE80211_SKB_RXCB(skb), beacon);
195 wlcore_hw_set_rx_csum(wl, desc, skb);
196
197 seq_num = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
198 wl1271_debug(DEBUG_RX, "rx skb 0x%p: %d B %s seq %d hlid %d", skb,
199 skb->len - desc->pad_len,
200 beacon ? "beacon" : "",
201 seq_num, *hlid);
202
203 skb_queue_tail(&wl->deferred_rx_queue, skb);
204 queue_work(wl->freezable_wq, &wl->netstack_work);
205
206 return is_data;
207}
208
209int wlcore_rx(struct wl1271 *wl, struct wl_fw_status *status)
210{
211 unsigned long active_hlids[BITS_TO_LONGS(WLCORE_MAX_LINKS)] = {0};
212 u32 buf_size;
213 u32 fw_rx_counter = status->fw_rx_counter % wl->num_rx_desc;
214 u32 drv_rx_counter = wl->rx_counter % wl->num_rx_desc;
215 u32 rx_counter;
216 u32 pkt_len, align_pkt_len;
217 u32 pkt_offset, des;
218 u8 hlid;
219 enum wl_rx_buf_align rx_align;
220 int ret = 0;
221
222
223 hlid = status->counters.hlid;
224
225 if (hlid < WLCORE_MAX_LINKS)
226 wl->links[hlid].fw_rate_mbps =
227 status->counters.tx_last_rate_mbps;
228
229 while (drv_rx_counter != fw_rx_counter) {
230 buf_size = 0;
231 rx_counter = drv_rx_counter;
232 while (rx_counter != fw_rx_counter) {
233 des = le32_to_cpu(status->rx_pkt_descs[rx_counter]);
234 pkt_len = wlcore_rx_get_buf_size(wl, des);
235 align_pkt_len = wlcore_rx_get_align_buf_size(wl,
236 pkt_len);
237 if (buf_size + align_pkt_len > wl->aggr_buf_size)
238 break;
239 buf_size += align_pkt_len;
240 rx_counter++;
241 rx_counter %= wl->num_rx_desc;
242 }
243
244 if (buf_size == 0) {
245 wl1271_warning("received empty data");
246 break;
247 }
248
249
250 des = le32_to_cpu(status->rx_pkt_descs[drv_rx_counter]);
251 ret = wlcore_hw_prepare_read(wl, des, buf_size);
252 if (ret < 0)
253 goto out;
254
255 ret = wlcore_read_data(wl, REG_SLV_MEM_DATA, wl->aggr_buf,
256 buf_size, true);
257 if (ret < 0)
258 goto out;
259
260
261 pkt_offset = 0;
262 while (pkt_offset < buf_size) {
263 des = le32_to_cpu(status->rx_pkt_descs[drv_rx_counter]);
264 pkt_len = wlcore_rx_get_buf_size(wl, des);
265 rx_align = wlcore_hw_get_rx_buf_align(wl, des);
266
267
268
269
270
271
272 if (wl1271_rx_handle_data(wl,
273 wl->aggr_buf + pkt_offset,
274 pkt_len, rx_align,
275 &hlid) == 1) {
276 if (hlid < wl->num_links)
277 __set_bit(hlid, active_hlids);
278 else
279 WARN(1,
280 "hlid (%d) exceeded MAX_LINKS\n",
281 hlid);
282 }
283
284 wl->rx_counter++;
285 drv_rx_counter++;
286 drv_rx_counter %= wl->num_rx_desc;
287 pkt_offset += wlcore_rx_get_align_buf_size(wl, pkt_len);
288 }
289 }
290
291
292
293
294
295 if (wl->quirks & WLCORE_QUIRK_END_OF_TRANSACTION) {
296 ret = wlcore_write32(wl, WL12XX_REG_RX_DRIVER_COUNTER,
297 wl->rx_counter);
298 if (ret < 0)
299 goto out;
300 }
301
302 wl12xx_rearm_rx_streaming(wl, active_hlids);
303
304out:
305 return ret;
306}
307
308#ifdef CONFIG_PM
309int wl1271_rx_filter_enable(struct wl1271 *wl,
310 int index, bool enable,
311 struct wl12xx_rx_filter *filter)
312{
313 int ret;
314
315 if (!!test_bit(index, wl->rx_filter_enabled) == enable) {
316 wl1271_warning("Request to enable an already "
317 "enabled rx filter %d", index);
318 return 0;
319 }
320
321 ret = wl1271_acx_set_rx_filter(wl, index, enable, filter);
322
323 if (ret) {
324 wl1271_error("Failed to %s rx data filter %d (err=%d)",
325 enable ? "enable" : "disable", index, ret);
326 return ret;
327 }
328
329 if (enable)
330 __set_bit(index, wl->rx_filter_enabled);
331 else
332 __clear_bit(index, wl->rx_filter_enabled);
333
334 return 0;
335}
336
337int wl1271_rx_filter_clear_all(struct wl1271 *wl)
338{
339 int i, ret = 0;
340
341 for (i = 0; i < WL1271_MAX_RX_FILTERS; i++) {
342 if (!test_bit(i, wl->rx_filter_enabled))
343 continue;
344 ret = wl1271_rx_filter_enable(wl, i, 0, NULL);
345 if (ret)
346 goto out;
347 }
348
349out:
350 return ret;
351}
352#endif
353