LXR linux/drivers/pinctrl/freescale/pinctrl-imx.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * IMX pinmux core definitions
   4 *
   5 * Copyright (C) 2012 Freescale Semiconductor, Inc.
   6 * Copyright (C) 2012 Linaro Ltd.
   7 *
   8 * Author: Dong Aisheng <dong.aisheng@linaro.org>
   9 */
  10
  11#ifndef __DRIVERS_PINCTRL_IMX_H
  12#define __DRIVERS_PINCTRL_IMX_H
  13
  14#include <linux/pinctrl/pinconf-generic.h>
  15#include <linux/pinctrl/pinmux.h>
  16
  17struct platform_device;
  18
  19extern struct pinmux_ops imx_pmx_ops;
  20
  21/**
  22 * struct imx_pin - describes a single i.MX pin
  23 * @pin: the pin_id of this pin
  24 * @mux_mode: the mux mode for this pin.
  25 * @input_reg: the select input register offset for this pin if any
  26 *      0 if no select input setting needed.
  27 * @input_val: the select input value for this pin.
  28 * @configs: the config for this pin.
  29 */
  30struct imx_pin {
  31        unsigned int pin;
  32        unsigned int mux_mode;
  33        u16 input_reg;
  34        unsigned int input_val;
  35        unsigned long config;
  36};
  37
  38/**
  39 * struct imx_pin_reg - describe a pin reg map
  40 * @mux_reg: mux register offset
  41 * @conf_reg: config register offset
  42 */
  43struct imx_pin_reg {
  44        s16 mux_reg;
  45        s16 conf_reg;
  46};
  47
  48/* decode a generic config into raw register value */
  49struct imx_cfg_params_decode {
  50        enum pin_config_param param;
  51        u32 mask;
  52        u8 shift;
  53        bool invert;
  54};
  55
  56struct imx_pinctrl_soc_info {
  57        const struct pinctrl_pin_desc *pins;
  58        unsigned int npins;
  59        unsigned int flags;
  60        const char *gpr_compatible;
  61
  62        /* MUX_MODE shift and mask in case SHARE_MUX_CONF_REG */
  63        unsigned int mux_mask;
  64        u8 mux_shift;
  65
  66        /* generic pinconf */
  67        bool generic_pinconf;
  68        const struct pinconf_generic_params *custom_params;
  69        unsigned int num_custom_params;
  70        const struct imx_cfg_params_decode *decodes;
  71        unsigned int num_decodes;
  72        void (*fixup)(unsigned long *configs, unsigned int num_configs,
  73                      u32 *raw_config);
  74
  75        int (*gpio_set_direction)(struct pinctrl_dev *pctldev,
  76                                  struct pinctrl_gpio_range *range,
  77                                  unsigned offset,
  78                                  bool input);
  79};
  80
  81/**
  82 * @dev: a pointer back to containing device
  83 * @base: the offset to the controller in virtual memory
  84 */
  85struct imx_pinctrl {
  86        struct device *dev;
  87        struct pinctrl_dev *pctl;
  88        void __iomem *base;
  89        void __iomem *input_sel_base;
  90        const struct imx_pinctrl_soc_info *info;
  91        struct imx_pin_reg *pin_regs;
  92        unsigned int group_index;
  93        struct mutex mutex;
  94};
  95
  96#define IMX_CFG_PARAMS_DECODE(p, m, o) \
  97        { .param = p, .mask = m, .shift = o, .invert = false, }
  98
  99#define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \
 100        { .param = p, .mask = m, .shift = o, .invert = true, }
 101
 102#define SHARE_MUX_CONF_REG      0x1
 103#define ZERO_OFFSET_VALID       0x2
 104
 105#define NO_MUX          0x0
 106#define NO_PAD          0x0
 107
 108#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
 109
 110#define PAD_CTL_MASK(len)       ((1 << len) - 1)
 111#define IMX_MUX_MASK    0x7
 112#define IOMUXC_CONFIG_SION      (0x1 << 4)
 113
 114int imx_pinctrl_probe(struct platform_device *pdev,
 115                        const struct imx_pinctrl_soc_info *info);
 116#endif /* __DRIVERS_PINCTRL_IMX_H */
 117