LXR linux/drivers/rtc/rtc-mxc

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Real Time Clock (RTC) Driver for i.MX53
   4 * Copyright (c) 2004-2011 Freescale Semiconductor, Inc.
   5 * Copyright (c) 2017 Beckhoff Automation GmbH & Co. KG
   6 */
   7
   8#include <linux/clk.h>
   9#include <linux/io.h>
  10#include <linux/module.h>
  11#include <linux/platform_device.h>
  12#include <linux/rtc.h>
  13
  14#define SRTC_LPPDR_INIT       0x41736166        /* init for glitch detect */
  15
  16#define SRTC_LPCR_EN_LP       BIT(3)    /* lp enable */
  17#define SRTC_LPCR_WAE         BIT(4)    /* lp wakeup alarm enable */
  18#define SRTC_LPCR_ALP         BIT(7)    /* lp alarm flag */
  19#define SRTC_LPCR_NSA         BIT(11)   /* lp non secure access */
  20#define SRTC_LPCR_NVE         BIT(14)   /* lp non valid state exit bit */
  21#define SRTC_LPCR_IE          BIT(15)   /* lp init state exit bit */
  22
  23#define SRTC_LPSR_ALP         BIT(3)    /* lp alarm flag */
  24#define SRTC_LPSR_NVES        BIT(14)   /* lp non-valid state exit status */
  25#define SRTC_LPSR_IES         BIT(15)   /* lp init state exit status */
  26
  27#define SRTC_LPSCMR     0x00    /* LP Secure Counter MSB Reg */
  28#define SRTC_LPSCLR     0x04    /* LP Secure Counter LSB Reg */
  29#define SRTC_LPSAR      0x08    /* LP Secure Alarm Reg */
  30#define SRTC_LPCR       0x10    /* LP Control Reg */
  31#define SRTC_LPSR       0x14    /* LP Status Reg */
  32#define SRTC_LPPDR      0x18    /* LP Power Supply Glitch Detector Reg */
  33
  34/* max. number of retries to read registers, 120 was max during test */
  35#define REG_READ_TIMEOUT 2000
  36
  37struct mxc_rtc_data {
  38        struct rtc_device *rtc;
  39        void __iomem *ioaddr;
  40        struct clk *clk;
  41        spinlock_t lock; /* protects register access */
  42        int irq;
  43};
  44
  45/*
  46 * This function does write synchronization for writes to the lp srtc block.
  47 * To take care of the asynchronous CKIL clock, all writes from the IP domain
  48 * will be synchronized to the CKIL domain.
  49 * The caller should hold the pdata->lock
  50 */
  51static void mxc_rtc_sync_lp_locked(struct device *dev, void __iomem *ioaddr)
  52{
  53        unsigned int i;
  54
  55        /* Wait for 3 CKIL cycles */
  56        for (i = 0; i < 3; i++) {
  57                const u32 count = readl(ioaddr + SRTC_LPSCLR);
  58                unsigned int timeout = REG_READ_TIMEOUT;
  59
  60                while ((readl(ioaddr + SRTC_LPSCLR)) == count) {
  61                        if (!--timeout) {
  62                                dev_err_once(dev, "SRTC_LPSCLR stuck! Check your hw.\n");
  63                                return;
  64                        }
  65                }
  66        }
  67}
  68
  69/* This function is the RTC interrupt service routine. */
  70static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
  71{
  72        struct device *dev = dev_id;
  73        struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
  74        void __iomem *ioaddr = pdata->ioaddr;
  75        unsigned long flags;
  76        u32 lp_status;
  77        u32 lp_cr;
  78
  79        spin_lock_irqsave(&pdata->lock, flags);
  80        if (clk_enable(pdata->clk)) {
  81                spin_unlock_irqrestore(&pdata->lock, flags);
  82                return IRQ_NONE;
  83        }
  84
  85        lp_status = readl(ioaddr + SRTC_LPSR);
  86        lp_cr = readl(ioaddr + SRTC_LPCR);
  87
  88        /* update irq data & counter */
  89        if (lp_status & SRTC_LPSR_ALP) {
  90                if (lp_cr & SRTC_LPCR_ALP)
  91                        rtc_update_irq(pdata->rtc, 1, RTC_AF | RTC_IRQF);
  92
  93                /* disable further lp alarm interrupts */
  94                lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);
  95        }
  96
  97        /* Update interrupt enables */
  98        writel(lp_cr, ioaddr + SRTC_LPCR);
  99
 100        /* clear interrupt status */
 101        writel(lp_status, ioaddr + SRTC_LPSR);
 102
 103        mxc_rtc_sync_lp_locked(dev, ioaddr);
 104        clk_disable(pdata->clk);
 105        spin_unlock_irqrestore(&pdata->lock, flags);
 106        return IRQ_HANDLED;
 107}
 108
 109/*
 110 * Enable clk and aquire spinlock
 111 * @return  0 if successful; non-zero otherwise.
 112 */
 113static int mxc_rtc_lock(struct mxc_rtc_data *const pdata)
 114{
 115        int ret;
 116
 117        spin_lock_irq(&pdata->lock);
 118        ret = clk_enable(pdata->clk);
 119        if (ret) {
 120                spin_unlock_irq(&pdata->lock);
 121                return ret;
 122        }
 123        return 0;
 124}
 125
 126static int mxc_rtc_unlock(struct mxc_rtc_data *const pdata)
 127{
 128        clk_disable(pdata->clk);
 129        spin_unlock_irq(&pdata->lock);
 130        return 0;
 131}
 132
 133/*
 134 * This function reads the current RTC time into tm in Gregorian date.
 135 *
 136 * @param  tm           contains the RTC time value upon return
 137 *
 138 * @return  0 if successful; non-zero otherwise.
 139 */
 140static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
 141{
 142        struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
 143        const int clk_failed = clk_enable(pdata->clk);
 144
 145        if (!clk_failed) {
 146                const time64_t now = readl(pdata->ioaddr + SRTC_LPSCMR);
 147
 148                rtc_time64_to_tm(now, tm);
 149                clk_disable(pdata->clk);
 150                return 0;
 151        }
 152        return clk_failed;
 153}
 154
 155/*
 156 * This function sets the internal RTC time based on tm in Gregorian date.
 157 *
 158 * @param  tm           the time value to be set in the RTC
 159 *
 160 * @return  0 if successful; non-zero otherwise.
 161 */
 162static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm)
 163{
 164        struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
 165        time64_t time = rtc_tm_to_time64(tm);
 166        int ret;
 167
 168        ret = mxc_rtc_lock(pdata);
 169        if (ret)
 170                return ret;
 171
 172        writel(time, pdata->ioaddr + SRTC_LPSCMR);
 173        mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
 174        return mxc_rtc_unlock(pdata);
 175}
 176
 177/*
 178 * This function reads the current alarm value into the passed in \b alrm
 179 * argument. It updates the \b alrm's pending field value based on the whether
 180 * an alarm interrupt occurs or not.
 181 *
 182 * @param  alrm         contains the RTC alarm value upon return
 183 *
 184 * @return  0 if successful; non-zero otherwise.
 185 */
 186static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 187{
 188        struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
 189        void __iomem *ioaddr = pdata->ioaddr;
 190        int ret;
 191
 192        ret = mxc_rtc_lock(pdata);
 193        if (ret)
 194                return ret;
 195
 196        rtc_time64_to_tm(readl(ioaddr + SRTC_LPSAR), &alrm->time);
 197        alrm->pending = !!(readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_ALP);
 198        return mxc_rtc_unlock(pdata);
 199}
 200
 201/*
 202 * Enable/Disable alarm interrupt
 203 * The caller should hold the pdata->lock
 204 */
 205static void mxc_rtc_alarm_irq_enable_locked(struct mxc_rtc_data *pdata,
 206                                            unsigned int enable)
 207{
 208        u32 lp_cr = readl(pdata->ioaddr + SRTC_LPCR);
 209
 210        if (enable)
 211                lp_cr |= (SRTC_LPCR_ALP | SRTC_LPCR_WAE);
 212        else
 213                lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);
 214
 215        writel(lp_cr, pdata->ioaddr + SRTC_LPCR);
 216}
 217
 218static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
 219{
 220        struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
 221        int ret = mxc_rtc_lock(pdata);
 222
 223        if (ret)
 224                return ret;
 225
 226        mxc_rtc_alarm_irq_enable_locked(pdata, enable);
 227        return mxc_rtc_unlock(pdata);
 228}
 229
 230/*
 231 * This function sets the RTC alarm based on passed in alrm.
 232 *
 233 * @param  alrm         the alarm value to be set in the RTC
 234 *
 235 * @return  0 if successful; non-zero otherwise.
 236 */
 237static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 238{
 239        const time64_t time = rtc_tm_to_time64(&alrm->time);
 240        struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
 241        int ret = mxc_rtc_lock(pdata);
 242
 243        if (ret)
 244                return ret;
 245
 246        writel((u32)time, pdata->ioaddr + SRTC_LPSAR);
 247
 248        /* clear alarm interrupt status bit */
 249        writel(SRTC_LPSR_ALP, pdata->ioaddr + SRTC_LPSR);
 250        mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
 251
 252        mxc_rtc_alarm_irq_enable_locked(pdata, alrm->enabled);
 253        mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
 254        mxc_rtc_unlock(pdata);
 255        return ret;
 256}
 257
 258static const struct rtc_class_ops mxc_rtc_ops = {
 259        .read_time = mxc_rtc_read_time,
 260        .set_time = mxc_rtc_set_time,
 261        .read_alarm = mxc_rtc_read_alarm,
 262        .set_alarm = mxc_rtc_set_alarm,
 263        .alarm_irq_enable = mxc_rtc_alarm_irq_enable,
 264};
 265
 266static int mxc_rtc_wait_for_flag(void __iomem *ioaddr, int flag)
 267{
 268        unsigned int timeout = REG_READ_TIMEOUT;
 269
 270        while (!(readl(ioaddr) & flag)) {
 271                if (!--timeout)
 272                        return -EBUSY;
 273        }
 274        return 0;
 275}
 276
 277static int mxc_rtc_probe(struct platform_device *pdev)
 278{
 279        struct mxc_rtc_data *pdata;
 280        struct resource *res;
 281        void __iomem *ioaddr;
 282        int ret = 0;
 283
 284        pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
 285        if (!pdata)
 286                return -ENOMEM;
 287
 288        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 289        pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
 290        if (IS_ERR(pdata->ioaddr))
 291                return PTR_ERR(pdata->ioaddr);
 292
 293        ioaddr = pdata->ioaddr;
 294
 295        pdata->clk = devm_clk_get(&pdev->dev, NULL);
 296        if (IS_ERR(pdata->clk)) {
 297                dev_err(&pdev->dev, "unable to get rtc clock!\n");
 298                return PTR_ERR(pdata->clk);
 299        }
 300
 301        spin_lock_init(&pdata->lock);
 302        pdata->irq = platform_get_irq(pdev, 0);
 303        if (pdata->irq < 0)
 304                return pdata->irq;
 305
 306        device_init_wakeup(&pdev->dev, 1);
 307
 308        ret = clk_prepare_enable(pdata->clk);
 309        if (ret)
 310                return ret;
 311        /* initialize glitch detect */
 312        writel(SRTC_LPPDR_INIT, ioaddr + SRTC_LPPDR);
 313
 314        /* clear lp interrupt status */
 315        writel(0xFFFFFFFF, ioaddr + SRTC_LPSR);
 316
 317        /* move out of init state */
 318        writel((SRTC_LPCR_IE | SRTC_LPCR_NSA), ioaddr + SRTC_LPCR);
 319        ret = mxc_rtc_wait_for_flag(ioaddr + SRTC_LPSR, SRTC_LPSR_IES);
 320        if (ret) {
 321                dev_err(&pdev->dev, "Timeout waiting for SRTC_LPSR_IES\n");
 322                clk_disable_unprepare(pdata->clk);
 323                return ret;
 324        }
 325
 326        /* move out of non-valid state */
 327        writel((SRTC_LPCR_IE | SRTC_LPCR_NVE | SRTC_LPCR_NSA |
 328                SRTC_LPCR_EN_LP), ioaddr + SRTC_LPCR);
 329        ret = mxc_rtc_wait_for_flag(ioaddr + SRTC_LPSR, SRTC_LPSR_NVES);
 330        if (ret) {
 331                dev_err(&pdev->dev, "Timeout waiting for SRTC_LPSR_NVES\n");
 332                clk_disable_unprepare(pdata->clk);
 333                return ret;
 334        }
 335
 336        pdata->rtc = devm_rtc_allocate_device(&pdev->dev);
 337        if (IS_ERR(pdata->rtc))
 338                return PTR_ERR(pdata->rtc);
 339
 340        pdata->rtc->ops = &mxc_rtc_ops;
 341        pdata->rtc->range_max = U32_MAX;
 342
 343        clk_disable(pdata->clk);
 344        platform_set_drvdata(pdev, pdata);
 345        ret =
 346            devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt, 0,
 347                             pdev->name, &pdev->dev);
 348        if (ret < 0) {
 349                dev_err(&pdev->dev, "interrupt not available.\n");
 350                clk_unprepare(pdata->clk);
 351                return ret;
 352        }
 353
 354        ret = rtc_register_device(pdata->rtc);
 355        if (ret < 0)
 356                clk_unprepare(pdata->clk);
 357
 358        return ret;
 359}
 360
 361static int mxc_rtc_remove(struct platform_device *pdev)
 362{
 363        struct mxc_rtc_data *pdata = platform_get_drvdata(pdev);
 364
 365        clk_disable_unprepare(pdata->clk);
 366        return 0;
 367}
 368
 369#ifdef CONFIG_PM_SLEEP
 370static int mxc_rtc_suspend(struct device *dev)
 371{
 372        struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
 373
 374        if (device_may_wakeup(dev))
 375                enable_irq_wake(pdata->irq);
 376
 377        return 0;
 378}
 379
 380static int mxc_rtc_resume(struct device *dev)
 381{
 382        struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
 383
 384        if (device_may_wakeup(dev))
 385                disable_irq_wake(pdata->irq);
 386
 387        return 0;
 388}
 389#endif
 390
 391static SIMPLE_DEV_PM_OPS(mxc_rtc_pm_ops, mxc_rtc_suspend, mxc_rtc_resume);
 392
 393static const struct of_device_id mxc_ids[] = {
 394        { .compatible = "fsl,imx53-rtc", },
 395        {}
 396};
 397
 398static struct platform_driver mxc_rtc_driver = {
 399        .driver = {
 400                .name = "mxc_rtc_v2",
 401                .of_match_table = mxc_ids,
 402                .pm = &mxc_rtc_pm_ops,
 403        },
 404        .probe = mxc_rtc_probe,
 405        .remove = mxc_rtc_remove,
 406};
 407
 408module_platform_driver(mxc_rtc_driver);
 409
 410MODULE_AUTHOR("Freescale Semiconductor, Inc.");
 411MODULE_DESCRIPTION("Real Time Clock (RTC) Driver for i.MX53");
 412MODULE_LICENSE("GPL");
 413