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47#include <linux/module.h>
48#include <linux/reboot.h>
49#include <linux/spinlock.h>
50#include <linux/pci_ids.h>
51#include <linux/interrupt.h>
52#include <linux/moduleparam.h>
53#include <linux/errno.h>
54#include <linux/types.h>
55#include <linux/delay.h>
56#include <linux/dma-mapping.h>
57#include <linux/timer.h>
58#include <linux/slab.h>
59#include <linux/pci.h>
60#include <linux/aer.h>
61#include <linux/circ_buf.h>
62#include <asm/dma.h>
63#include <asm/io.h>
64#include <linux/uaccess.h>
65#include <scsi/scsi_host.h>
66#include <scsi/scsi.h>
67#include <scsi/scsi_cmnd.h>
68#include <scsi/scsi_tcq.h>
69#include <scsi/scsi_device.h>
70#include <scsi/scsi_transport.h>
71#include <scsi/scsicam.h>
72#include "arcmsr.h"
73MODULE_AUTHOR("Nick Cheng, C.L. Huang <support@areca.com.tw>");
74MODULE_DESCRIPTION("Areca ARC11xx/12xx/16xx/188x SAS/SATA RAID Controller Driver");
75MODULE_LICENSE("Dual BSD/GPL");
76MODULE_VERSION(ARCMSR_DRIVER_VERSION);
77
78static int msix_enable = 1;
79module_param(msix_enable, int, S_IRUGO);
80MODULE_PARM_DESC(msix_enable, "Enable MSI-X interrupt(0 ~ 1), msix_enable=1(enable), =0(disable)");
81
82static int msi_enable = 1;
83module_param(msi_enable, int, S_IRUGO);
84MODULE_PARM_DESC(msi_enable, "Enable MSI interrupt(0 ~ 1), msi_enable=1(enable), =0(disable)");
85
86static int host_can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD;
87module_param(host_can_queue, int, S_IRUGO);
88MODULE_PARM_DESC(host_can_queue, " adapter queue depth(32 ~ 1024), default is 128");
89
90static int cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN;
91module_param(cmd_per_lun, int, S_IRUGO);
92MODULE_PARM_DESC(cmd_per_lun, " device queue depth(1 ~ 128), default is 32");
93
94static int set_date_time = 0;
95module_param(set_date_time, int, S_IRUGO);
96MODULE_PARM_DESC(set_date_time, " send date, time to iop(0 ~ 1), set_date_time=1(enable), default(=0) is disable");
97
98#define ARCMSR_SLEEPTIME 10
99#define ARCMSR_RETRYCOUNT 12
100
101static wait_queue_head_t wait_q;
102static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
103 struct scsi_cmnd *cmd);
104static int arcmsr_iop_confirm(struct AdapterControlBlock *acb);
105static int arcmsr_abort(struct scsi_cmnd *);
106static int arcmsr_bus_reset(struct scsi_cmnd *);
107static int arcmsr_bios_param(struct scsi_device *sdev,
108 struct block_device *bdev, sector_t capacity, int *info);
109static int arcmsr_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
110static int arcmsr_probe(struct pci_dev *pdev,
111 const struct pci_device_id *id);
112static int arcmsr_suspend(struct pci_dev *pdev, pm_message_t state);
113static int arcmsr_resume(struct pci_dev *pdev);
114static void arcmsr_remove(struct pci_dev *pdev);
115static void arcmsr_shutdown(struct pci_dev *pdev);
116static void arcmsr_iop_init(struct AdapterControlBlock *acb);
117static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb);
118static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb);
119static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
120 u32 intmask_org);
121static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
122static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb);
123static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb);
124static void arcmsr_request_device_map(struct timer_list *t);
125static void arcmsr_message_isr_bh_fn(struct work_struct *work);
126static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb);
127static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
128static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *pACB);
129static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb);
130static void arcmsr_hbaE_message_isr(struct AdapterControlBlock *acb);
131static void arcmsr_hbaE_postqueue_isr(struct AdapterControlBlock *acb);
132static void arcmsr_hardware_reset(struct AdapterControlBlock *acb);
133static const char *arcmsr_info(struct Scsi_Host *);
134static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb);
135static void arcmsr_free_irq(struct pci_dev *, struct AdapterControlBlock *);
136static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb);
137static void arcmsr_set_iop_datetime(struct timer_list *);
138static int arcmsr_adjust_disk_queue_depth(struct scsi_device *sdev, int queue_depth)
139{
140 if (queue_depth > ARCMSR_MAX_CMD_PERLUN)
141 queue_depth = ARCMSR_MAX_CMD_PERLUN;
142 return scsi_change_queue_depth(sdev, queue_depth);
143}
144
145static struct scsi_host_template arcmsr_scsi_host_template = {
146 .module = THIS_MODULE,
147 .name = "Areca SAS/SATA RAID driver",
148 .info = arcmsr_info,
149 .queuecommand = arcmsr_queue_command,
150 .eh_abort_handler = arcmsr_abort,
151 .eh_bus_reset_handler = arcmsr_bus_reset,
152 .bios_param = arcmsr_bios_param,
153 .change_queue_depth = arcmsr_adjust_disk_queue_depth,
154 .can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD,
155 .this_id = ARCMSR_SCSI_INITIATOR_ID,
156 .sg_tablesize = ARCMSR_DEFAULT_SG_ENTRIES,
157 .max_sectors = ARCMSR_MAX_XFER_SECTORS_C,
158 .cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN,
159 .use_clustering = ENABLE_CLUSTERING,
160 .shost_attrs = arcmsr_host_attrs,
161 .no_write_same = 1,
162};
163
164static struct pci_device_id arcmsr_device_id_table[] = {
165 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110),
166 .driver_data = ACB_ADAPTER_TYPE_A},
167 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1120),
168 .driver_data = ACB_ADAPTER_TYPE_A},
169 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1130),
170 .driver_data = ACB_ADAPTER_TYPE_A},
171 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1160),
172 .driver_data = ACB_ADAPTER_TYPE_A},
173 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1170),
174 .driver_data = ACB_ADAPTER_TYPE_A},
175 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1200),
176 .driver_data = ACB_ADAPTER_TYPE_B},
177 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1201),
178 .driver_data = ACB_ADAPTER_TYPE_B},
179 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1202),
180 .driver_data = ACB_ADAPTER_TYPE_B},
181 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1203),
182 .driver_data = ACB_ADAPTER_TYPE_B},
183 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1210),
184 .driver_data = ACB_ADAPTER_TYPE_A},
185 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1214),
186 .driver_data = ACB_ADAPTER_TYPE_D},
187 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1220),
188 .driver_data = ACB_ADAPTER_TYPE_A},
189 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1230),
190 .driver_data = ACB_ADAPTER_TYPE_A},
191 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1260),
192 .driver_data = ACB_ADAPTER_TYPE_A},
193 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1270),
194 .driver_data = ACB_ADAPTER_TYPE_A},
195 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1280),
196 .driver_data = ACB_ADAPTER_TYPE_A},
197 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1380),
198 .driver_data = ACB_ADAPTER_TYPE_A},
199 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1381),
200 .driver_data = ACB_ADAPTER_TYPE_A},
201 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1680),
202 .driver_data = ACB_ADAPTER_TYPE_A},
203 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1681),
204 .driver_data = ACB_ADAPTER_TYPE_A},
205 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1880),
206 .driver_data = ACB_ADAPTER_TYPE_C},
207 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1884),
208 .driver_data = ACB_ADAPTER_TYPE_E},
209 {0, 0},
210};
211MODULE_DEVICE_TABLE(pci, arcmsr_device_id_table);
212
213static struct pci_driver arcmsr_pci_driver = {
214 .name = "arcmsr",
215 .id_table = arcmsr_device_id_table,
216 .probe = arcmsr_probe,
217 .remove = arcmsr_remove,
218 .suspend = arcmsr_suspend,
219 .resume = arcmsr_resume,
220 .shutdown = arcmsr_shutdown,
221};
222
223
224
225
226
227static void arcmsr_free_mu(struct AdapterControlBlock *acb)
228{
229 switch (acb->adapter_type) {
230 case ACB_ADAPTER_TYPE_B:
231 case ACB_ADAPTER_TYPE_D:
232 case ACB_ADAPTER_TYPE_E: {
233 dma_free_coherent(&acb->pdev->dev, acb->roundup_ccbsize,
234 acb->dma_coherent2, acb->dma_coherent_handle2);
235 break;
236 }
237 }
238}
239
240static bool arcmsr_remap_pciregion(struct AdapterControlBlock *acb)
241{
242 struct pci_dev *pdev = acb->pdev;
243 switch (acb->adapter_type){
244 case ACB_ADAPTER_TYPE_A:{
245 acb->pmuA = ioremap(pci_resource_start(pdev,0), pci_resource_len(pdev,0));
246 if (!acb->pmuA) {
247 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
248 return false;
249 }
250 break;
251 }
252 case ACB_ADAPTER_TYPE_B:{
253 void __iomem *mem_base0, *mem_base1;
254 mem_base0 = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
255 if (!mem_base0) {
256 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
257 return false;
258 }
259 mem_base1 = ioremap(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2));
260 if (!mem_base1) {
261 iounmap(mem_base0);
262 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
263 return false;
264 }
265 acb->mem_base0 = mem_base0;
266 acb->mem_base1 = mem_base1;
267 break;
268 }
269 case ACB_ADAPTER_TYPE_C:{
270 acb->pmuC = ioremap_nocache(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1));
271 if (!acb->pmuC) {
272 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
273 return false;
274 }
275 if (readl(&acb->pmuC->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
276 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &acb->pmuC->outbound_doorbell_clear);
277 return true;
278 }
279 break;
280 }
281 case ACB_ADAPTER_TYPE_D: {
282 void __iomem *mem_base0;
283 unsigned long addr, range, flags;
284
285 addr = (unsigned long)pci_resource_start(pdev, 0);
286 range = pci_resource_len(pdev, 0);
287 flags = pci_resource_flags(pdev, 0);
288 mem_base0 = ioremap(addr, range);
289 if (!mem_base0) {
290 pr_notice("arcmsr%d: memory mapping region fail\n",
291 acb->host->host_no);
292 return false;
293 }
294 acb->mem_base0 = mem_base0;
295 break;
296 }
297 case ACB_ADAPTER_TYPE_E: {
298 acb->pmuE = ioremap(pci_resource_start(pdev, 1),
299 pci_resource_len(pdev, 1));
300 if (!acb->pmuE) {
301 pr_notice("arcmsr%d: memory mapping region fail \n",
302 acb->host->host_no);
303 return false;
304 }
305 writel(0, &acb->pmuE->host_int_status);
306 writel(ARCMSR_HBEMU_DOORBELL_SYNC, &acb->pmuE->iobound_doorbell);
307 acb->in_doorbell = 0;
308 acb->out_doorbell = 0;
309 break;
310 }
311 }
312 return true;
313}
314
315static void arcmsr_unmap_pciregion(struct AdapterControlBlock *acb)
316{
317 switch (acb->adapter_type) {
318 case ACB_ADAPTER_TYPE_A:{
319 iounmap(acb->pmuA);
320 }
321 break;
322 case ACB_ADAPTER_TYPE_B:{
323 iounmap(acb->mem_base0);
324 iounmap(acb->mem_base1);
325 }
326
327 break;
328 case ACB_ADAPTER_TYPE_C:{
329 iounmap(acb->pmuC);
330 }
331 break;
332 case ACB_ADAPTER_TYPE_D:
333 iounmap(acb->mem_base0);
334 break;
335 case ACB_ADAPTER_TYPE_E:
336 iounmap(acb->pmuE);
337 break;
338 }
339}
340
341static irqreturn_t arcmsr_do_interrupt(int irq, void *dev_id)
342{
343 irqreturn_t handle_state;
344 struct AdapterControlBlock *acb = dev_id;
345
346 handle_state = arcmsr_interrupt(acb);
347 return handle_state;
348}
349
350static int arcmsr_bios_param(struct scsi_device *sdev,
351 struct block_device *bdev, sector_t capacity, int *geom)
352{
353 int heads, sectors, cylinders, total_capacity;
354
355 if (scsi_partsize(bdev, capacity, geom))
356 return 0;
357
358 total_capacity = capacity;
359 heads = 64;
360 sectors = 32;
361 cylinders = total_capacity / (heads * sectors);
362 if (cylinders > 1024) {
363 heads = 255;
364 sectors = 63;
365 cylinders = total_capacity / (heads * sectors);
366 }
367 geom[0] = heads;
368 geom[1] = sectors;
369 geom[2] = cylinders;
370 return 0;
371}
372
373static uint8_t arcmsr_hbaA_wait_msgint_ready(struct AdapterControlBlock *acb)
374{
375 struct MessageUnit_A __iomem *reg = acb->pmuA;
376 int i;
377
378 for (i = 0; i < 2000; i++) {
379 if (readl(®->outbound_intstatus) &
380 ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
381 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT,
382 ®->outbound_intstatus);
383 return true;
384 }
385 msleep(10);
386 }
387
388 return false;
389}
390
391static uint8_t arcmsr_hbaB_wait_msgint_ready(struct AdapterControlBlock *acb)
392{
393 struct MessageUnit_B *reg = acb->pmuB;
394 int i;
395
396 for (i = 0; i < 2000; i++) {
397 if (readl(reg->iop2drv_doorbell)
398 & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
399 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN,
400 reg->iop2drv_doorbell);
401 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT,
402 reg->drv2iop_doorbell);
403 return true;
404 }
405 msleep(10);
406 }
407
408 return false;
409}
410
411static uint8_t arcmsr_hbaC_wait_msgint_ready(struct AdapterControlBlock *pACB)
412{
413 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
414 int i;
415
416 for (i = 0; i < 2000; i++) {
417 if (readl(&phbcmu->outbound_doorbell)
418 & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
419 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR,
420 &phbcmu->outbound_doorbell_clear);
421 return true;
422 }
423 msleep(10);
424 }
425
426 return false;
427}
428
429static bool arcmsr_hbaD_wait_msgint_ready(struct AdapterControlBlock *pACB)
430{
431 struct MessageUnit_D *reg = pACB->pmuD;
432 int i;
433
434 for (i = 0; i < 2000; i++) {
435 if (readl(reg->outbound_doorbell)
436 & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) {
437 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE,
438 reg->outbound_doorbell);
439 return true;
440 }
441 msleep(10);
442 }
443 return false;
444}
445
446static bool arcmsr_hbaE_wait_msgint_ready(struct AdapterControlBlock *pACB)
447{
448 int i;
449 uint32_t read_doorbell;
450 struct MessageUnit_E __iomem *phbcmu = pACB->pmuE;
451
452 for (i = 0; i < 2000; i++) {
453 read_doorbell = readl(&phbcmu->iobound_doorbell);
454 if ((read_doorbell ^ pACB->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
455 writel(0, &phbcmu->host_int_status);
456 pACB->in_doorbell = read_doorbell;
457 return true;
458 }
459 msleep(10);
460 }
461 return false;
462}
463
464static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb)
465{
466 struct MessageUnit_A __iomem *reg = acb->pmuA;
467 int retry_count = 30;
468 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0);
469 do {
470 if (arcmsr_hbaA_wait_msgint_ready(acb))
471 break;
472 else {
473 retry_count--;
474 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
475 timeout, retry count down = %d \n", acb->host->host_no, retry_count);
476 }
477 } while (retry_count != 0);
478}
479
480static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb)
481{
482 struct MessageUnit_B *reg = acb->pmuB;
483 int retry_count = 30;
484 writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell);
485 do {
486 if (arcmsr_hbaB_wait_msgint_ready(acb))
487 break;
488 else {
489 retry_count--;
490 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
491 timeout,retry count down = %d \n", acb->host->host_no, retry_count);
492 }
493 } while (retry_count != 0);
494}
495
496static void arcmsr_hbaC_flush_cache(struct AdapterControlBlock *pACB)
497{
498 struct MessageUnit_C __iomem *reg = pACB->pmuC;
499 int retry_count = 30;
500 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0);
501 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
502 do {
503 if (arcmsr_hbaC_wait_msgint_ready(pACB)) {
504 break;
505 } else {
506 retry_count--;
507 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
508 timeout,retry count down = %d \n", pACB->host->host_no, retry_count);
509 }
510 } while (retry_count != 0);
511 return;
512}
513
514static void arcmsr_hbaD_flush_cache(struct AdapterControlBlock *pACB)
515{
516 int retry_count = 15;
517 struct MessageUnit_D *reg = pACB->pmuD;
518
519 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, reg->inbound_msgaddr0);
520 do {
521 if (arcmsr_hbaD_wait_msgint_ready(pACB))
522 break;
523
524 retry_count--;
525 pr_notice("arcmsr%d: wait 'flush adapter "
526 "cache' timeout, retry count down = %d\n",
527 pACB->host->host_no, retry_count);
528 } while (retry_count != 0);
529}
530
531static void arcmsr_hbaE_flush_cache(struct AdapterControlBlock *pACB)
532{
533 int retry_count = 30;
534 struct MessageUnit_E __iomem *reg = pACB->pmuE;
535
536 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0);
537 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
538 writel(pACB->out_doorbell, ®->iobound_doorbell);
539 do {
540 if (arcmsr_hbaE_wait_msgint_ready(pACB))
541 break;
542 retry_count--;
543 pr_notice("arcmsr%d: wait 'flush adapter "
544 "cache' timeout, retry count down = %d\n",
545 pACB->host->host_no, retry_count);
546 } while (retry_count != 0);
547}
548
549static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
550{
551 switch (acb->adapter_type) {
552
553 case ACB_ADAPTER_TYPE_A: {
554 arcmsr_hbaA_flush_cache(acb);
555 }
556 break;
557
558 case ACB_ADAPTER_TYPE_B: {
559 arcmsr_hbaB_flush_cache(acb);
560 }
561 break;
562 case ACB_ADAPTER_TYPE_C: {
563 arcmsr_hbaC_flush_cache(acb);
564 }
565 break;
566 case ACB_ADAPTER_TYPE_D:
567 arcmsr_hbaD_flush_cache(acb);
568 break;
569 case ACB_ADAPTER_TYPE_E:
570 arcmsr_hbaE_flush_cache(acb);
571 break;
572 }
573}
574
575static bool arcmsr_alloc_io_queue(struct AdapterControlBlock *acb)
576{
577 bool rtn = true;
578 void *dma_coherent;
579 dma_addr_t dma_coherent_handle;
580 struct pci_dev *pdev = acb->pdev;
581
582 switch (acb->adapter_type) {
583 case ACB_ADAPTER_TYPE_B: {
584 struct MessageUnit_B *reg;
585 acb->roundup_ccbsize = roundup(sizeof(struct MessageUnit_B), 32);
586 dma_coherent = dma_zalloc_coherent(&pdev->dev, acb->roundup_ccbsize,
587 &dma_coherent_handle, GFP_KERNEL);
588 if (!dma_coherent) {
589 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no);
590 return false;
591 }
592 acb->dma_coherent_handle2 = dma_coherent_handle;
593 acb->dma_coherent2 = dma_coherent;
594 reg = (struct MessageUnit_B *)dma_coherent;
595 acb->pmuB = reg;
596 if (acb->pdev->device == PCI_DEVICE_ID_ARECA_1203) {
597 reg->drv2iop_doorbell = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_1203);
598 reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK_1203);
599 reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_1203);
600 reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK_1203);
601 } else {
602 reg->drv2iop_doorbell = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL);
603 reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK);
604 reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL);
605 reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK);
606 }
607 reg->message_wbuffer = MEM_BASE1(ARCMSR_MESSAGE_WBUFFER);
608 reg->message_rbuffer = MEM_BASE1(ARCMSR_MESSAGE_RBUFFER);
609 reg->message_rwbuffer = MEM_BASE1(ARCMSR_MESSAGE_RWBUFFER);
610 }
611 break;
612 case ACB_ADAPTER_TYPE_D: {
613 struct MessageUnit_D *reg;
614
615 acb->roundup_ccbsize = roundup(sizeof(struct MessageUnit_D), 32);
616 dma_coherent = dma_zalloc_coherent(&pdev->dev, acb->roundup_ccbsize,
617 &dma_coherent_handle, GFP_KERNEL);
618 if (!dma_coherent) {
619 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no);
620 return false;
621 }
622 acb->dma_coherent_handle2 = dma_coherent_handle;
623 acb->dma_coherent2 = dma_coherent;
624 reg = (struct MessageUnit_D *)dma_coherent;
625 acb->pmuD = reg;
626 reg->chip_id = MEM_BASE0(ARCMSR_ARC1214_CHIP_ID);
627 reg->cpu_mem_config = MEM_BASE0(ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION);
628 reg->i2o_host_interrupt_mask = MEM_BASE0(ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK);
629 reg->sample_at_reset = MEM_BASE0(ARCMSR_ARC1214_SAMPLE_RESET);
630 reg->reset_request = MEM_BASE0(ARCMSR_ARC1214_RESET_REQUEST);
631 reg->host_int_status = MEM_BASE0(ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS);
632 reg->pcief0_int_enable = MEM_BASE0(ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE);
633 reg->inbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE0);
634 reg->inbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE1);
635 reg->outbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE0);
636 reg->outbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE1);
637 reg->inbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_INBOUND_DOORBELL);
638 reg->outbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL);
639 reg->outbound_doorbell_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE);
640 reg->inboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW);
641 reg->inboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH);
642 reg->inboundlist_write_pointer = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER);
643 reg->outboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW);
644 reg->outboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH);
645 reg->outboundlist_copy_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER);
646 reg->outboundlist_read_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER);
647 reg->outboundlist_interrupt_cause = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE);
648 reg->outboundlist_interrupt_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE);
649 reg->message_wbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_WBUFFER);
650 reg->message_rbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RBUFFER);
651 reg->msgcode_rwbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RWBUFFER);
652 }
653 break;
654 case ACB_ADAPTER_TYPE_E: {
655 uint32_t completeQ_size;
656 completeQ_size = sizeof(struct deliver_completeQ) * ARCMSR_MAX_HBE_DONEQUEUE + 128;
657 acb->roundup_ccbsize = roundup(completeQ_size, 32);
658 dma_coherent = dma_zalloc_coherent(&pdev->dev, acb->roundup_ccbsize,
659 &dma_coherent_handle, GFP_KERNEL);
660 if (!dma_coherent){
661 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no);
662 return false;
663 }
664 acb->dma_coherent_handle2 = dma_coherent_handle;
665 acb->dma_coherent2 = dma_coherent;
666 acb->pCompletionQ = dma_coherent;
667 acb->completionQ_entry = acb->roundup_ccbsize / sizeof(struct deliver_completeQ);
668 acb->doneq_index = 0;
669 }
670 break;
671 default:
672 break;
673 }
674 return rtn;
675}
676
677static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb)
678{
679 struct pci_dev *pdev = acb->pdev;
680 void *dma_coherent;
681 dma_addr_t dma_coherent_handle;
682 struct CommandControlBlock *ccb_tmp;
683 int i = 0, j = 0;
684 dma_addr_t cdb_phyaddr;
685 unsigned long roundup_ccbsize;
686 unsigned long max_xfer_len;
687 unsigned long max_sg_entrys;
688 uint32_t firm_config_version;
689
690 for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
691 for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
692 acb->devstate[i][j] = ARECA_RAID_GONE;
693
694 max_xfer_len = ARCMSR_MAX_XFER_LEN;
695 max_sg_entrys = ARCMSR_DEFAULT_SG_ENTRIES;
696 firm_config_version = acb->firm_cfg_version;
697 if((firm_config_version & 0xFF) >= 3){
698 max_xfer_len = (ARCMSR_CDB_SG_PAGE_LENGTH << ((firm_config_version >> 8) & 0xFF)) * 1024;
699 max_sg_entrys = (max_xfer_len/4096);
700 }
701 acb->host->max_sectors = max_xfer_len/512;
702 acb->host->sg_tablesize = max_sg_entrys;
703 roundup_ccbsize = roundup(sizeof(struct CommandControlBlock) + (max_sg_entrys - 1) * sizeof(struct SG64ENTRY), 32);
704 acb->uncache_size = roundup_ccbsize * acb->maxFreeCCB;
705 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->uncache_size, &dma_coherent_handle, GFP_KERNEL);
706 if(!dma_coherent){
707 printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error\n", acb->host->host_no);
708 return -ENOMEM;
709 }
710 acb->dma_coherent = dma_coherent;
711 acb->dma_coherent_handle = dma_coherent_handle;
712 memset(dma_coherent, 0, acb->uncache_size);
713 acb->ccbsize = roundup_ccbsize;
714 ccb_tmp = dma_coherent;
715 acb->vir2phy_offset = (unsigned long)dma_coherent - (unsigned long)dma_coherent_handle;
716 for(i = 0; i < acb->maxFreeCCB; i++){
717 cdb_phyaddr = dma_coherent_handle + offsetof(struct CommandControlBlock, arcmsr_cdb);
718 switch (acb->adapter_type) {
719 case ACB_ADAPTER_TYPE_A:
720 case ACB_ADAPTER_TYPE_B:
721 ccb_tmp->cdb_phyaddr = cdb_phyaddr >> 5;
722 break;
723 case ACB_ADAPTER_TYPE_C:
724 case ACB_ADAPTER_TYPE_D:
725 case ACB_ADAPTER_TYPE_E:
726 ccb_tmp->cdb_phyaddr = cdb_phyaddr;
727 break;
728 }
729 acb->pccb_pool[i] = ccb_tmp;
730 ccb_tmp->acb = acb;
731 ccb_tmp->smid = (u32)i << 16;
732 INIT_LIST_HEAD(&ccb_tmp->list);
733 list_add_tail(&ccb_tmp->list, &acb->ccb_free_list);
734 ccb_tmp = (struct CommandControlBlock *)((unsigned long)ccb_tmp + roundup_ccbsize);
735 dma_coherent_handle = dma_coherent_handle + roundup_ccbsize;
736 }
737 return 0;
738}
739
740static void arcmsr_message_isr_bh_fn(struct work_struct *work)
741{
742 struct AdapterControlBlock *acb = container_of(work,
743 struct AdapterControlBlock, arcmsr_do_message_isr_bh);
744 char *acb_dev_map = (char *)acb->device_map;
745 uint32_t __iomem *signature = NULL;
746 char __iomem *devicemap = NULL;
747 int target, lun;
748 struct scsi_device *psdev;
749 char diff, temp;
750
751 acb->acb_flags &= ~ACB_F_MSG_GET_CONFIG;
752 switch (acb->adapter_type) {
753 case ACB_ADAPTER_TYPE_A: {
754 struct MessageUnit_A __iomem *reg = acb->pmuA;
755
756 signature = (uint32_t __iomem *)(®->message_rwbuffer[0]);
757 devicemap = (char __iomem *)(®->message_rwbuffer[21]);
758 break;
759 }
760 case ACB_ADAPTER_TYPE_B: {
761 struct MessageUnit_B *reg = acb->pmuB;
762
763 signature = (uint32_t __iomem *)(®->message_rwbuffer[0]);
764 devicemap = (char __iomem *)(®->message_rwbuffer[21]);
765 break;
766 }
767 case ACB_ADAPTER_TYPE_C: {
768 struct MessageUnit_C __iomem *reg = acb->pmuC;
769
770 signature = (uint32_t __iomem *)(®->msgcode_rwbuffer[0]);
771 devicemap = (char __iomem *)(®->msgcode_rwbuffer[21]);
772 break;
773 }
774 case ACB_ADAPTER_TYPE_D: {
775 struct MessageUnit_D *reg = acb->pmuD;
776
777 signature = (uint32_t __iomem *)(®->msgcode_rwbuffer[0]);
778 devicemap = (char __iomem *)(®->msgcode_rwbuffer[21]);
779 break;
780 }
781 case ACB_ADAPTER_TYPE_E: {
782 struct MessageUnit_E __iomem *reg = acb->pmuE;
783
784 signature = (uint32_t __iomem *)(®->msgcode_rwbuffer[0]);
785 devicemap = (char __iomem *)(®->msgcode_rwbuffer[21]);
786 break;
787 }
788 }
789 atomic_inc(&acb->rq_map_token);
790 if (readl(signature) != ARCMSR_SIGNATURE_GET_CONFIG)
791 return;
792 for (target = 0; target < ARCMSR_MAX_TARGETID - 1;
793 target++) {
794 temp = readb(devicemap);
795 diff = (*acb_dev_map) ^ temp;
796 if (diff != 0) {
797 *acb_dev_map = temp;
798 for (lun = 0; lun < ARCMSR_MAX_TARGETLUN;
799 lun++) {
800 if ((diff & 0x01) == 1 &&
801 (temp & 0x01) == 1) {
802 scsi_add_device(acb->host,
803 0, target, lun);
804 } else if ((diff & 0x01) == 1
805 && (temp & 0x01) == 0) {
806 psdev = scsi_device_lookup(acb->host,
807 0, target, lun);
808 if (psdev != NULL) {
809 scsi_remove_device(psdev);
810 scsi_device_put(psdev);
811 }
812 }
813 temp >>= 1;
814 diff >>= 1;
815 }
816 }
817 devicemap++;
818 acb_dev_map++;
819 }
820}
821
822static int
823arcmsr_request_irq(struct pci_dev *pdev, struct AdapterControlBlock *acb)
824{
825 unsigned long flags;
826 int nvec, i;
827
828 if (msix_enable == 0)
829 goto msi_int0;
830 nvec = pci_alloc_irq_vectors(pdev, 1, ARCMST_NUM_MSIX_VECTORS,
831 PCI_IRQ_MSIX);
832 if (nvec > 0) {
833 pr_info("arcmsr%d: msi-x enabled\n", acb->host->host_no);
834 flags = 0;
835 } else {
836msi_int0:
837 if (msi_enable == 1) {
838 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
839 if (nvec == 1) {
840 dev_info(&pdev->dev, "msi enabled\n");
841 goto msi_int1;
842 }
843 }
844 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY);
845 if (nvec < 1)
846 return FAILED;
847msi_int1:
848 flags = IRQF_SHARED;
849 }
850
851 acb->vector_count = nvec;
852 for (i = 0; i < nvec; i++) {
853 if (request_irq(pci_irq_vector(pdev, i), arcmsr_do_interrupt,
854 flags, "arcmsr", acb)) {
855 pr_warn("arcmsr%d: request_irq =%d failed!\n",
856 acb->host->host_no, pci_irq_vector(pdev, i));
857 goto out_free_irq;
858 }
859 }
860
861 return SUCCESS;
862out_free_irq:
863 while (--i >= 0)
864 free_irq(pci_irq_vector(pdev, i), acb);
865 pci_free_irq_vectors(pdev);
866 return FAILED;
867}
868
869static void arcmsr_init_get_devmap_timer(struct AdapterControlBlock *pacb)
870{
871 INIT_WORK(&pacb->arcmsr_do_message_isr_bh, arcmsr_message_isr_bh_fn);
872 atomic_set(&pacb->rq_map_token, 16);
873 atomic_set(&pacb->ante_token_value, 16);
874 pacb->fw_flag = FW_NORMAL;
875 timer_setup(&pacb->eternal_timer, arcmsr_request_device_map, 0);
876 pacb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ);
877 add_timer(&pacb->eternal_timer);
878}
879
880static void arcmsr_init_set_datetime_timer(struct AdapterControlBlock *pacb)
881{
882 timer_setup(&pacb->refresh_timer, arcmsr_set_iop_datetime, 0);
883 pacb->refresh_timer.expires = jiffies + msecs_to_jiffies(60 * 1000);
884 add_timer(&pacb->refresh_timer);
885}
886
887static int arcmsr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
888{
889 struct Scsi_Host *host;
890 struct AdapterControlBlock *acb;
891 uint8_t bus,dev_fun;
892 int error;
893 error = pci_enable_device(pdev);
894 if(error){
895 return -ENODEV;
896 }
897 host = scsi_host_alloc(&arcmsr_scsi_host_template, sizeof(struct AdapterControlBlock));
898 if(!host){
899 goto pci_disable_dev;
900 }
901 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
902 if(error){
903 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
904 if(error){
905 printk(KERN_WARNING
906 "scsi%d: No suitable DMA mask available\n",
907 host->host_no);
908 goto scsi_host_release;
909 }
910 }
911 init_waitqueue_head(&wait_q);
912 bus = pdev->bus->number;
913 dev_fun = pdev->devfn;
914 acb = (struct AdapterControlBlock *) host->hostdata;
915 memset(acb,0,sizeof(struct AdapterControlBlock));
916 acb->pdev = pdev;
917 acb->host = host;
918 host->max_lun = ARCMSR_MAX_TARGETLUN;
919 host->max_id = ARCMSR_MAX_TARGETID;
920 host->max_cmd_len = 16;
921 if ((host_can_queue < ARCMSR_MIN_OUTSTANDING_CMD) || (host_can_queue > ARCMSR_MAX_OUTSTANDING_CMD))
922 host_can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD;
923 host->can_queue = host_can_queue;
924 if ((cmd_per_lun < ARCMSR_MIN_CMD_PERLUN) || (cmd_per_lun > ARCMSR_MAX_CMD_PERLUN))
925 cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN;
926 host->cmd_per_lun = cmd_per_lun;
927 host->this_id = ARCMSR_SCSI_INITIATOR_ID;
928 host->unique_id = (bus << 8) | dev_fun;
929 pci_set_drvdata(pdev, host);
930 pci_set_master(pdev);
931 error = pci_request_regions(pdev, "arcmsr");
932 if(error){
933 goto scsi_host_release;
934 }
935 spin_lock_init(&acb->eh_lock);
936 spin_lock_init(&acb->ccblist_lock);
937 spin_lock_init(&acb->postq_lock);
938 spin_lock_init(&acb->doneq_lock);
939 spin_lock_init(&acb->rqbuffer_lock);
940 spin_lock_init(&acb->wqbuffer_lock);
941 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
942 ACB_F_MESSAGE_RQBUFFER_CLEARED |
943 ACB_F_MESSAGE_WQBUFFER_READED);
944 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
945 INIT_LIST_HEAD(&acb->ccb_free_list);
946 acb->adapter_type = id->driver_data;
947 error = arcmsr_remap_pciregion(acb);
948 if(!error){
949 goto pci_release_regs;
950 }
951 error = arcmsr_alloc_io_queue(acb);
952 if (!error)
953 goto unmap_pci_region;
954 error = arcmsr_get_firmware_spec(acb);
955 if(!error){
956 goto free_hbb_mu;
957 }
958 error = arcmsr_alloc_ccb_pool(acb);
959 if(error){
960 goto free_hbb_mu;
961 }
962 error = scsi_add_host(host, &pdev->dev);
963 if(error){
964 goto free_ccb_pool;
965 }
966 if (arcmsr_request_irq(pdev, acb) == FAILED)
967 goto scsi_host_remove;
968 arcmsr_iop_init(acb);
969 arcmsr_init_get_devmap_timer(acb);
970 if (set_date_time)
971 arcmsr_init_set_datetime_timer(acb);
972 if(arcmsr_alloc_sysfs_attr(acb))
973 goto out_free_sysfs;
974 scsi_scan_host(host);
975 return 0;
976out_free_sysfs:
977 if (set_date_time)
978 del_timer_sync(&acb->refresh_timer);
979 del_timer_sync(&acb->eternal_timer);
980 flush_work(&acb->arcmsr_do_message_isr_bh);
981 arcmsr_stop_adapter_bgrb(acb);
982 arcmsr_flush_adapter_cache(acb);
983 arcmsr_free_irq(pdev, acb);
984scsi_host_remove:
985 scsi_remove_host(host);
986free_ccb_pool:
987 arcmsr_free_ccb_pool(acb);
988free_hbb_mu:
989 arcmsr_free_mu(acb);
990unmap_pci_region:
991 arcmsr_unmap_pciregion(acb);
992pci_release_regs:
993 pci_release_regions(pdev);
994scsi_host_release:
995 scsi_host_put(host);
996pci_disable_dev:
997 pci_disable_device(pdev);
998 return -ENODEV;
999}
1000
1001static void arcmsr_free_irq(struct pci_dev *pdev,
1002 struct AdapterControlBlock *acb)
1003{
1004 int i;
1005
1006 for (i = 0; i < acb->vector_count; i++)
1007 free_irq(pci_irq_vector(pdev, i), acb);
1008 pci_free_irq_vectors(pdev);
1009}
1010
1011static int arcmsr_suspend(struct pci_dev *pdev, pm_message_t state)
1012{
1013 uint32_t intmask_org;
1014 struct Scsi_Host *host = pci_get_drvdata(pdev);
1015 struct AdapterControlBlock *acb =
1016 (struct AdapterControlBlock *)host->hostdata;
1017
1018 intmask_org = arcmsr_disable_outbound_ints(acb);
1019 arcmsr_free_irq(pdev, acb);
1020 del_timer_sync(&acb->eternal_timer);
1021 if (set_date_time)
1022 del_timer_sync(&acb->refresh_timer);
1023 flush_work(&acb->arcmsr_do_message_isr_bh);
1024 arcmsr_stop_adapter_bgrb(acb);
1025 arcmsr_flush_adapter_cache(acb);
1026 pci_set_drvdata(pdev, host);
1027 pci_save_state(pdev);
1028 pci_disable_device(pdev);
1029 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1030 return 0;
1031}
1032
1033static int arcmsr_resume(struct pci_dev *pdev)
1034{
1035 int error;
1036 struct Scsi_Host *host = pci_get_drvdata(pdev);
1037 struct AdapterControlBlock *acb =
1038 (struct AdapterControlBlock *)host->hostdata;
1039
1040 pci_set_power_state(pdev, PCI_D0);
1041 pci_enable_wake(pdev, PCI_D0, 0);
1042 pci_restore_state(pdev);
1043 if (pci_enable_device(pdev)) {
1044 pr_warn("%s: pci_enable_device error\n", __func__);
1045 return -ENODEV;
1046 }
1047 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1048 if (error) {
1049 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1050 if (error) {
1051 pr_warn("scsi%d: No suitable DMA mask available\n",
1052 host->host_no);
1053 goto controller_unregister;
1054 }
1055 }
1056 pci_set_master(pdev);
1057 if (arcmsr_request_irq(pdev, acb) == FAILED)
1058 goto controller_stop;
1059 arcmsr_iop_init(acb);
1060 arcmsr_init_get_devmap_timer(acb);
1061 if (set_date_time)
1062 arcmsr_init_set_datetime_timer(acb);
1063 return 0;
1064controller_stop:
1065 arcmsr_stop_adapter_bgrb(acb);
1066 arcmsr_flush_adapter_cache(acb);
1067controller_unregister:
1068 scsi_remove_host(host);
1069 arcmsr_free_ccb_pool(acb);
1070 arcmsr_unmap_pciregion(acb);
1071 pci_release_regions(pdev);
1072 scsi_host_put(host);
1073 pci_disable_device(pdev);
1074 return -ENODEV;
1075}
1076
1077static uint8_t arcmsr_hbaA_abort_allcmd(struct AdapterControlBlock *acb)
1078{
1079 struct MessageUnit_A __iomem *reg = acb->pmuA;
1080 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, ®->inbound_msgaddr0);
1081 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
1082 printk(KERN_NOTICE
1083 "arcmsr%d: wait 'abort all outstanding command' timeout\n"
1084 , acb->host->host_no);
1085 return false;
1086 }
1087 return true;
1088}
1089
1090static uint8_t arcmsr_hbaB_abort_allcmd(struct AdapterControlBlock *acb)
1091{
1092 struct MessageUnit_B *reg = acb->pmuB;
1093
1094 writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell);
1095 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
1096 printk(KERN_NOTICE
1097 "arcmsr%d: wait 'abort all outstanding command' timeout\n"
1098 , acb->host->host_no);
1099 return false;
1100 }
1101 return true;
1102}
1103static uint8_t arcmsr_hbaC_abort_allcmd(struct AdapterControlBlock *pACB)
1104{
1105 struct MessageUnit_C __iomem *reg = pACB->pmuC;
1106 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, ®->inbound_msgaddr0);
1107 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
1108 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
1109 printk(KERN_NOTICE
1110 "arcmsr%d: wait 'abort all outstanding command' timeout\n"
1111 , pACB->host->host_no);
1112 return false;
1113 }
1114 return true;
1115}
1116
1117static uint8_t arcmsr_hbaD_abort_allcmd(struct AdapterControlBlock *pACB)
1118{
1119 struct MessageUnit_D *reg = pACB->pmuD;
1120
1121 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, reg->inbound_msgaddr0);
1122 if (!arcmsr_hbaD_wait_msgint_ready(pACB)) {
1123 pr_notice("arcmsr%d: wait 'abort all outstanding "
1124 "command' timeout\n", pACB->host->host_no);
1125 return false;
1126 }
1127 return true;
1128}
1129
1130static uint8_t arcmsr_hbaE_abort_allcmd(struct AdapterControlBlock *pACB)
1131{
1132 struct MessageUnit_E __iomem *reg = pACB->pmuE;
1133
1134 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, ®->inbound_msgaddr0);
1135 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
1136 writel(pACB->out_doorbell, ®->iobound_doorbell);
1137 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
1138 pr_notice("arcmsr%d: wait 'abort all outstanding "
1139 "command' timeout\n", pACB->host->host_no);
1140 return false;
1141 }
1142 return true;
1143}
1144
1145static uint8_t arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
1146{
1147 uint8_t rtnval = 0;
1148 switch (acb->adapter_type) {
1149 case ACB_ADAPTER_TYPE_A: {
1150 rtnval = arcmsr_hbaA_abort_allcmd(acb);
1151 }
1152 break;
1153
1154 case ACB_ADAPTER_TYPE_B: {
1155 rtnval = arcmsr_hbaB_abort_allcmd(acb);
1156 }
1157 break;
1158
1159 case ACB_ADAPTER_TYPE_C: {
1160 rtnval = arcmsr_hbaC_abort_allcmd(acb);
1161 }
1162 break;
1163
1164 case ACB_ADAPTER_TYPE_D:
1165 rtnval = arcmsr_hbaD_abort_allcmd(acb);
1166 break;
1167 case ACB_ADAPTER_TYPE_E:
1168 rtnval = arcmsr_hbaE_abort_allcmd(acb);
1169 break;
1170 }
1171 return rtnval;
1172}
1173
1174static void arcmsr_pci_unmap_dma(struct CommandControlBlock *ccb)
1175{
1176 struct scsi_cmnd *pcmd = ccb->pcmd;
1177
1178 scsi_dma_unmap(pcmd);
1179}
1180
1181static void arcmsr_ccb_complete(struct CommandControlBlock *ccb)
1182{
1183 struct AdapterControlBlock *acb = ccb->acb;
1184 struct scsi_cmnd *pcmd = ccb->pcmd;
1185 unsigned long flags;
1186 atomic_dec(&acb->ccboutstandingcount);
1187 arcmsr_pci_unmap_dma(ccb);
1188 ccb->startdone = ARCMSR_CCB_DONE;
1189 spin_lock_irqsave(&acb->ccblist_lock, flags);
1190 list_add_tail(&ccb->list, &acb->ccb_free_list);
1191 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
1192 pcmd->scsi_done(pcmd);
1193}
1194
1195static void arcmsr_report_sense_info(struct CommandControlBlock *ccb)
1196{
1197
1198 struct scsi_cmnd *pcmd = ccb->pcmd;
1199 struct SENSE_DATA *sensebuffer = (struct SENSE_DATA *)pcmd->sense_buffer;
1200 pcmd->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
1201 if (sensebuffer) {
1202 int sense_data_length =
1203 sizeof(struct SENSE_DATA) < SCSI_SENSE_BUFFERSIZE
1204 ? sizeof(struct SENSE_DATA) : SCSI_SENSE_BUFFERSIZE;
1205 memset(sensebuffer, 0, SCSI_SENSE_BUFFERSIZE);
1206 memcpy(sensebuffer, ccb->arcmsr_cdb.SenseData, sense_data_length);
1207 sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
1208 sensebuffer->Valid = 1;
1209 pcmd->result |= (DRIVER_SENSE << 24);
1210 }
1211}
1212
1213static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb)
1214{
1215 u32 orig_mask = 0;
1216 switch (acb->adapter_type) {
1217 case ACB_ADAPTER_TYPE_A : {
1218 struct MessageUnit_A __iomem *reg = acb->pmuA;
1219 orig_mask = readl(®->outbound_intmask);
1220 writel(orig_mask|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, \
1221 ®->outbound_intmask);
1222 }
1223 break;
1224 case ACB_ADAPTER_TYPE_B : {
1225 struct MessageUnit_B *reg = acb->pmuB;
1226 orig_mask = readl(reg->iop2drv_doorbell_mask);
1227 writel(0, reg->iop2drv_doorbell_mask);
1228 }
1229 break;
1230 case ACB_ADAPTER_TYPE_C:{
1231 struct MessageUnit_C __iomem *reg = acb->pmuC;
1232
1233 orig_mask = readl(®->host_int_mask);
1234 writel(orig_mask|ARCMSR_HBCMU_ALL_INTMASKENABLE, ®->host_int_mask);
1235 }
1236 break;
1237 case ACB_ADAPTER_TYPE_D: {
1238 struct MessageUnit_D *reg = acb->pmuD;
1239
1240 writel(ARCMSR_ARC1214_ALL_INT_DISABLE, reg->pcief0_int_enable);
1241 }
1242 break;
1243 case ACB_ADAPTER_TYPE_E: {
1244 struct MessageUnit_E __iomem *reg = acb->pmuE;
1245 orig_mask = readl(®->host_int_mask);
1246 writel(orig_mask | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR, ®->host_int_mask);
1247 readl(®->host_int_mask);
1248 }
1249 break;
1250 }
1251 return orig_mask;
1252}
1253
1254static void arcmsr_report_ccb_state(struct AdapterControlBlock *acb,
1255 struct CommandControlBlock *ccb, bool error)
1256{
1257 uint8_t id, lun;
1258 id = ccb->pcmd->device->id;
1259 lun = ccb->pcmd->device->lun;
1260 if (!error) {
1261 if (acb->devstate[id][lun] == ARECA_RAID_GONE)
1262 acb->devstate[id][lun] = ARECA_RAID_GOOD;
1263 ccb->pcmd->result = DID_OK << 16;
1264 arcmsr_ccb_complete(ccb);
1265 }else{
1266 switch (ccb->arcmsr_cdb.DeviceStatus) {
1267 case ARCMSR_DEV_SELECT_TIMEOUT: {
1268 acb->devstate[id][lun] = ARECA_RAID_GONE;
1269 ccb->pcmd->result = DID_NO_CONNECT << 16;
1270 arcmsr_ccb_complete(ccb);
1271 }
1272 break;
1273
1274 case ARCMSR_DEV_ABORTED:
1275
1276 case ARCMSR_DEV_INIT_FAIL: {
1277 acb->devstate[id][lun] = ARECA_RAID_GONE;
1278 ccb->pcmd->result = DID_BAD_TARGET << 16;
1279 arcmsr_ccb_complete(ccb);
1280 }
1281 break;
1282
1283 case ARCMSR_DEV_CHECK_CONDITION: {
1284 acb->devstate[id][lun] = ARECA_RAID_GOOD;
1285 arcmsr_report_sense_info(ccb);
1286 arcmsr_ccb_complete(ccb);
1287 }
1288 break;
1289
1290 default:
1291 printk(KERN_NOTICE
1292 "arcmsr%d: scsi id = %d lun = %d isr get command error done, \
1293 but got unknown DeviceStatus = 0x%x \n"
1294 , acb->host->host_no
1295 , id
1296 , lun
1297 , ccb->arcmsr_cdb.DeviceStatus);
1298 acb->devstate[id][lun] = ARECA_RAID_GONE;
1299 ccb->pcmd->result = DID_NO_CONNECT << 16;
1300 arcmsr_ccb_complete(ccb);
1301 break;
1302 }
1303 }
1304}
1305
1306static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, struct CommandControlBlock *pCCB, bool error)
1307{
1308 int id, lun;
1309 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
1310 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
1311 struct scsi_cmnd *abortcmd = pCCB->pcmd;
1312 if (abortcmd) {
1313 id = abortcmd->device->id;
1314 lun = abortcmd->device->lun;
1315 abortcmd->result |= DID_ABORT << 16;
1316 arcmsr_ccb_complete(pCCB);
1317 printk(KERN_NOTICE "arcmsr%d: pCCB ='0x%p' isr got aborted command \n",
1318 acb->host->host_no, pCCB);
1319 }
1320 return;
1321 }
1322 printk(KERN_NOTICE "arcmsr%d: isr get an illegal ccb command \
1323 done acb = '0x%p'"
1324 "ccb = '0x%p' ccbacb = '0x%p' startdone = 0x%x"
1325 " ccboutstandingcount = %d \n"
1326 , acb->host->host_no
1327 , acb
1328 , pCCB
1329 , pCCB->acb
1330 , pCCB->startdone
1331 , atomic_read(&acb->ccboutstandingcount));
1332 return;
1333 }
1334 arcmsr_report_ccb_state(acb, pCCB, error);
1335}
1336
1337static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
1338{
1339 int i = 0;
1340 uint32_t flag_ccb, ccb_cdb_phy;
1341 struct ARCMSR_CDB *pARCMSR_CDB;
1342 bool error;
1343 struct CommandControlBlock *pCCB;
1344 switch (acb->adapter_type) {
1345
1346 case ACB_ADAPTER_TYPE_A: {
1347 struct MessageUnit_A __iomem *reg = acb->pmuA;
1348 uint32_t outbound_intstatus;
1349 outbound_intstatus = readl(®->outbound_intstatus) &
1350 acb->outbound_int_enable;
1351
1352 writel(outbound_intstatus, ®->outbound_intstatus);
1353 while(((flag_ccb = readl(®->outbound_queueport)) != 0xFFFFFFFF)
1354 && (i++ < acb->maxOutstanding)) {
1355 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
1356 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1357 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
1358 arcmsr_drain_donequeue(acb, pCCB, error);
1359 }
1360 }
1361 break;
1362
1363 case ACB_ADAPTER_TYPE_B: {
1364 struct MessageUnit_B *reg = acb->pmuB;
1365
1366 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
1367 for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
1368 flag_ccb = reg->done_qbuffer[i];
1369 if (flag_ccb != 0) {
1370 reg->done_qbuffer[i] = 0;
1371 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));
1372 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1373 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
1374 arcmsr_drain_donequeue(acb, pCCB, error);
1375 }
1376 reg->post_qbuffer[i] = 0;
1377 }
1378 reg->doneq_index = 0;
1379 reg->postq_index = 0;
1380 }
1381 break;
1382 case ACB_ADAPTER_TYPE_C: {
1383 struct MessageUnit_C __iomem *reg = acb->pmuC;
1384 while ((readl(®->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < acb->maxOutstanding)) {
1385
1386 flag_ccb = readl(®->outbound_queueport_low);
1387 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
1388 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+ccb_cdb_phy);
1389 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1390 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
1391 arcmsr_drain_donequeue(acb, pCCB, error);
1392 }
1393 }
1394 break;
1395 case ACB_ADAPTER_TYPE_D: {
1396 struct MessageUnit_D *pmu = acb->pmuD;
1397 uint32_t outbound_write_pointer;
1398 uint32_t doneq_index, index_stripped, addressLow, residual, toggle;
1399 unsigned long flags;
1400
1401 residual = atomic_read(&acb->ccboutstandingcount);
1402 for (i = 0; i < residual; i++) {
1403 spin_lock_irqsave(&acb->doneq_lock, flags);
1404 outbound_write_pointer =
1405 pmu->done_qbuffer[0].addressLow + 1;
1406 doneq_index = pmu->doneq_index;
1407 if ((doneq_index & 0xFFF) !=
1408 (outbound_write_pointer & 0xFFF)) {
1409 toggle = doneq_index & 0x4000;
1410 index_stripped = (doneq_index & 0xFFF) + 1;
1411 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
1412 pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
1413 ((toggle ^ 0x4000) + 1);
1414 doneq_index = pmu->doneq_index;
1415 spin_unlock_irqrestore(&acb->doneq_lock, flags);
1416 addressLow = pmu->done_qbuffer[doneq_index &
1417 0xFFF].addressLow;
1418 ccb_cdb_phy = (addressLow & 0xFFFFFFF0);
1419 pARCMSR_CDB = (struct ARCMSR_CDB *)
1420 (acb->vir2phy_offset + ccb_cdb_phy);
1421 pCCB = container_of(pARCMSR_CDB,
1422 struct CommandControlBlock, arcmsr_cdb);
1423 error = (addressLow &
1424 ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ?
1425 true : false;
1426 arcmsr_drain_donequeue(acb, pCCB, error);
1427 writel(doneq_index,
1428 pmu->outboundlist_read_pointer);
1429 } else {
1430 spin_unlock_irqrestore(&acb->doneq_lock, flags);
1431 mdelay(10);
1432 }
1433 }
1434 pmu->postq_index = 0;
1435 pmu->doneq_index = 0x40FF;
1436 }
1437 break;
1438 case ACB_ADAPTER_TYPE_E:
1439 arcmsr_hbaE_postqueue_isr(acb);
1440 break;
1441 }
1442}
1443
1444static void arcmsr_remove_scsi_devices(struct AdapterControlBlock *acb)
1445{
1446 char *acb_dev_map = (char *)acb->device_map;
1447 int target, lun, i;
1448 struct scsi_device *psdev;
1449 struct CommandControlBlock *ccb;
1450 char temp;
1451
1452 for (i = 0; i < acb->maxFreeCCB; i++) {
1453 ccb = acb->pccb_pool[i];
1454 if (ccb->startdone == ARCMSR_CCB_START) {
1455 ccb->pcmd->result = DID_NO_CONNECT << 16;
1456 arcmsr_pci_unmap_dma(ccb);
1457 ccb->pcmd->scsi_done(ccb->pcmd);
1458 }
1459 }
1460 for (target = 0; target < ARCMSR_MAX_TARGETID; target++) {
1461 temp = *acb_dev_map;
1462 if (temp) {
1463 for (lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) {
1464 if (temp & 1) {
1465 psdev = scsi_device_lookup(acb->host,
1466 0, target, lun);
1467 if (psdev != NULL) {
1468 scsi_remove_device(psdev);
1469 scsi_device_put(psdev);
1470 }
1471 }
1472 temp >>= 1;
1473 }
1474 *acb_dev_map = 0;
1475 }
1476 acb_dev_map++;
1477 }
1478}
1479
1480static void arcmsr_free_pcidev(struct AdapterControlBlock *acb)
1481{
1482 struct pci_dev *pdev;
1483 struct Scsi_Host *host;
1484
1485 host = acb->host;
1486 arcmsr_free_sysfs_attr(acb);
1487 scsi_remove_host(host);
1488 flush_work(&acb->arcmsr_do_message_isr_bh);
1489 del_timer_sync(&acb->eternal_timer);
1490 if (set_date_time)
1491 del_timer_sync(&acb->refresh_timer);
1492 pdev = acb->pdev;
1493 arcmsr_free_irq(pdev, acb);
1494 arcmsr_free_ccb_pool(acb);
1495 arcmsr_free_mu(acb);
1496 arcmsr_unmap_pciregion(acb);
1497 pci_release_regions(pdev);
1498 scsi_host_put(host);
1499 pci_disable_device(pdev);
1500}
1501
1502static void arcmsr_remove(struct pci_dev *pdev)
1503{
1504 struct Scsi_Host *host = pci_get_drvdata(pdev);
1505 struct AdapterControlBlock *acb =
1506 (struct AdapterControlBlock *) host->hostdata;
1507 int poll_count = 0;
1508 uint16_t dev_id;
1509
1510 pci_read_config_word(pdev, PCI_DEVICE_ID, &dev_id);
1511 if (dev_id == 0xffff) {
1512 acb->acb_flags &= ~ACB_F_IOP_INITED;
1513 acb->acb_flags |= ACB_F_ADAPTER_REMOVED;
1514 arcmsr_remove_scsi_devices(acb);
1515 arcmsr_free_pcidev(acb);
1516 return;
1517 }
1518 arcmsr_free_sysfs_attr(acb);
1519 scsi_remove_host(host);
1520 flush_work(&acb->arcmsr_do_message_isr_bh);
1521 del_timer_sync(&acb->eternal_timer);
1522 if (set_date_time)
1523 del_timer_sync(&acb->refresh_timer);
1524 arcmsr_disable_outbound_ints(acb);
1525 arcmsr_stop_adapter_bgrb(acb);
1526 arcmsr_flush_adapter_cache(acb);
1527 acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
1528 acb->acb_flags &= ~ACB_F_IOP_INITED;
1529
1530 for (poll_count = 0; poll_count < acb->maxOutstanding; poll_count++){
1531 if (!atomic_read(&acb->ccboutstandingcount))
1532 break;
1533 arcmsr_interrupt(acb);
1534 msleep(25);
1535 }
1536
1537 if (atomic_read(&acb->ccboutstandingcount)) {
1538 int i;
1539
1540 arcmsr_abort_allcmd(acb);
1541 arcmsr_done4abort_postqueue(acb);
1542 for (i = 0; i < acb->maxFreeCCB; i++) {
1543 struct CommandControlBlock *ccb = acb->pccb_pool[i];
1544 if (ccb->startdone == ARCMSR_CCB_START) {
1545 ccb->startdone = ARCMSR_CCB_ABORTED;
1546 ccb->pcmd->result = DID_ABORT << 16;
1547 arcmsr_ccb_complete(ccb);
1548 }
1549 }
1550 }
1551 arcmsr_free_irq(pdev, acb);
1552 arcmsr_free_ccb_pool(acb);
1553 arcmsr_free_mu(acb);
1554 arcmsr_unmap_pciregion(acb);
1555 pci_release_regions(pdev);
1556 scsi_host_put(host);
1557 pci_disable_device(pdev);
1558}
1559
1560static void arcmsr_shutdown(struct pci_dev *pdev)
1561{
1562 struct Scsi_Host *host = pci_get_drvdata(pdev);
1563 struct AdapterControlBlock *acb =
1564 (struct AdapterControlBlock *)host->hostdata;
1565 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED)
1566 return;
1567 del_timer_sync(&acb->eternal_timer);
1568 if (set_date_time)
1569 del_timer_sync(&acb->refresh_timer);
1570 arcmsr_disable_outbound_ints(acb);
1571 arcmsr_free_irq(pdev, acb);
1572 flush_work(&acb->arcmsr_do_message_isr_bh);
1573 arcmsr_stop_adapter_bgrb(acb);
1574 arcmsr_flush_adapter_cache(acb);
1575}
1576
1577static int arcmsr_module_init(void)
1578{
1579 int error = 0;
1580 error = pci_register_driver(&arcmsr_pci_driver);
1581 return error;
1582}
1583
1584static void arcmsr_module_exit(void)
1585{
1586 pci_unregister_driver(&arcmsr_pci_driver);
1587}
1588module_init(arcmsr_module_init);
1589module_exit(arcmsr_module_exit);
1590
1591static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
1592 u32 intmask_org)
1593{
1594 u32 mask;
1595 switch (acb->adapter_type) {
1596
1597 case ACB_ADAPTER_TYPE_A: {
1598 struct MessageUnit_A __iomem *reg = acb->pmuA;
1599 mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE |
1600 ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|
1601 ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
1602 writel(mask, ®->outbound_intmask);
1603 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
1604 }
1605 break;
1606
1607 case ACB_ADAPTER_TYPE_B: {
1608 struct MessageUnit_B *reg = acb->pmuB;
1609 mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK |
1610 ARCMSR_IOP2DRV_DATA_READ_OK |
1611 ARCMSR_IOP2DRV_CDB_DONE |
1612 ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
1613 writel(mask, reg->iop2drv_doorbell_mask);
1614 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
1615 }
1616 break;
1617 case ACB_ADAPTER_TYPE_C: {
1618 struct MessageUnit_C __iomem *reg = acb->pmuC;
1619 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK|ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
1620 writel(intmask_org & mask, ®->host_int_mask);
1621 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
1622 }
1623 break;
1624 case ACB_ADAPTER_TYPE_D: {
1625 struct MessageUnit_D *reg = acb->pmuD;
1626
1627 mask = ARCMSR_ARC1214_ALL_INT_ENABLE;
1628 writel(intmask_org | mask, reg->pcief0_int_enable);
1629 break;
1630 }
1631 case ACB_ADAPTER_TYPE_E: {
1632 struct MessageUnit_E __iomem *reg = acb->pmuE;
1633
1634 mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR);
1635 writel(intmask_org & mask, ®->host_int_mask);
1636 break;
1637 }
1638 }
1639}
1640
1641static int arcmsr_build_ccb(struct AdapterControlBlock *acb,
1642 struct CommandControlBlock *ccb, struct scsi_cmnd *pcmd)
1643{
1644 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
1645 int8_t *psge = (int8_t *)&arcmsr_cdb->u;
1646 __le32 address_lo, address_hi;
1647 int arccdbsize = 0x30;
1648 __le32 length = 0;
1649 int i;
1650 struct scatterlist *sg;
1651 int nseg;
1652 ccb->pcmd = pcmd;
1653 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
1654 arcmsr_cdb->TargetID = pcmd->device->id;
1655 arcmsr_cdb->LUN = pcmd->device->lun;
1656 arcmsr_cdb->Function = 1;
1657 arcmsr_cdb->msgContext = 0;
1658 memcpy(arcmsr_cdb->Cdb, pcmd->cmnd, pcmd->cmd_len);
1659
1660 nseg = scsi_dma_map(pcmd);
1661 if (unlikely(nseg > acb->host->sg_tablesize || nseg < 0))
1662 return FAILED;
1663 scsi_for_each_sg(pcmd, sg, nseg, i) {
1664
1665 length = cpu_to_le32(sg_dma_len(sg));
1666 address_lo = cpu_to_le32(dma_addr_lo32(sg_dma_address(sg)));
1667 address_hi = cpu_to_le32(dma_addr_hi32(sg_dma_address(sg)));
1668 if (address_hi == 0) {
1669 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
1670
1671 pdma_sg->address = address_lo;
1672 pdma_sg->length = length;
1673 psge += sizeof (struct SG32ENTRY);
1674 arccdbsize += sizeof (struct SG32ENTRY);
1675 } else {
1676 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
1677
1678 pdma_sg->addresshigh = address_hi;
1679 pdma_sg->address = address_lo;
1680 pdma_sg->length = length|cpu_to_le32(IS_SG64_ADDR);
1681 psge += sizeof (struct SG64ENTRY);
1682 arccdbsize += sizeof (struct SG64ENTRY);
1683 }
1684 }
1685 arcmsr_cdb->sgcount = (uint8_t)nseg;
1686 arcmsr_cdb->DataLength = scsi_bufflen(pcmd);
1687 arcmsr_cdb->msgPages = arccdbsize/0x100 + (arccdbsize % 0x100 ? 1 : 0);
1688 if ( arccdbsize > 256)
1689 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
1690 if (pcmd->sc_data_direction == DMA_TO_DEVICE)
1691 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
1692 ccb->arc_cdb_size = arccdbsize;
1693 return SUCCESS;
1694}
1695
1696static void arcmsr_post_ccb(struct AdapterControlBlock *acb, struct CommandControlBlock *ccb)
1697{
1698 uint32_t cdb_phyaddr = ccb->cdb_phyaddr;
1699 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
1700 atomic_inc(&acb->ccboutstandingcount);
1701 ccb->startdone = ARCMSR_CCB_START;
1702 switch (acb->adapter_type) {
1703 case ACB_ADAPTER_TYPE_A: {
1704 struct MessageUnit_A __iomem *reg = acb->pmuA;
1705
1706 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE)
1707 writel(cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,
1708 ®->inbound_queueport);
1709 else
1710 writel(cdb_phyaddr, ®->inbound_queueport);
1711 break;
1712 }
1713
1714 case ACB_ADAPTER_TYPE_B: {
1715 struct MessageUnit_B *reg = acb->pmuB;
1716 uint32_t ending_index, index = reg->postq_index;
1717
1718 ending_index = ((index + 1) % ARCMSR_MAX_HBB_POSTQUEUE);
1719 reg->post_qbuffer[ending_index] = 0;
1720 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1721 reg->post_qbuffer[index] =
1722 cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE;
1723 } else {
1724 reg->post_qbuffer[index] = cdb_phyaddr;
1725 }
1726 index++;
1727 index %= ARCMSR_MAX_HBB_POSTQUEUE;
1728 reg->postq_index = index;
1729 writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell);
1730 }
1731 break;
1732 case ACB_ADAPTER_TYPE_C: {
1733 struct MessageUnit_C __iomem *phbcmu = acb->pmuC;
1734 uint32_t ccb_post_stamp, arc_cdb_size;
1735
1736 arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size;
1737 ccb_post_stamp = (cdb_phyaddr | ((arc_cdb_size - 1) >> 6) | 1);
1738 if (acb->cdb_phyaddr_hi32) {
1739 writel(acb->cdb_phyaddr_hi32, &phbcmu->inbound_queueport_high);
1740 writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
1741 } else {
1742 writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
1743 }
1744 }
1745 break;
1746 case ACB_ADAPTER_TYPE_D: {
1747 struct MessageUnit_D *pmu = acb->pmuD;
1748 u16 index_stripped;
1749 u16 postq_index, toggle;
1750 unsigned long flags;
1751 struct InBound_SRB *pinbound_srb;
1752
1753 spin_lock_irqsave(&acb->postq_lock, flags);
1754 postq_index = pmu->postq_index;
1755 pinbound_srb = (struct InBound_SRB *)&(pmu->post_qbuffer[postq_index & 0xFF]);
1756 pinbound_srb->addressHigh = dma_addr_hi32(cdb_phyaddr);
1757 pinbound_srb->addressLow = dma_addr_lo32(cdb_phyaddr);
1758 pinbound_srb->length = ccb->arc_cdb_size >> 2;
1759 arcmsr_cdb->msgContext = dma_addr_lo32(cdb_phyaddr);
1760 toggle = postq_index & 0x4000;
1761 index_stripped = postq_index + 1;
1762 index_stripped &= (ARCMSR_MAX_ARC1214_POSTQUEUE - 1);
1763 pmu->postq_index = index_stripped ? (index_stripped | toggle) :
1764 (toggle ^ 0x4000);
1765 writel(postq_index, pmu->inboundlist_write_pointer);
1766 spin_unlock_irqrestore(&acb->postq_lock, flags);
1767 break;
1768 }
1769 case ACB_ADAPTER_TYPE_E: {
1770 struct MessageUnit_E __iomem *pmu = acb->pmuE;
1771 u32 ccb_post_stamp, arc_cdb_size;
1772
1773 arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size;
1774 ccb_post_stamp = (ccb->smid | ((arc_cdb_size - 1) >> 6));
1775 writel(0, &pmu->inbound_queueport_high);
1776 writel(ccb_post_stamp, &pmu->inbound_queueport_low);
1777 break;
1778 }
1779 }
1780}
1781
1782static void arcmsr_hbaA_stop_bgrb(struct AdapterControlBlock *acb)
1783{
1784 struct MessageUnit_A __iomem *reg = acb->pmuA;
1785 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1786 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, ®->inbound_msgaddr0);
1787 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
1788 printk(KERN_NOTICE
1789 "arcmsr%d: wait 'stop adapter background rebulid' timeout\n"
1790 , acb->host->host_no);
1791 }
1792}
1793
1794static void arcmsr_hbaB_stop_bgrb(struct AdapterControlBlock *acb)
1795{
1796 struct MessageUnit_B *reg = acb->pmuB;
1797 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1798 writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell);
1799
1800 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
1801 printk(KERN_NOTICE
1802 "arcmsr%d: wait 'stop adapter background rebulid' timeout\n"
1803 , acb->host->host_no);
1804 }
1805}
1806
1807static void arcmsr_hbaC_stop_bgrb(struct AdapterControlBlock *pACB)
1808{
1809 struct MessageUnit_C __iomem *reg = pACB->pmuC;
1810 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
1811 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, ®->inbound_msgaddr0);
1812 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
1813 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
1814 printk(KERN_NOTICE
1815 "arcmsr%d: wait 'stop adapter background rebulid' timeout\n"
1816 , pACB->host->host_no);
1817 }
1818 return;
1819}
1820
1821static void arcmsr_hbaD_stop_bgrb(struct AdapterControlBlock *pACB)
1822{
1823 struct MessageUnit_D *reg = pACB->pmuD;
1824
1825 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
1826 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, reg->inbound_msgaddr0);
1827 if (!arcmsr_hbaD_wait_msgint_ready(pACB))
1828 pr_notice("arcmsr%d: wait 'stop adapter background rebulid' "
1829 "timeout\n", pACB->host->host_no);
1830}
1831
1832static void arcmsr_hbaE_stop_bgrb(struct AdapterControlBlock *pACB)
1833{
1834 struct MessageUnit_E __iomem *reg = pACB->pmuE;
1835
1836 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
1837 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, ®->inbound_msgaddr0);
1838 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
1839 writel(pACB->out_doorbell, ®->iobound_doorbell);
1840 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
1841 pr_notice("arcmsr%d: wait 'stop adapter background rebulid' "
1842 "timeout\n", pACB->host->host_no);
1843 }
1844}
1845
1846static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
1847{
1848 switch (acb->adapter_type) {
1849 case ACB_ADAPTER_TYPE_A: {
1850 arcmsr_hbaA_stop_bgrb(acb);
1851 }
1852 break;
1853
1854 case ACB_ADAPTER_TYPE_B: {
1855 arcmsr_hbaB_stop_bgrb(acb);
1856 }
1857 break;
1858 case ACB_ADAPTER_TYPE_C: {
1859 arcmsr_hbaC_stop_bgrb(acb);
1860 }
1861 break;
1862 case ACB_ADAPTER_TYPE_D:
1863 arcmsr_hbaD_stop_bgrb(acb);
1864 break;
1865 case ACB_ADAPTER_TYPE_E:
1866 arcmsr_hbaE_stop_bgrb(acb);
1867 break;
1868 }
1869}
1870
1871static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb)
1872{
1873 dma_free_coherent(&acb->pdev->dev, acb->uncache_size, acb->dma_coherent, acb->dma_coherent_handle);
1874}
1875
1876static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
1877{
1878 switch (acb->adapter_type) {
1879 case ACB_ADAPTER_TYPE_A: {
1880 struct MessageUnit_A __iomem *reg = acb->pmuA;
1881 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, ®->inbound_doorbell);
1882 }
1883 break;
1884
1885 case ACB_ADAPTER_TYPE_B: {
1886 struct MessageUnit_B *reg = acb->pmuB;
1887 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
1888 }
1889 break;
1890 case ACB_ADAPTER_TYPE_C: {
1891 struct MessageUnit_C __iomem *reg = acb->pmuC;
1892
1893 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, ®->inbound_doorbell);
1894 }
1895 break;
1896 case ACB_ADAPTER_TYPE_D: {
1897 struct MessageUnit_D *reg = acb->pmuD;
1898 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
1899 reg->inbound_doorbell);
1900 }
1901 break;
1902 case ACB_ADAPTER_TYPE_E: {
1903 struct MessageUnit_E __iomem *reg = acb->pmuE;
1904 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
1905 writel(acb->out_doorbell, ®->iobound_doorbell);
1906 }
1907 break;
1908 }
1909}
1910
1911static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
1912{
1913 switch (acb->adapter_type) {
1914 case ACB_ADAPTER_TYPE_A: {
1915 struct MessageUnit_A __iomem *reg = acb->pmuA;
1916
1917
1918
1919
1920 writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, ®->inbound_doorbell);
1921 }
1922 break;
1923
1924 case ACB_ADAPTER_TYPE_B: {
1925 struct MessageUnit_B *reg = acb->pmuB;
1926
1927
1928
1929
1930 writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell);
1931 }
1932 break;
1933 case ACB_ADAPTER_TYPE_C: {
1934 struct MessageUnit_C __iomem *reg = acb->pmuC;
1935
1936
1937
1938
1939 writel(ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK, ®->inbound_doorbell);
1940 }
1941 break;
1942 case ACB_ADAPTER_TYPE_D: {
1943 struct MessageUnit_D *reg = acb->pmuD;
1944 writel(ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY,
1945 reg->inbound_doorbell);
1946 }
1947 break;
1948 case ACB_ADAPTER_TYPE_E: {
1949 struct MessageUnit_E __iomem *reg = acb->pmuE;
1950 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK;
1951 writel(acb->out_doorbell, ®->iobound_doorbell);
1952 }
1953 break;
1954 }
1955}
1956
1957struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *acb)
1958{
1959 struct QBUFFER __iomem *qbuffer = NULL;
1960 switch (acb->adapter_type) {
1961
1962 case ACB_ADAPTER_TYPE_A: {
1963 struct MessageUnit_A __iomem *reg = acb->pmuA;
1964 qbuffer = (struct QBUFFER __iomem *)®->message_rbuffer;
1965 }
1966 break;
1967
1968 case ACB_ADAPTER_TYPE_B: {
1969 struct MessageUnit_B *reg = acb->pmuB;
1970 qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
1971 }
1972 break;
1973 case ACB_ADAPTER_TYPE_C: {
1974 struct MessageUnit_C __iomem *phbcmu = acb->pmuC;
1975 qbuffer = (struct QBUFFER __iomem *)&phbcmu->message_rbuffer;
1976 }
1977 break;
1978 case ACB_ADAPTER_TYPE_D: {
1979 struct MessageUnit_D *reg = acb->pmuD;
1980 qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
1981 }
1982 break;
1983 case ACB_ADAPTER_TYPE_E: {
1984 struct MessageUnit_E __iomem *reg = acb->pmuE;
1985 qbuffer = (struct QBUFFER __iomem *)®->message_rbuffer;
1986 }
1987 break;
1988 }
1989 return qbuffer;
1990}
1991
1992static struct QBUFFER __iomem *arcmsr_get_iop_wqbuffer(struct AdapterControlBlock *acb)
1993{
1994 struct QBUFFER __iomem *pqbuffer = NULL;
1995 switch (acb->adapter_type) {
1996
1997 case ACB_ADAPTER_TYPE_A: {
1998 struct MessageUnit_A __iomem *reg = acb->pmuA;
1999 pqbuffer = (struct QBUFFER __iomem *) ®->message_wbuffer;
2000 }
2001 break;
2002
2003 case ACB_ADAPTER_TYPE_B: {
2004 struct MessageUnit_B *reg = acb->pmuB;
2005 pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
2006 }
2007 break;
2008 case ACB_ADAPTER_TYPE_C: {
2009 struct MessageUnit_C __iomem *reg = acb->pmuC;
2010 pqbuffer = (struct QBUFFER __iomem *)®->message_wbuffer;
2011 }
2012 break;
2013 case ACB_ADAPTER_TYPE_D: {
2014 struct MessageUnit_D *reg = acb->pmuD;
2015 pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
2016 }
2017 break;
2018 case ACB_ADAPTER_TYPE_E: {
2019 struct MessageUnit_E __iomem *reg = acb->pmuE;
2020 pqbuffer = (struct QBUFFER __iomem *)®->message_wbuffer;
2021 }
2022 break;
2023 }
2024 return pqbuffer;
2025}
2026
2027static uint32_t
2028arcmsr_Read_iop_rqbuffer_in_DWORD(struct AdapterControlBlock *acb,
2029 struct QBUFFER __iomem *prbuffer)
2030{
2031 uint8_t *pQbuffer;
2032 uint8_t *buf1 = NULL;
2033 uint32_t __iomem *iop_data;
2034 uint32_t iop_len, data_len, *buf2 = NULL;
2035
2036 iop_data = (uint32_t __iomem *)prbuffer->data;
2037 iop_len = readl(&prbuffer->data_len);
2038 if (iop_len > 0) {
2039 buf1 = kmalloc(128, GFP_ATOMIC);
2040 buf2 = (uint32_t *)buf1;
2041 if (buf1 == NULL)
2042 return 0;
2043 data_len = iop_len;
2044 while (data_len >= 4) {
2045 *buf2++ = readl(iop_data);
2046 iop_data++;
2047 data_len -= 4;
2048 }
2049 if (data_len)
2050 *buf2 = readl(iop_data);
2051 buf2 = (uint32_t *)buf1;
2052 }
2053 while (iop_len > 0) {
2054 pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex];
2055 *pQbuffer = *buf1;
2056 acb->rqbuf_putIndex++;
2057
2058 acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
2059 buf1++;
2060 iop_len--;
2061 }
2062 kfree(buf2);
2063
2064 arcmsr_iop_message_read(acb);
2065 return 1;
2066}
2067
2068uint32_t
2069arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
2070 struct QBUFFER __iomem *prbuffer) {
2071
2072 uint8_t *pQbuffer;
2073 uint8_t __iomem *iop_data;
2074 uint32_t iop_len;
2075
2076 if (acb->adapter_type > ACB_ADAPTER_TYPE_B)
2077 return arcmsr_Read_iop_rqbuffer_in_DWORD(acb, prbuffer);
2078 iop_data = (uint8_t __iomem *)prbuffer->data;
2079 iop_len = readl(&prbuffer->data_len);
2080 while (iop_len > 0) {
2081 pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex];
2082 *pQbuffer = readb(iop_data);
2083 acb->rqbuf_putIndex++;
2084 acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
2085 iop_data++;
2086 iop_len--;
2087 }
2088 arcmsr_iop_message_read(acb);
2089 return 1;
2090}
2091
2092static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
2093{
2094 unsigned long flags;
2095 struct QBUFFER __iomem *prbuffer;
2096 int32_t buf_empty_len;
2097
2098 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
2099 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2100 buf_empty_len = (acb->rqbuf_putIndex - acb->rqbuf_getIndex - 1) &
2101 (ARCMSR_MAX_QBUFFER - 1);
2102 if (buf_empty_len >= readl(&prbuffer->data_len)) {
2103 if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2104 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2105 } else
2106 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2107 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
2108}
2109
2110static void arcmsr_write_ioctldata2iop_in_DWORD(struct AdapterControlBlock *acb)
2111{
2112 uint8_t *pQbuffer;
2113 struct QBUFFER __iomem *pwbuffer;
2114 uint8_t *buf1 = NULL;
2115 uint32_t __iomem *iop_data;
2116 uint32_t allxfer_len = 0, data_len, *buf2 = NULL, data;
2117
2118 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
2119 buf1 = kmalloc(128, GFP_ATOMIC);
2120 buf2 = (uint32_t *)buf1;
2121 if (buf1 == NULL)
2122 return;
2123
2124 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
2125 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
2126 iop_data = (uint32_t __iomem *)pwbuffer->data;
2127 while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex)
2128 && (allxfer_len < 124)) {
2129 pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex];
2130 *buf1 = *pQbuffer;
2131 acb->wqbuf_getIndex++;
2132 acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER;
2133 buf1++;
2134 allxfer_len++;
2135 }
2136 data_len = allxfer_len;
2137 buf1 = (uint8_t *)buf2;
2138 while (data_len >= 4) {
2139 data = *buf2++;
2140 writel(data, iop_data);
2141 iop_data++;
2142 data_len -= 4;
2143 }
2144 if (data_len) {
2145 data = *buf2;
2146 writel(data, iop_data);
2147 }
2148 writel(allxfer_len, &pwbuffer->data_len);
2149 kfree(buf1);
2150 arcmsr_iop_message_wrote(acb);
2151 }
2152}
2153
2154void
2155arcmsr_write_ioctldata2iop(struct AdapterControlBlock *acb)
2156{
2157 uint8_t *pQbuffer;
2158 struct QBUFFER __iomem *pwbuffer;
2159 uint8_t __iomem *iop_data;
2160 int32_t allxfer_len = 0;
2161
2162 if (acb->adapter_type > ACB_ADAPTER_TYPE_B) {
2163 arcmsr_write_ioctldata2iop_in_DWORD(acb);
2164 return;
2165 }
2166 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
2167 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
2168 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
2169 iop_data = (uint8_t __iomem *)pwbuffer->data;
2170 while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex)
2171 && (allxfer_len < 124)) {
2172 pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex];
2173 writeb(*pQbuffer, iop_data);
2174 acb->wqbuf_getIndex++;
2175 acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER;
2176 iop_data++;
2177 allxfer_len++;
2178 }
2179 writel(allxfer_len, &pwbuffer->data_len);
2180 arcmsr_iop_message_wrote(acb);
2181 }
2182}
2183
2184static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
2185{
2186 unsigned long flags;
2187
2188 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
2189 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READED;
2190 if (acb->wqbuf_getIndex != acb->wqbuf_putIndex)
2191 arcmsr_write_ioctldata2iop(acb);
2192 if (acb->wqbuf_getIndex == acb->wqbuf_putIndex)
2193 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
2194 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
2195}
2196
2197static void arcmsr_hbaA_doorbell_isr(struct AdapterControlBlock *acb)
2198{
2199 uint32_t outbound_doorbell;
2200 struct MessageUnit_A __iomem *reg = acb->pmuA;
2201 outbound_doorbell = readl(®->outbound_doorbell);
2202 do {
2203 writel(outbound_doorbell, ®->outbound_doorbell);
2204 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK)
2205 arcmsr_iop2drv_data_wrote_handle(acb);
2206 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK)
2207 arcmsr_iop2drv_data_read_handle(acb);
2208 outbound_doorbell = readl(®->outbound_doorbell);
2209 } while (outbound_doorbell & (ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK
2210 | ARCMSR_OUTBOUND_IOP331_DATA_READ_OK));
2211}
2212static void arcmsr_hbaC_doorbell_isr(struct AdapterControlBlock *pACB)
2213{
2214 uint32_t outbound_doorbell;
2215 struct MessageUnit_C __iomem *reg = pACB->pmuC;
2216
2217
2218
2219
2220
2221
2222
2223 outbound_doorbell = readl(®->outbound_doorbell);
2224 do {
2225 writel(outbound_doorbell, ®->outbound_doorbell_clear);
2226 readl(®->outbound_doorbell_clear);
2227 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK)
2228 arcmsr_iop2drv_data_wrote_handle(pACB);
2229 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK)
2230 arcmsr_iop2drv_data_read_handle(pACB);
2231 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE)
2232 arcmsr_hbaC_message_isr(pACB);
2233 outbound_doorbell = readl(®->outbound_doorbell);
2234 } while (outbound_doorbell & (ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK
2235 | ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK
2236 | ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE));
2237}
2238
2239static void arcmsr_hbaD_doorbell_isr(struct AdapterControlBlock *pACB)
2240{
2241 uint32_t outbound_doorbell;
2242 struct MessageUnit_D *pmu = pACB->pmuD;
2243
2244 outbound_doorbell = readl(pmu->outbound_doorbell);
2245 do {
2246 writel(outbound_doorbell, pmu->outbound_doorbell);
2247 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE)
2248 arcmsr_hbaD_message_isr(pACB);
2249 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK)
2250 arcmsr_iop2drv_data_wrote_handle(pACB);
2251 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK)
2252 arcmsr_iop2drv_data_read_handle(pACB);
2253 outbound_doorbell = readl(pmu->outbound_doorbell);
2254 } while (outbound_doorbell & (ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK
2255 | ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK
2256 | ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE));
2257}
2258
2259static void arcmsr_hbaE_doorbell_isr(struct AdapterControlBlock *pACB)
2260{
2261 uint32_t outbound_doorbell, in_doorbell, tmp;
2262 struct MessageUnit_E __iomem *reg = pACB->pmuE;
2263
2264 in_doorbell = readl(®->iobound_doorbell);
2265 outbound_doorbell = in_doorbell ^ pACB->in_doorbell;
2266 do {
2267 writel(0, ®->host_int_status);
2268 if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) {
2269 arcmsr_iop2drv_data_wrote_handle(pACB);
2270 }
2271 if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) {
2272 arcmsr_iop2drv_data_read_handle(pACB);
2273 }
2274 if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
2275 arcmsr_hbaE_message_isr(pACB);
2276 }
2277 tmp = in_doorbell;
2278 in_doorbell = readl(®->iobound_doorbell);
2279 outbound_doorbell = tmp ^ in_doorbell;
2280 } while (outbound_doorbell & (ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK
2281 | ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK
2282 | ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE));
2283 pACB->in_doorbell = in_doorbell;
2284}
2285
2286static void arcmsr_hbaA_postqueue_isr(struct AdapterControlBlock *acb)
2287{
2288 uint32_t flag_ccb;
2289 struct MessageUnit_A __iomem *reg = acb->pmuA;
2290 struct ARCMSR_CDB *pARCMSR_CDB;
2291 struct CommandControlBlock *pCCB;
2292 bool error;
2293 while ((flag_ccb = readl(®->outbound_queueport)) != 0xFFFFFFFF) {
2294 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
2295 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
2296 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
2297 arcmsr_drain_donequeue(acb, pCCB, error);
2298 }
2299}
2300static void arcmsr_hbaB_postqueue_isr(struct AdapterControlBlock *acb)
2301{
2302 uint32_t index;
2303 uint32_t flag_ccb;
2304 struct MessageUnit_B *reg = acb->pmuB;
2305 struct ARCMSR_CDB *pARCMSR_CDB;
2306 struct CommandControlBlock *pCCB;
2307 bool error;
2308 index = reg->doneq_index;
2309 while ((flag_ccb = reg->done_qbuffer[index]) != 0) {
2310 reg->done_qbuffer[index] = 0;
2311 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));
2312 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
2313 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
2314 arcmsr_drain_donequeue(acb, pCCB, error);
2315 index++;
2316 index %= ARCMSR_MAX_HBB_POSTQUEUE;
2317 reg->doneq_index = index;
2318 }
2319}
2320
2321static void arcmsr_hbaC_postqueue_isr(struct AdapterControlBlock *acb)
2322{
2323 struct MessageUnit_C __iomem *phbcmu;
2324 struct ARCMSR_CDB *arcmsr_cdb;
2325 struct CommandControlBlock *ccb;
2326 uint32_t flag_ccb, ccb_cdb_phy, throttling = 0;
2327 int error;
2328
2329 phbcmu = acb->pmuC;
2330
2331
2332
2333 while ((flag_ccb = readl(&phbcmu->outbound_queueport_low)) !=
2334 0xFFFFFFFF) {
2335 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
2336 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset
2337 + ccb_cdb_phy);
2338 ccb = container_of(arcmsr_cdb, struct CommandControlBlock,
2339 arcmsr_cdb);
2340 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
2341 ? true : false;
2342
2343 arcmsr_drain_donequeue(acb, ccb, error);
2344 throttling++;
2345 if (throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
2346 writel(ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING,
2347 &phbcmu->inbound_doorbell);
2348 throttling = 0;
2349 }
2350 }
2351}
2352
2353static void arcmsr_hbaD_postqueue_isr(struct AdapterControlBlock *acb)
2354{
2355 u32 outbound_write_pointer, doneq_index, index_stripped, toggle;
2356 uint32_t addressLow, ccb_cdb_phy;
2357 int error;
2358 struct MessageUnit_D *pmu;
2359 struct ARCMSR_CDB *arcmsr_cdb;
2360 struct CommandControlBlock *ccb;
2361 unsigned long flags;
2362
2363 spin_lock_irqsave(&acb->doneq_lock, flags);
2364 pmu = acb->pmuD;
2365 outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1;
2366 doneq_index = pmu->doneq_index;
2367 if ((doneq_index & 0xFFF) != (outbound_write_pointer & 0xFFF)) {
2368 do {
2369 toggle = doneq_index & 0x4000;
2370 index_stripped = (doneq_index & 0xFFF) + 1;
2371 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
2372 pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
2373 ((toggle ^ 0x4000) + 1);
2374 doneq_index = pmu->doneq_index;
2375 addressLow = pmu->done_qbuffer[doneq_index &
2376 0xFFF].addressLow;
2377 ccb_cdb_phy = (addressLow & 0xFFFFFFF0);
2378 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset
2379 + ccb_cdb_phy);
2380 ccb = container_of(arcmsr_cdb,
2381 struct CommandControlBlock, arcmsr_cdb);
2382 error = (addressLow & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
2383 ? true : false;
2384 arcmsr_drain_donequeue(acb, ccb, error);
2385 writel(doneq_index, pmu->outboundlist_read_pointer);
2386 } while ((doneq_index & 0xFFF) !=
2387 (outbound_write_pointer & 0xFFF));
2388 }
2389 writel(ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR,
2390 pmu->outboundlist_interrupt_cause);
2391 readl(pmu->outboundlist_interrupt_cause);
2392 spin_unlock_irqrestore(&acb->doneq_lock, flags);
2393}
2394
2395static void arcmsr_hbaE_postqueue_isr(struct AdapterControlBlock *acb)
2396{
2397 uint32_t doneq_index;
2398 uint16_t cmdSMID;
2399 int error;
2400 struct MessageUnit_E __iomem *pmu;
2401 struct CommandControlBlock *ccb;
2402 unsigned long flags;
2403
2404 spin_lock_irqsave(&acb->doneq_lock, flags);
2405 doneq_index = acb->doneq_index;
2406 pmu = acb->pmuE;
2407 while ((readl(&pmu->reply_post_producer_index) & 0xFFFF) != doneq_index) {
2408 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
2409 ccb = acb->pccb_pool[cmdSMID];
2410 error = (acb->pCompletionQ[doneq_index].cmdFlag
2411 & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
2412 arcmsr_drain_donequeue(acb, ccb, error);
2413 doneq_index++;
2414 if (doneq_index >= acb->completionQ_entry)
2415 doneq_index = 0;
2416 }
2417 acb->doneq_index = doneq_index;
2418 writel(doneq_index, &pmu->reply_post_consumer_index);
2419 spin_unlock_irqrestore(&acb->doneq_lock, flags);
2420}
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430static void arcmsr_hbaA_message_isr(struct AdapterControlBlock *acb)
2431{
2432 struct MessageUnit_A __iomem *reg = acb->pmuA;
2433
2434 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, ®->outbound_intstatus);
2435 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
2436 schedule_work(&acb->arcmsr_do_message_isr_bh);
2437}
2438static void arcmsr_hbaB_message_isr(struct AdapterControlBlock *acb)
2439{
2440 struct MessageUnit_B *reg = acb->pmuB;
2441
2442
2443 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
2444 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
2445 schedule_work(&acb->arcmsr_do_message_isr_bh);
2446}
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *acb)
2457{
2458 struct MessageUnit_C __iomem *reg = acb->pmuC;
2459
2460 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, ®->outbound_doorbell_clear);
2461 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
2462 schedule_work(&acb->arcmsr_do_message_isr_bh);
2463}
2464
2465static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb)
2466{
2467 struct MessageUnit_D *reg = acb->pmuD;
2468
2469 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, reg->outbound_doorbell);
2470 readl(reg->outbound_doorbell);
2471 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
2472 schedule_work(&acb->arcmsr_do_message_isr_bh);
2473}
2474
2475static void arcmsr_hbaE_message_isr(struct AdapterControlBlock *acb)
2476{
2477 struct MessageUnit_E __iomem *reg = acb->pmuE;
2478
2479 writel(0, ®->host_int_status);
2480 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
2481 schedule_work(&acb->arcmsr_do_message_isr_bh);
2482}
2483
2484static int arcmsr_hbaA_handle_isr(struct AdapterControlBlock *acb)
2485{
2486 uint32_t outbound_intstatus;
2487 struct MessageUnit_A __iomem *reg = acb->pmuA;
2488 outbound_intstatus = readl(®->outbound_intstatus) &
2489 acb->outbound_int_enable;
2490 if (!(outbound_intstatus & ARCMSR_MU_OUTBOUND_HANDLE_INT))
2491 return IRQ_NONE;
2492 do {
2493 writel(outbound_intstatus, ®->outbound_intstatus);
2494 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT)
2495 arcmsr_hbaA_doorbell_isr(acb);
2496 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT)
2497 arcmsr_hbaA_postqueue_isr(acb);
2498 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT)
2499 arcmsr_hbaA_message_isr(acb);
2500 outbound_intstatus = readl(®->outbound_intstatus) &
2501 acb->outbound_int_enable;
2502 } while (outbound_intstatus & (ARCMSR_MU_OUTBOUND_DOORBELL_INT
2503 | ARCMSR_MU_OUTBOUND_POSTQUEUE_INT
2504 | ARCMSR_MU_OUTBOUND_MESSAGE0_INT));
2505 return IRQ_HANDLED;
2506}
2507
2508static int arcmsr_hbaB_handle_isr(struct AdapterControlBlock *acb)
2509{
2510 uint32_t outbound_doorbell;
2511 struct MessageUnit_B *reg = acb->pmuB;
2512 outbound_doorbell = readl(reg->iop2drv_doorbell) &
2513 acb->outbound_int_enable;
2514 if (!outbound_doorbell)
2515 return IRQ_NONE;
2516 do {
2517 writel(~outbound_doorbell, reg->iop2drv_doorbell);
2518 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
2519 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK)
2520 arcmsr_iop2drv_data_wrote_handle(acb);
2521 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK)
2522 arcmsr_iop2drv_data_read_handle(acb);
2523 if (outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE)
2524 arcmsr_hbaB_postqueue_isr(acb);
2525 if (outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE)
2526 arcmsr_hbaB_message_isr(acb);
2527 outbound_doorbell = readl(reg->iop2drv_doorbell) &
2528 acb->outbound_int_enable;
2529 } while (outbound_doorbell & (ARCMSR_IOP2DRV_DATA_WRITE_OK
2530 | ARCMSR_IOP2DRV_DATA_READ_OK
2531 | ARCMSR_IOP2DRV_CDB_DONE
2532 | ARCMSR_IOP2DRV_MESSAGE_CMD_DONE));
2533 return IRQ_HANDLED;
2534}
2535
2536static int arcmsr_hbaC_handle_isr(struct AdapterControlBlock *pACB)
2537{
2538 uint32_t host_interrupt_status;
2539 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
2540
2541
2542
2543
2544
2545 host_interrupt_status = readl(&phbcmu->host_int_status) &
2546 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
2547 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR);
2548 if (!host_interrupt_status)
2549 return IRQ_NONE;
2550 do {
2551 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR)
2552 arcmsr_hbaC_doorbell_isr(pACB);
2553
2554 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)
2555 arcmsr_hbaC_postqueue_isr(pACB);
2556 host_interrupt_status = readl(&phbcmu->host_int_status);
2557 } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
2558 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR));
2559 return IRQ_HANDLED;
2560}
2561
2562static irqreturn_t arcmsr_hbaD_handle_isr(struct AdapterControlBlock *pACB)
2563{
2564 u32 host_interrupt_status;
2565 struct MessageUnit_D *pmu = pACB->pmuD;
2566
2567 host_interrupt_status = readl(pmu->host_int_status) &
2568 (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR |
2569 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR);
2570 if (!host_interrupt_status)
2571 return IRQ_NONE;
2572 do {
2573
2574 if (host_interrupt_status &
2575 ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR)
2576 arcmsr_hbaD_postqueue_isr(pACB);
2577 if (host_interrupt_status &
2578 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR)
2579 arcmsr_hbaD_doorbell_isr(pACB);
2580 host_interrupt_status = readl(pmu->host_int_status);
2581 } while (host_interrupt_status &
2582 (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR |
2583 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR));
2584 return IRQ_HANDLED;
2585}
2586
2587static irqreturn_t arcmsr_hbaE_handle_isr(struct AdapterControlBlock *pACB)
2588{
2589 uint32_t host_interrupt_status;
2590 struct MessageUnit_E __iomem *pmu = pACB->pmuE;
2591
2592 host_interrupt_status = readl(&pmu->host_int_status) &
2593 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
2594 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR);
2595 if (!host_interrupt_status)
2596 return IRQ_NONE;
2597 do {
2598
2599 if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) {
2600 arcmsr_hbaE_doorbell_isr(pACB);
2601 }
2602
2603 if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) {
2604 arcmsr_hbaE_postqueue_isr(pACB);
2605 }
2606 host_interrupt_status = readl(&pmu->host_int_status);
2607 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
2608 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR));
2609 return IRQ_HANDLED;
2610}
2611
2612static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb)
2613{
2614 switch (acb->adapter_type) {
2615 case ACB_ADAPTER_TYPE_A:
2616 return arcmsr_hbaA_handle_isr(acb);
2617 break;
2618 case ACB_ADAPTER_TYPE_B:
2619 return arcmsr_hbaB_handle_isr(acb);
2620 break;
2621 case ACB_ADAPTER_TYPE_C:
2622 return arcmsr_hbaC_handle_isr(acb);
2623 case ACB_ADAPTER_TYPE_D:
2624 return arcmsr_hbaD_handle_isr(acb);
2625 case ACB_ADAPTER_TYPE_E:
2626 return arcmsr_hbaE_handle_isr(acb);
2627 default:
2628 return IRQ_NONE;
2629 }
2630}
2631
2632static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
2633{
2634 if (acb) {
2635
2636 if (acb->acb_flags & ACB_F_MSG_START_BGRB) {
2637 uint32_t intmask_org;
2638 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
2639 intmask_org = arcmsr_disable_outbound_ints(acb);
2640 arcmsr_stop_adapter_bgrb(acb);
2641 arcmsr_flush_adapter_cache(acb);
2642 arcmsr_enable_outbound_ints(acb, intmask_org);
2643 }
2644 }
2645}
2646
2647
2648void arcmsr_clear_iop2drv_rqueue_buffer(struct AdapterControlBlock *acb)
2649{
2650 uint32_t i;
2651
2652 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2653 for (i = 0; i < 15; i++) {
2654 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2655 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2656 acb->rqbuf_getIndex = 0;
2657 acb->rqbuf_putIndex = 0;
2658 arcmsr_iop_message_read(acb);
2659 mdelay(30);
2660 } else if (acb->rqbuf_getIndex !=
2661 acb->rqbuf_putIndex) {
2662 acb->rqbuf_getIndex = 0;
2663 acb->rqbuf_putIndex = 0;
2664 mdelay(30);
2665 } else
2666 break;
2667 }
2668 }
2669}
2670
2671static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
2672 struct scsi_cmnd *cmd)
2673{
2674 char *buffer;
2675 unsigned short use_sg;
2676 int retvalue = 0, transfer_len = 0;
2677 unsigned long flags;
2678 struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2679 uint32_t controlcode = (uint32_t)cmd->cmnd[5] << 24 |
2680 (uint32_t)cmd->cmnd[6] << 16 |
2681 (uint32_t)cmd->cmnd[7] << 8 |
2682 (uint32_t)cmd->cmnd[8];
2683 struct scatterlist *sg;
2684
2685 use_sg = scsi_sg_count(cmd);
2686 sg = scsi_sglist(cmd);
2687 buffer = kmap_atomic(sg_page(sg)) + sg->offset;
2688 if (use_sg > 1) {
2689 retvalue = ARCMSR_MESSAGE_FAIL;
2690 goto message_out;
2691 }
2692 transfer_len += sg->length;
2693 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
2694 retvalue = ARCMSR_MESSAGE_FAIL;
2695 pr_info("%s: ARCMSR_MESSAGE_FAIL!\n", __func__);
2696 goto message_out;
2697 }
2698 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *)buffer;
2699 switch (controlcode) {
2700 case ARCMSR_MESSAGE_READ_RQBUFFER: {
2701 unsigned char *ver_addr;
2702 uint8_t *ptmpQbuffer;
2703 uint32_t allxfer_len = 0;
2704 ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC);
2705 if (!ver_addr) {
2706 retvalue = ARCMSR_MESSAGE_FAIL;
2707 pr_info("%s: memory not enough!\n", __func__);
2708 goto message_out;
2709 }
2710 ptmpQbuffer = ver_addr;
2711 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
2712 if (acb->rqbuf_getIndex != acb->rqbuf_putIndex) {
2713 unsigned int tail = acb->rqbuf_getIndex;
2714 unsigned int head = acb->rqbuf_putIndex;
2715 unsigned int cnt_to_end = CIRC_CNT_TO_END(head, tail, ARCMSR_MAX_QBUFFER);
2716
2717 allxfer_len = CIRC_CNT(head, tail, ARCMSR_MAX_QBUFFER);
2718 if (allxfer_len > ARCMSR_API_DATA_BUFLEN)
2719 allxfer_len = ARCMSR_API_DATA_BUFLEN;
2720
2721 if (allxfer_len <= cnt_to_end)
2722 memcpy(ptmpQbuffer, acb->rqbuffer + tail, allxfer_len);
2723 else {
2724 memcpy(ptmpQbuffer, acb->rqbuffer + tail, cnt_to_end);
2725 memcpy(ptmpQbuffer + cnt_to_end, acb->rqbuffer, allxfer_len - cnt_to_end);
2726 }
2727 acb->rqbuf_getIndex = (acb->rqbuf_getIndex + allxfer_len) % ARCMSR_MAX_QBUFFER;
2728 }
2729 memcpy(pcmdmessagefld->messagedatabuffer, ver_addr,
2730 allxfer_len);
2731 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2732 struct QBUFFER __iomem *prbuffer;
2733 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2734 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2735 if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2736 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2737 }
2738 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
2739 kfree(ver_addr);
2740 pcmdmessagefld->cmdmessage.Length = allxfer_len;
2741 if (acb->fw_flag == FW_DEADLOCK)
2742 pcmdmessagefld->cmdmessage.ReturnCode =
2743 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2744 else
2745 pcmdmessagefld->cmdmessage.ReturnCode =
2746 ARCMSR_MESSAGE_RETURNCODE_OK;
2747 break;
2748 }
2749 case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2750 unsigned char *ver_addr;
2751 uint32_t user_len;
2752 int32_t cnt2end;
2753 uint8_t *pQbuffer, *ptmpuserbuffer;
2754
2755 user_len = pcmdmessagefld->cmdmessage.Length;
2756 if (user_len > ARCMSR_API_DATA_BUFLEN) {
2757 retvalue = ARCMSR_MESSAGE_FAIL;
2758 goto message_out;
2759 }
2760
2761 ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC);
2762 if (!ver_addr) {
2763 retvalue = ARCMSR_MESSAGE_FAIL;
2764 goto message_out;
2765 }
2766 ptmpuserbuffer = ver_addr;
2767
2768 memcpy(ptmpuserbuffer,
2769 pcmdmessagefld->messagedatabuffer, user_len);
2770 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
2771 if (acb->wqbuf_putIndex != acb->wqbuf_getIndex) {
2772 struct SENSE_DATA *sensebuffer =
2773 (struct SENSE_DATA *)cmd->sense_buffer;
2774 arcmsr_write_ioctldata2iop(acb);
2775
2776 sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
2777 sensebuffer->SenseKey = ILLEGAL_REQUEST;
2778 sensebuffer->AdditionalSenseLength = 0x0A;
2779 sensebuffer->AdditionalSenseCode = 0x20;
2780 sensebuffer->Valid = 1;
2781 retvalue = ARCMSR_MESSAGE_FAIL;
2782 } else {
2783 pQbuffer = &acb->wqbuffer[acb->wqbuf_putIndex];
2784 cnt2end = ARCMSR_MAX_QBUFFER - acb->wqbuf_putIndex;
2785 if (user_len > cnt2end) {
2786 memcpy(pQbuffer, ptmpuserbuffer, cnt2end);
2787 ptmpuserbuffer += cnt2end;
2788 user_len -= cnt2end;
2789 acb->wqbuf_putIndex = 0;
2790 pQbuffer = acb->wqbuffer;
2791 }
2792 memcpy(pQbuffer, ptmpuserbuffer, user_len);
2793 acb->wqbuf_putIndex += user_len;
2794 acb->wqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
2795 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2796 acb->acb_flags &=
2797 ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2798 arcmsr_write_ioctldata2iop(acb);
2799 }
2800 }
2801 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
2802 kfree(ver_addr);
2803 if (acb->fw_flag == FW_DEADLOCK)
2804 pcmdmessagefld->cmdmessage.ReturnCode =
2805 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2806 else
2807 pcmdmessagefld->cmdmessage.ReturnCode =
2808 ARCMSR_MESSAGE_RETURNCODE_OK;
2809 break;
2810 }
2811 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2812 uint8_t *pQbuffer = acb->rqbuffer;
2813
2814 arcmsr_clear_iop2drv_rqueue_buffer(acb);
2815 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
2816 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2817 acb->rqbuf_getIndex = 0;
2818 acb->rqbuf_putIndex = 0;
2819 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2820 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
2821 if (acb->fw_flag == FW_DEADLOCK)
2822 pcmdmessagefld->cmdmessage.ReturnCode =
2823 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2824 else
2825 pcmdmessagefld->cmdmessage.ReturnCode =
2826 ARCMSR_MESSAGE_RETURNCODE_OK;
2827 break;
2828 }
2829 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
2830 uint8_t *pQbuffer = acb->wqbuffer;
2831 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
2832 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
2833 ACB_F_MESSAGE_WQBUFFER_READED);
2834 acb->wqbuf_getIndex = 0;
2835 acb->wqbuf_putIndex = 0;
2836 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2837 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
2838 if (acb->fw_flag == FW_DEADLOCK)
2839 pcmdmessagefld->cmdmessage.ReturnCode =
2840 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2841 else
2842 pcmdmessagefld->cmdmessage.ReturnCode =
2843 ARCMSR_MESSAGE_RETURNCODE_OK;
2844 break;
2845 }
2846 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2847 uint8_t *pQbuffer;
2848 arcmsr_clear_iop2drv_rqueue_buffer(acb);
2849 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
2850 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2851 acb->rqbuf_getIndex = 0;
2852 acb->rqbuf_putIndex = 0;
2853 pQbuffer = acb->rqbuffer;
2854 memset(pQbuffer, 0, sizeof(struct QBUFFER));
2855 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
2856 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
2857 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
2858 ACB_F_MESSAGE_WQBUFFER_READED);
2859 acb->wqbuf_getIndex = 0;
2860 acb->wqbuf_putIndex = 0;
2861 pQbuffer = acb->wqbuffer;
2862 memset(pQbuffer, 0, sizeof(struct QBUFFER));
2863 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
2864 if (acb->fw_flag == FW_DEADLOCK)
2865 pcmdmessagefld->cmdmessage.ReturnCode =
2866 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2867 else
2868 pcmdmessagefld->cmdmessage.ReturnCode =
2869 ARCMSR_MESSAGE_RETURNCODE_OK;
2870 break;
2871 }
2872 case ARCMSR_MESSAGE_RETURN_CODE_3F: {
2873 if (acb->fw_flag == FW_DEADLOCK)
2874 pcmdmessagefld->cmdmessage.ReturnCode =
2875 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2876 else
2877 pcmdmessagefld->cmdmessage.ReturnCode =
2878 ARCMSR_MESSAGE_RETURNCODE_3F;
2879 break;
2880 }
2881 case ARCMSR_MESSAGE_SAY_HELLO: {
2882 int8_t *hello_string = "Hello! I am ARCMSR";
2883 if (acb->fw_flag == FW_DEADLOCK)
2884 pcmdmessagefld->cmdmessage.ReturnCode =
2885 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2886 else
2887 pcmdmessagefld->cmdmessage.ReturnCode =
2888 ARCMSR_MESSAGE_RETURNCODE_OK;
2889 memcpy(pcmdmessagefld->messagedatabuffer,
2890 hello_string, (int16_t)strlen(hello_string));
2891 break;
2892 }
2893 case ARCMSR_MESSAGE_SAY_GOODBYE: {
2894 if (acb->fw_flag == FW_DEADLOCK)
2895 pcmdmessagefld->cmdmessage.ReturnCode =
2896 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2897 else
2898 pcmdmessagefld->cmdmessage.ReturnCode =
2899 ARCMSR_MESSAGE_RETURNCODE_OK;
2900 arcmsr_iop_parking(acb);
2901 break;
2902 }
2903 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: {
2904 if (acb->fw_flag == FW_DEADLOCK)
2905 pcmdmessagefld->cmdmessage.ReturnCode =
2906 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2907 else
2908 pcmdmessagefld->cmdmessage.ReturnCode =
2909 ARCMSR_MESSAGE_RETURNCODE_OK;
2910 arcmsr_flush_adapter_cache(acb);
2911 break;
2912 }
2913 default:
2914 retvalue = ARCMSR_MESSAGE_FAIL;
2915 pr_info("%s: unknown controlcode!\n", __func__);
2916 }
2917message_out:
2918 if (use_sg) {
2919 struct scatterlist *sg = scsi_sglist(cmd);
2920 kunmap_atomic(buffer - sg->offset);
2921 }
2922 return retvalue;
2923}
2924
2925static struct CommandControlBlock *arcmsr_get_freeccb(struct AdapterControlBlock *acb)
2926{
2927 struct list_head *head = &acb->ccb_free_list;
2928 struct CommandControlBlock *ccb = NULL;
2929 unsigned long flags;
2930 spin_lock_irqsave(&acb->ccblist_lock, flags);
2931 if (!list_empty(head)) {
2932 ccb = list_entry(head->next, struct CommandControlBlock, list);
2933 list_del_init(&ccb->list);
2934 }else{
2935 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
2936 return NULL;
2937 }
2938 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
2939 return ccb;
2940}
2941
2942static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
2943 struct scsi_cmnd *cmd)
2944{
2945 switch (cmd->cmnd[0]) {
2946 case INQUIRY: {
2947 unsigned char inqdata[36];
2948 char *buffer;
2949 struct scatterlist *sg;
2950
2951 if (cmd->device->lun) {
2952 cmd->result = (DID_TIME_OUT << 16);
2953 cmd->scsi_done(cmd);
2954 return;
2955 }
2956 inqdata[0] = TYPE_PROCESSOR;
2957
2958 inqdata[1] = 0;
2959
2960 inqdata[2] = 0;
2961
2962 inqdata[4] = 31;
2963
2964 strncpy(&inqdata[8], "Areca ", 8);
2965
2966 strncpy(&inqdata[16], "RAID controller ", 16);
2967
2968 strncpy(&inqdata[32], "R001", 4);
2969
2970 sg = scsi_sglist(cmd);
2971 buffer = kmap_atomic(sg_page(sg)) + sg->offset;
2972
2973 memcpy(buffer, inqdata, sizeof(inqdata));
2974 sg = scsi_sglist(cmd);
2975 kunmap_atomic(buffer - sg->offset);
2976
2977 cmd->scsi_done(cmd);
2978 }
2979 break;
2980 case WRITE_BUFFER:
2981 case READ_BUFFER: {
2982 if (arcmsr_iop_message_xfer(acb, cmd))
2983 cmd->result = (DID_ERROR << 16);
2984 cmd->scsi_done(cmd);
2985 }
2986 break;
2987 default:
2988 cmd->scsi_done(cmd);
2989 }
2990}
2991
2992static int arcmsr_queue_command_lck(struct scsi_cmnd *cmd,
2993 void (* done)(struct scsi_cmnd *))
2994{
2995 struct Scsi_Host *host = cmd->device->host;
2996 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
2997 struct CommandControlBlock *ccb;
2998 int target = cmd->device->id;
2999
3000 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED) {
3001 cmd->result = (DID_NO_CONNECT << 16);
3002 cmd->scsi_done(cmd);
3003 return 0;
3004 }
3005 cmd->scsi_done = done;
3006 cmd->host_scribble = NULL;
3007 cmd->result = 0;
3008 if (target == 16) {
3009
3010 arcmsr_handle_virtual_command(acb, cmd);
3011 return 0;
3012 }
3013 ccb = arcmsr_get_freeccb(acb);
3014 if (!ccb)
3015 return SCSI_MLQUEUE_HOST_BUSY;
3016 if (arcmsr_build_ccb( acb, ccb, cmd ) == FAILED) {
3017 cmd->result = (DID_ERROR << 16) | (RESERVATION_CONFLICT << 1);
3018 cmd->scsi_done(cmd);
3019 return 0;
3020 }
3021 arcmsr_post_ccb(acb, ccb);
3022 return 0;
3023}
3024
3025static DEF_SCSI_QCMD(arcmsr_queue_command)
3026
3027static void arcmsr_get_adapter_config(struct AdapterControlBlock *pACB, uint32_t *rwbuffer)
3028{
3029 int count;
3030 uint32_t *acb_firm_model = (uint32_t *)pACB->firm_model;
3031 uint32_t *acb_firm_version = (uint32_t *)pACB->firm_version;
3032 uint32_t *acb_device_map = (uint32_t *)pACB->device_map;
3033 uint32_t *firm_model = &rwbuffer[15];
3034 uint32_t *firm_version = &rwbuffer[17];
3035 uint32_t *device_map = &rwbuffer[21];
3036
3037 count = 2;
3038 while (count) {
3039 *acb_firm_model = readl(firm_model);
3040 acb_firm_model++;
3041 firm_model++;
3042 count--;
3043 }
3044 count = 4;
3045 while (count) {
3046 *acb_firm_version = readl(firm_version);
3047 acb_firm_version++;
3048 firm_version++;
3049 count--;
3050 }
3051 count = 4;
3052 while (count) {
3053 *acb_device_map = readl(device_map);
3054 acb_device_map++;
3055 device_map++;
3056 count--;
3057 }
3058 pACB->signature = readl(&rwbuffer[0]);
3059 pACB->firm_request_len = readl(&rwbuffer[1]);
3060 pACB->firm_numbers_queue = readl(&rwbuffer[2]);
3061 pACB->firm_sdram_size = readl(&rwbuffer[3]);
3062 pACB->firm_hd_channels = readl(&rwbuffer[4]);
3063 pACB->firm_cfg_version = readl(&rwbuffer[25]);
3064 pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n",
3065 pACB->host->host_no,
3066 pACB->firm_model,
3067 pACB->firm_version);
3068}
3069
3070static bool arcmsr_hbaA_get_config(struct AdapterControlBlock *acb)
3071{
3072 struct MessageUnit_A __iomem *reg = acb->pmuA;
3073
3074 arcmsr_wait_firmware_ready(acb);
3075 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
3076 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
3077 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
3078 miscellaneous data' timeout \n", acb->host->host_no);
3079 return false;
3080 }
3081 arcmsr_get_adapter_config(acb, reg->message_rwbuffer);
3082 return true;
3083}
3084static bool arcmsr_hbaB_get_config(struct AdapterControlBlock *acb)
3085{
3086 struct MessageUnit_B *reg = acb->pmuB;
3087
3088 arcmsr_wait_firmware_ready(acb);
3089 writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
3090 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
3091 printk(KERN_ERR "arcmsr%d: can't set driver mode.\n", acb->host->host_no);
3092 return false;
3093 }
3094 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
3095 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
3096 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
3097 miscellaneous data' timeout \n", acb->host->host_no);
3098 return false;
3099 }
3100 arcmsr_get_adapter_config(acb, reg->message_rwbuffer);
3101 return true;
3102}
3103
3104static bool arcmsr_hbaC_get_config(struct AdapterControlBlock *pACB)
3105{
3106 uint32_t intmask_org;
3107 struct MessageUnit_C __iomem *reg = pACB->pmuC;
3108
3109
3110 intmask_org = readl(®->host_int_mask);
3111 writel(intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE, ®->host_int_mask);
3112
3113 arcmsr_wait_firmware_ready(pACB);
3114
3115 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
3116 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
3117
3118 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
3119 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
3120 miscellaneous data' timeout \n", pACB->host->host_no);
3121 return false;
3122 }
3123 arcmsr_get_adapter_config(pACB, reg->msgcode_rwbuffer);
3124 return true;
3125}
3126
3127static bool arcmsr_hbaD_get_config(struct AdapterControlBlock *acb)
3128{
3129 struct MessageUnit_D *reg = acb->pmuD;
3130
3131 if (readl(acb->pmuD->outbound_doorbell) &
3132 ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) {
3133 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE,
3134 acb->pmuD->outbound_doorbell);
3135 }
3136 arcmsr_wait_firmware_ready(acb);
3137
3138 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0);
3139
3140 if (!arcmsr_hbaD_wait_msgint_ready(acb)) {
3141 pr_notice("arcmsr%d: wait get adapter firmware "
3142 "miscellaneous data timeout\n", acb->host->host_no);
3143 return false;
3144 }
3145 arcmsr_get_adapter_config(acb, reg->msgcode_rwbuffer);
3146 return true;
3147}
3148
3149static bool arcmsr_hbaE_get_config(struct AdapterControlBlock *pACB)
3150{
3151 struct MessageUnit_E __iomem *reg = pACB->pmuE;
3152 uint32_t intmask_org;
3153
3154
3155 intmask_org = readl(®->host_int_mask);
3156 writel(intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE, ®->host_int_mask);
3157
3158 arcmsr_wait_firmware_ready(pACB);
3159 mdelay(20);
3160
3161 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
3162
3163 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3164 writel(pACB->out_doorbell, ®->iobound_doorbell);
3165
3166 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
3167 pr_notice("arcmsr%d: wait get adapter firmware "
3168 "miscellaneous data timeout\n", pACB->host->host_no);
3169 return false;
3170 }
3171 arcmsr_get_adapter_config(pACB, reg->msgcode_rwbuffer);
3172 return true;
3173}
3174
3175static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
3176{
3177 bool rtn = false;
3178
3179 switch (acb->adapter_type) {
3180 case ACB_ADAPTER_TYPE_A:
3181 rtn = arcmsr_hbaA_get_config(acb);
3182 break;
3183 case ACB_ADAPTER_TYPE_B:
3184 rtn = arcmsr_hbaB_get_config(acb);
3185 break;
3186 case ACB_ADAPTER_TYPE_C:
3187 rtn = arcmsr_hbaC_get_config(acb);
3188 break;
3189 case ACB_ADAPTER_TYPE_D:
3190 rtn = arcmsr_hbaD_get_config(acb);
3191 break;
3192 case ACB_ADAPTER_TYPE_E:
3193 rtn = arcmsr_hbaE_get_config(acb);
3194 break;
3195 default:
3196 break;
3197 }
3198 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3199 if (acb->host->can_queue >= acb->firm_numbers_queue)
3200 acb->host->can_queue = acb->maxOutstanding;
3201 else
3202 acb->maxOutstanding = acb->host->can_queue;
3203 acb->maxFreeCCB = acb->host->can_queue;
3204 if (acb->maxFreeCCB < ARCMSR_MAX_FREECCB_NUM)
3205 acb->maxFreeCCB += 64;
3206 return rtn;
3207}
3208
3209static int arcmsr_hbaA_polling_ccbdone(struct AdapterControlBlock *acb,
3210 struct CommandControlBlock *poll_ccb)
3211{
3212 struct MessageUnit_A __iomem *reg = acb->pmuA;
3213 struct CommandControlBlock *ccb;
3214 struct ARCMSR_CDB *arcmsr_cdb;
3215 uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = 0;
3216 int rtn;
3217 bool error;
3218 polling_hba_ccb_retry:
3219 poll_count++;
3220 outbound_intstatus = readl(®->outbound_intstatus) & acb->outbound_int_enable;
3221 writel(outbound_intstatus, ®->outbound_intstatus);
3222 while (1) {
3223 if ((flag_ccb = readl(®->outbound_queueport)) == 0xFFFFFFFF) {
3224 if (poll_ccb_done){
3225 rtn = SUCCESS;
3226 break;
3227 }else {
3228 msleep(25);
3229 if (poll_count > 100){
3230 rtn = FAILED;
3231 break;
3232 }
3233 goto polling_hba_ccb_retry;
3234 }
3235 }
3236 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
3237 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
3238 poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0;
3239 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
3240 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
3241 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
3242 " poll command abort successfully \n"
3243 , acb->host->host_no
3244 , ccb->pcmd->device->id
3245 , (u32)ccb->pcmd->device->lun
3246 , ccb);
3247 ccb->pcmd->result = DID_ABORT << 16;
3248 arcmsr_ccb_complete(ccb);
3249 continue;
3250 }
3251 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
3252 " command done ccb = '0x%p'"
3253 "ccboutstandingcount = %d \n"
3254 , acb->host->host_no
3255 , ccb
3256 , atomic_read(&acb->ccboutstandingcount));
3257 continue;
3258 }
3259 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
3260 arcmsr_report_ccb_state(acb, ccb, error);
3261 }
3262 return rtn;
3263}
3264
3265static int arcmsr_hbaB_polling_ccbdone(struct AdapterControlBlock *acb,
3266 struct CommandControlBlock *poll_ccb)
3267{
3268 struct MessageUnit_B *reg = acb->pmuB;
3269 struct ARCMSR_CDB *arcmsr_cdb;
3270 struct CommandControlBlock *ccb;
3271 uint32_t flag_ccb, poll_ccb_done = 0, poll_count = 0;
3272 int index, rtn;
3273 bool error;
3274 polling_hbb_ccb_retry:
3275
3276 poll_count++;
3277
3278 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
3279 while(1){
3280 index = reg->doneq_index;
3281 flag_ccb = reg->done_qbuffer[index];
3282 if (flag_ccb == 0) {
3283 if (poll_ccb_done){
3284 rtn = SUCCESS;
3285 break;
3286 }else {
3287 msleep(25);
3288 if (poll_count > 100){
3289 rtn = FAILED;
3290 break;
3291 }
3292 goto polling_hbb_ccb_retry;
3293 }
3294 }
3295 reg->done_qbuffer[index] = 0;
3296 index++;
3297
3298 index %= ARCMSR_MAX_HBB_POSTQUEUE;
3299 reg->doneq_index = index;
3300
3301 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
3302 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
3303 poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0;
3304 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
3305 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
3306 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
3307 " poll command abort successfully \n"
3308 ,acb->host->host_no
3309 ,ccb->pcmd->device->id
3310 ,(u32)ccb->pcmd->device->lun
3311 ,ccb);
3312 ccb->pcmd->result = DID_ABORT << 16;
3313 arcmsr_ccb_complete(ccb);
3314 continue;
3315 }
3316 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
3317 " command done ccb = '0x%p'"
3318 "ccboutstandingcount = %d \n"
3319 , acb->host->host_no
3320 , ccb
3321 , atomic_read(&acb->ccboutstandingcount));
3322 continue;
3323 }
3324 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
3325 arcmsr_report_ccb_state(acb, ccb, error);
3326 }
3327 return rtn;
3328}
3329
3330static int arcmsr_hbaC_polling_ccbdone(struct AdapterControlBlock *acb,
3331 struct CommandControlBlock *poll_ccb)
3332{
3333 struct MessageUnit_C __iomem *reg = acb->pmuC;
3334 uint32_t flag_ccb, ccb_cdb_phy;
3335 struct ARCMSR_CDB *arcmsr_cdb;
3336 bool error;
3337 struct CommandControlBlock *pCCB;
3338 uint32_t poll_ccb_done = 0, poll_count = 0;
3339 int rtn;
3340polling_hbc_ccb_retry:
3341 poll_count++;
3342 while (1) {
3343 if ((readl(®->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) == 0) {
3344 if (poll_ccb_done) {
3345 rtn = SUCCESS;
3346 break;
3347 } else {
3348 msleep(25);
3349 if (poll_count > 100) {
3350 rtn = FAILED;
3351 break;
3352 }
3353 goto polling_hbc_ccb_retry;
3354 }
3355 }
3356 flag_ccb = readl(®->outbound_queueport_low);
3357 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
3358 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
3359 pCCB = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
3360 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
3361
3362 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
3363 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
3364 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
3365 " poll command abort successfully \n"
3366 , acb->host->host_no
3367 , pCCB->pcmd->device->id
3368 , (u32)pCCB->pcmd->device->lun
3369 , pCCB);
3370 pCCB->pcmd->result = DID_ABORT << 16;
3371 arcmsr_ccb_complete(pCCB);
3372 continue;
3373 }
3374 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
3375 " command done ccb = '0x%p'"
3376 "ccboutstandingcount = %d \n"
3377 , acb->host->host_no
3378 , pCCB
3379 , atomic_read(&acb->ccboutstandingcount));
3380 continue;
3381 }
3382 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
3383 arcmsr_report_ccb_state(acb, pCCB, error);
3384 }
3385 return rtn;
3386}
3387
3388static int arcmsr_hbaD_polling_ccbdone(struct AdapterControlBlock *acb,
3389 struct CommandControlBlock *poll_ccb)
3390{
3391 bool error;
3392 uint32_t poll_ccb_done = 0, poll_count = 0, flag_ccb, ccb_cdb_phy;
3393 int rtn, doneq_index, index_stripped, outbound_write_pointer, toggle;
3394 unsigned long flags;
3395 struct ARCMSR_CDB *arcmsr_cdb;
3396 struct CommandControlBlock *pCCB;
3397 struct MessageUnit_D *pmu = acb->pmuD;
3398
3399polling_hbaD_ccb_retry:
3400 poll_count++;
3401 while (1) {
3402 spin_lock_irqsave(&acb->doneq_lock, flags);
3403 outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1;
3404 doneq_index = pmu->doneq_index;
3405 if ((outbound_write_pointer & 0xFFF) == (doneq_index & 0xFFF)) {
3406 spin_unlock_irqrestore(&acb->doneq_lock, flags);
3407 if (poll_ccb_done) {
3408 rtn = SUCCESS;
3409 break;
3410 } else {
3411 msleep(25);
3412 if (poll_count > 40) {
3413 rtn = FAILED;
3414 break;
3415 }
3416 goto polling_hbaD_ccb_retry;
3417 }
3418 }
3419 toggle = doneq_index & 0x4000;
3420 index_stripped = (doneq_index & 0xFFF) + 1;
3421 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
3422 pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
3423 ((toggle ^ 0x4000) + 1);
3424 doneq_index = pmu->doneq_index;
3425 spin_unlock_irqrestore(&acb->doneq_lock, flags);
3426 flag_ccb = pmu->done_qbuffer[doneq_index & 0xFFF].addressLow;
3427 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
3428 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset +
3429 ccb_cdb_phy);
3430 pCCB = container_of(arcmsr_cdb, struct CommandControlBlock,
3431 arcmsr_cdb);
3432 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
3433 if ((pCCB->acb != acb) ||
3434 (pCCB->startdone != ARCMSR_CCB_START)) {
3435 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
3436 pr_notice("arcmsr%d: scsi id = %d "
3437 "lun = %d ccb = '0x%p' poll command "
3438 "abort successfully\n"
3439 , acb->host->host_no
3440 , pCCB->pcmd->device->id
3441 , (u32)pCCB->pcmd->device->lun
3442 , pCCB);
3443 pCCB->pcmd->result = DID_ABORT << 16;
3444 arcmsr_ccb_complete(pCCB);
3445 continue;
3446 }
3447 pr_notice("arcmsr%d: polling an illegal "
3448 "ccb command done ccb = '0x%p' "
3449 "ccboutstandingcount = %d\n"
3450 , acb->host->host_no
3451 , pCCB
3452 , atomic_read(&acb->ccboutstandingcount));
3453 continue;
3454 }
3455 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
3456 ? true : false;
3457 arcmsr_report_ccb_state(acb, pCCB, error);
3458 }
3459 return rtn;
3460}
3461
3462static int arcmsr_hbaE_polling_ccbdone(struct AdapterControlBlock *acb,
3463 struct CommandControlBlock *poll_ccb)
3464{
3465 bool error;
3466 uint32_t poll_ccb_done = 0, poll_count = 0, doneq_index;
3467 uint16_t cmdSMID;
3468 unsigned long flags;
3469 int rtn;
3470 struct CommandControlBlock *pCCB;
3471 struct MessageUnit_E __iomem *reg = acb->pmuE;
3472
3473 polling_hbaC_ccb_retry:
3474 poll_count++;
3475 while (1) {
3476 spin_lock_irqsave(&acb->doneq_lock, flags);
3477 doneq_index = acb->doneq_index;
3478 if ((readl(®->reply_post_producer_index) & 0xFFFF) ==
3479 doneq_index) {
3480 spin_unlock_irqrestore(&acb->doneq_lock, flags);
3481 if (poll_ccb_done) {
3482 rtn = SUCCESS;
3483 break;
3484 } else {
3485 msleep(25);
3486 if (poll_count > 40) {
3487 rtn = FAILED;
3488 break;
3489 }
3490 goto polling_hbaC_ccb_retry;
3491 }
3492 }
3493 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
3494 doneq_index++;
3495 if (doneq_index >= acb->completionQ_entry)
3496 doneq_index = 0;
3497 acb->doneq_index = doneq_index;
3498 spin_unlock_irqrestore(&acb->doneq_lock, flags);
3499 pCCB = acb->pccb_pool[cmdSMID];
3500 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
3501
3502 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
3503 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
3504 pr_notice("arcmsr%d: scsi id = %d "
3505 "lun = %d ccb = '0x%p' poll command "
3506 "abort successfully\n"
3507 , acb->host->host_no
3508 , pCCB->pcmd->device->id
3509 , (u32)pCCB->pcmd->device->lun
3510 , pCCB);
3511 pCCB->pcmd->result = DID_ABORT << 16;
3512 arcmsr_ccb_complete(pCCB);
3513 continue;
3514 }
3515 pr_notice("arcmsr%d: polling an illegal "
3516 "ccb command done ccb = '0x%p' "
3517 "ccboutstandingcount = %d\n"
3518 , acb->host->host_no
3519 , pCCB
3520 , atomic_read(&acb->ccboutstandingcount));
3521 continue;
3522 }
3523 error = (acb->pCompletionQ[doneq_index].cmdFlag &
3524 ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
3525 arcmsr_report_ccb_state(acb, pCCB, error);
3526 }
3527 writel(doneq_index, ®->reply_post_consumer_index);
3528 return rtn;
3529}
3530
3531static int arcmsr_polling_ccbdone(struct AdapterControlBlock *acb,
3532 struct CommandControlBlock *poll_ccb)
3533{
3534 int rtn = 0;
3535 switch (acb->adapter_type) {
3536
3537 case ACB_ADAPTER_TYPE_A: {
3538 rtn = arcmsr_hbaA_polling_ccbdone(acb, poll_ccb);
3539 }
3540 break;
3541
3542 case ACB_ADAPTER_TYPE_B: {
3543 rtn = arcmsr_hbaB_polling_ccbdone(acb, poll_ccb);
3544 }
3545 break;
3546 case ACB_ADAPTER_TYPE_C: {
3547 rtn = arcmsr_hbaC_polling_ccbdone(acb, poll_ccb);
3548 }
3549 break;
3550 case ACB_ADAPTER_TYPE_D:
3551 rtn = arcmsr_hbaD_polling_ccbdone(acb, poll_ccb);
3552 break;
3553 case ACB_ADAPTER_TYPE_E:
3554 rtn = arcmsr_hbaE_polling_ccbdone(acb, poll_ccb);
3555 break;
3556 }
3557 return rtn;
3558}
3559
3560static void arcmsr_set_iop_datetime(struct timer_list *t)
3561{
3562 struct AdapterControlBlock *pacb = from_timer(pacb, t, refresh_timer);
3563 unsigned int next_time;
3564 struct tm tm;
3565
3566 union {
3567 struct {
3568 uint16_t signature;
3569 uint8_t year;
3570 uint8_t month;
3571 uint8_t date;
3572 uint8_t hour;
3573 uint8_t minute;
3574 uint8_t second;
3575 } a;
3576 struct {
3577 uint32_t msg_time[2];
3578 } b;
3579 } datetime;
3580
3581 time64_to_tm(ktime_get_real_seconds(), -sys_tz.tz_minuteswest * 60, &tm);
3582
3583 datetime.a.signature = 0x55AA;
3584 datetime.a.year = tm.tm_year - 100;
3585 datetime.a.month = tm.tm_mon;
3586 datetime.a.date = tm.tm_mday;
3587 datetime.a.hour = tm.tm_hour;
3588 datetime.a.minute = tm.tm_min;
3589 datetime.a.second = tm.tm_sec;
3590
3591 switch (pacb->adapter_type) {
3592 case ACB_ADAPTER_TYPE_A: {
3593 struct MessageUnit_A __iomem *reg = pacb->pmuA;
3594 writel(datetime.b.msg_time[0], ®->message_rwbuffer[0]);
3595 writel(datetime.b.msg_time[1], ®->message_rwbuffer[1]);
3596 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0);
3597 break;
3598 }
3599 case ACB_ADAPTER_TYPE_B: {
3600 uint32_t __iomem *rwbuffer;
3601 struct MessageUnit_B *reg = pacb->pmuB;
3602 rwbuffer = reg->message_rwbuffer;
3603 writel(datetime.b.msg_time[0], rwbuffer++);
3604 writel(datetime.b.msg_time[1], rwbuffer++);
3605 writel(ARCMSR_MESSAGE_SYNC_TIMER, reg->drv2iop_doorbell);
3606 break;
3607 }
3608 case ACB_ADAPTER_TYPE_C: {
3609 struct MessageUnit_C __iomem *reg = pacb->pmuC;
3610 writel(datetime.b.msg_time[0], ®->msgcode_rwbuffer[0]);
3611 writel(datetime.b.msg_time[1], ®->msgcode_rwbuffer[1]);
3612 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0);
3613 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
3614 break;
3615 }
3616 case ACB_ADAPTER_TYPE_D: {
3617 uint32_t __iomem *rwbuffer;
3618 struct MessageUnit_D *reg = pacb->pmuD;
3619 rwbuffer = reg->msgcode_rwbuffer;
3620 writel(datetime.b.msg_time[0], rwbuffer++);
3621 writel(datetime.b.msg_time[1], rwbuffer++);
3622 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, reg->inbound_msgaddr0);
3623 break;
3624 }
3625 case ACB_ADAPTER_TYPE_E: {
3626 struct MessageUnit_E __iomem *reg = pacb->pmuE;
3627 writel(datetime.b.msg_time[0], ®->msgcode_rwbuffer[0]);
3628 writel(datetime.b.msg_time[1], ®->msgcode_rwbuffer[1]);
3629 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0);
3630 pacb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3631 writel(pacb->out_doorbell, ®->iobound_doorbell);
3632 break;
3633 }
3634 }
3635 if (sys_tz.tz_minuteswest)
3636 next_time = ARCMSR_HOURS;
3637 else
3638 next_time = ARCMSR_MINUTES;
3639 mod_timer(&pacb->refresh_timer, jiffies + msecs_to_jiffies(next_time));
3640}
3641
3642static int arcmsr_iop_confirm(struct AdapterControlBlock *acb)
3643{
3644 uint32_t cdb_phyaddr, cdb_phyaddr_hi32;
3645 dma_addr_t dma_coherent_handle;
3646
3647
3648
3649
3650
3651
3652
3653 switch (acb->adapter_type) {
3654 case ACB_ADAPTER_TYPE_B:
3655 case ACB_ADAPTER_TYPE_D:
3656 dma_coherent_handle = acb->dma_coherent_handle2;
3657 break;
3658 case ACB_ADAPTER_TYPE_E:
3659 dma_coherent_handle = acb->dma_coherent_handle +
3660 offsetof(struct CommandControlBlock, arcmsr_cdb);
3661 break;
3662 default:
3663 dma_coherent_handle = acb->dma_coherent_handle;
3664 break;
3665 }
3666 cdb_phyaddr = lower_32_bits(dma_coherent_handle);
3667 cdb_phyaddr_hi32 = upper_32_bits(dma_coherent_handle);
3668 acb->cdb_phyaddr_hi32 = cdb_phyaddr_hi32;
3669
3670
3671
3672
3673
3674 switch (acb->adapter_type) {
3675
3676 case ACB_ADAPTER_TYPE_A: {
3677 if (cdb_phyaddr_hi32 != 0) {
3678 struct MessageUnit_A __iomem *reg = acb->pmuA;
3679 writel(ARCMSR_SIGNATURE_SET_CONFIG, \
3680 ®->message_rwbuffer[0]);
3681 writel(cdb_phyaddr_hi32, ®->message_rwbuffer[1]);
3682 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, \
3683 ®->inbound_msgaddr0);
3684 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
3685 printk(KERN_NOTICE "arcmsr%d: ""set ccb high \
3686 part physical address timeout\n",
3687 acb->host->host_no);
3688 return 1;
3689 }
3690 }
3691 }
3692 break;
3693
3694 case ACB_ADAPTER_TYPE_B: {
3695 uint32_t __iomem *rwbuffer;
3696
3697 struct MessageUnit_B *reg = acb->pmuB;
3698 reg->postq_index = 0;
3699 reg->doneq_index = 0;
3700 writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell);
3701 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
3702 printk(KERN_NOTICE "arcmsr%d: cannot set driver mode\n", \
3703 acb->host->host_no);
3704 return 1;
3705 }
3706 rwbuffer = reg->message_rwbuffer;
3707
3708 writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
3709
3710 writel(cdb_phyaddr_hi32, rwbuffer++);
3711
3712 writel(cdb_phyaddr, rwbuffer++);
3713
3714 writel(cdb_phyaddr + 1056, rwbuffer++);
3715
3716 writel(1056, rwbuffer);
3717
3718 writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell);
3719 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
3720 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
3721 timeout \n",acb->host->host_no);
3722 return 1;
3723 }
3724 writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
3725 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
3726 pr_err("arcmsr%d: can't set driver mode.\n",
3727 acb->host->host_no);
3728 return 1;
3729 }
3730 }
3731 break;
3732 case ACB_ADAPTER_TYPE_C: {
3733 if (cdb_phyaddr_hi32 != 0) {
3734 struct MessageUnit_C __iomem *reg = acb->pmuC;
3735
3736 printk(KERN_NOTICE "arcmsr%d: cdb_phyaddr_hi32=0x%x\n",
3737 acb->adapter_index, cdb_phyaddr_hi32);
3738 writel(ARCMSR_SIGNATURE_SET_CONFIG, ®->msgcode_rwbuffer[0]);
3739 writel(cdb_phyaddr_hi32, ®->msgcode_rwbuffer[1]);
3740 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, ®->inbound_msgaddr0);
3741 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
3742 if (!arcmsr_hbaC_wait_msgint_ready(acb)) {
3743 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
3744 timeout \n", acb->host->host_no);
3745 return 1;
3746 }
3747 }
3748 }
3749 break;
3750 case ACB_ADAPTER_TYPE_D: {
3751 uint32_t __iomem *rwbuffer;
3752 struct MessageUnit_D *reg = acb->pmuD;
3753 reg->postq_index = 0;
3754 reg->doneq_index = 0;
3755 rwbuffer = reg->msgcode_rwbuffer;
3756 writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
3757 writel(cdb_phyaddr_hi32, rwbuffer++);
3758 writel(cdb_phyaddr, rwbuffer++);
3759 writel(cdb_phyaddr + (ARCMSR_MAX_ARC1214_POSTQUEUE *
3760 sizeof(struct InBound_SRB)), rwbuffer++);
3761 writel(0x100, rwbuffer);
3762 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, reg->inbound_msgaddr0);
3763 if (!arcmsr_hbaD_wait_msgint_ready(acb)) {
3764 pr_notice("arcmsr%d: 'set command Q window' timeout\n",
3765 acb->host->host_no);
3766 return 1;
3767 }
3768 }
3769 break;
3770 case ACB_ADAPTER_TYPE_E: {
3771 struct MessageUnit_E __iomem *reg = acb->pmuE;
3772 writel(ARCMSR_SIGNATURE_SET_CONFIG, ®->msgcode_rwbuffer[0]);
3773 writel(ARCMSR_SIGNATURE_1884, ®->msgcode_rwbuffer[1]);
3774 writel(cdb_phyaddr, ®->msgcode_rwbuffer[2]);
3775 writel(cdb_phyaddr_hi32, ®->msgcode_rwbuffer[3]);
3776 writel(acb->ccbsize, ®->msgcode_rwbuffer[4]);
3777 dma_coherent_handle = acb->dma_coherent_handle2;
3778 cdb_phyaddr = (uint32_t)(dma_coherent_handle & 0xffffffff);
3779 cdb_phyaddr_hi32 = (uint32_t)((dma_coherent_handle >> 16) >> 16);
3780 writel(cdb_phyaddr, ®->msgcode_rwbuffer[5]);
3781 writel(cdb_phyaddr_hi32, ®->msgcode_rwbuffer[6]);
3782 writel(acb->roundup_ccbsize, ®->msgcode_rwbuffer[7]);
3783 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, ®->inbound_msgaddr0);
3784 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3785 writel(acb->out_doorbell, ®->iobound_doorbell);
3786 if (!arcmsr_hbaE_wait_msgint_ready(acb)) {
3787 pr_notice("arcmsr%d: 'set command Q window' timeout \n",
3788 acb->host->host_no);
3789 return 1;
3790 }
3791 }
3792 break;
3793 }
3794 return 0;
3795}
3796
3797static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb)
3798{
3799 uint32_t firmware_state = 0;
3800 switch (acb->adapter_type) {
3801
3802 case ACB_ADAPTER_TYPE_A: {
3803 struct MessageUnit_A __iomem *reg = acb->pmuA;
3804 do {
3805 if (!(acb->acb_flags & ACB_F_IOP_INITED))
3806 msleep(20);
3807 firmware_state = readl(®->outbound_msgaddr1);
3808 } while ((firmware_state & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0);
3809 }
3810 break;
3811
3812 case ACB_ADAPTER_TYPE_B: {
3813 struct MessageUnit_B *reg = acb->pmuB;
3814 do {
3815 if (!(acb->acb_flags & ACB_F_IOP_INITED))
3816 msleep(20);
3817 firmware_state = readl(reg->iop2drv_doorbell);
3818 } while ((firmware_state & ARCMSR_MESSAGE_FIRMWARE_OK) == 0);
3819 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
3820 }
3821 break;
3822 case ACB_ADAPTER_TYPE_C: {
3823 struct MessageUnit_C __iomem *reg = acb->pmuC;
3824 do {
3825 if (!(acb->acb_flags & ACB_F_IOP_INITED))
3826 msleep(20);
3827 firmware_state = readl(®->outbound_msgaddr1);
3828 } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
3829 }
3830 break;
3831 case ACB_ADAPTER_TYPE_D: {
3832 struct MessageUnit_D *reg = acb->pmuD;
3833 do {
3834 if (!(acb->acb_flags & ACB_F_IOP_INITED))
3835 msleep(20);
3836 firmware_state = readl(reg->outbound_msgaddr1);
3837 } while ((firmware_state &
3838 ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK) == 0);
3839 }
3840 break;
3841 case ACB_ADAPTER_TYPE_E: {
3842 struct MessageUnit_E __iomem *reg = acb->pmuE;
3843 do {
3844 if (!(acb->acb_flags & ACB_F_IOP_INITED))
3845 msleep(20);
3846 firmware_state = readl(®->outbound_msgaddr1);
3847 } while ((firmware_state & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0);
3848 }
3849 break;
3850 }
3851}
3852
3853static void arcmsr_request_device_map(struct timer_list *t)
3854{
3855 struct AdapterControlBlock *acb = from_timer(acb, t, eternal_timer);
3856 if (unlikely(atomic_read(&acb->rq_map_token) == 0) ||
3857 (acb->acb_flags & ACB_F_BUS_RESET) ||
3858 (acb->acb_flags & ACB_F_ABORT)) {
3859 mod_timer(&acb->eternal_timer,
3860 jiffies + msecs_to_jiffies(6 * HZ));
3861 } else {
3862 acb->fw_flag = FW_NORMAL;
3863 if (atomic_read(&acb->ante_token_value) ==
3864 atomic_read(&acb->rq_map_token)) {
3865 atomic_set(&acb->rq_map_token, 16);
3866 }
3867 atomic_set(&acb->ante_token_value,
3868 atomic_read(&acb->rq_map_token));
3869 if (atomic_dec_and_test(&acb->rq_map_token)) {
3870 mod_timer(&acb->eternal_timer, jiffies +
3871 msecs_to_jiffies(6 * HZ));
3872 return;
3873 }
3874 switch (acb->adapter_type) {
3875 case ACB_ADAPTER_TYPE_A: {
3876 struct MessageUnit_A __iomem *reg = acb->pmuA;
3877 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
3878 break;
3879 }
3880 case ACB_ADAPTER_TYPE_B: {
3881 struct MessageUnit_B *reg = acb->pmuB;
3882 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
3883 break;
3884 }
3885 case ACB_ADAPTER_TYPE_C: {
3886 struct MessageUnit_C __iomem *reg = acb->pmuC;
3887 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
3888 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
3889 break;
3890 }
3891 case ACB_ADAPTER_TYPE_D: {
3892 struct MessageUnit_D *reg = acb->pmuD;
3893 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0);
3894 break;
3895 }
3896 case ACB_ADAPTER_TYPE_E: {
3897 struct MessageUnit_E __iomem *reg = acb->pmuE;
3898 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
3899 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3900 writel(acb->out_doorbell, ®->iobound_doorbell);
3901 break;
3902 }
3903 default:
3904 return;
3905 }
3906 acb->acb_flags |= ACB_F_MSG_GET_CONFIG;
3907 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
3908 }
3909}
3910
3911static void arcmsr_hbaA_start_bgrb(struct AdapterControlBlock *acb)
3912{
3913 struct MessageUnit_A __iomem *reg = acb->pmuA;
3914 acb->acb_flags |= ACB_F_MSG_START_BGRB;
3915 writel(ARCMSR_INBOUND_MESG0_START_BGRB, ®->inbound_msgaddr0);
3916 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
3917 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
3918 rebulid' timeout \n", acb->host->host_no);
3919 }
3920}
3921
3922static void arcmsr_hbaB_start_bgrb(struct AdapterControlBlock *acb)
3923{
3924 struct MessageUnit_B *reg = acb->pmuB;
3925 acb->acb_flags |= ACB_F_MSG_START_BGRB;
3926 writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell);
3927 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
3928 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
3929 rebulid' timeout \n",acb->host->host_no);
3930 }
3931}
3932
3933static void arcmsr_hbaC_start_bgrb(struct AdapterControlBlock *pACB)
3934{
3935 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
3936 pACB->acb_flags |= ACB_F_MSG_START_BGRB;
3937 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &phbcmu->inbound_msgaddr0);
3938 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &phbcmu->inbound_doorbell);
3939 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
3940 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
3941 rebulid' timeout \n", pACB->host->host_no);
3942 }
3943 return;
3944}
3945
3946static void arcmsr_hbaD_start_bgrb(struct AdapterControlBlock *pACB)
3947{
3948 struct MessageUnit_D *pmu = pACB->pmuD;
3949
3950 pACB->acb_flags |= ACB_F_MSG_START_BGRB;
3951 writel(ARCMSR_INBOUND_MESG0_START_BGRB, pmu->inbound_msgaddr0);
3952 if (!arcmsr_hbaD_wait_msgint_ready(pACB)) {
3953 pr_notice("arcmsr%d: wait 'start adapter "
3954 "background rebulid' timeout\n", pACB->host->host_no);
3955 }
3956}
3957
3958static void arcmsr_hbaE_start_bgrb(struct AdapterControlBlock *pACB)
3959{
3960 struct MessageUnit_E __iomem *pmu = pACB->pmuE;
3961
3962 pACB->acb_flags |= ACB_F_MSG_START_BGRB;
3963 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &pmu->inbound_msgaddr0);
3964 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3965 writel(pACB->out_doorbell, &pmu->iobound_doorbell);
3966 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
3967 pr_notice("arcmsr%d: wait 'start adapter "
3968 "background rebulid' timeout \n", pACB->host->host_no);
3969 }
3970}
3971
3972static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
3973{
3974 switch (acb->adapter_type) {
3975 case ACB_ADAPTER_TYPE_A:
3976 arcmsr_hbaA_start_bgrb(acb);
3977 break;
3978 case ACB_ADAPTER_TYPE_B:
3979 arcmsr_hbaB_start_bgrb(acb);
3980 break;
3981 case ACB_ADAPTER_TYPE_C:
3982 arcmsr_hbaC_start_bgrb(acb);
3983 break;
3984 case ACB_ADAPTER_TYPE_D:
3985 arcmsr_hbaD_start_bgrb(acb);
3986 break;
3987 case ACB_ADAPTER_TYPE_E:
3988 arcmsr_hbaE_start_bgrb(acb);
3989 break;
3990 }
3991}
3992
3993static void arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock *acb)
3994{
3995 switch (acb->adapter_type) {
3996 case ACB_ADAPTER_TYPE_A: {
3997 struct MessageUnit_A __iomem *reg = acb->pmuA;
3998 uint32_t outbound_doorbell;
3999
4000 outbound_doorbell = readl(®->outbound_doorbell);
4001
4002 writel(outbound_doorbell, ®->outbound_doorbell);
4003 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, ®->inbound_doorbell);
4004 }
4005 break;
4006
4007 case ACB_ADAPTER_TYPE_B: {
4008 struct MessageUnit_B *reg = acb->pmuB;
4009 uint32_t outbound_doorbell, i;
4010 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
4011 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
4012
4013 for(i=0; i < 200; i++) {
4014 msleep(20);
4015 outbound_doorbell = readl(reg->iop2drv_doorbell);
4016 if( outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
4017 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
4018 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
4019 } else
4020 break;
4021 }
4022 }
4023 break;
4024 case ACB_ADAPTER_TYPE_C: {
4025 struct MessageUnit_C __iomem *reg = acb->pmuC;
4026 uint32_t outbound_doorbell, i;
4027
4028 outbound_doorbell = readl(®->outbound_doorbell);
4029 writel(outbound_doorbell, ®->outbound_doorbell_clear);
4030 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, ®->inbound_doorbell);
4031 for (i = 0; i < 200; i++) {
4032 msleep(20);
4033 outbound_doorbell = readl(®->outbound_doorbell);
4034 if (outbound_doorbell &
4035 ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
4036 writel(outbound_doorbell,
4037 ®->outbound_doorbell_clear);
4038 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK,
4039 ®->inbound_doorbell);
4040 } else
4041 break;
4042 }
4043 }
4044 break;
4045 case ACB_ADAPTER_TYPE_D: {
4046 struct MessageUnit_D *reg = acb->pmuD;
4047 uint32_t outbound_doorbell, i;
4048
4049 outbound_doorbell = readl(reg->outbound_doorbell);
4050 writel(outbound_doorbell, reg->outbound_doorbell);
4051 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
4052 reg->inbound_doorbell);
4053 for (i = 0; i < 200; i++) {
4054 msleep(20);
4055 outbound_doorbell = readl(reg->outbound_doorbell);
4056 if (outbound_doorbell &
4057 ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK) {
4058 writel(outbound_doorbell,
4059 reg->outbound_doorbell);
4060 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
4061 reg->inbound_doorbell);
4062 } else
4063 break;
4064 }
4065 }
4066 break;
4067 case ACB_ADAPTER_TYPE_E: {
4068 struct MessageUnit_E __iomem *reg = acb->pmuE;
4069 uint32_t i, tmp;
4070
4071 acb->in_doorbell = readl(®->iobound_doorbell);
4072 writel(0, ®->host_int_status);
4073 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
4074 writel(acb->out_doorbell, ®->iobound_doorbell);
4075 for(i=0; i < 200; i++) {
4076 msleep(20);
4077 tmp = acb->in_doorbell;
4078 acb->in_doorbell = readl(®->iobound_doorbell);
4079 if((tmp ^ acb->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) {
4080 writel(0, ®->host_int_status);
4081 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
4082 writel(acb->out_doorbell, ®->iobound_doorbell);
4083 } else
4084 break;
4085 }
4086 }
4087 break;
4088 }
4089}
4090
4091static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
4092{
4093 switch (acb->adapter_type) {
4094 case ACB_ADAPTER_TYPE_A:
4095 return;
4096 case ACB_ADAPTER_TYPE_B:
4097 {
4098 struct MessageUnit_B *reg = acb->pmuB;
4099 writel(ARCMSR_MESSAGE_ACTIVE_EOI_MODE, reg->drv2iop_doorbell);
4100 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
4101 printk(KERN_NOTICE "ARCMSR IOP enables EOI_MODE TIMEOUT");
4102 return;
4103 }
4104 }
4105 break;
4106 case ACB_ADAPTER_TYPE_C:
4107 return;
4108 }
4109 return;
4110}
4111
4112static void arcmsr_hardware_reset(struct AdapterControlBlock *acb)
4113{
4114 uint8_t value[64];
4115 int i, count = 0;
4116 struct MessageUnit_A __iomem *pmuA = acb->pmuA;
4117 struct MessageUnit_C __iomem *pmuC = acb->pmuC;
4118 struct MessageUnit_D *pmuD = acb->pmuD;
4119
4120
4121 printk(KERN_NOTICE "arcmsr%d: executing hw bus reset .....\n", acb->host->host_no);
4122 for (i = 0; i < 64; i++) {
4123 pci_read_config_byte(acb->pdev, i, &value[i]);
4124 }
4125
4126 if ((acb->dev_id == 0x1680)) {
4127 writel(ARCMSR_ARC1680_BUS_RESET, &pmuA->reserved1[0]);
4128 } else if ((acb->dev_id == 0x1880)) {
4129 do {
4130 count++;
4131 writel(0xF, &pmuC->write_sequence);
4132 writel(0x4, &pmuC->write_sequence);
4133 writel(0xB, &pmuC->write_sequence);
4134 writel(0x2, &pmuC->write_sequence);
4135 writel(0x7, &pmuC->write_sequence);
4136 writel(0xD, &pmuC->write_sequence);
4137 } while (((readl(&pmuC->host_diagnostic) & ARCMSR_ARC1880_DiagWrite_ENABLE) == 0) && (count < 5));
4138 writel(ARCMSR_ARC1880_RESET_ADAPTER, &pmuC->host_diagnostic);
4139 } else if (acb->dev_id == 0x1884) {
4140 struct MessageUnit_E __iomem *pmuE = acb->pmuE;
4141 do {
4142 count++;
4143 writel(0x4, &pmuE->write_sequence_3xxx);
4144 writel(0xB, &pmuE->write_sequence_3xxx);
4145 writel(0x2, &pmuE->write_sequence_3xxx);
4146 writel(0x7, &pmuE->write_sequence_3xxx);
4147 writel(0xD, &pmuE->write_sequence_3xxx);
4148 mdelay(10);
4149 } while (((readl(&pmuE->host_diagnostic_3xxx) &
4150 ARCMSR_ARC1884_DiagWrite_ENABLE) == 0) && (count < 5));
4151 writel(ARCMSR_ARC188X_RESET_ADAPTER, &pmuE->host_diagnostic_3xxx);
4152 } else if ((acb->dev_id == 0x1214)) {
4153 writel(0x20, pmuD->reset_request);
4154 } else {
4155 pci_write_config_byte(acb->pdev, 0x84, 0x20);
4156 }
4157 msleep(2000);
4158
4159 for (i = 0; i < 64; i++) {
4160 pci_write_config_byte(acb->pdev, i, value[i]);
4161 }
4162 msleep(1000);
4163 return;
4164}
4165
4166static bool arcmsr_reset_in_progress(struct AdapterControlBlock *acb)
4167{
4168 bool rtn = true;
4169
4170 switch(acb->adapter_type) {
4171 case ACB_ADAPTER_TYPE_A:{
4172 struct MessageUnit_A __iomem *reg = acb->pmuA;
4173 rtn = ((readl(®->outbound_msgaddr1) &
4174 ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) ? true : false;
4175 }
4176 break;
4177 case ACB_ADAPTER_TYPE_B:{
4178 struct MessageUnit_B *reg = acb->pmuB;
4179 rtn = ((readl(reg->iop2drv_doorbell) &
4180 ARCMSR_MESSAGE_FIRMWARE_OK) == 0) ? true : false;
4181 }
4182 break;
4183 case ACB_ADAPTER_TYPE_C:{
4184 struct MessageUnit_C __iomem *reg = acb->pmuC;
4185 rtn = (readl(®->host_diagnostic) & 0x04) ? true : false;
4186 }
4187 break;
4188 case ACB_ADAPTER_TYPE_D:{
4189 struct MessageUnit_D *reg = acb->pmuD;
4190 rtn = ((readl(reg->sample_at_reset) & 0x80) == 0) ?
4191 true : false;
4192 }
4193 break;
4194 case ACB_ADAPTER_TYPE_E:{
4195 struct MessageUnit_E __iomem *reg = acb->pmuE;
4196 rtn = (readl(®->host_diagnostic_3xxx) &
4197 ARCMSR_ARC188X_RESET_ADAPTER) ? true : false;
4198 }
4199 break;
4200 }
4201 return rtn;
4202}
4203
4204static void arcmsr_iop_init(struct AdapterControlBlock *acb)
4205{
4206 uint32_t intmask_org;
4207
4208 intmask_org = arcmsr_disable_outbound_ints(acb);
4209 arcmsr_wait_firmware_ready(acb);
4210 arcmsr_iop_confirm(acb);
4211
4212 arcmsr_start_adapter_bgrb(acb);
4213
4214 arcmsr_clear_doorbell_queue_buffer(acb);
4215 arcmsr_enable_eoi_mode(acb);
4216
4217 arcmsr_enable_outbound_ints(acb, intmask_org);
4218 acb->acb_flags |= ACB_F_IOP_INITED;
4219}
4220
4221static uint8_t arcmsr_iop_reset(struct AdapterControlBlock *acb)
4222{
4223 struct CommandControlBlock *ccb;
4224 uint32_t intmask_org;
4225 uint8_t rtnval = 0x00;
4226 int i = 0;
4227 unsigned long flags;
4228
4229 if (atomic_read(&acb->ccboutstandingcount) != 0) {
4230
4231 intmask_org = arcmsr_disable_outbound_ints(acb);
4232
4233 rtnval = arcmsr_abort_allcmd(acb);
4234
4235 arcmsr_done4abort_postqueue(acb);
4236 for (i = 0; i < acb->maxFreeCCB; i++) {
4237 ccb = acb->pccb_pool[i];
4238 if (ccb->startdone == ARCMSR_CCB_START) {
4239 scsi_dma_unmap(ccb->pcmd);
4240 ccb->startdone = ARCMSR_CCB_DONE;
4241 ccb->ccb_flags = 0;
4242 spin_lock_irqsave(&acb->ccblist_lock, flags);
4243 list_add_tail(&ccb->list, &acb->ccb_free_list);
4244 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
4245 }
4246 }
4247 atomic_set(&acb->ccboutstandingcount, 0);
4248
4249 arcmsr_enable_outbound_ints(acb, intmask_org);
4250 return rtnval;
4251 }
4252 return rtnval;
4253}
4254
4255static int arcmsr_bus_reset(struct scsi_cmnd *cmd)
4256{
4257 struct AdapterControlBlock *acb;
4258 int retry_count = 0;
4259 int rtn = FAILED;
4260 acb = (struct AdapterControlBlock *) cmd->device->host->hostdata;
4261 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED)
4262 return SUCCESS;
4263 pr_notice("arcmsr: executing bus reset eh.....num_resets = %d,"
4264 " num_aborts = %d \n", acb->num_resets, acb->num_aborts);
4265 acb->num_resets++;
4266
4267 if (acb->acb_flags & ACB_F_BUS_RESET) {
4268 long timeout;
4269 pr_notice("arcmsr: there is a bus reset eh proceeding...\n");
4270 timeout = wait_event_timeout(wait_q, (acb->acb_flags
4271 & ACB_F_BUS_RESET) == 0, 220 * HZ);
4272 if (timeout)
4273 return SUCCESS;
4274 }
4275 acb->acb_flags |= ACB_F_BUS_RESET;
4276 if (!arcmsr_iop_reset(acb)) {
4277 arcmsr_hardware_reset(acb);
4278 acb->acb_flags &= ~ACB_F_IOP_INITED;
4279wait_reset_done:
4280 ssleep(ARCMSR_SLEEPTIME);
4281 if (arcmsr_reset_in_progress(acb)) {
4282 if (retry_count > ARCMSR_RETRYCOUNT) {
4283 acb->fw_flag = FW_DEADLOCK;
4284 pr_notice("arcmsr%d: waiting for hw bus reset"
4285 " return, RETRY TERMINATED!!\n",
4286 acb->host->host_no);
4287 return FAILED;
4288 }
4289 retry_count++;
4290 goto wait_reset_done;
4291 }
4292 arcmsr_iop_init(acb);
4293 atomic_set(&acb->rq_map_token, 16);
4294 atomic_set(&acb->ante_token_value, 16);
4295 acb->fw_flag = FW_NORMAL;
4296 mod_timer(&acb->eternal_timer, jiffies +
4297 msecs_to_jiffies(6 * HZ));
4298 acb->acb_flags &= ~ACB_F_BUS_RESET;
4299 rtn = SUCCESS;
4300 pr_notice("arcmsr: scsi bus reset eh returns with success\n");
4301 } else {
4302 acb->acb_flags &= ~ACB_F_BUS_RESET;
4303 atomic_set(&acb->rq_map_token, 16);
4304 atomic_set(&acb->ante_token_value, 16);
4305 acb->fw_flag = FW_NORMAL;
4306 mod_timer(&acb->eternal_timer, jiffies +
4307 msecs_to_jiffies(6 * HZ));
4308 rtn = SUCCESS;
4309 }
4310 return rtn;
4311}
4312
4313static int arcmsr_abort_one_cmd(struct AdapterControlBlock *acb,
4314 struct CommandControlBlock *ccb)
4315{
4316 int rtn;
4317 rtn = arcmsr_polling_ccbdone(acb, ccb);
4318 return rtn;
4319}
4320
4321static int arcmsr_abort(struct scsi_cmnd *cmd)
4322{
4323 struct AdapterControlBlock *acb =
4324 (struct AdapterControlBlock *)cmd->device->host->hostdata;
4325 int i = 0;
4326 int rtn = FAILED;
4327 uint32_t intmask_org;
4328
4329 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED)
4330 return SUCCESS;
4331 printk(KERN_NOTICE
4332 "arcmsr%d: abort device command of scsi id = %d lun = %d\n",
4333 acb->host->host_no, cmd->device->id, (u32)cmd->device->lun);
4334 acb->acb_flags |= ACB_F_ABORT;
4335 acb->num_aborts++;
4336
4337
4338
4339
4340
4341
4342 if (!atomic_read(&acb->ccboutstandingcount)) {
4343 acb->acb_flags &= ~ACB_F_ABORT;
4344 return rtn;
4345 }
4346
4347 intmask_org = arcmsr_disable_outbound_ints(acb);
4348 for (i = 0; i < acb->maxFreeCCB; i++) {
4349 struct CommandControlBlock *ccb = acb->pccb_pool[i];
4350 if (ccb->startdone == ARCMSR_CCB_START && ccb->pcmd == cmd) {
4351 ccb->startdone = ARCMSR_CCB_ABORTED;
4352 rtn = arcmsr_abort_one_cmd(acb, ccb);
4353 break;
4354 }
4355 }
4356 acb->acb_flags &= ~ACB_F_ABORT;
4357 arcmsr_enable_outbound_ints(acb, intmask_org);
4358 return rtn;
4359}
4360
4361static const char *arcmsr_info(struct Scsi_Host *host)
4362{
4363 struct AdapterControlBlock *acb =
4364 (struct AdapterControlBlock *) host->hostdata;
4365 static char buf[256];
4366 char *type;
4367 int raid6 = 1;
4368 switch (acb->pdev->device) {
4369 case PCI_DEVICE_ID_ARECA_1110:
4370 case PCI_DEVICE_ID_ARECA_1200:
4371 case PCI_DEVICE_ID_ARECA_1202:
4372 case PCI_DEVICE_ID_ARECA_1210:
4373 raid6 = 0;
4374
4375 case PCI_DEVICE_ID_ARECA_1120:
4376 case PCI_DEVICE_ID_ARECA_1130:
4377 case PCI_DEVICE_ID_ARECA_1160:
4378 case PCI_DEVICE_ID_ARECA_1170:
4379 case PCI_DEVICE_ID_ARECA_1201:
4380 case PCI_DEVICE_ID_ARECA_1203:
4381 case PCI_DEVICE_ID_ARECA_1220:
4382 case PCI_DEVICE_ID_ARECA_1230:
4383 case PCI_DEVICE_ID_ARECA_1260:
4384 case PCI_DEVICE_ID_ARECA_1270:
4385 case PCI_DEVICE_ID_ARECA_1280:
4386 type = "SATA";
4387 break;
4388 case PCI_DEVICE_ID_ARECA_1214:
4389 case PCI_DEVICE_ID_ARECA_1380:
4390 case PCI_DEVICE_ID_ARECA_1381:
4391 case PCI_DEVICE_ID_ARECA_1680:
4392 case PCI_DEVICE_ID_ARECA_1681:
4393 case PCI_DEVICE_ID_ARECA_1880:
4394 case PCI_DEVICE_ID_ARECA_1884:
4395 type = "SAS/SATA";
4396 break;
4397 default:
4398 type = "unknown";
4399 raid6 = 0;
4400 break;
4401 }
4402 sprintf(buf, "Areca %s RAID Controller %s\narcmsr version %s\n",
4403 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION);
4404 return buf;
4405}
4406
