LXR linux/drivers/spi/spi-sprd-adi.c

   1/*
   2 * Copyright (C) 2017 Spreadtrum Communications Inc.
   3 *
   4 * SPDX-License-Identifier: GPL-2.0
   5 */
   6
   7#include <linux/delay.h>
   8#include <linux/hwspinlock.h>
   9#include <linux/init.h>
  10#include <linux/io.h>
  11#include <linux/kernel.h>
  12#include <linux/module.h>
  13#include <linux/of.h>
  14#include <linux/of_device.h>
  15#include <linux/platform_device.h>
  16#include <linux/reboot.h>
  17#include <linux/spi/spi.h>
  18#include <linux/sizes.h>
  19
  20/* Registers definitions for ADI controller */
  21#define REG_ADI_CTRL0                   0x4
  22#define REG_ADI_CHN_PRIL                0x8
  23#define REG_ADI_CHN_PRIH                0xc
  24#define REG_ADI_INT_EN                  0x10
  25#define REG_ADI_INT_RAW                 0x14
  26#define REG_ADI_INT_MASK                0x18
  27#define REG_ADI_INT_CLR                 0x1c
  28#define REG_ADI_GSSI_CFG0               0x20
  29#define REG_ADI_GSSI_CFG1               0x24
  30#define REG_ADI_RD_CMD                  0x28
  31#define REG_ADI_RD_DATA                 0x2c
  32#define REG_ADI_ARM_FIFO_STS            0x30
  33#define REG_ADI_STS                     0x34
  34#define REG_ADI_EVT_FIFO_STS            0x38
  35#define REG_ADI_ARM_CMD_STS             0x3c
  36#define REG_ADI_CHN_EN                  0x40
  37#define REG_ADI_CHN_ADDR(id)            (0x44 + (id - 2) * 4)
  38#define REG_ADI_CHN_EN1                 0x20c
  39
  40/* Bits definitions for register REG_ADI_GSSI_CFG0 */
  41#define BIT_CLK_ALL_ON                  BIT(30)
  42
  43/* Bits definitions for register REG_ADI_RD_DATA */
  44#define BIT_RD_CMD_BUSY                 BIT(31)
  45#define RD_ADDR_SHIFT                   16
  46#define RD_VALUE_MASK                   GENMASK(15, 0)
  47#define RD_ADDR_MASK                    GENMASK(30, 16)
  48
  49/* Bits definitions for register REG_ADI_ARM_FIFO_STS */
  50#define BIT_FIFO_FULL                   BIT(11)
  51#define BIT_FIFO_EMPTY                  BIT(10)
  52
  53/*
  54 * ADI slave devices include RTC, ADC, regulator, charger, thermal and so on.
  55 * The slave devices address offset is always 0x8000 and size is 4K.
  56 */
  57#define ADI_SLAVE_ADDR_SIZE             SZ_4K
  58#define ADI_SLAVE_OFFSET                0x8000
  59
  60/* Timeout (ms) for the trylock of hardware spinlocks */
  61#define ADI_HWSPINLOCK_TIMEOUT          5000
  62/*
  63 * ADI controller has 50 channels including 2 software channels
  64 * and 48 hardware channels.
  65 */
  66#define ADI_HW_CHNS                     50
  67
  68#define ADI_FIFO_DRAIN_TIMEOUT          1000
  69#define ADI_READ_TIMEOUT                2000
  70#define REG_ADDR_LOW_MASK               GENMASK(11, 0)
  71
  72/* Registers definitions for PMIC watchdog controller */
  73#define REG_WDG_LOAD_LOW                0x80
  74#define REG_WDG_LOAD_HIGH               0x84
  75#define REG_WDG_CTRL                    0x88
  76#define REG_WDG_LOCK                    0xa0
  77
  78/* Bits definitions for register REG_WDG_CTRL */
  79#define BIT_WDG_RUN                     BIT(1)
  80#define BIT_WDG_RST                     BIT(3)
  81
  82/* Registers definitions for PMIC */
  83#define PMIC_RST_STATUS                 0xee8
  84#define PMIC_MODULE_EN                  0xc08
  85#define PMIC_CLK_EN                     0xc18
  86#define BIT_WDG_EN                      BIT(2)
  87
  88/* Definition of PMIC reset status register */
  89#define HWRST_STATUS_RECOVERY           0x20
  90#define HWRST_STATUS_NORMAL             0x40
  91#define HWRST_STATUS_ALARM              0x50
  92#define HWRST_STATUS_SLEEP              0x60
  93#define HWRST_STATUS_FASTBOOT           0x30
  94#define HWRST_STATUS_SPECIAL            0x70
  95#define HWRST_STATUS_PANIC              0x80
  96#define HWRST_STATUS_CFTREBOOT          0x90
  97#define HWRST_STATUS_AUTODLOADER        0xa0
  98#define HWRST_STATUS_IQMODE             0xb0
  99#define HWRST_STATUS_SPRDISK            0xc0
 100
 101/* Use default timeout 50 ms that converts to watchdog values */
 102#define WDG_LOAD_VAL                    ((50 * 1000) / 32768)
 103#define WDG_LOAD_MASK                   GENMASK(15, 0)
 104#define WDG_UNLOCK_KEY                  0xe551
 105
 106struct sprd_adi {
 107        struct spi_controller   *ctlr;
 108        struct device           *dev;
 109        void __iomem            *base;
 110        struct hwspinlock       *hwlock;
 111        unsigned long           slave_vbase;
 112        unsigned long           slave_pbase;
 113        struct notifier_block   restart_handler;
 114};
 115
 116static int sprd_adi_check_paddr(struct sprd_adi *sadi, u32 paddr)
 117{
 118        if (paddr < sadi->slave_pbase || paddr >
 119            (sadi->slave_pbase + ADI_SLAVE_ADDR_SIZE)) {
 120                dev_err(sadi->dev,
 121                        "slave physical address is incorrect, addr = 0x%x\n",
 122                        paddr);
 123                return -EINVAL;
 124        }
 125
 126        return 0;
 127}
 128
 129static unsigned long sprd_adi_to_vaddr(struct sprd_adi *sadi, u32 paddr)
 130{
 131        return (paddr - sadi->slave_pbase + sadi->slave_vbase);
 132}
 133
 134static int sprd_adi_drain_fifo(struct sprd_adi *sadi)
 135{
 136        u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
 137        u32 sts;
 138
 139        do {
 140                sts = readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS);
 141                if (sts & BIT_FIFO_EMPTY)
 142                        break;
 143
 144                cpu_relax();
 145        } while (--timeout);
 146
 147        if (timeout == 0) {
 148                dev_err(sadi->dev, "drain write fifo timeout\n");
 149                return -EBUSY;
 150        }
 151
 152        return 0;
 153}
 154
 155static int sprd_adi_fifo_is_full(struct sprd_adi *sadi)
 156{
 157        return readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS) & BIT_FIFO_FULL;
 158}
 159
 160static int sprd_adi_read(struct sprd_adi *sadi, u32 reg_paddr, u32 *read_val)
 161{
 162        int read_timeout = ADI_READ_TIMEOUT;
 163        unsigned long flags;
 164        u32 val, rd_addr;
 165        int ret;
 166
 167        ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
 168                                          ADI_HWSPINLOCK_TIMEOUT,
 169                                          &flags);
 170        if (ret) {
 171                dev_err(sadi->dev, "get the hw lock failed\n");
 172                return ret;
 173        }
 174
 175        /*
 176         * Set the physical register address need to read into RD_CMD register,
 177         * then ADI controller will start to transfer automatically.
 178         */
 179        writel_relaxed(reg_paddr, sadi->base + REG_ADI_RD_CMD);
 180
 181        /*
 182         * Wait read operation complete, the BIT_RD_CMD_BUSY will be set
 183         * simultaneously when writing read command to register, and the
 184         * BIT_RD_CMD_BUSY will be cleared after the read operation is
 185         * completed.
 186         */
 187        do {
 188                val = readl_relaxed(sadi->base + REG_ADI_RD_DATA);
 189                if (!(val & BIT_RD_CMD_BUSY))
 190                        break;
 191
 192                cpu_relax();
 193        } while (--read_timeout);
 194
 195        if (read_timeout == 0) {
 196                dev_err(sadi->dev, "ADI read timeout\n");
 197                ret = -EBUSY;
 198                goto out;
 199        }
 200
 201        /*
 202         * The return value includes data and read register address, from bit 0
 203         * to bit 15 are data, and from bit 16 to bit 30 are read register
 204         * address. Then we can check the returned register address to validate
 205         * data.
 206         */
 207        rd_addr = (val & RD_ADDR_MASK ) >> RD_ADDR_SHIFT;
 208
 209        if (rd_addr != (reg_paddr & REG_ADDR_LOW_MASK)) {
 210                dev_err(sadi->dev, "read error, reg addr = 0x%x, val = 0x%x\n",
 211                        reg_paddr, val);
 212                ret = -EIO;
 213                goto out;
 214        }
 215
 216        *read_val = val & RD_VALUE_MASK;
 217
 218out:
 219        hwspin_unlock_irqrestore(sadi->hwlock, &flags);
 220        return ret;
 221}
 222
 223static int sprd_adi_write(struct sprd_adi *sadi, u32 reg_paddr, u32 val)
 224{
 225        unsigned long reg = sprd_adi_to_vaddr(sadi, reg_paddr);
 226        u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
 227        unsigned long flags;
 228        int ret;
 229
 230        ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
 231                                          ADI_HWSPINLOCK_TIMEOUT,
 232                                          &flags);
 233        if (ret) {
 234                dev_err(sadi->dev, "get the hw lock failed\n");
 235                return ret;
 236        }
 237
 238        ret = sprd_adi_drain_fifo(sadi);
 239        if (ret < 0)
 240                goto out;
 241
 242        /*
 243         * we should wait for write fifo is empty before writing data to PMIC
 244         * registers.
 245         */
 246        do {
 247                if (!sprd_adi_fifo_is_full(sadi)) {
 248                        writel_relaxed(val, (void __iomem *)reg);
 249                        break;
 250                }
 251
 252                cpu_relax();
 253        } while (--timeout);
 254
 255        if (timeout == 0) {
 256                dev_err(sadi->dev, "write fifo is full\n");
 257                ret = -EBUSY;
 258        }
 259
 260out:
 261        hwspin_unlock_irqrestore(sadi->hwlock, &flags);
 262        return ret;
 263}
 264
 265static int sprd_adi_transfer_one(struct spi_controller *ctlr,
 266                                 struct spi_device *spi_dev,
 267                                 struct spi_transfer *t)
 268{
 269        struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
 270        u32 phy_reg, val;
 271        int ret;
 272
 273        if (t->rx_buf) {
 274                phy_reg = *(u32 *)t->rx_buf + sadi->slave_pbase;
 275
 276                ret = sprd_adi_check_paddr(sadi, phy_reg);
 277                if (ret)
 278                        return ret;
 279
 280                ret = sprd_adi_read(sadi, phy_reg, &val);
 281                if (ret)
 282                        return ret;
 283
 284                *(u32 *)t->rx_buf = val;
 285        } else if (t->tx_buf) {
 286                u32 *p = (u32 *)t->tx_buf;
 287
 288                /*
 289                 * Get the physical register address need to write and convert
 290                 * the physical address to virtual address. Since we need
 291                 * virtual register address to write.
 292                 */
 293                phy_reg = *p++ + sadi->slave_pbase;
 294                ret = sprd_adi_check_paddr(sadi, phy_reg);
 295                if (ret)
 296                        return ret;
 297
 298                val = *p;
 299                ret = sprd_adi_write(sadi, phy_reg, val);
 300                if (ret)
 301                        return ret;
 302        } else {
 303                dev_err(sadi->dev, "no buffer for transfer\n");
 304                return -EINVAL;
 305        }
 306
 307        return 0;
 308}
 309
 310static int sprd_adi_restart_handler(struct notifier_block *this,
 311                                    unsigned long mode, void *cmd)
 312{
 313        struct sprd_adi *sadi = container_of(this, struct sprd_adi,
 314                                             restart_handler);
 315        u32 val, reboot_mode = 0;
 316
 317        if (!cmd)
 318                reboot_mode = HWRST_STATUS_NORMAL;
 319        else if (!strncmp(cmd, "recovery", 8))
 320                reboot_mode = HWRST_STATUS_RECOVERY;
 321        else if (!strncmp(cmd, "alarm", 5))
 322                reboot_mode = HWRST_STATUS_ALARM;
 323        else if (!strncmp(cmd, "fastsleep", 9))
 324                reboot_mode = HWRST_STATUS_SLEEP;
 325        else if (!strncmp(cmd, "bootloader", 10))
 326                reboot_mode = HWRST_STATUS_FASTBOOT;
 327        else if (!strncmp(cmd, "panic", 5))
 328                reboot_mode = HWRST_STATUS_PANIC;
 329        else if (!strncmp(cmd, "special", 7))
 330                reboot_mode = HWRST_STATUS_SPECIAL;
 331        else if (!strncmp(cmd, "cftreboot", 9))
 332                reboot_mode = HWRST_STATUS_CFTREBOOT;
 333        else if (!strncmp(cmd, "autodloader", 11))
 334                reboot_mode = HWRST_STATUS_AUTODLOADER;
 335        else if (!strncmp(cmd, "iqmode", 6))
 336                reboot_mode = HWRST_STATUS_IQMODE;
 337        else if (!strncmp(cmd, "sprdisk", 7))
 338                reboot_mode = HWRST_STATUS_SPRDISK;
 339        else
 340                reboot_mode = HWRST_STATUS_NORMAL;
 341
 342        /* Record the reboot mode */
 343        sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val);
 344        val |= reboot_mode;
 345        sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val);
 346
 347        /* Enable the interface clock of the watchdog */
 348        sprd_adi_read(sadi, sadi->slave_pbase + PMIC_MODULE_EN, &val);
 349        val |= BIT_WDG_EN;
 350        sprd_adi_write(sadi, sadi->slave_pbase + PMIC_MODULE_EN, val);
 351
 352        /* Enable the work clock of the watchdog */
 353        sprd_adi_read(sadi, sadi->slave_pbase + PMIC_CLK_EN, &val);
 354        val |= BIT_WDG_EN;
 355        sprd_adi_write(sadi, sadi->slave_pbase + PMIC_CLK_EN, val);
 356
 357        /* Unlock the watchdog */
 358        sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOCK, WDG_UNLOCK_KEY);
 359
 360        /* Load the watchdog timeout value, 50ms is always enough. */
 361        sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_LOW,
 362                       WDG_LOAD_VAL & WDG_LOAD_MASK);
 363        sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_HIGH, 0);
 364
 365        /* Start the watchdog to reset system */
 366        sprd_adi_read(sadi, sadi->slave_pbase + REG_WDG_CTRL, &val);
 367        val |= BIT_WDG_RUN | BIT_WDG_RST;
 368        sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_CTRL, val);
 369
 370        mdelay(1000);
 371
 372        dev_emerg(sadi->dev, "Unable to restart system\n");
 373        return NOTIFY_DONE;
 374}
 375
 376static void sprd_adi_hw_init(struct sprd_adi *sadi)
 377{
 378        struct device_node *np = sadi->dev->of_node;
 379        int i, size, chn_cnt;
 380        const __be32 *list;
 381        u32 tmp;
 382
 383        /* Address bits select default 12 bits */
 384        writel_relaxed(0, sadi->base + REG_ADI_CTRL0);
 385
 386        /* Set all channels as default priority */
 387        writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIL);
 388        writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIH);
 389
 390        /* Set clock auto gate mode */
 391        tmp = readl_relaxed(sadi->base + REG_ADI_GSSI_CFG0);
 392        tmp &= ~BIT_CLK_ALL_ON;
 393        writel_relaxed(tmp, sadi->base + REG_ADI_GSSI_CFG0);
 394
 395        /* Set hardware channels setting */
 396        list = of_get_property(np, "sprd,hw-channels", &size);
 397        if (!list || !size) {
 398                dev_info(sadi->dev, "no hw channels setting in node\n");
 399                return;
 400        }
 401
 402        chn_cnt = size / 8;
 403        for (i = 0; i < chn_cnt; i++) {
 404                u32 value;
 405                u32 chn_id = be32_to_cpu(*list++);
 406                u32 chn_config = be32_to_cpu(*list++);
 407
 408                /* Channel 0 and 1 are software channels */
 409                if (chn_id < 2)
 410                        continue;
 411
 412                writel_relaxed(chn_config, sadi->base +
 413                               REG_ADI_CHN_ADDR(chn_id));
 414
 415                if (chn_id < 32) {
 416                        value = readl_relaxed(sadi->base + REG_ADI_CHN_EN);
 417                        value |= BIT(chn_id);
 418                        writel_relaxed(value, sadi->base + REG_ADI_CHN_EN);
 419                } else if (chn_id < ADI_HW_CHNS) {
 420                        value = readl_relaxed(sadi->base + REG_ADI_CHN_EN1);
 421                        value |= BIT(chn_id - 32);
 422                        writel_relaxed(value, sadi->base + REG_ADI_CHN_EN1);
 423                }
 424        }
 425}
 426
 427static int sprd_adi_probe(struct platform_device *pdev)
 428{
 429        struct device_node *np = pdev->dev.of_node;
 430        struct spi_controller *ctlr;
 431        struct sprd_adi *sadi;
 432        struct resource *res;
 433        u32 num_chipselect;
 434        int ret;
 435
 436        if (!np) {
 437                dev_err(&pdev->dev, "can not find the adi bus node\n");
 438                return -ENODEV;
 439        }
 440
 441        pdev->id = of_alias_get_id(np, "spi");
 442        num_chipselect = of_get_child_count(np);
 443
 444        ctlr = spi_alloc_master(&pdev->dev, sizeof(struct sprd_adi));
 445        if (!ctlr)
 446                return -ENOMEM;
 447
 448        dev_set_drvdata(&pdev->dev, ctlr);
 449        sadi = spi_controller_get_devdata(ctlr);
 450
 451        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 452        sadi->base = devm_ioremap_resource(&pdev->dev, res);
 453        if (IS_ERR(sadi->base)) {
 454                ret = PTR_ERR(sadi->base);
 455                goto put_ctlr;
 456        }
 457
 458        sadi->slave_vbase = (unsigned long)sadi->base + ADI_SLAVE_OFFSET;
 459        sadi->slave_pbase = res->start + ADI_SLAVE_OFFSET;
 460        sadi->ctlr = ctlr;
 461        sadi->dev = &pdev->dev;
 462        ret = of_hwspin_lock_get_id(np, 0);
 463        if (ret < 0) {
 464                dev_err(&pdev->dev, "can not get the hardware spinlock\n");
 465                goto put_ctlr;
 466        }
 467
 468        sadi->hwlock = hwspin_lock_request_specific(ret);
 469        if (!sadi->hwlock) {
 470                ret = -ENXIO;
 471                goto put_ctlr;
 472        }
 473
 474        sprd_adi_hw_init(sadi);
 475
 476        ctlr->dev.of_node = pdev->dev.of_node;
 477        ctlr->bus_num = pdev->id;
 478        ctlr->num_chipselect = num_chipselect;
 479        ctlr->flags = SPI_MASTER_HALF_DUPLEX;
 480        ctlr->bits_per_word_mask = 0;
 481        ctlr->transfer_one = sprd_adi_transfer_one;
 482
 483        ret = devm_spi_register_controller(&pdev->dev, ctlr);
 484        if (ret) {
 485                dev_err(&pdev->dev, "failed to register SPI controller\n");
 486                goto free_hwlock;
 487        }
 488
 489        sadi->restart_handler.notifier_call = sprd_adi_restart_handler;
 490        sadi->restart_handler.priority = 128;
 491        ret = register_restart_handler(&sadi->restart_handler);
 492        if (ret) {
 493                dev_err(&pdev->dev, "can not register restart handler\n");
 494                goto free_hwlock;
 495        }
 496
 497        return 0;
 498
 499free_hwlock:
 500        hwspin_lock_free(sadi->hwlock);
 501put_ctlr:
 502        spi_controller_put(ctlr);
 503        return ret;
 504}
 505
 506static int sprd_adi_remove(struct platform_device *pdev)
 507{
 508        struct spi_controller *ctlr = dev_get_drvdata(&pdev->dev);
 509        struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
 510
 511        unregister_restart_handler(&sadi->restart_handler);
 512        hwspin_lock_free(sadi->hwlock);
 513        return 0;
 514}
 515
 516static const struct of_device_id sprd_adi_of_match[] = {
 517        {
 518                .compatible = "sprd,sc9860-adi",
 519        },
 520        { },
 521};
 522MODULE_DEVICE_TABLE(of, sprd_adi_of_match);
 523
 524static struct platform_driver sprd_adi_driver = {
 525        .driver = {
 526                .name = "sprd-adi",
 527                .of_match_table = sprd_adi_of_match,
 528        },
 529        .probe = sprd_adi_probe,
 530        .remove = sprd_adi_remove,
 531};
 532module_platform_driver(sprd_adi_driver);
 533
 534MODULE_DESCRIPTION("Spreadtrum ADI Controller Driver");
 535MODULE_AUTHOR("Baolin Wang <Baolin.Wang@spreadtrum.com>");
 536MODULE_LICENSE("GPL v2");
 537