1
2#ifndef _RTL819XU_HTTYPE_H_
3#define _RTL819XU_HTTYPE_H_
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13#define HT_OPMODE_NO_PROTECT 0
14#define HT_OPMODE_OPTIONAL 1
15#define HT_OPMODE_40MHZ_PROTECT 2
16#define HT_OPMODE_MIXED 3
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20
21#define MIMO_PS_STATIC 0
22#define MIMO_PS_DYNAMIC 1
23#define MIMO_PS_NOLIMIT 3
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30
31#define sHTCLng 4
32
33
34#define HT_SUPPORTED_MCS_1SS_BITMAP 0x000000ff
35#define HT_SUPPORTED_MCS_2SS_BITMAP 0x0000ff00
36#define HT_SUPPORTED_MCS_1SS_2SS_BITMAP HT_MCS_1SS_BITMAP|HT_MCS_1SS_2SS_BITMAP
37
38
39typedef enum _HT_MCS_RATE {
40 HT_MCS0 = 0x00000001,
41 HT_MCS1 = 0x00000002,
42 HT_MCS2 = 0x00000004,
43 HT_MCS3 = 0x00000008,
44 HT_MCS4 = 0x00000010,
45 HT_MCS5 = 0x00000020,
46 HT_MCS6 = 0x00000040,
47 HT_MCS7 = 0x00000080,
48 HT_MCS8 = 0x00000100,
49 HT_MCS9 = 0x00000200,
50 HT_MCS10 = 0x00000400,
51 HT_MCS11 = 0x00000800,
52 HT_MCS12 = 0x00001000,
53 HT_MCS13 = 0x00002000,
54 HT_MCS14 = 0x00004000,
55 HT_MCS15 = 0x00008000,
56
57} HT_MCS_RATE, *PHT_MCS_RATE;
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61
62typedef enum _HT_CHANNEL_WIDTH {
63 HT_CHANNEL_WIDTH_20 = 0,
64 HT_CHANNEL_WIDTH_20_40 = 1,
65}HT_CHANNEL_WIDTH, *PHT_CHANNEL_WIDTH;
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70
71typedef enum _HT_EXTCHNL_OFFSET {
72 HT_EXTCHNL_OFFSET_NO_EXT = 0,
73 HT_EXTCHNL_OFFSET_UPPER = 1,
74 HT_EXTCHNL_OFFSET_NO_DEF = 2,
75 HT_EXTCHNL_OFFSET_LOWER = 3,
76}HT_EXTCHNL_OFFSET, *PHT_EXTCHNL_OFFSET;
77
78typedef enum _CHNLOP {
79 CHNLOP_NONE = 0,
80 CHNLOP_SCAN = 1,
81 CHNLOP_SWBW = 2,
82 CHNLOP_SWCHNL = 3,
83} CHNLOP, *PCHNLOP;
84
85
86#define CHHLOP_IN_PROGRESS(_pHTInfo) \
87 ((_pHTInfo)->ChnlOp > CHNLOP_NONE) ? TRUE : FALSE
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123typedef enum _HT_ACTION {
124 ACT_RECOMMAND_WIDTH = 0,
125 ACT_MIMO_PWR_SAVE = 1,
126 ACT_PSMP = 2,
127 ACT_SET_PCO_PHASE = 3,
128 ACT_MIMO_CHL_MEASURE = 4,
129 ACT_RECIPROCITY_CORRECT = 5,
130 ACT_MIMO_CSI_MATRICS = 6,
131 ACT_MIMO_NOCOMPR_STEER = 7,
132 ACT_MIMO_COMPR_STEER = 8,
133 ACT_ANTENNA_SELECT = 9,
134} HT_ACTION, *PHT_ACTION;
135
136
137
138typedef enum _HT_Bandwidth_40MHZ_Sub_Carrier {
139 SC_MODE_DUPLICATE = 0,
140 SC_MODE_LOWER = 1,
141 SC_MODE_UPPER = 2,
142 SC_MODE_FULL40MHZ = 3,
143}HT_BW40_SC_E;
144
145typedef struct _HT_CAPABILITY_ELE {
146
147
148 u8 AdvCoding:1;
149 u8 ChlWidth:1;
150 u8 MimoPwrSave:2;
151 u8 GreenField:1;
152 u8 ShortGI20Mhz:1;
153 u8 ShortGI40Mhz:1;
154 u8 TxSTBC:1;
155 u8 RxSTBC:2;
156 u8 DelayBA:1;
157 u8 MaxAMSDUSize:1;
158 u8 DssCCk:1;
159 u8 PSMP:1;
160 u8 Rsvd1:1;
161 u8 LSigTxopProtect:1;
162
163
164 u8 MaxRxAMPDUFactor:2;
165 u8 MPDUDensity:3;
166 u8 Rsvd2:3;
167
168
169 u8 MCS[16];
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172
173 u16 ExtHTCapInfo;
174
175
176 u8 TxBFCap[4];
177
178
179 u8 ASCap;
180
181} __attribute__ ((packed)) HT_CAPABILITY_ELE, *PHT_CAPABILITY_ELE;
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187
188typedef struct _HT_INFORMATION_ELE {
189 u8 ControlChl;
190
191 u8 ExtChlOffset:2;
192 u8 RecommemdedTxWidth:1;
193 u8 RIFS:1;
194 u8 PSMPAccessOnly:1;
195 u8 SrvIntGranularity:3;
196
197 u8 OptMode:2;
198 u8 NonGFDevPresent:1;
199 u8 Revd1:5;
200 u8 Revd2:8;
201
202 u8 Rsvd3:6;
203 u8 DualBeacon:1;
204 u8 DualCTSProtect:1;
205
206 u8 SecondaryBeacon:1;
207 u8 LSigTxopProtectFull:1;
208 u8 PcoActive:1;
209 u8 PcoPhase:1;
210 u8 Rsvd4:4;
211
212 u8 BasicMSC[16];
213} __attribute__ ((packed)) HT_INFORMATION_ELE, *PHT_INFORMATION_ELE;
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218
219typedef struct _MIMOPS_CTRL {
220 u8 MimoPsEnable:1;
221 u8 MimoPsMode:1;
222 u8 Reserved:6;
223} MIMOPS_CTRL, *PMIMOPS_CTRL;
224
225typedef enum _HT_SPEC_VER {
226 HT_SPEC_VER_IEEE = 0,
227 HT_SPEC_VER_EWC = 1,
228}HT_SPEC_VER, *PHT_SPEC_VER;
229
230typedef enum _HT_AGGRE_MODE_E {
231 HT_AGG_AUTO = 0,
232 HT_AGG_FORCE_ENABLE = 1,
233 HT_AGG_FORCE_DISABLE = 2,
234}HT_AGGRE_MODE_E, *PHT_AGGRE_MODE_E;
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241
242typedef struct _RT_HIGH_THROUGHPUT {
243 u8 bEnableHT;
244 u8 bCurrentHTSupport;
245
246 u8 bRegBW40MHz;
247 u8 bCurBW40MHz;
248
249 u8 bRegShortGI40MHz;
250 u8 bCurShortGI40MHz;
251
252 u8 bRegShortGI20MHz;
253 u8 bCurShortGI20MHz;
254
255 u8 bRegSuppCCK;
256 u8 bCurSuppCCK;
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259 HT_SPEC_VER ePeerHTSpecVer;
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263 HT_CAPABILITY_ELE SelfHTCap;
264 HT_INFORMATION_ELE SelfHTInfo;
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267 u8 PeerHTCapBuf[32];
268 u8 PeerHTInfoBuf[32];
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272 u8 bAMSDU_Support;
273 u16 nAMSDU_MaxSize;
274 u8 bCurrent_AMSDU_Support;
275 u16 nCurrent_AMSDU_MaxSize;
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279 u8 bAMPDUEnable;
280 u8 bCurrentAMPDUEnable;
281 u8 AMPDU_Factor;
282 u8 CurrentAMPDUFactor;
283 u8 MPDU_Density;
284 u8 CurrentMPDUDensity;
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287 HT_AGGRE_MODE_E ForcedAMPDUMode;
288 u8 ForcedAMPDUFactor;
289 u8 ForcedMPDUDensity;
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292 HT_AGGRE_MODE_E ForcedAMSDUMode;
293 u16 ForcedAMSDUMaxSize;
294
295 u8 bForcedShortGI;
296
297 u8 CurrentOpMode;
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300 u8 SelfMimoPs;
301 u8 PeerMimoPs;
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304 HT_EXTCHNL_OFFSET CurSTAExtChnlOffset;
305 u8 bCurTxBW40MHz;
306 u8 PeerBandwidth;
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309 u8 bSwBwInProgress;
310 CHNLOP ChnlOp;
311 u8 SwBwStep;
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315 u8 bRegRT2RTAggregation;
316 u8 bCurrentRT2RTAggregation;
317 u8 bCurrentRT2RTLongSlotTime;
318 u8 szRT2RTAggBuffer[10];
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321 u8 bRegRxReorderEnable;
322 u8 bCurRxReorderEnable;
323 u8 RxReorderWinSize;
324 u8 RxReorderPendingTime;
325 u16 RxReorderDropCounter;
326
327#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
328 u8 UsbTxAggrNum;
329#endif
330#ifdef USB_RX_AGGREGATION_SUPPORT
331 u8 UsbRxFwAggrEn;
332 u8 UsbRxFwAggrPageNum;
333 u8 UsbRxFwAggrPacketNum;
334 u8 UsbRxFwAggrTimeout;
335#endif
336
337
338 u8 bIsPeerBcm;
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341 u8 IOTPeer;
342 u32 IOTAction;
343} __attribute__ ((packed)) RT_HIGH_THROUGHPUT, *PRT_HIGH_THROUGHPUT;
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351typedef struct _RT_HTINFO_STA_ENTRY {
352 u8 bEnableHT;
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354 u8 bSupportCck;
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356 u16 AMSDU_MaxSize;
357
358 u8 AMPDU_Factor;
359 u8 MPDU_Density;
360
361 u8 HTHighestOperaRate;
362
363 u8 bBw40MHz;
364
365 u8 MimoPs;
366
367 u8 McsRateSet[16];
368
369
370}RT_HTINFO_STA_ENTRY, *PRT_HTINFO_STA_ENTRY;
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381typedef struct _BSS_HT {
382
383 u8 bdSupportHT;
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386 u8 bdHTCapBuf[32];
387 u16 bdHTCapLen;
388 u8 bdHTInfoBuf[32];
389 u16 bdHTInfoLen;
390
391 HT_SPEC_VER bdHTSpecVer;
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395 u8 bdRT2RTAggregation;
396 u8 bdRT2RTLongSlotTime;
397} __attribute__ ((packed)) BSS_HT, *PBSS_HT;
398
399typedef struct _MIMO_RSSI {
400 u32 EnableAntenna;
401 u32 AntennaA;
402 u32 AntennaB;
403 u32 AntennaC;
404 u32 AntennaD;
405 u32 Average;
406}MIMO_RSSI, *PMIMO_RSSI;
407
408typedef struct _MIMO_EVM {
409 u32 EVM1;
410 u32 EVM2;
411}MIMO_EVM, *PMIMO_EVM;
412
413typedef struct _FALSE_ALARM_STATISTICS {
414 u32 Cnt_Parity_Fail;
415 u32 Cnt_Rate_Illegal;
416 u32 Cnt_Crc8_fail;
417 u32 Cnt_all;
418}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;
419
420
421extern u8 MCS_FILTER_ALL[16];
422extern u8 MCS_FILTER_1SS[16];
423
424
425
426
427#define PICK_RATE(_nLegacyRate, _nMcsRate) \
428 (_nMcsRate==0)?(_nLegacyRate&0x7f):(_nMcsRate)
429
430#define LEGACY_WIRELESS_MODE IEEE_MODE_MASK
431
432#define CURRENT_RATE(WirelessMode, LegacyRate, HTRate) \
433 ((WirelessMode & (LEGACY_WIRELESS_MODE))!=0)?\
434 (LegacyRate):\
435 (PICK_RATE(LegacyRate, HTRate))
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439
440#define RATE_ADPT_1SS_MASK 0xFF
441#define RATE_ADPT_2SS_MASK 0xF0
442#define RATE_ADPT_MCS32_MASK 0x01
443
444#define IS_11N_MCS_RATE(rate) (rate&0x80)
445
446typedef enum _HT_AGGRE_SIZE {
447 HT_AGG_SIZE_8K = 0,
448 HT_AGG_SIZE_16K = 1,
449 HT_AGG_SIZE_32K = 2,
450 HT_AGG_SIZE_64K = 3,
451}HT_AGGRE_SIZE_E, *PHT_AGGRE_SIZE_E;
452
453
454typedef enum _HT_IOT_PEER
455{
456 HT_IOT_PEER_UNKNOWN = 0,
457 HT_IOT_PEER_REALTEK = 1,
458 HT_IOT_PEER_BROADCOM = 2,
459 HT_IOT_PEER_RALINK = 3,
460 HT_IOT_PEER_ATHEROS = 4,
461 HT_IOT_PEER_CISCO= 5,
462 HT_IOT_PEER_MAX = 6
463}HT_IOT_PEER_E, *PHTIOT_PEER_E;
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467
468typedef enum _HT_IOT_ACTION {
469 HT_IOT_ACT_TX_USE_AMSDU_4K = 0x00000001,
470 HT_IOT_ACT_TX_USE_AMSDU_8K = 0x00000002,
471 HT_IOT_ACT_DISABLE_MCS14 = 0x00000004,
472 HT_IOT_ACT_DISABLE_MCS15 = 0x00000008,
473 HT_IOT_ACT_DISABLE_ALL_2SS = 0x00000010,
474 HT_IOT_ACT_DISABLE_EDCA_TURBO = 0x00000020,
475 HT_IOT_ACT_MGNT_USE_CCK_6M = 0x00000040,
476 HT_IOT_ACT_CDD_FSYNC = 0x00000080,
477 HT_IOT_ACT_PURE_N_MODE = 0x00000100,
478 HT_IOT_ACT_FORCED_CTS2SELF = 0x00000200,
479}HT_IOT_ACTION_E, *PHT_IOT_ACTION_E;
480
481#endif
482