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15#ifndef __PHYDMDIG_H__
16#define __PHYDMDIG_H__
17
18#define DIG_VERSION "1.32"
19
20
21#define DM_DIG_MAX_PAUSE_TYPE 0x7
22
23enum dig_goupcheck_level {
24 DIG_GOUPCHECK_LEVEL_0,
25 DIG_GOUPCHECK_LEVEL_1,
26 DIG_GOUPCHECK_LEVEL_2
27
28};
29
30struct dig_thres {
31 bool is_stop_dig;
32 bool is_ignore_dig;
33 bool is_psd_in_progress;
34
35 u8 dig_enable_flag;
36 u8 dig_ext_port_stage;
37
38 int rssi_low_thresh;
39 int rssi_high_thresh;
40
41 u32 fa_low_thresh;
42 u32 fa_high_thresh;
43
44 u8 cur_sta_connect_state;
45 u8 pre_sta_connect_state;
46 u8 cur_multi_sta_connect_state;
47
48 u8 pre_ig_value;
49 u8 cur_ig_value;
50 u8 backup_ig_value;
51 u8 bt30_cur_igi;
52 u8 igi_backup;
53
54 s8 backoff_val;
55 s8 backoff_val_range_max;
56 s8 backoff_val_range_min;
57 u8 rx_gain_range_max;
58 u8 rx_gain_range_min;
59 u8 rssi_val_min;
60
61 u8 pre_cck_cca_thres;
62 u8 cur_cck_cca_thres;
63 u8 pre_cck_pd_state;
64 u8 cur_cck_pd_state;
65 u8 cck_pd_backup;
66 u8 pause_cckpd_level;
67 u8 pause_cckpd_value[DM_DIG_MAX_PAUSE_TYPE + 1];
68
69 u8 large_fa_hit;
70 u8 large_fa_timeout;
71
72
73 u8 forbidden_igi;
74 u32 recover_cnt;
75
76 u8 dig_dynamic_min_0;
77 u8 dig_dynamic_min_1;
78 bool is_media_connect_0;
79 bool is_media_connect_1;
80
81 u32 ant_div_rssi_max;
82 u32 rssi_max;
83
84 u8 *is_p2p_in_process;
85
86 u8 pause_dig_level;
87 u8 pause_dig_value[DM_DIG_MAX_PAUSE_TYPE + 1];
88
89 u32 cck_fa_ma;
90 enum dig_goupcheck_level dig_go_up_check_level;
91 u8 aaa_default;
92
93 u8 rf_gain_idx;
94 u8 agc_table_idx;
95 u8 big_jump_lmt[16];
96 u8 enable_adjust_big_jump : 1;
97 u8 big_jump_step1 : 3;
98 u8 big_jump_step2 : 2;
99 u8 big_jump_step3 : 2;
100};
101
102struct false_alarm_stat {
103 u32 cnt_parity_fail;
104 u32 cnt_rate_illegal;
105 u32 cnt_crc8_fail;
106 u32 cnt_mcs_fail;
107 u32 cnt_ofdm_fail;
108 u32 cnt_ofdm_fail_pre;
109 u32 cnt_cck_fail;
110 u32 cnt_all;
111 u32 cnt_all_pre;
112 u32 cnt_fast_fsync;
113 u32 cnt_sb_search_fail;
114 u32 cnt_ofdm_cca;
115 u32 cnt_cck_cca;
116 u32 cnt_cca_all;
117 u32 cnt_bw_usc;
118 u32 cnt_bw_lsc;
119 u32 cnt_cck_crc32_error;
120 u32 cnt_cck_crc32_ok;
121 u32 cnt_ofdm_crc32_error;
122 u32 cnt_ofdm_crc32_ok;
123 u32 cnt_ht_crc32_error;
124 u32 cnt_ht_crc32_ok;
125 u32 cnt_vht_crc32_error;
126 u32 cnt_vht_crc32_ok;
127 u32 cnt_crc32_error_all;
128 u32 cnt_crc32_ok_all;
129 bool cck_block_enable;
130 bool ofdm_block_enable;
131 u32 dbg_port0;
132 bool edcca_flag;
133};
134
135enum dm_dig_op {
136 DIG_TYPE_THRESH_HIGH = 0,
137 DIG_TYPE_THRESH_LOW = 1,
138 DIG_TYPE_BACKOFF = 2,
139 DIG_TYPE_RX_GAIN_MIN = 3,
140 DIG_TYPE_RX_GAIN_MAX = 4,
141 DIG_TYPE_ENABLE = 5,
142 DIG_TYPE_DISABLE = 6,
143 DIG_OP_TYPE_MAX
144};
145
146enum phydm_pause_type { PHYDM_PAUSE = BIT(0), PHYDM_RESUME = BIT(1) };
147
148enum phydm_pause_level {
149
150 PHYDM_PAUSE_LEVEL_0 = 0,
151 PHYDM_PAUSE_LEVEL_1 = 1,
152 PHYDM_PAUSE_LEVEL_2 = 2,
153 PHYDM_PAUSE_LEVEL_3 = 3,
154 PHYDM_PAUSE_LEVEL_4 = 4,
155 PHYDM_PAUSE_LEVEL_5 = 5,
156 PHYDM_PAUSE_LEVEL_6 = 6,
157 PHYDM_PAUSE_LEVEL_7 = DM_DIG_MAX_PAUSE_TYPE
158};
159
160#define DM_DIG_THRESH_HIGH 40
161#define DM_DIG_THRESH_LOW 35
162
163#define DM_FALSEALARM_THRESH_LOW 400
164#define DM_FALSEALARM_THRESH_HIGH 1000
165
166#define DM_DIG_MAX_NIC 0x3e
167#define DM_DIG_MIN_NIC 0x20
168#define DM_DIG_MAX_OF_MIN_NIC 0x3e
169
170#define DM_DIG_MAX_AP 0x3e
171#define DM_DIG_MIN_AP 0x20
172#define DM_DIG_MAX_OF_MIN 0x2A
173#define DM_DIG_MIN_AP_DFS 0x20
174
175#define DM_DIG_MAX_NIC_HP 0x46
176#define DM_DIG_MIN_NIC_HP 0x2e
177
178#define DM_DIG_MAX_AP_HP 0x42
179#define DM_DIG_MIN_AP_HP 0x30
180
181
182
183
184#define DM_DIG_FA_TH0 0x200
185
186#define DM_DIG_FA_TH1 0x300
187#define DM_DIG_FA_TH2 0x400
188
189#define DM_DIG_FA_TH0_92D 0x100
190#define DM_DIG_FA_TH1_92D 0x400
191#define DM_DIG_FA_TH2_92D 0x600
192
193#define DM_DIG_BACKOFF_MAX 12
194#define DM_DIG_BACKOFF_MIN -4
195#define DM_DIG_BACKOFF_DEFAULT 10
196
197#define DM_DIG_FA_TH0_LPS 4
198#define DM_DIG_FA_TH1_LPS 15
199#define DM_DIG_FA_TH2_LPS 30
200#define RSSI_OFFSET_DIG 0x05
201#define LARGE_FA_TIMEOUT 60
202
203void odm_change_dynamic_init_gain_thresh(void *dm_void, u32 dm_type,
204 u32 dm_value);
205
206void odm_write_dig(void *dm_void, u8 current_igi);
207
208void odm_pause_dig(void *dm_void, enum phydm_pause_type pause_type,
209 enum phydm_pause_level pause_level, u8 igi_value);
210
211void odm_dig_init(void *dm_void);
212
213void odm_DIG(void *dm_void);
214
215void odm_dig_by_rssi_lps(void *dm_void);
216
217void odm_false_alarm_counter_statistics(void *dm_void);
218
219void odm_pause_cck_packet_detection(void *dm_void,
220 enum phydm_pause_type pause_type,
221 enum phydm_pause_level pause_level,
222 u8 cck_pd_threshold);
223
224void odm_cck_packet_detection_thresh(void *dm_void);
225
226void odm_write_cck_cca_thres(void *dm_void, u8 cur_cck_cca_thres);
227
228bool phydm_dig_go_up_check(void *dm_void);
229
230#endif
231
