LXR linux/include/linux/perf/arm

   1/*
   2 *  linux/arch/arm/include/asm/pmu.h
   3 *
   4 *  Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation.
   9 *
  10 */
  11
  12#ifndef __ARM_PMU_H__
  13#define __ARM_PMU_H__
  14
  15#include <linux/interrupt.h>
  16#include <linux/perf_event.h>
  17#include <linux/platform_device.h>
  18#include <linux/sysfs.h>
  19#include <asm/cputype.h>
  20
  21#ifdef CONFIG_ARM_PMU
  22
  23/*
  24 * The ARMv7 CPU PMU supports up to 32 event counters.
  25 */
  26#define ARMPMU_MAX_HWEVENTS             32
  27
  28/*
  29 * ARM PMU hw_event flags
  30 */
  31/* Event uses a 64bit counter */
  32#define ARMPMU_EVT_64BIT                1
  33
  34#define HW_OP_UNSUPPORTED               0xFFFF
  35#define C(_x)                           PERF_COUNT_HW_CACHE_##_x
  36#define CACHE_OP_UNSUPPORTED            0xFFFF
  37
  38#define PERF_MAP_ALL_UNSUPPORTED                                        \
  39        [0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED
  40
  41#define PERF_CACHE_MAP_ALL_UNSUPPORTED                                  \
  42[0 ... C(MAX) - 1] = {                                                  \
  43        [0 ... C(OP_MAX) - 1] = {                                       \
  44                [0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED,       \
  45        },                                                              \
  46}
  47
  48/* The events for a given PMU register set. */
  49struct pmu_hw_events {
  50        /*
  51         * The events that are active on the PMU for the given index.
  52         */
  53        struct perf_event       *events[ARMPMU_MAX_HWEVENTS];
  54
  55        /*
  56         * A 1 bit for an index indicates that the counter is being used for
  57         * an event. A 0 means that the counter can be used.
  58         */
  59        DECLARE_BITMAP(used_mask, ARMPMU_MAX_HWEVENTS);
  60
  61        /*
  62         * Hardware lock to serialize accesses to PMU registers. Needed for the
  63         * read/modify/write sequences.
  64         */
  65        raw_spinlock_t          pmu_lock;
  66
  67        /*
  68         * When using percpu IRQs, we need a percpu dev_id. Place it here as we
  69         * already have to allocate this struct per cpu.
  70         */
  71        struct arm_pmu          *percpu_pmu;
  72
  73        int irq;
  74};
  75
  76enum armpmu_attr_groups {
  77        ARMPMU_ATTR_GROUP_COMMON,
  78        ARMPMU_ATTR_GROUP_EVENTS,
  79        ARMPMU_ATTR_GROUP_FORMATS,
  80        ARMPMU_NR_ATTR_GROUPS
  81};
  82
  83struct arm_pmu {
  84        struct pmu      pmu;
  85        cpumask_t       supported_cpus;
  86        char            *name;
  87        irqreturn_t     (*handle_irq)(struct arm_pmu *pmu);
  88        void            (*enable)(struct perf_event *event);
  89        void            (*disable)(struct perf_event *event);
  90        int             (*get_event_idx)(struct pmu_hw_events *hw_events,
  91                                         struct perf_event *event);
  92        void            (*clear_event_idx)(struct pmu_hw_events *hw_events,
  93                                         struct perf_event *event);
  94        int             (*set_event_filter)(struct hw_perf_event *evt,
  95                                            struct perf_event_attr *attr);
  96        u64             (*read_counter)(struct perf_event *event);
  97        void            (*write_counter)(struct perf_event *event, u64 val);
  98        void            (*start)(struct arm_pmu *);
  99        void            (*stop)(struct arm_pmu *);
 100        void            (*reset)(void *);
 101        int             (*map_event)(struct perf_event *event);
 102        int             (*filter_match)(struct perf_event *event);
 103        int             num_events;
 104        bool            secure_access; /* 32-bit ARM only */
 105#define ARMV8_PMUV3_MAX_COMMON_EVENTS           0x40
 106        DECLARE_BITMAP(pmceid_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS);
 107#define ARMV8_PMUV3_EXT_COMMON_EVENT_BASE       0x4000
 108        DECLARE_BITMAP(pmceid_ext_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS);
 109        struct platform_device  *plat_device;
 110        struct pmu_hw_events    __percpu *hw_events;
 111        struct hlist_node       node;
 112        struct notifier_block   cpu_pm_nb;
 113        /* the attr_groups array must be NULL-terminated */
 114        const struct attribute_group *attr_groups[ARMPMU_NR_ATTR_GROUPS + 1];
 115
 116        /* Only to be used by ACPI probing code */
 117        unsigned long acpi_cpuid;
 118};
 119
 120#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
 121
 122u64 armpmu_event_update(struct perf_event *event);
 123
 124int armpmu_event_set_period(struct perf_event *event);
 125
 126int armpmu_map_event(struct perf_event *event,
 127                     const unsigned (*event_map)[PERF_COUNT_HW_MAX],
 128                     const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
 129                                                [PERF_COUNT_HW_CACHE_OP_MAX]
 130                                                [PERF_COUNT_HW_CACHE_RESULT_MAX],
 131                     u32 raw_event_mask);
 132
 133typedef int (*armpmu_init_fn)(struct arm_pmu *);
 134
 135struct pmu_probe_info {
 136        unsigned int cpuid;
 137        unsigned int mask;
 138        armpmu_init_fn init;
 139};
 140
 141#define PMU_PROBE(_cpuid, _mask, _fn)   \
 142{                                       \
 143        .cpuid = (_cpuid),              \
 144        .mask = (_mask),                \
 145        .init = (_fn),                  \
 146}
 147
 148#define ARM_PMU_PROBE(_cpuid, _fn) \
 149        PMU_PROBE(_cpuid, ARM_CPU_PART_MASK, _fn)
 150
 151#define ARM_PMU_XSCALE_MASK     ((0xff << 24) | ARM_CPU_XSCALE_ARCH_MASK)
 152
 153#define XSCALE_PMU_PROBE(_version, _fn) \
 154        PMU_PROBE(ARM_CPU_IMP_INTEL << 24 | _version, ARM_PMU_XSCALE_MASK, _fn)
 155
 156int arm_pmu_device_probe(struct platform_device *pdev,
 157                         const struct of_device_id *of_table,
 158                         const struct pmu_probe_info *probe_table);
 159
 160#ifdef CONFIG_ACPI
 161int arm_pmu_acpi_probe(armpmu_init_fn init_fn);
 162#else
 163static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; }
 164#endif
 165
 166/* Internal functions only for core arm_pmu code */
 167struct arm_pmu *armpmu_alloc(void);
 168struct arm_pmu *armpmu_alloc_atomic(void);
 169void armpmu_free(struct arm_pmu *pmu);
 170int armpmu_register(struct arm_pmu *pmu);
 171int armpmu_request_irq(int irq, int cpu);
 172void armpmu_free_irq(int irq, int cpu);
 173
 174#define ARMV8_PMU_PDEV_NAME "armv8-pmu"
 175
 176#endif /* CONFIG_ARM_PMU */
 177
 178#define ARMV8_SPE_PDEV_NAME "arm,spe-v1"
 179
 180#endif /* __ARM_PMU_H__ */
 181