LXR linux/include/linux/uwb/whci.h

   1/*
   2 * Wireless Host Controller Interface for Ultra-Wide-Band and Wireless USB
   3 *
   4 * Copyright (C) 2005-2006 Intel Corporation
   5 * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
   6 *
   7 * This program is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU General Public License version
   9 * 2 as published by the Free Software Foundation.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software
  18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  19 * 02110-1301, USA.
  20 *
  21 *
  22 *
  23 * References:
  24 *   [WHCI] Wireless Host Controller Interface Specification for
  25 *          Certified Wireless Universal Serial Bus, revision 0.95.
  26 */
  27#ifndef _LINUX_UWB_WHCI_H_
  28#define _LINUX_UWB_WHCI_H_
  29
  30#include <linux/pci.h>
  31
  32/*
  33 * UWB interface capability registers (offsets from UWBBASE)
  34 *
  35 * [WHCI] section 2.2
  36 */
  37#define UWBCAPINFO      0x00 /* == UWBCAPDATA(0) */
  38#  define UWBCAPINFO_TO_N_CAPS(c)       (((c) >> 0)  & 0xFull)
  39#define UWBCAPDATA(n)   (8*(n))
  40#  define UWBCAPDATA_TO_VERSION(c)      (((c) >> 32) & 0xFFFFull)
  41#  define UWBCAPDATA_TO_OFFSET(c)       (((c) >> 18) & 0x3FFFull)
  42#  define UWBCAPDATA_TO_BAR(c)          (((c) >> 16) & 0x3ull)
  43#  define UWBCAPDATA_TO_SIZE(c)         ((((c) >> 8) & 0xFFull) * sizeof(u32))
  44#  define UWBCAPDATA_TO_CAP_ID(c)       (((c) >> 0)  & 0xFFull)
  45
  46/* Size of the WHCI capability data (including the RC capability) for
  47   a device with n capabilities. */
  48#define UWBCAPDATA_SIZE(n) (8 + 8*(n))
  49
  50
  51/*
  52 * URC registers (offsets from URCBASE)
  53 *
  54 * [WHCI] section 2.3
  55 */
  56#define URCCMD          0x00
  57#  define URCCMD_RESET          (1 << 31)  /* UMC Hardware reset */
  58#  define URCCMD_RS             (1 << 30)  /* Run/Stop */
  59#  define URCCMD_EARV           (1 << 29)  /* Event Address Register Valid */
  60#  define URCCMD_ACTIVE         (1 << 15)  /* Command is active */
  61#  define URCCMD_IWR            (1 << 14)  /* Interrupt When Ready */
  62#  define URCCMD_SIZE_MASK      0x00000fff /* Command size mask */
  63#define URCSTS          0x04
  64#  define URCSTS_EPS            (1 << 17)  /* Event Processing Status */
  65#  define URCSTS_HALTED         (1 << 16)  /* RC halted */
  66#  define URCSTS_HSE            (1 << 10)  /* Host System Error...fried */
  67#  define URCSTS_ER             (1 <<  9)  /* Event Ready */
  68#  define URCSTS_RCI            (1 <<  8)  /* Ready for Command Interrupt */
  69#  define URCSTS_INT_MASK       0x00000700 /* URC interrupt sources */
  70#  define URCSTS_ISI            0x000000ff /* Interrupt Source Identification */
  71#define URCINTR         0x08
  72#  define URCINTR_EN_ALL        0x000007ff /* Enable all interrupt sources */
  73#define URCCMDADDR      0x10
  74#define URCEVTADDR      0x18
  75#  define URCEVTADDR_OFFSET_MASK 0xfff    /* Event pointer offset mask */
  76
  77
  78/** Write 32 bit @value to little endian register at @addr */
  79static inline
  80void le_writel(u32 value, void __iomem *addr)
  81{
  82        iowrite32(value, addr);
  83}
  84
  85
  86/** Read from 32 bit little endian register at @addr */
  87static inline
  88u32 le_readl(void __iomem *addr)
  89{
  90        return ioread32(addr);
  91}
  92
  93
  94/** Write 64 bit @value to little endian register at @addr */
  95static inline
  96void le_writeq(u64 value, void __iomem *addr)
  97{
  98        iowrite32(value, addr);
  99        iowrite32(value >> 32, addr + 4);
 100}
 101
 102
 103/** Read from 64 bit little endian register at @addr */
 104static inline
 105u64 le_readq(void __iomem *addr)
 106{
 107        u64 value;
 108        value  = ioread32(addr);
 109        value |= (u64)ioread32(addr + 4) << 32;
 110        return value;
 111}
 112
 113extern int whci_wait_for(struct device *dev, u32 __iomem *reg,
 114                         u32 mask, u32 result,
 115                         unsigned long max_ms,  const char *tag);
 116
 117#endif /* #ifndef _LINUX_UWB_WHCI_H_ */
 118