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11#define pr_fmt(fmt) "MityOMAPL138: " fmt
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/console.h>
16#include <linux/platform_device.h>
17#include <linux/mtd/partitions.h>
18#include <linux/regulator/machine.h>
19#include <linux/i2c.h>
20#include <linux/platform_data/at24.h>
21#include <linux/etherdevice.h>
22#include <linux/spi/spi.h>
23#include <linux/spi/flash.h>
24
25#include <asm/io.h>
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <mach/common.h>
29#include "cp_intc.h"
30#include <mach/da8xx.h>
31#include <linux/platform_data/mtd-davinci.h>
32#include <linux/platform_data/mtd-davinci-aemif.h>
33#include <mach/mux.h>
34#include <linux/platform_data/spi-davinci.h>
35
36#define MITYOMAPL138_PHY_ID ""
37
38#define FACTORY_CONFIG_MAGIC 0x012C0138
39#define FACTORY_CONFIG_VERSION 0x00010001
40
41
42struct factory_config {
43 u32 magic;
44 u32 version;
45 u8 mac[6];
46 u32 fpga_type;
47 u32 spare;
48 u32 serialnumber;
49 char partnum[32];
50};
51
52static struct factory_config factory_config;
53
54#ifdef CONFIG_CPU_FREQ
55struct part_no_info {
56 const char *part_no;
57 int max_freq;
58};
59
60static struct part_no_info mityomapl138_pn_info[] = {
61 {
62 .part_no = "L138-C",
63 .max_freq = 300000,
64 },
65 {
66 .part_no = "L138-D",
67 .max_freq = 375000,
68 },
69 {
70 .part_no = "L138-F",
71 .max_freq = 456000,
72 },
73 {
74 .part_no = "1808-C",
75 .max_freq = 300000,
76 },
77 {
78 .part_no = "1808-D",
79 .max_freq = 375000,
80 },
81 {
82 .part_no = "1808-F",
83 .max_freq = 456000,
84 },
85 {
86 .part_no = "1810-D",
87 .max_freq = 375000,
88 },
89};
90
91static void mityomapl138_cpufreq_init(const char *partnum)
92{
93 int i, ret;
94
95 for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
96
97
98
99
100
101
102
103 if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
104 strlen(mityomapl138_pn_info[i].part_no))) {
105 da850_max_speed = mityomapl138_pn_info[i].max_freq;
106 break;
107 }
108 }
109
110 ret = da850_register_cpufreq("pll0_sysclk3");
111 if (ret)
112 pr_warn("cpufreq registration failed: %d\n", ret);
113}
114#else
115static void mityomapl138_cpufreq_init(const char *partnum) { }
116#endif
117
118static void read_factory_config(struct nvmem_device *nvmem, void *context)
119{
120 int ret;
121 const char *partnum = NULL;
122 struct davinci_soc_info *soc_info = &davinci_soc_info;
123
124 if (!IS_BUILTIN(CONFIG_NVMEM)) {
125 pr_warn("Factory Config not available without CONFIG_NVMEM\n");
126 goto bad_config;
127 }
128
129 ret = nvmem_device_read(nvmem, 0, sizeof(factory_config),
130 &factory_config);
131 if (ret != sizeof(struct factory_config)) {
132 pr_warn("Read Factory Config Failed: %d\n", ret);
133 goto bad_config;
134 }
135
136 if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
137 pr_warn("Factory Config Magic Wrong (%X)\n",
138 factory_config.magic);
139 goto bad_config;
140 }
141
142 if (factory_config.version != FACTORY_CONFIG_VERSION) {
143 pr_warn("Factory Config Version Wrong (%X)\n",
144 factory_config.version);
145 goto bad_config;
146 }
147
148 pr_info("Found MAC = %pM\n", factory_config.mac);
149 if (is_valid_ether_addr(factory_config.mac))
150 memcpy(soc_info->emac_pdata->mac_addr,
151 factory_config.mac, ETH_ALEN);
152 else
153 pr_warn("Invalid MAC found in factory config block\n");
154
155 partnum = factory_config.partnum;
156 pr_info("Part Number = %s\n", partnum);
157
158bad_config:
159
160 mityomapl138_cpufreq_init(partnum);
161}
162
163static struct at24_platform_data mityomapl138_fd_chip = {
164 .byte_len = 256,
165 .page_size = 8,
166 .flags = AT24_FLAG_READONLY | AT24_FLAG_IRUGO,
167 .setup = read_factory_config,
168 .context = NULL,
169};
170
171static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
172 .bus_freq = 100,
173 .bus_delay = 0,
174};
175
176
177
178static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
179 {
180 .supply = "cvdd",
181 },
182};
183
184
185static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
186 {
187 .supply = "usb0_vdda18",
188 },
189 {
190 .supply = "usb1_vdda18",
191 },
192 {
193 .supply = "ddr_dvdd18",
194 },
195 {
196 .supply = "sata_vddr",
197 },
198};
199
200
201static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
202 {
203 .supply = "sata_vdd",
204 },
205 {
206 .supply = "usb_cvdd",
207 },
208 {
209 .supply = "pll0_vdda",
210 },
211 {
212 .supply = "pll1_vdda",
213 },
214};
215
216
217static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
218 {
219 .supply = "1.8v_aux",
220 },
221};
222
223
224static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
225 {
226 .supply = "vccaux",
227 },
228};
229
230static struct regulator_init_data tps65023_regulator_data[] = {
231
232 {
233 .constraints = {
234 .min_uV = 1150000,
235 .max_uV = 1350000,
236 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
237 REGULATOR_CHANGE_STATUS,
238 .boot_on = 1,
239 },
240 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
241 .consumer_supplies = tps65023_dcdc1_consumers,
242 },
243
244 {
245 .constraints = {
246 .min_uV = 1800000,
247 .max_uV = 1800000,
248 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
249 .boot_on = 1,
250 },
251 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
252 .consumer_supplies = tps65023_dcdc2_consumers,
253 },
254
255 {
256 .constraints = {
257 .min_uV = 1200000,
258 .max_uV = 1200000,
259 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
260 .boot_on = 1,
261 },
262 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
263 .consumer_supplies = tps65023_dcdc3_consumers,
264 },
265
266 {
267 .constraints = {
268 .min_uV = 1800000,
269 .max_uV = 1800000,
270 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
271 .boot_on = 1,
272 },
273 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
274 .consumer_supplies = tps65023_ldo1_consumers,
275 },
276
277 {
278 .constraints = {
279 .min_uV = 2500000,
280 .max_uV = 3300000,
281 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
282 REGULATOR_CHANGE_STATUS,
283 .boot_on = 1,
284 },
285 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
286 .consumer_supplies = tps65023_ldo2_consumers,
287 },
288};
289
290static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
291 {
292 I2C_BOARD_INFO("tps65023", 0x48),
293 .platform_data = &tps65023_regulator_data[0],
294 },
295 {
296 I2C_BOARD_INFO("24c02", 0x50),
297 .platform_data = &mityomapl138_fd_chip,
298 },
299};
300
301static int __init pmic_tps65023_init(void)
302{
303 return i2c_register_board_info(1, mityomap_tps65023_info,
304 ARRAY_SIZE(mityomap_tps65023_info));
305}
306
307
308
309
310
311static struct mtd_partition spi_flash_partitions[] = {
312 [0] = {
313 .name = "ubl",
314 .offset = 0,
315 .size = SZ_64K,
316 .mask_flags = MTD_WRITEABLE,
317 },
318 [1] = {
319 .name = "u-boot",
320 .offset = MTDPART_OFS_APPEND,
321 .size = SZ_512K,
322 .mask_flags = MTD_WRITEABLE,
323 },
324 [2] = {
325 .name = "u-boot-env",
326 .offset = MTDPART_OFS_APPEND,
327 .size = SZ_64K,
328 .mask_flags = MTD_WRITEABLE,
329 },
330 [3] = {
331 .name = "periph-config",
332 .offset = MTDPART_OFS_APPEND,
333 .size = SZ_64K,
334 .mask_flags = MTD_WRITEABLE,
335 },
336 [4] = {
337 .name = "reserved",
338 .offset = MTDPART_OFS_APPEND,
339 .size = SZ_256K + SZ_64K,
340 },
341 [5] = {
342 .name = "kernel",
343 .offset = MTDPART_OFS_APPEND,
344 .size = SZ_2M + SZ_1M,
345 },
346 [6] = {
347 .name = "fpga",
348 .offset = MTDPART_OFS_APPEND,
349 .size = SZ_2M,
350 },
351 [7] = {
352 .name = "spare",
353 .offset = MTDPART_OFS_APPEND,
354 .size = MTDPART_SIZ_FULL,
355 },
356};
357
358static struct flash_platform_data mityomapl138_spi_flash_data = {
359 .name = "m25p80",
360 .parts = spi_flash_partitions,
361 .nr_parts = ARRAY_SIZE(spi_flash_partitions),
362 .type = "m24p64",
363};
364
365static struct davinci_spi_config spi_eprom_config = {
366 .io_type = SPI_IO_TYPE_DMA,
367 .c2tdelay = 8,
368 .t2cdelay = 8,
369};
370
371static struct spi_board_info mityomapl138_spi_flash_info[] = {
372 {
373 .modalias = "m25p80",
374 .platform_data = &mityomapl138_spi_flash_data,
375 .controller_data = &spi_eprom_config,
376 .mode = SPI_MODE_0,
377 .max_speed_hz = 30000000,
378 .bus_num = 1,
379 .chip_select = 0,
380 },
381};
382
383
384
385
386
387static struct mtd_partition mityomapl138_nandflash_partition[] = {
388 {
389 .name = "rootfs",
390 .offset = 0,
391 .size = SZ_128M,
392 .mask_flags = 0,
393 },
394 {
395 .name = "homefs",
396 .offset = MTDPART_OFS_APPEND,
397 .size = MTDPART_SIZ_FULL,
398 .mask_flags = 0,
399 },
400};
401
402static struct davinci_nand_pdata mityomapl138_nandflash_data = {
403 .core_chipsel = 1,
404 .parts = mityomapl138_nandflash_partition,
405 .nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition),
406 .ecc_mode = NAND_ECC_HW,
407 .bbt_options = NAND_BBT_USE_FLASH,
408 .options = NAND_BUSWIDTH_16,
409 .ecc_bits = 1,
410};
411
412static struct resource mityomapl138_nandflash_resource[] = {
413 {
414 .start = DA8XX_AEMIF_CS3_BASE,
415 .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
416 .flags = IORESOURCE_MEM,
417 },
418 {
419 .start = DA8XX_AEMIF_CTL_BASE,
420 .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
421 .flags = IORESOURCE_MEM,
422 },
423};
424
425static struct platform_device mityomapl138_nandflash_device = {
426 .name = "davinci_nand",
427 .id = 1,
428 .dev = {
429 .platform_data = &mityomapl138_nandflash_data,
430 },
431 .num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource),
432 .resource = mityomapl138_nandflash_resource,
433};
434
435static struct platform_device *mityomapl138_devices[] __initdata = {
436 &mityomapl138_nandflash_device,
437};
438
439static void __init mityomapl138_setup_nand(void)
440{
441 platform_add_devices(mityomapl138_devices,
442 ARRAY_SIZE(mityomapl138_devices));
443
444 if (davinci_aemif_setup(&mityomapl138_nandflash_device))
445 pr_warn("%s: Cannot configure AEMIF\n", __func__);
446}
447
448static const short mityomap_mii_pins[] = {
449 DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
450 DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
451 DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
452 DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
453 DA850_MDIO_D,
454 -1
455};
456
457static const short mityomap_rmii_pins[] = {
458 DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
459 DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
460 DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
461 DA850_MDIO_D,
462 -1
463};
464
465static void __init mityomapl138_config_emac(void)
466{
467 void __iomem *cfg_chip3_base;
468 int ret;
469 u32 val;
470 struct davinci_soc_info *soc_info = &davinci_soc_info;
471
472 soc_info->emac_pdata->rmii_en = 0;
473
474 cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
475 val = __raw_readl(cfg_chip3_base);
476
477 if (soc_info->emac_pdata->rmii_en) {
478 val |= BIT(8);
479 ret = davinci_cfg_reg_list(mityomap_rmii_pins);
480 pr_info("RMII PHY configured\n");
481 } else {
482 val &= ~BIT(8);
483 ret = davinci_cfg_reg_list(mityomap_mii_pins);
484 pr_info("MII PHY configured\n");
485 }
486
487 if (ret) {
488 pr_warn("mii/rmii mux setup failed: %d\n", ret);
489 return;
490 }
491
492
493 __raw_writel(val, cfg_chip3_base);
494
495 soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
496
497 ret = da8xx_register_emac();
498 if (ret)
499 pr_warn("emac registration failed: %d\n", ret);
500}
501
502static void __init mityomapl138_init(void)
503{
504 int ret;
505
506
507 ret = da850_register_edma(NULL);
508 if (ret)
509 pr_warn("edma registration failed: %d\n", ret);
510
511 ret = da8xx_register_watchdog();
512 if (ret)
513 pr_warn("watchdog registration failed: %d\n", ret);
514
515 davinci_serial_init(da8xx_serial_device);
516
517 ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
518 if (ret)
519 pr_warn("i2c0 registration failed: %d\n", ret);
520
521 ret = pmic_tps65023_init();
522 if (ret)
523 pr_warn("TPS65023 PMIC init failed: %d\n", ret);
524
525 mityomapl138_setup_nand();
526
527 ret = spi_register_board_info(mityomapl138_spi_flash_info,
528 ARRAY_SIZE(mityomapl138_spi_flash_info));
529 if (ret)
530 pr_warn("spi info registration failed: %d\n", ret);
531
532 ret = da8xx_register_spi_bus(1,
533 ARRAY_SIZE(mityomapl138_spi_flash_info));
534 if (ret)
535 pr_warn("spi 1 registration failed: %d\n", ret);
536
537 mityomapl138_config_emac();
538
539 ret = da8xx_register_rtc();
540 if (ret)
541 pr_warn("rtc setup failed: %d\n", ret);
542
543 ret = da8xx_register_cpuidle();
544 if (ret)
545 pr_warn("cpuidle registration failed: %d\n", ret);
546
547 davinci_pm_init();
548}
549
550#ifdef CONFIG_SERIAL_8250_CONSOLE
551static int __init mityomapl138_console_init(void)
552{
553 if (!machine_is_mityomapl138())
554 return 0;
555
556 return add_preferred_console("ttyS", 1, "115200");
557}
558console_initcall(mityomapl138_console_init);
559#endif
560
561static void __init mityomapl138_map_io(void)
562{
563 da850_init();
564}
565
566MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
567 .atag_offset = 0x100,
568 .map_io = mityomapl138_map_io,
569 .init_irq = cp_intc_init,
570 .init_time = da850_init_time,
571 .init_machine = mityomapl138_init,
572 .init_late = davinci_init_late,
573 .dma_zone_size = SZ_128M,
574MACHINE_END
575
