LXR linux/arch/powerpc/platforms/83xx/misc.c

   1/*
   2 * misc setup functions for MPC83xx
   3 *
   4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
   5 *
   6 * This program is free software; you can redistribute  it and/or modify it
   7 * under  the terms of  the GNU General  Public License as published by the
   8 * Free Software Foundation;  either version 2 of the  License, or (at your
   9 * option) any later version.
  10 */
  11
  12#include <linux/stddef.h>
  13#include <linux/kernel.h>
  14#include <linux/of_platform.h>
  15#include <linux/pci.h>
  16
  17#include <asm/debug.h>
  18#include <asm/io.h>
  19#include <asm/hw_irq.h>
  20#include <asm/ipic.h>
  21#include <soc/fsl/qe/qe_ic.h>
  22#include <sysdev/fsl_soc.h>
  23#include <sysdev/fsl_pci.h>
  24
  25#include "mpc83xx.h"
  26
  27static __be32 __iomem *restart_reg_base;
  28
  29static int __init mpc83xx_restart_init(void)
  30{
  31        /* map reset restart_reg_baseister space */
  32        restart_reg_base = ioremap(get_immrbase() + 0x900, 0xff);
  33
  34        return 0;
  35}
  36
  37arch_initcall(mpc83xx_restart_init);
  38
  39void __noreturn mpc83xx_restart(char *cmd)
  40{
  41#define RST_OFFSET      0x00000900
  42#define RST_PROT_REG    0x00000018
  43#define RST_CTRL_REG    0x0000001c
  44
  45        local_irq_disable();
  46
  47        if (restart_reg_base) {
  48                /* enable software reset "RSTE" */
  49                out_be32(restart_reg_base + (RST_PROT_REG >> 2), 0x52535445);
  50
  51                /* set software hard reset */
  52                out_be32(restart_reg_base + (RST_CTRL_REG >> 2), 0x2);
  53        } else {
  54                printk (KERN_EMERG "Error: Restart registers not mapped, spinning!\n");
  55        }
  56
  57        for (;;) ;
  58}
  59
  60long __init mpc83xx_time_init(void)
  61{
  62#define SPCR_OFFSET     0x00000110
  63#define SPCR_TBEN       0x00400000
  64        __be32 __iomem *spcr = ioremap(get_immrbase() + SPCR_OFFSET, 4);
  65        __be32 tmp;
  66
  67        tmp = in_be32(spcr);
  68        out_be32(spcr, tmp | SPCR_TBEN);
  69
  70        iounmap(spcr);
  71
  72        return 0;
  73}
  74
  75void __init mpc83xx_ipic_init_IRQ(void)
  76{
  77        struct device_node *np;
  78
  79        /* looking for fsl,pq2pro-pic which is asl compatible with fsl,ipic */
  80        np = of_find_compatible_node(NULL, NULL, "fsl,ipic");
  81        if (!np)
  82                np = of_find_node_by_type(NULL, "ipic");
  83        if (!np)
  84                return;
  85
  86        ipic_init(np, 0);
  87
  88        of_node_put(np);
  89
  90        /* Initialize the default interrupt mapping priorities,
  91         * in case the boot rom changed something on us.
  92         */
  93        ipic_set_default_priority();
  94}
  95
  96#ifdef CONFIG_QUICC_ENGINE
  97void __init mpc83xx_qe_init_IRQ(void)
  98{
  99        struct device_node *np;
 100
 101        np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
 102        if (!np) {
 103                np = of_find_node_by_type(NULL, "qeic");
 104                if (!np)
 105                        return;
 106        }
 107        qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
 108        of_node_put(np);
 109}
 110
 111void __init mpc83xx_ipic_and_qe_init_IRQ(void)
 112{
 113        mpc83xx_ipic_init_IRQ();
 114        mpc83xx_qe_init_IRQ();
 115}
 116#endif /* CONFIG_QUICC_ENGINE */
 117
 118static const struct of_device_id of_bus_ids[] __initconst = {
 119        { .type = "soc", },
 120        { .compatible = "soc", },
 121        { .compatible = "simple-bus" },
 122        { .compatible = "gianfar" },
 123        { .compatible = "gpio-leds", },
 124        { .type = "qe", },
 125        { .compatible = "fsl,qe", },
 126        {},
 127};
 128
 129int __init mpc83xx_declare_of_platform_devices(void)
 130{
 131        of_platform_bus_probe(NULL, of_bus_ids, NULL);
 132        return 0;
 133}
 134
 135#ifdef CONFIG_PCI
 136void __init mpc83xx_setup_pci(void)
 137{
 138        struct device_node *np;
 139
 140        for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
 141                mpc83xx_add_bridge(np);
 142        for_each_compatible_node(np, "pci", "fsl,mpc8314-pcie")
 143                mpc83xx_add_bridge(np);
 144}
 145#endif
 146
 147void __init mpc83xx_setup_arch(void)
 148{
 149        if (ppc_md.progress)
 150                ppc_md.progress("mpc83xx_setup_arch()", 0);
 151}
 152
 153int machine_check_83xx(struct pt_regs *regs)
 154{
 155        u32 mask = 1 << (31 - IPIC_MCP_WDT);
 156
 157        if (!(regs->msr & SRR1_MCE_MCP) || !(ipic_get_mcp_status() & mask))
 158                return machine_check_generic(regs);
 159        ipic_clear_mcp_status(mask);
 160
 161        if (debugger_fault_handler(regs))
 162                return 1;
 163
 164        die("Watchdog NMI Reset", regs, 0);
 165
 166        return 1;
 167}
 168