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11#include <linux/kernel_stat.h>
12#include <linux/interrupt.h>
13#include <linux/seq_file.h>
14#include <linux/proc_fs.h>
15#include <linux/profile.h>
16#include <linux/export.h>
17#include <linux/kernel.h>
18#include <linux/ftrace.h>
19#include <linux/errno.h>
20#include <linux/slab.h>
21#include <linux/init.h>
22#include <linux/cpu.h>
23#include <linux/irq.h>
24#include <asm/irq_regs.h>
25#include <asm/cputime.h>
26#include <asm/lowcore.h>
27#include <asm/irq.h>
28#include <asm/hw_irq.h>
29#include "entry.h"
30
31DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat);
32EXPORT_PER_CPU_SYMBOL_GPL(irq_stat);
33
34struct irq_class {
35 int irq;
36 char *name;
37 char *desc;
38};
39
40
41
42
43
44
45
46
47
48
49
50static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = {
51 {.irq = EXT_INTERRUPT, .name = "EXT"},
52 {.irq = IO_INTERRUPT, .name = "I/O"},
53 {.irq = THIN_INTERRUPT, .name = "AIO"},
54};
55
56
57
58
59
60
61static const struct irq_class irqclass_sub_desc[] = {
62 {.irq = IRQEXT_CLK, .name = "CLK", .desc = "[EXT] Clock Comparator"},
63 {.irq = IRQEXT_EXC, .name = "EXC", .desc = "[EXT] External Call"},
64 {.irq = IRQEXT_EMS, .name = "EMS", .desc = "[EXT] Emergency Signal"},
65 {.irq = IRQEXT_TMR, .name = "TMR", .desc = "[EXT] CPU Timer"},
66 {.irq = IRQEXT_TLA, .name = "TAL", .desc = "[EXT] Timing Alert"},
67 {.irq = IRQEXT_PFL, .name = "PFL", .desc = "[EXT] Pseudo Page Fault"},
68 {.irq = IRQEXT_DSD, .name = "DSD", .desc = "[EXT] DASD Diag"},
69 {.irq = IRQEXT_VRT, .name = "VRT", .desc = "[EXT] Virtio"},
70 {.irq = IRQEXT_SCP, .name = "SCP", .desc = "[EXT] Service Call"},
71 {.irq = IRQEXT_IUC, .name = "IUC", .desc = "[EXT] IUCV"},
72 {.irq = IRQEXT_CMS, .name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"},
73 {.irq = IRQEXT_CMC, .name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"},
74 {.irq = IRQEXT_FTP, .name = "FTP", .desc = "[EXT] HMC FTP Service"},
75 {.irq = IRQIO_CIO, .name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"},
76 {.irq = IRQIO_DAS, .name = "DAS", .desc = "[I/O] DASD"},
77 {.irq = IRQIO_C15, .name = "C15", .desc = "[I/O] 3215"},
78 {.irq = IRQIO_C70, .name = "C70", .desc = "[I/O] 3270"},
79 {.irq = IRQIO_TAP, .name = "TAP", .desc = "[I/O] Tape"},
80 {.irq = IRQIO_VMR, .name = "VMR", .desc = "[I/O] Unit Record Devices"},
81 {.irq = IRQIO_LCS, .name = "LCS", .desc = "[I/O] LCS"},
82 {.irq = IRQIO_CTC, .name = "CTC", .desc = "[I/O] CTC"},
83 {.irq = IRQIO_ADM, .name = "ADM", .desc = "[I/O] EADM Subchannel"},
84 {.irq = IRQIO_CSC, .name = "CSC", .desc = "[I/O] CHSC Subchannel"},
85 {.irq = IRQIO_VIR, .name = "VIR", .desc = "[I/O] Virtual I/O Devices"},
86 {.irq = IRQIO_QAI, .name = "QAI", .desc = "[AIO] QDIO Adapter Interrupt"},
87 {.irq = IRQIO_APB, .name = "APB", .desc = "[AIO] AP Bus"},
88 {.irq = IRQIO_PCF, .name = "PCF", .desc = "[AIO] PCI Floating Interrupt"},
89 {.irq = IRQIO_PCD, .name = "PCD", .desc = "[AIO] PCI Directed Interrupt"},
90 {.irq = IRQIO_MSI, .name = "MSI", .desc = "[AIO] MSI Interrupt"},
91 {.irq = IRQIO_VAI, .name = "VAI", .desc = "[AIO] Virtual I/O Devices AI"},
92 {.irq = IRQIO_GAL, .name = "GAL", .desc = "[AIO] GIB Alert"},
93 {.irq = NMI_NMI, .name = "NMI", .desc = "[NMI] Machine Check"},
94 {.irq = CPU_RST, .name = "RST", .desc = "[CPU] CPU Restart"},
95};
96
97void __init init_IRQ(void)
98{
99 BUILD_BUG_ON(ARRAY_SIZE(irqclass_sub_desc) != NR_ARCH_IRQS);
100 init_cio_interrupts();
101 init_airq_interrupts();
102 init_ext_interrupts();
103}
104
105void do_IRQ(struct pt_regs *regs, int irq)
106{
107 struct pt_regs *old_regs;
108
109 old_regs = set_irq_regs(regs);
110 irq_enter();
111 if (tod_after_eq(S390_lowcore.int_clock,
112 S390_lowcore.clock_comparator))
113
114 clock_comparator_work();
115 generic_handle_irq(irq);
116 irq_exit();
117 set_irq_regs(old_regs);
118}
119
120static void show_msi_interrupt(struct seq_file *p, int irq)
121{
122 struct irq_desc *desc;
123 unsigned long flags;
124 int cpu;
125
126 irq_lock_sparse();
127 desc = irq_to_desc(irq);
128 if (!desc)
129 goto out;
130
131 raw_spin_lock_irqsave(&desc->lock, flags);
132 seq_printf(p, "%3d: ", irq);
133 for_each_online_cpu(cpu)
134 seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu));
135
136 if (desc->irq_data.chip)
137 seq_printf(p, " %8s", desc->irq_data.chip->name);
138
139 if (desc->action)
140 seq_printf(p, " %s", desc->action->name);
141
142 seq_putc(p, '\n');
143 raw_spin_unlock_irqrestore(&desc->lock, flags);
144out:
145 irq_unlock_sparse();
146}
147
148
149
150
151int show_interrupts(struct seq_file *p, void *v)
152{
153 int index = *(loff_t *) v;
154 int cpu, irq;
155
156 get_online_cpus();
157 if (index == 0) {
158 seq_puts(p, " ");
159 for_each_online_cpu(cpu)
160 seq_printf(p, "CPU%-8d", cpu);
161 seq_putc(p, '\n');
162 }
163 if (index < NR_IRQS_BASE) {
164 seq_printf(p, "%s: ", irqclass_main_desc[index].name);
165 irq = irqclass_main_desc[index].irq;
166 for_each_online_cpu(cpu)
167 seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu));
168 seq_putc(p, '\n');
169 goto out;
170 }
171 if (index < nr_irqs) {
172 show_msi_interrupt(p, index);
173 goto out;
174 }
175 for (index = 0; index < NR_ARCH_IRQS; index++) {
176 seq_printf(p, "%s: ", irqclass_sub_desc[index].name);
177 irq = irqclass_sub_desc[index].irq;
178 for_each_online_cpu(cpu)
179 seq_printf(p, "%10u ",
180 per_cpu(irq_stat, cpu).irqs[irq]);
181 if (irqclass_sub_desc[index].desc)
182 seq_printf(p, " %s", irqclass_sub_desc[index].desc);
183 seq_putc(p, '\n');
184 }
185out:
186 put_online_cpus();
187 return 0;
188}
189
190unsigned int arch_dynirq_lower_bound(unsigned int from)
191{
192 return from < NR_IRQS_BASE ? NR_IRQS_BASE : from;
193}
194
195
196
197
198void do_softirq_own_stack(void)
199{
200 unsigned long old, new;
201
202 old = current_stack_pointer();
203
204 new = S390_lowcore.async_stack;
205 if (((new - old) >> (PAGE_SHIFT + THREAD_SIZE_ORDER)) != 0) {
206
207 new -= STACK_FRAME_OVERHEAD;
208 ((struct stack_frame *) new)->back_chain = old;
209 asm volatile(" la 15,0(%0)\n"
210 " brasl 14,__do_softirq\n"
211 " la 15,0(%1)\n"
212 : : "a" (new), "a" (old)
213 : "0", "1", "2", "3", "4", "5", "14",
214 "cc", "memory" );
215 } else {
216
217 __do_softirq();
218 }
219}
220
221
222
223
224
225static struct hlist_head ext_int_hash[32] ____cacheline_aligned;
226
227struct ext_int_info {
228 ext_int_handler_t handler;
229 struct hlist_node entry;
230 struct rcu_head rcu;
231 u16 code;
232};
233
234
235static DEFINE_SPINLOCK(ext_int_hash_lock);
236
237static inline int ext_hash(u16 code)
238{
239 BUILD_BUG_ON(!is_power_of_2(ARRAY_SIZE(ext_int_hash)));
240
241 return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1);
242}
243
244int register_external_irq(u16 code, ext_int_handler_t handler)
245{
246 struct ext_int_info *p;
247 unsigned long flags;
248 int index;
249
250 p = kmalloc(sizeof(*p), GFP_ATOMIC);
251 if (!p)
252 return -ENOMEM;
253 p->code = code;
254 p->handler = handler;
255 index = ext_hash(code);
256
257 spin_lock_irqsave(&ext_int_hash_lock, flags);
258 hlist_add_head_rcu(&p->entry, &ext_int_hash[index]);
259 spin_unlock_irqrestore(&ext_int_hash_lock, flags);
260 return 0;
261}
262EXPORT_SYMBOL(register_external_irq);
263
264int unregister_external_irq(u16 code, ext_int_handler_t handler)
265{
266 struct ext_int_info *p;
267 unsigned long flags;
268 int index = ext_hash(code);
269
270 spin_lock_irqsave(&ext_int_hash_lock, flags);
271 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
272 if (p->code == code && p->handler == handler) {
273 hlist_del_rcu(&p->entry);
274 kfree_rcu(p, rcu);
275 }
276 }
277 spin_unlock_irqrestore(&ext_int_hash_lock, flags);
278 return 0;
279}
280EXPORT_SYMBOL(unregister_external_irq);
281
282static irqreturn_t do_ext_interrupt(int irq, void *dummy)
283{
284 struct pt_regs *regs = get_irq_regs();
285 struct ext_code ext_code;
286 struct ext_int_info *p;
287 int index;
288
289 ext_code = *(struct ext_code *) ®s->int_code;
290 if (ext_code.code != EXT_IRQ_CLK_COMP)
291 set_cpu_flag(CIF_NOHZ_DELAY);
292
293 index = ext_hash(ext_code.code);
294 rcu_read_lock();
295 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
296 if (unlikely(p->code != ext_code.code))
297 continue;
298 p->handler(ext_code, regs->int_parm, regs->int_parm_long);
299 }
300 rcu_read_unlock();
301 return IRQ_HANDLED;
302}
303
304static struct irqaction external_interrupt = {
305 .name = "EXT",
306 .handler = do_ext_interrupt,
307};
308
309void __init init_ext_interrupts(void)
310{
311 int idx;
312
313 for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++)
314 INIT_HLIST_HEAD(&ext_int_hash[idx]);
315
316 irq_set_chip_and_handler(EXT_INTERRUPT,
317 &dummy_irq_chip, handle_percpu_irq);
318 setup_irq(EXT_INTERRUPT, &external_interrupt);
319}
320
321static DEFINE_SPINLOCK(irq_subclass_lock);
322static unsigned char irq_subclass_refcount[64];
323
324void irq_subclass_register(enum irq_subclass subclass)
325{
326 spin_lock(&irq_subclass_lock);
327 if (!irq_subclass_refcount[subclass])
328 ctl_set_bit(0, subclass);
329 irq_subclass_refcount[subclass]++;
330 spin_unlock(&irq_subclass_lock);
331}
332EXPORT_SYMBOL(irq_subclass_register);
333
334void irq_subclass_unregister(enum irq_subclass subclass)
335{
336 spin_lock(&irq_subclass_lock);
337 irq_subclass_refcount[subclass]--;
338 if (!irq_subclass_refcount[subclass])
339 ctl_clear_bit(0, subclass);
340 spin_unlock(&irq_subclass_lock);
341}
342EXPORT_SYMBOL(irq_subclass_unregister);
343
