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15#include <linux/gpio.h>
16#include <linux/platform_device.h>
17#include <linux/of_device.h>
18#include <linux/module.h>
19#include <linux/irq.h>
20#include <linux/interrupt.h>
21#include <linux/irqchip/chained_irq.h>
22#include <linux/acpi.h>
23
24
25
26
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30
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34
35
36
37#define GPIO_OUTPUT_EN 0x00
38#define GPIO_PADDRV 0x08
39#define GPIO_INT_EN00 0x18
40#define GPIO_INT_EN10 0x20
41#define GPIO_INT_EN20 0x28
42#define GPIO_INT_EN30 0x30
43#define GPIO_INT_POL 0x38
44#define GPIO_INT_TYPE 0x40
45#define GPIO_INT_STAT 0x48
46
47#define GPIO_9XX_BYTESWAP 0X00
48#define GPIO_9XX_CTRL 0X04
49#define GPIO_9XX_OUTPUT_EN 0x14
50#define GPIO_9XX_PADDRV 0x24
51
52
53
54
55#define GPIO_9XX_INT_EN00 0x44
56#define GPIO_9XX_INT_EN10 0x54
57#define GPIO_9XX_INT_EN20 0x64
58#define GPIO_9XX_INT_EN30 0x74
59#define GPIO_9XX_INT_POL 0x104
60#define GPIO_9XX_INT_TYPE 0x114
61#define GPIO_9XX_INT_STAT 0x124
62
63#define GPIO_3XX_INT_EN00 0x18
64#define GPIO_3XX_INT_EN10 0x20
65#define GPIO_3XX_INT_EN20 0x28
66#define GPIO_3XX_INT_EN30 0x30
67#define GPIO_3XX_INT_POL 0x78
68#define GPIO_3XX_INT_TYPE 0x80
69#define GPIO_3XX_INT_STAT 0x88
70
71
72#define XLP_GPIO_IRQ_TYPE_LVL 0x0
73#define XLP_GPIO_IRQ_TYPE_EDGE 0x1
74
75
76#define XLP_GPIO_IRQ_POL_HIGH 0x0
77#define XLP_GPIO_IRQ_POL_LOW 0x1
78
79#define XLP_GPIO_REGSZ 32
80#define XLP_GPIO_IRQ_BASE 768
81#define XLP_MAX_NR_GPIO 96
82
83
84enum {
85 XLP_GPIO_VARIANT_XLP832 = 1,
86 XLP_GPIO_VARIANT_XLP316,
87 XLP_GPIO_VARIANT_XLP208,
88 XLP_GPIO_VARIANT_XLP980,
89 XLP_GPIO_VARIANT_XLP532,
90 GPIO_VARIANT_VULCAN
91};
92
93struct xlp_gpio_priv {
94 struct gpio_chip chip;
95 DECLARE_BITMAP(gpio_enabled_mask, XLP_MAX_NR_GPIO);
96 void __iomem *gpio_intr_en;
97 void __iomem *gpio_intr_stat;
98 void __iomem *gpio_intr_type;
99 void __iomem *gpio_intr_pol;
100 void __iomem *gpio_out_en;
101 void __iomem *gpio_paddrv;
102 spinlock_t lock;
103};
104
105static int xlp_gpio_get_reg(void __iomem *addr, unsigned gpio)
106{
107 u32 pos, regset;
108
109 pos = gpio % XLP_GPIO_REGSZ;
110 regset = (gpio / XLP_GPIO_REGSZ) * 4;
111 return !!(readl(addr + regset) & BIT(pos));
112}
113
114static void xlp_gpio_set_reg(void __iomem *addr, unsigned gpio, int state)
115{
116 u32 value, pos, regset;
117
118 pos = gpio % XLP_GPIO_REGSZ;
119 regset = (gpio / XLP_GPIO_REGSZ) * 4;
120 value = readl(addr + regset);
121
122 if (state)
123 value |= BIT(pos);
124 else
125 value &= ~BIT(pos);
126
127 writel(value, addr + regset);
128}
129
130static void xlp_gpio_irq_disable(struct irq_data *d)
131{
132 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
133 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
134 unsigned long flags;
135
136 spin_lock_irqsave(&priv->lock, flags);
137 xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
138 __clear_bit(d->hwirq, priv->gpio_enabled_mask);
139 spin_unlock_irqrestore(&priv->lock, flags);
140}
141
142static void xlp_gpio_irq_mask_ack(struct irq_data *d)
143{
144 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
145 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
146 unsigned long flags;
147
148 spin_lock_irqsave(&priv->lock, flags);
149 xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
150 xlp_gpio_set_reg(priv->gpio_intr_stat, d->hwirq, 0x1);
151 __clear_bit(d->hwirq, priv->gpio_enabled_mask);
152 spin_unlock_irqrestore(&priv->lock, flags);
153}
154
155static void xlp_gpio_irq_unmask(struct irq_data *d)
156{
157 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
158 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
159 unsigned long flags;
160
161 spin_lock_irqsave(&priv->lock, flags);
162 xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x1);
163 __set_bit(d->hwirq, priv->gpio_enabled_mask);
164 spin_unlock_irqrestore(&priv->lock, flags);
165}
166
167static int xlp_gpio_set_irq_type(struct irq_data *d, unsigned int type)
168{
169 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
170 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
171 int pol, irq_type;
172
173 switch (type) {
174 case IRQ_TYPE_EDGE_RISING:
175 irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
176 pol = XLP_GPIO_IRQ_POL_HIGH;
177 break;
178 case IRQ_TYPE_EDGE_FALLING:
179 irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
180 pol = XLP_GPIO_IRQ_POL_LOW;
181 break;
182 case IRQ_TYPE_LEVEL_HIGH:
183 irq_type = XLP_GPIO_IRQ_TYPE_LVL;
184 pol = XLP_GPIO_IRQ_POL_HIGH;
185 break;
186 case IRQ_TYPE_LEVEL_LOW:
187 irq_type = XLP_GPIO_IRQ_TYPE_LVL;
188 pol = XLP_GPIO_IRQ_POL_LOW;
189 break;
190 default:
191 return -EINVAL;
192 }
193
194 xlp_gpio_set_reg(priv->gpio_intr_type, d->hwirq, irq_type);
195 xlp_gpio_set_reg(priv->gpio_intr_pol, d->hwirq, pol);
196
197 return 0;
198}
199
200static struct irq_chip xlp_gpio_irq_chip = {
201 .name = "XLP-GPIO",
202 .irq_mask_ack = xlp_gpio_irq_mask_ack,
203 .irq_disable = xlp_gpio_irq_disable,
204 .irq_set_type = xlp_gpio_set_irq_type,
205 .irq_unmask = xlp_gpio_irq_unmask,
206 .flags = IRQCHIP_ONESHOT_SAFE,
207};
208
209static void xlp_gpio_generic_handler(struct irq_desc *desc)
210{
211 struct xlp_gpio_priv *priv = irq_desc_get_handler_data(desc);
212 struct irq_chip *irqchip = irq_desc_get_chip(desc);
213 int gpio, regoff;
214 u32 gpio_stat;
215
216 regoff = -1;
217 gpio_stat = 0;
218
219 chained_irq_enter(irqchip, desc);
220 for_each_set_bit(gpio, priv->gpio_enabled_mask, XLP_MAX_NR_GPIO) {
221 if (regoff != gpio / XLP_GPIO_REGSZ) {
222 regoff = gpio / XLP_GPIO_REGSZ;
223 gpio_stat = readl(priv->gpio_intr_stat + regoff * 4);
224 }
225
226 if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ))
227 generic_handle_irq(irq_find_mapping(
228 priv->chip.irq.domain, gpio));
229 }
230 chained_irq_exit(irqchip, desc);
231}
232
233static int xlp_gpio_dir_output(struct gpio_chip *gc, unsigned gpio, int state)
234{
235 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
236
237 BUG_ON(gpio >= gc->ngpio);
238 xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x1);
239
240 return 0;
241}
242
243static int xlp_gpio_dir_input(struct gpio_chip *gc, unsigned gpio)
244{
245 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
246
247 BUG_ON(gpio >= gc->ngpio);
248 xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x0);
249
250 return 0;
251}
252
253static int xlp_gpio_get(struct gpio_chip *gc, unsigned gpio)
254{
255 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
256
257 BUG_ON(gpio >= gc->ngpio);
258 return xlp_gpio_get_reg(priv->gpio_paddrv, gpio);
259}
260
261static void xlp_gpio_set(struct gpio_chip *gc, unsigned gpio, int state)
262{
263 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
264
265 BUG_ON(gpio >= gc->ngpio);
266 xlp_gpio_set_reg(priv->gpio_paddrv, gpio, state);
267}
268
269static const struct of_device_id xlp_gpio_of_ids[] = {
270 {
271 .compatible = "netlogic,xlp832-gpio",
272 .data = (void *)XLP_GPIO_VARIANT_XLP832,
273 },
274 {
275 .compatible = "netlogic,xlp316-gpio",
276 .data = (void *)XLP_GPIO_VARIANT_XLP316,
277 },
278 {
279 .compatible = "netlogic,xlp208-gpio",
280 .data = (void *)XLP_GPIO_VARIANT_XLP208,
281 },
282 {
283 .compatible = "netlogic,xlp980-gpio",
284 .data = (void *)XLP_GPIO_VARIANT_XLP980,
285 },
286 {
287 .compatible = "netlogic,xlp532-gpio",
288 .data = (void *)XLP_GPIO_VARIANT_XLP532,
289 },
290 {
291 .compatible = "brcm,vulcan-gpio",
292 .data = (void *)GPIO_VARIANT_VULCAN,
293 },
294 { },
295};
296MODULE_DEVICE_TABLE(of, xlp_gpio_of_ids);
297
298static int xlp_gpio_probe(struct platform_device *pdev)
299{
300 struct gpio_chip *gc;
301 struct gpio_irq_chip *girq;
302 struct resource *iores;
303 struct xlp_gpio_priv *priv;
304 void __iomem *gpio_base;
305 int irq_base, irq, err;
306 int ngpio;
307 u32 soc_type;
308
309 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
310 if (!iores)
311 return -ENODEV;
312
313 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
314 if (!priv)
315 return -ENOMEM;
316
317 gpio_base = devm_ioremap_resource(&pdev->dev, iores);
318 if (IS_ERR(gpio_base))
319 return PTR_ERR(gpio_base);
320
321 irq = platform_get_irq(pdev, 0);
322 if (irq < 0)
323 return irq;
324
325 if (pdev->dev.of_node) {
326 soc_type = (uintptr_t)of_device_get_match_data(&pdev->dev);
327 } else {
328 const struct acpi_device_id *acpi_id;
329
330 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
331 &pdev->dev);
332 if (!acpi_id || !acpi_id->driver_data) {
333 dev_err(&pdev->dev, "Unable to match ACPI ID\n");
334 return -ENODEV;
335 }
336 soc_type = (uintptr_t) acpi_id->driver_data;
337 }
338
339 switch (soc_type) {
340 case XLP_GPIO_VARIANT_XLP832:
341 priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN;
342 priv->gpio_paddrv = gpio_base + GPIO_PADDRV;
343 priv->gpio_intr_stat = gpio_base + GPIO_INT_STAT;
344 priv->gpio_intr_type = gpio_base + GPIO_INT_TYPE;
345 priv->gpio_intr_pol = gpio_base + GPIO_INT_POL;
346 priv->gpio_intr_en = gpio_base + GPIO_INT_EN00;
347 ngpio = 41;
348 break;
349 case XLP_GPIO_VARIANT_XLP208:
350 case XLP_GPIO_VARIANT_XLP316:
351 priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN;
352 priv->gpio_paddrv = gpio_base + GPIO_PADDRV;
353 priv->gpio_intr_stat = gpio_base + GPIO_3XX_INT_STAT;
354 priv->gpio_intr_type = gpio_base + GPIO_3XX_INT_TYPE;
355 priv->gpio_intr_pol = gpio_base + GPIO_3XX_INT_POL;
356 priv->gpio_intr_en = gpio_base + GPIO_3XX_INT_EN00;
357
358 ngpio = (soc_type == XLP_GPIO_VARIANT_XLP208) ? 42 : 57;
359 break;
360 case XLP_GPIO_VARIANT_XLP980:
361 case XLP_GPIO_VARIANT_XLP532:
362 case GPIO_VARIANT_VULCAN:
363 priv->gpio_out_en = gpio_base + GPIO_9XX_OUTPUT_EN;
364 priv->gpio_paddrv = gpio_base + GPIO_9XX_PADDRV;
365 priv->gpio_intr_stat = gpio_base + GPIO_9XX_INT_STAT;
366 priv->gpio_intr_type = gpio_base + GPIO_9XX_INT_TYPE;
367 priv->gpio_intr_pol = gpio_base + GPIO_9XX_INT_POL;
368 priv->gpio_intr_en = gpio_base + GPIO_9XX_INT_EN00;
369
370 if (soc_type == XLP_GPIO_VARIANT_XLP980)
371 ngpio = 66;
372 else if (soc_type == XLP_GPIO_VARIANT_XLP532)
373 ngpio = 67;
374 else
375 ngpio = 70;
376 break;
377 default:
378 dev_err(&pdev->dev, "Unknown Processor type!\n");
379 return -ENODEV;
380 }
381
382 bitmap_zero(priv->gpio_enabled_mask, XLP_MAX_NR_GPIO);
383
384 gc = &priv->chip;
385
386 gc->owner = THIS_MODULE;
387 gc->label = dev_name(&pdev->dev);
388 gc->base = 0;
389 gc->parent = &pdev->dev;
390 gc->ngpio = ngpio;
391 gc->of_node = pdev->dev.of_node;
392 gc->direction_output = xlp_gpio_dir_output;
393 gc->direction_input = xlp_gpio_dir_input;
394 gc->set = xlp_gpio_set;
395 gc->get = xlp_gpio_get;
396
397 spin_lock_init(&priv->lock);
398
399
400 if (soc_type != GPIO_VARIANT_VULCAN) {
401 irq_base = devm_irq_alloc_descs(&pdev->dev, -1,
402 XLP_GPIO_IRQ_BASE,
403 gc->ngpio, 0);
404 if (irq_base < 0) {
405 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
406 return irq_base;
407 }
408 } else {
409 irq_base = 0;
410 }
411
412 girq = &gc->irq;
413 girq->chip = &xlp_gpio_irq_chip;
414 girq->parent_handler = xlp_gpio_generic_handler;
415 girq->num_parents = 1;
416 girq->parents = devm_kcalloc(&pdev->dev, 1,
417 sizeof(*girq->parents),
418 GFP_KERNEL);
419 if (!girq->parents)
420 return -ENOMEM;
421 girq->parents[0] = irq;
422 girq->first = irq_base;
423 girq->default_type = IRQ_TYPE_NONE;
424 girq->handler = handle_level_irq;
425
426 err = gpiochip_add_data(gc, priv);
427 if (err < 0)
428 return err;
429
430 dev_info(&pdev->dev, "registered %d GPIOs\n", gc->ngpio);
431
432 return 0;
433}
434
435#ifdef CONFIG_ACPI
436static const struct acpi_device_id xlp_gpio_acpi_match[] = {
437 { "BRCM9006", GPIO_VARIANT_VULCAN },
438 { "CAV9006", GPIO_VARIANT_VULCAN },
439 {},
440};
441MODULE_DEVICE_TABLE(acpi, xlp_gpio_acpi_match);
442#endif
443
444static struct platform_driver xlp_gpio_driver = {
445 .driver = {
446 .name = "xlp-gpio",
447 .of_match_table = xlp_gpio_of_ids,
448 .acpi_match_table = ACPI_PTR(xlp_gpio_acpi_match),
449 },
450 .probe = xlp_gpio_probe,
451};
452module_platform_driver(xlp_gpio_driver);
453
454MODULE_AUTHOR("Kamlakant Patel <kamlakant.patel@broadcom.com>");
455MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
456MODULE_DESCRIPTION("Netlogic XLP GPIO Driver");
457MODULE_LICENSE("GPL v2");
458
