LXR linux/drivers/gpu/drm/amd/display/dc/dcn20/dcn20

   1/*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26
  27#include "dcn20_hubbub.h"
  28#include "reg_helper.h"
  29#include "clk_mgr.h"
  30
  31#define REG(reg)\
  32        hubbub1->regs->reg
  33
  34#define CTX \
  35        hubbub1->base.ctx
  36
  37#undef FN
  38#define FN(reg_name, field_name) \
  39        hubbub1->shifts->field_name, hubbub1->masks->field_name
  40
  41#define REG(reg)\
  42        hubbub1->regs->reg
  43
  44#define CTX \
  45        hubbub1->base.ctx
  46
  47#undef FN
  48#define FN(reg_name, field_name) \
  49        hubbub1->shifts->field_name, hubbub1->masks->field_name
  50
  51#ifdef NUM_VMID
  52#undef NUM_VMID
  53#endif
  54#define NUM_VMID 16
  55
  56bool hubbub2_dcc_support_swizzle(
  57                enum swizzle_mode_values swizzle,
  58                unsigned int bytes_per_element,
  59                enum segment_order *segment_order_horz,
  60                enum segment_order *segment_order_vert)
  61{
  62        bool standard_swizzle = false;
  63        bool display_swizzle = false;
  64        bool render_swizzle = false;
  65
  66        switch (swizzle) {
  67        case DC_SW_4KB_S:
  68        case DC_SW_64KB_S:
  69        case DC_SW_VAR_S:
  70        case DC_SW_4KB_S_X:
  71        case DC_SW_64KB_S_X:
  72        case DC_SW_VAR_S_X:
  73                standard_swizzle = true;
  74                break;
  75        case DC_SW_64KB_R_X:
  76                render_swizzle = true;
  77                break;
  78        case DC_SW_4KB_D:
  79        case DC_SW_64KB_D:
  80        case DC_SW_VAR_D:
  81        case DC_SW_4KB_D_X:
  82        case DC_SW_64KB_D_X:
  83        case DC_SW_VAR_D_X:
  84                display_swizzle = true;
  85                break;
  86        default:
  87                break;
  88        }
  89
  90        if (standard_swizzle) {
  91                if (bytes_per_element == 1) {
  92                        *segment_order_horz = segment_order__contiguous;
  93                        *segment_order_vert = segment_order__na;
  94                        return true;
  95                }
  96                if (bytes_per_element == 2) {
  97                        *segment_order_horz = segment_order__non_contiguous;
  98                        *segment_order_vert = segment_order__contiguous;
  99                        return true;
 100                }
 101                if (bytes_per_element == 4) {
 102                        *segment_order_horz = segment_order__non_contiguous;
 103                        *segment_order_vert = segment_order__contiguous;
 104                        return true;
 105                }
 106                if (bytes_per_element == 8) {
 107                        *segment_order_horz = segment_order__na;
 108                        *segment_order_vert = segment_order__contiguous;
 109                        return true;
 110                }
 111        }
 112        if (render_swizzle) {
 113                if (bytes_per_element == 2) {
 114                        *segment_order_horz = segment_order__contiguous;
 115                        *segment_order_vert = segment_order__contiguous;
 116                        return true;
 117                }
 118                if (bytes_per_element == 4) {
 119                        *segment_order_horz = segment_order__non_contiguous;
 120                        *segment_order_vert = segment_order__contiguous;
 121                        return true;
 122                }
 123                if (bytes_per_element == 8) {
 124                        *segment_order_horz = segment_order__contiguous;
 125                        *segment_order_vert = segment_order__non_contiguous;
 126                        return true;
 127                }
 128        }
 129        if (display_swizzle && bytes_per_element == 8) {
 130                *segment_order_horz = segment_order__contiguous;
 131                *segment_order_vert = segment_order__non_contiguous;
 132                return true;
 133        }
 134
 135        return false;
 136}
 137
 138bool hubbub2_dcc_support_pixel_format(
 139                enum surface_pixel_format format,
 140                unsigned int *bytes_per_element)
 141{
 142        /* DML: get_bytes_per_element */
 143        switch (format) {
 144        case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
 145        case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 146                *bytes_per_element = 2;
 147                return true;
 148        case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 149        case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 150        case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 151        case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 152        case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
 153        case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
 154        case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
 155        case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
 156        case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
 157        case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
 158                *bytes_per_element = 4;
 159                return true;
 160        case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 161        case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 162        case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 163                *bytes_per_element = 8;
 164                return true;
 165        default:
 166                return false;
 167        }
 168}
 169
 170static void hubbub2_get_blk256_size(unsigned int *blk256_width, unsigned int *blk256_height,
 171                unsigned int bytes_per_element)
 172{
 173        /* copied from DML.  might want to refactor DML to leverage from DML */
 174        /* DML : get_blk256_size */
 175        if (bytes_per_element == 1) {
 176                *blk256_width = 16;
 177                *blk256_height = 16;
 178        } else if (bytes_per_element == 2) {
 179                *blk256_width = 16;
 180                *blk256_height = 8;
 181        } else if (bytes_per_element == 4) {
 182                *blk256_width = 8;
 183                *blk256_height = 8;
 184        } else if (bytes_per_element == 8) {
 185                *blk256_width = 8;
 186                *blk256_height = 4;
 187        }
 188}
 189
 190static void hubbub2_det_request_size(
 191                unsigned int detile_buf_size,
 192                unsigned int height,
 193                unsigned int width,
 194                unsigned int bpe,
 195                bool *req128_horz_wc,
 196                bool *req128_vert_wc)
 197{
 198        unsigned int blk256_height = 0;
 199        unsigned int blk256_width = 0;
 200        unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc;
 201
 202        hubbub2_get_blk256_size(&blk256_width, &blk256_height, bpe);
 203
 204        swath_bytes_horz_wc = width * blk256_height * bpe;
 205        swath_bytes_vert_wc = height * blk256_width * bpe;
 206
 207        *req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ?
 208                        false : /* full 256B request */
 209                        true; /* half 128b request */
 210
 211        *req128_vert_wc = (2 * swath_bytes_vert_wc <= detile_buf_size) ?
 212                        false : /* full 256B request */
 213                        true; /* half 128b request */
 214}
 215
 216bool hubbub2_get_dcc_compression_cap(struct hubbub *hubbub,
 217                const struct dc_dcc_surface_param *input,
 218                struct dc_surface_dcc_cap *output)
 219{
 220        struct dc *dc = hubbub->ctx->dc;
 221        /* implement section 1.6.2.1 of DCN1_Programming_Guide.docx */
 222        enum dcc_control dcc_control;
 223        unsigned int bpe;
 224        enum segment_order segment_order_horz, segment_order_vert;
 225        bool req128_horz_wc, req128_vert_wc;
 226
 227        memset(output, 0, sizeof(*output));
 228
 229        if (dc->debug.disable_dcc == DCC_DISABLE)
 230                return false;
 231
 232        if (!hubbub->funcs->dcc_support_pixel_format(input->format,
 233                        &bpe))
 234                return false;
 235
 236        if (!hubbub->funcs->dcc_support_swizzle(input->swizzle_mode, bpe,
 237                        &segment_order_horz, &segment_order_vert))
 238                return false;
 239
 240        hubbub2_det_request_size(TO_DCN20_HUBBUB(hubbub)->detile_buf_size,
 241                        input->surface_size.height,  input->surface_size.width,
 242                        bpe, &req128_horz_wc, &req128_vert_wc);
 243
 244        if (!req128_horz_wc && !req128_vert_wc) {
 245                dcc_control = dcc_control__256_256_xxx;
 246        } else if (input->scan == SCAN_DIRECTION_HORIZONTAL) {
 247                if (!req128_horz_wc)
 248                        dcc_control = dcc_control__256_256_xxx;
 249                else if (segment_order_horz == segment_order__contiguous)
 250                        dcc_control = dcc_control__128_128_xxx;
 251                else
 252                        dcc_control = dcc_control__256_64_64;
 253        } else if (input->scan == SCAN_DIRECTION_VERTICAL) {
 254                if (!req128_vert_wc)
 255                        dcc_control = dcc_control__256_256_xxx;
 256                else if (segment_order_vert == segment_order__contiguous)
 257                        dcc_control = dcc_control__128_128_xxx;
 258                else
 259                        dcc_control = dcc_control__256_64_64;
 260        } else {
 261                if ((req128_horz_wc &&
 262                        segment_order_horz == segment_order__non_contiguous) ||
 263                        (req128_vert_wc &&
 264                        segment_order_vert == segment_order__non_contiguous))
 265                        /* access_dir not known, must use most constraining */
 266                        dcc_control = dcc_control__256_64_64;
 267                else
 268                        /* reg128 is true for either horz and vert
 269                         * but segment_order is contiguous
 270                         */
 271                        dcc_control = dcc_control__128_128_xxx;
 272        }
 273
 274        /* Exception for 64KB_R_X */
 275        if ((bpe == 2) && (input->swizzle_mode == DC_SW_64KB_R_X))
 276                dcc_control = dcc_control__128_128_xxx;
 277
 278        if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&
 279                dcc_control != dcc_control__256_256_xxx)
 280                return false;
 281
 282        switch (dcc_control) {
 283        case dcc_control__256_256_xxx:
 284                output->grph.rgb.max_uncompressed_blk_size = 256;
 285                output->grph.rgb.max_compressed_blk_size = 256;
 286                output->grph.rgb.independent_64b_blks = false;
 287                break;
 288        case dcc_control__128_128_xxx:
 289                output->grph.rgb.max_uncompressed_blk_size = 128;
 290                output->grph.rgb.max_compressed_blk_size = 128;
 291                output->grph.rgb.independent_64b_blks = false;
 292                break;
 293        case dcc_control__256_64_64:
 294                output->grph.rgb.max_uncompressed_blk_size = 256;
 295                output->grph.rgb.max_compressed_blk_size = 64;
 296                output->grph.rgb.independent_64b_blks = true;
 297                break;
 298        default:
 299                ASSERT(false);
 300                break;
 301        }
 302        output->capable = true;
 303        output->const_color_support = true;
 304
 305        return true;
 306}
 307
 308static enum dcn_hubbub_page_table_depth page_table_depth_to_hw(unsigned int page_table_depth)
 309{
 310        enum dcn_hubbub_page_table_depth depth = 0;
 311
 312        switch (page_table_depth) {
 313        case 1:
 314                depth = DCN_PAGE_TABLE_DEPTH_1_LEVEL;
 315                break;
 316        case 2:
 317                depth = DCN_PAGE_TABLE_DEPTH_2_LEVEL;
 318                break;
 319        case 3:
 320                depth = DCN_PAGE_TABLE_DEPTH_3_LEVEL;
 321                break;
 322        case 4:
 323                depth = DCN_PAGE_TABLE_DEPTH_4_LEVEL;
 324                break;
 325        default:
 326                ASSERT(false);
 327                break;
 328        }
 329
 330        return depth;
 331}
 332
 333static enum dcn_hubbub_page_table_block_size page_table_block_size_to_hw(unsigned int page_table_block_size)
 334{
 335        enum dcn_hubbub_page_table_block_size block_size = 0;
 336
 337        switch (page_table_block_size) {
 338        case 4096:
 339                block_size = DCN_PAGE_TABLE_BLOCK_SIZE_4KB;
 340                break;
 341        case 65536:
 342                block_size = DCN_PAGE_TABLE_BLOCK_SIZE_64KB;
 343                break;
 344        case 32768:
 345                block_size = DCN_PAGE_TABLE_BLOCK_SIZE_32KB;
 346                break;
 347        default:
 348                ASSERT(false);
 349                block_size = page_table_block_size;
 350                break;
 351        }
 352
 353        return block_size;
 354}
 355
 356void hubbub2_init_vm_ctx(struct hubbub *hubbub,
 357                struct dcn_hubbub_virt_addr_config *va_config,
 358                int vmid)
 359{
 360        struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
 361        struct dcn_vmid_page_table_config virt_config;
 362
 363        virt_config.page_table_start_addr = va_config->page_table_start_addr >> 12;
 364        virt_config.page_table_end_addr = va_config->page_table_end_addr >> 12;
 365        virt_config.depth = page_table_depth_to_hw(va_config->page_table_depth);
 366        virt_config.block_size = page_table_block_size_to_hw(va_config->page_table_block_size);
 367        virt_config.page_table_base_addr = va_config->page_table_base_addr;
 368
 369        dcn20_vmid_setup(&hubbub1->vmid[vmid], &virt_config);
 370}
 371
 372int hubbub2_init_dchub_sys_ctx(struct hubbub *hubbub,
 373                struct dcn_hubbub_phys_addr_config *pa_config)
 374{
 375        struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
 376        struct dcn_vmid_page_table_config phys_config;
 377
 378        REG_SET(DCN_VM_FB_LOCATION_BASE, 0,
 379                        FB_BASE, pa_config->system_aperture.fb_base >> 24);
 380        REG_SET(DCN_VM_FB_LOCATION_TOP, 0,
 381                        FB_TOP, pa_config->system_aperture.fb_top >> 24);
 382        REG_SET(DCN_VM_FB_OFFSET, 0,
 383                        FB_OFFSET, pa_config->system_aperture.fb_offset >> 24);
 384        REG_SET(DCN_VM_AGP_BOT, 0,
 385                        AGP_BOT, pa_config->system_aperture.agp_bot >> 24);
 386        REG_SET(DCN_VM_AGP_TOP, 0,
 387                        AGP_TOP, pa_config->system_aperture.agp_top >> 24);
 388        REG_SET(DCN_VM_AGP_BASE, 0,
 389                        AGP_BASE, pa_config->system_aperture.agp_base >> 24);
 390
 391        REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0,
 392                        DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, (pa_config->page_table_default_page_addr >> 44) & 0xF);
 393        REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0,
 394                        DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, (pa_config->page_table_default_page_addr >> 12) & 0xFFFFFFFF);
 395
 396        if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) {
 397                phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12;
 398                phys_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr >> 12;
 399                phys_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
 400                phys_config.depth = 0;
 401                phys_config.block_size = 0;
 402                // Init VMID 0 based on PA config
 403                dcn20_vmid_setup(&hubbub1->vmid[0], &phys_config);
 404        }
 405
 406        return NUM_VMID;
 407}
 408
 409void hubbub2_update_dchub(struct hubbub *hubbub,
 410                struct dchub_init_data *dh_data)
 411{
 412        struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
 413
 414        if (REG(DCN_VM_FB_LOCATION_TOP) == 0)
 415                return;
 416
 417        switch (dh_data->fb_mode) {
 418        case FRAME_BUFFER_MODE_ZFB_ONLY:
 419                /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
 420                REG_UPDATE(DCN_VM_FB_LOCATION_TOP,
 421                                FB_TOP, 0);
 422
 423                REG_UPDATE(DCN_VM_FB_LOCATION_BASE,
 424                                FB_BASE, 0xFFFFFF);
 425
 426                /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
 427                REG_UPDATE(DCN_VM_AGP_BASE,
 428                                AGP_BASE, dh_data->zfb_phys_addr_base >> 24);
 429
 430                /*This field defines the bottom range of the AGP aperture and represents the 24*/
 431                /*MSBs, bits [47:24] of the 48 address bits*/
 432                REG_UPDATE(DCN_VM_AGP_BOT,
 433                                AGP_BOT, dh_data->zfb_mc_base_addr >> 24);
 434
 435                /*This field defines the top range of the AGP aperture and represents the 24*/
 436                /*MSBs, bits [47:24] of the 48 address bits*/
 437                REG_UPDATE(DCN_VM_AGP_TOP,
 438                                AGP_TOP, (dh_data->zfb_mc_base_addr +
 439                                                dh_data->zfb_size_in_byte - 1) >> 24);
 440                break;
 441        case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
 442                /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
 443
 444                /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
 445                REG_UPDATE(DCN_VM_AGP_BASE,
 446                                AGP_BASE, dh_data->zfb_phys_addr_base >> 24);
 447
 448                /*This field defines the bottom range of the AGP aperture and represents the 24*/
 449                /*MSBs, bits [47:24] of the 48 address bits*/
 450                REG_UPDATE(DCN_VM_AGP_BOT,
 451                                AGP_BOT, dh_data->zfb_mc_base_addr >> 24);
 452
 453                /*This field defines the top range of the AGP aperture and represents the 24*/
 454                /*MSBs, bits [47:24] of the 48 address bits*/
 455                REG_UPDATE(DCN_VM_AGP_TOP,
 456                                AGP_TOP, (dh_data->zfb_mc_base_addr +
 457                                                dh_data->zfb_size_in_byte - 1) >> 24);
 458                break;
 459        case FRAME_BUFFER_MODE_LOCAL_ONLY:
 460                /*Should not touch FB LOCATION (should be done by VBIOS)*/
 461
 462                /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
 463                REG_UPDATE(DCN_VM_AGP_BASE,
 464                                AGP_BASE, 0);
 465
 466                /*This field defines the bottom range of the AGP aperture and represents the 24*/
 467                /*MSBs, bits [47:24] of the 48 address bits*/
 468                REG_UPDATE(DCN_VM_AGP_BOT,
 469                                AGP_BOT, 0xFFFFFF);
 470
 471                /*This field defines the top range of the AGP aperture and represents the 24*/
 472                /*MSBs, bits [47:24] of the 48 address bits*/
 473                REG_UPDATE(DCN_VM_AGP_TOP,
 474                                AGP_TOP, 0);
 475                break;
 476        default:
 477                break;
 478        }
 479
 480        dh_data->dchub_initialzied = true;
 481        dh_data->dchub_info_valid = false;
 482}
 483
 484void hubbub2_wm_read_state(struct hubbub *hubbub,
 485                struct dcn_hubbub_wm *wm)
 486{
 487        struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
 488
 489        struct dcn_hubbub_wm_set *s;
 490
 491        memset(wm, 0, sizeof(struct dcn_hubbub_wm));
 492
 493        s = &wm->sets[0];
 494        s->wm_set = 0;
 495        s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
 496        if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A))
 497                s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A);
 498        if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {
 499                s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
 500                s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
 501        }
 502        s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
 503
 504        s = &wm->sets[1];
 505        s->wm_set = 1;
 506        s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B);
 507        if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B))
 508                s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B);
 509        if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {
 510                s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);
 511                s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B);
 512        }
 513        s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B);
 514
 515        s = &wm->sets[2];
 516        s->wm_set = 2;
 517        s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C);
 518        if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C))
 519                s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C);
 520        if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {
 521                s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C);
 522                s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C);
 523        }
 524        s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C);
 525
 526        s = &wm->sets[3];
 527        s->wm_set = 3;
 528        s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D);
 529        if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D))
 530                s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D);
 531        if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {
 532                s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D);
 533                s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D);
 534        }
 535        s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
 536}
 537
 538void hubbub2_get_dchub_ref_freq(struct hubbub *hubbub,
 539                unsigned int dccg_ref_freq_inKhz,
 540                unsigned int *dchub_ref_freq_inKhz)
 541{
 542        struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
 543        uint32_t ref_div = 0;
 544        uint32_t ref_en = 0;
 545
 546        REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div,
 547                        DCHUBBUB_GLOBAL_TIMER_ENABLE, &ref_en);
 548
 549        if (ref_en) {
 550                if (ref_div == 2)
 551                        *dchub_ref_freq_inKhz = dccg_ref_freq_inKhz / 2;
 552                else
 553                        *dchub_ref_freq_inKhz = dccg_ref_freq_inKhz;
 554
 555                // DC hub reference frequency must be around 50Mhz, otherwise there may be
 556                // overflow/underflow issues when doing HUBBUB programming
 557                if (*dchub_ref_freq_inKhz < 40000 || *dchub_ref_freq_inKhz > 60000)
 558                        ASSERT_CRITICAL(false);
 559
 560                return;
 561        } else {
 562                *dchub_ref_freq_inKhz = dccg_ref_freq_inKhz;
 563
 564                // HUBBUB global timer must be enabled.
 565                ASSERT_CRITICAL(false);
 566                return;
 567        }
 568}
 569
 570static bool hubbub2_program_watermarks(
 571                struct hubbub *hubbub,
 572                struct dcn_watermark_set *watermarks,
 573                unsigned int refclk_mhz,
 574                bool safe_to_lower)
 575{
 576        struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
 577        bool wm_pending = false;
 578        /*
 579         * Need to clamp to max of the register values (i.e. no wrap)
 580         * for dcn1, all wm registers are 21-bit wide
 581         */
 582        if (hubbub1_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
 583                wm_pending = true;
 584
 585        if (hubbub1_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
 586                wm_pending = true;
 587
 588        /*
 589         * There's a special case when going from p-state support to p-state unsupported
 590         * here we are going to LOWER watermarks to go to dummy p-state only, but this has
 591         * to be done prepare_bandwidth, not optimize
 592         */
 593        if (hubbub1->base.ctx->dc->clk_mgr->clks.prev_p_state_change_support == true &&
 594                hubbub1->base.ctx->dc->clk_mgr->clks.p_state_change_support == false)
 595                safe_to_lower = true;
 596
 597        hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower);
 598
 599        REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0,
 600                        DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
 601        REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 180);
 602
 603        hubbub->funcs->allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
 604        return wm_pending;
 605}
 606
 607static const struct hubbub_funcs hubbub2_funcs = {
 608        .update_dchub = hubbub2_update_dchub,
 609        .init_dchub_sys_ctx = hubbub2_init_dchub_sys_ctx,
 610        .init_vm_ctx = hubbub2_init_vm_ctx,
 611        .dcc_support_swizzle = hubbub2_dcc_support_swizzle,
 612        .dcc_support_pixel_format = hubbub2_dcc_support_pixel_format,
 613        .get_dcc_compression_cap = hubbub2_get_dcc_compression_cap,
 614        .wm_read_state = hubbub2_wm_read_state,
 615        .get_dchub_ref_freq = hubbub2_get_dchub_ref_freq,
 616        .program_watermarks = hubbub2_program_watermarks,
 617        .is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled,
 618        .allow_self_refresh_control = hubbub1_allow_self_refresh_control,
 619};
 620
 621void hubbub2_construct(struct dcn20_hubbub *hubbub,
 622        struct dc_context *ctx,
 623        const struct dcn_hubbub_registers *hubbub_regs,
 624        const struct dcn_hubbub_shift *hubbub_shift,
 625        const struct dcn_hubbub_mask *hubbub_mask)
 626{
 627        hubbub->base.ctx = ctx;
 628
 629        hubbub->base.funcs = &hubbub2_funcs;
 630
 631        hubbub->regs = hubbub_regs;
 632        hubbub->shifts = hubbub_shift;
 633        hubbub->masks = hubbub_mask;
 634
 635        hubbub->debug_test_index_pstate = 0xB;
 636        hubbub->detile_buf_size = 164 * 1024; /* 164KB for DCN2.0 */
 637}
 638