LXR linux/drivers/gpu/drm/amd/display/dc/dcn20/dcn20

   1/*
   2 * Copyright 2012-15 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#include "reg_helper.h"
  27#include "dcn20_optc.h"
  28#include "dc.h"
  29
  30#define REG(reg)\
  31        optc1->tg_regs->reg
  32
  33#define CTX \
  34        optc1->base.ctx
  35
  36#undef FN
  37#define FN(reg_name, field_name) \
  38        optc1->tg_shift->field_name, optc1->tg_mask->field_name
  39
  40/**
  41 * Enable CRTC
  42 * Enable CRTC - call ASIC Control Object to enable Timing generator.
  43 */
  44bool optc2_enable_crtc(struct timing_generator *optc)
  45{
  46        /* TODO FPGA wait for answer
  47         * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE
  48         * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK
  49         */
  50        struct optc *optc1 = DCN10TG_FROM_TG(optc);
  51
  52        /* opp instance for OTG. For DCN1.0, ODM is remoed.
  53         * OPP and OPTC should 1:1 mapping
  54         */
  55        REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
  56                        OPTC_SEG0_SRC_SEL, optc->inst);
  57
  58        /* VTG enable first is for HW workaround */
  59        REG_UPDATE(CONTROL,
  60                        VTG0_ENABLE, 1);
  61
  62        REG_SEQ_START();
  63
  64        /* Enable CRTC */
  65        REG_UPDATE_2(OTG_CONTROL,
  66                        OTG_DISABLE_POINT_CNTL, 3,
  67                        OTG_MASTER_EN, 1);
  68
  69        REG_SEQ_SUBMIT();
  70        REG_SEQ_WAIT_DONE();
  71
  72        return true;
  73}
  74
  75/**
  76 * DRR double buffering control to select buffer point
  77 * for V_TOTAL, H_TOTAL, VTOTAL_MIN, VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers
  78 * Options: anytime, start of frame, dp start of frame (range timing)
  79 */
  80void optc2_set_timing_db_mode(struct timing_generator *optc, bool enable)
  81{
  82        struct optc *optc1 = DCN10TG_FROM_TG(optc);
  83
  84        uint32_t blank_data_double_buffer_enable = enable ? 1 : 0;
  85
  86        REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
  87                OTG_RANGE_TIMING_DBUF_UPDATE_MODE, blank_data_double_buffer_enable);
  88}
  89
  90/**
  91 *For the below, I'm not sure how your GSL parameters are stored in your env,
  92 * so I will assume a gsl_params struct for now
  93 */
  94void optc2_set_gsl(struct timing_generator *optc,
  95                   const struct gsl_params *params)
  96{
  97        struct optc *optc1 = DCN10TG_FROM_TG(optc);
  98
  99/**
 100 * There are (MAX_OPTC+1)/2 gsl groups available for use.
 101 * In each group (assign an OTG to a group by setting OTG_GSLX_EN = 1,
 102 * set one of the OTGs to be the master (OTG_GSL_MASTER_EN = 1) and the rest are slaves.
 103 */
 104        REG_UPDATE_5(OTG_GSL_CONTROL,
 105                OTG_GSL0_EN, params->gsl0_en,
 106                OTG_GSL1_EN, params->gsl1_en,
 107                OTG_GSL2_EN, params->gsl2_en,
 108                OTG_GSL_MASTER_EN, params->gsl_master_en,
 109                OTG_GSL_MASTER_MODE, params->gsl_master_mode);
 110}
 111
 112
 113/* Use the gsl allow flip as the master update lock */
 114void optc2_use_gsl_as_master_update_lock(struct timing_generator *optc,
 115                   const struct gsl_params *params)
 116{
 117        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 118
 119        REG_UPDATE(OTG_GSL_CONTROL,
 120                OTG_MASTER_UPDATE_LOCK_GSL_EN, params->master_update_lock_gsl_en);
 121}
 122
 123/* You can control the GSL timing by limiting GSL to a window (X,Y) */
 124void optc2_set_gsl_window(struct timing_generator *optc,
 125                   const struct gsl_params *params)
 126{
 127        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 128
 129        REG_SET_2(OTG_GSL_WINDOW_X, 0,
 130                OTG_GSL_WINDOW_START_X, params->gsl_window_start_x,
 131                OTG_GSL_WINDOW_END_X, params->gsl_window_end_x);
 132        REG_SET_2(OTG_GSL_WINDOW_Y, 0,
 133                OTG_GSL_WINDOW_START_Y, params->gsl_window_start_y,
 134                OTG_GSL_WINDOW_END_Y, params->gsl_window_end_y);
 135}
 136
 137/**
 138 * Vupdate keepout can be set to a window to block the update lock for that pipe from changing.
 139 * Start offset begins with vstartup and goes for x number of clocks,
 140 * end offset starts from end of vupdate to x number of clocks.
 141 */
 142void optc2_set_vupdate_keepout(struct timing_generator *optc,
 143                   const struct vupdate_keepout_params *params)
 144{
 145        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 146
 147        REG_SET_3(OTG_VUPDATE_KEEPOUT, 0,
 148                MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, params->start_offset,
 149                MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, params->end_offset,
 150                OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, params->enable);
 151}
 152
 153void optc2_set_gsl_source_select(
 154                struct timing_generator *optc,
 155                int group_idx,
 156                uint32_t gsl_ready_signal)
 157{
 158        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 159
 160        switch (group_idx) {
 161        case 1:
 162                REG_UPDATE(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, gsl_ready_signal);
 163                break;
 164        case 2:
 165                REG_UPDATE(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, gsl_ready_signal);
 166                break;
 167        case 3:
 168                REG_UPDATE(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, gsl_ready_signal);
 169                break;
 170        default:
 171                break;
 172        }
 173}
 174
 175/* DSC encoder frame start controls: x = h position, line_num = # of lines from vstartup */
 176void optc2_set_dsc_encoder_frame_start(struct timing_generator *optc,
 177                                        int x_position,
 178                                        int line_num)
 179{
 180        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 181
 182        REG_SET_2(OTG_DSC_START_POSITION, 0,
 183                        OTG_DSC_START_POSITION_X, x_position,
 184                        OTG_DSC_START_POSITION_LINE_NUM, line_num);
 185}
 186
 187/* Set DSC-related configuration.
 188 *   dsc_mode: 0 disables DSC, other values enable DSC in specified format
 189 *   sc_bytes_per_pixel: Bytes per pixel in u3.28 format
 190 *   dsc_slice_width: Slice width in pixels
 191 */
 192void optc2_set_dsc_config(struct timing_generator *optc,
 193                                        enum optc_dsc_mode dsc_mode,
 194                                        uint32_t dsc_bytes_per_pixel,
 195                                        uint32_t dsc_slice_width)
 196{
 197        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 198
 199        REG_UPDATE(OPTC_DATA_FORMAT_CONTROL,
 200                OPTC_DSC_MODE, dsc_mode);
 201
 202        REG_SET(OPTC_BYTES_PER_PIXEL, 0,
 203                OPTC_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel);
 204
 205        REG_UPDATE(OPTC_WIDTH_CONTROL,
 206                OPTC_DSC_SLICE_WIDTH, dsc_slice_width);
 207}
 208
 209/*TEMP: Need to figure out inheritance model here.*/
 210bool optc2_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
 211{
 212        return optc1_is_two_pixels_per_containter(timing);
 213}
 214
 215void optc2_set_odm_bypass(struct timing_generator *optc,
 216                const struct dc_crtc_timing *dc_crtc_timing)
 217{
 218        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 219        uint32_t h_div_2 = 0;
 220
 221        REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
 222                        OPTC_NUM_OF_INPUT_SEGMENT, 0,
 223                        OPTC_SEG0_SRC_SEL, optc->inst,
 224                        OPTC_SEG1_SRC_SEL, 0xf);
 225        REG_WRITE(OTG_H_TIMING_CNTL, 0);
 226
 227        h_div_2 = optc2_is_two_pixels_per_containter(dc_crtc_timing);
 228        REG_UPDATE(OTG_H_TIMING_CNTL,
 229                        OTG_H_TIMING_DIV_BY2, h_div_2);
 230        REG_SET(OPTC_MEMORY_CONFIG, 0,
 231                        OPTC_MEM_SEL, 0);
 232        optc1->opp_count = 1;
 233}
 234
 235void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
 236                struct dc_crtc_timing *timing)
 237{
 238        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 239        int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
 240                        / opp_cnt;
 241        uint32_t memory_mask;
 242
 243        ASSERT(opp_cnt == 2);
 244
 245        /* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic
 246         * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1);
 247         * Program OTG register MASTER_UPDATE_LOCK_DB_X/Y to the position before DP frame start
 248         * REG_SET_2(OTG_GLOBAL_CONTROL1, 0,
 249         *              MASTER_UPDATE_LOCK_DB_X, 160,
 250         *              MASTER_UPDATE_LOCK_DB_Y, 240);
 251         */
 252
 253        /* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192,
 254         * however, for ODM combine we can simplify by always using 4.
 255         * To make sure there's no overlap, each instance "reserves" 2 memories and
 256         * they are uniquely combined here.
 257         */
 258        memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
 259
 260        if (REG(OPTC_MEMORY_CONFIG))
 261                REG_SET(OPTC_MEMORY_CONFIG, 0,
 262                        OPTC_MEM_SEL, memory_mask);
 263
 264        REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
 265                        OPTC_NUM_OF_INPUT_SEGMENT, 1,
 266                        OPTC_SEG0_SRC_SEL, opp_id[0],
 267                        OPTC_SEG1_SRC_SEL, opp_id[1]);
 268
 269        REG_UPDATE(OPTC_WIDTH_CONTROL,
 270                        OPTC_SEGMENT_WIDTH, mpcc_hactive);
 271
 272        REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1);
 273        optc1->opp_count = opp_cnt;
 274}
 275
 276void optc2_get_optc_source(struct timing_generator *optc,
 277                uint32_t *num_of_src_opp,
 278                uint32_t *src_opp_id_0,
 279                uint32_t *src_opp_id_1)
 280{
 281        uint32_t num_of_input_segments;
 282        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 283
 284        REG_GET_3(OPTC_DATA_SOURCE_SELECT,
 285                        OPTC_NUM_OF_INPUT_SEGMENT, &num_of_input_segments,
 286                        OPTC_SEG0_SRC_SEL, src_opp_id_0,
 287                        OPTC_SEG1_SRC_SEL, src_opp_id_1);
 288
 289        if (num_of_input_segments == 1)
 290                *num_of_src_opp = 2;
 291        else
 292                *num_of_src_opp = 1;
 293
 294        /* Work around VBIOS not updating OPTC_NUM_OF_INPUT_SEGMENT */
 295        if (*src_opp_id_1 == 0xf)
 296                *num_of_src_opp = 1;
 297}
 298
 299void optc2_set_dwb_source(struct timing_generator *optc,
 300                uint32_t dwb_pipe_inst)
 301{
 302        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 303
 304        if (dwb_pipe_inst == 0)
 305                REG_UPDATE(DWB_SOURCE_SELECT,
 306                                OPTC_DWB0_SOURCE_SELECT, optc->inst);
 307        else if (dwb_pipe_inst == 1)
 308                REG_UPDATE(DWB_SOURCE_SELECT,
 309                                OPTC_DWB1_SOURCE_SELECT, optc->inst);
 310}
 311
 312void optc2_triplebuffer_lock(struct timing_generator *optc)
 313{
 314        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 315
 316        REG_SET(OTG_GLOBAL_CONTROL0, 0,
 317                OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
 318
 319        REG_SET(OTG_VUPDATE_KEEPOUT, 0,
 320                OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
 321
 322        REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
 323                OTG_MASTER_UPDATE_LOCK, 1);
 324
 325        if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
 326                REG_WAIT(OTG_MASTER_UPDATE_LOCK,
 327                                UPDATE_LOCK_STATUS, 1,
 328                                1, 10);
 329}
 330
 331void optc2_triplebuffer_unlock(struct timing_generator *optc)
 332{
 333        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 334
 335        REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
 336                OTG_MASTER_UPDATE_LOCK, 0);
 337
 338        REG_SET(OTG_VUPDATE_KEEPOUT, 0,
 339                OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 0);
 340
 341}
 342
 343void optc2_lock_doublebuffer_enable(struct timing_generator *optc)
 344{
 345        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 346        uint32_t v_blank_start = 0;
 347        uint32_t h_blank_start = 0;
 348
 349        REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 1);
 350
 351        REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1,
 352                        DIG_UPDATE_LOCATION, 20);
 353
 354        REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start);
 355
 356        REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start);
 357
 358        REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
 359                        MASTER_UPDATE_LOCK_DB_X,
 360                        h_blank_start - 200 - 1,
 361                        MASTER_UPDATE_LOCK_DB_Y,
 362                        v_blank_start - 1);
 363}
 364
 365void optc2_lock_doublebuffer_disable(struct timing_generator *optc)
 366{
 367        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 368
 369        REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
 370                                MASTER_UPDATE_LOCK_DB_X,
 371                                0,
 372                                MASTER_UPDATE_LOCK_DB_Y,
 373                                0);
 374
 375        REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0,
 376                                DIG_UPDATE_LOCATION, 0);
 377
 378        REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 0);
 379}
 380
 381void optc2_setup_manual_trigger(struct timing_generator *optc)
 382{
 383        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 384
 385        REG_SET_8(OTG_TRIGA_CNTL, 0,
 386                        OTG_TRIGA_SOURCE_SELECT, 21,
 387                        OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
 388                        OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
 389                        OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
 390                        OTG_TRIGA_POLARITY_SELECT, 0,
 391                        OTG_TRIGA_FREQUENCY_SELECT, 0,
 392                        OTG_TRIGA_DELAY, 0,
 393                        OTG_TRIGA_CLEAR, 1);
 394}
 395
 396void optc2_program_manual_trigger(struct timing_generator *optc)
 397{
 398        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 399
 400        REG_SET(OTG_TRIGA_MANUAL_TRIG, 0,
 401                        OTG_TRIGA_MANUAL_TRIG, 1);
 402}
 403
 404bool optc2_configure_crc(struct timing_generator *optc,
 405                          const struct crc_params *params)
 406{
 407        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 408
 409        REG_SET_2(OTG_CRC_CNTL2, 0,
 410                        OTG_CRC_DSC_MODE, params->dsc_mode,
 411                        OTG_CRC_DATA_STREAM_COMBINE_MODE, params->odm_mode);
 412
 413        return optc1_configure_crc(optc, params);
 414}
 415
 416static struct timing_generator_funcs dcn20_tg_funcs = {
 417                .validate_timing = optc1_validate_timing,
 418                .program_timing = optc1_program_timing,
 419                .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
 420                .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
 421                .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
 422                .program_global_sync = optc1_program_global_sync,
 423                .enable_crtc = optc2_enable_crtc,
 424                .disable_crtc = optc1_disable_crtc,
 425                /* used by enable_timing_synchronization. Not need for FPGA */
 426                .is_counter_moving = optc1_is_counter_moving,
 427                .get_position = optc1_get_position,
 428                .get_frame_count = optc1_get_vblank_counter,
 429                .get_scanoutpos = optc1_get_crtc_scanoutpos,
 430                .get_otg_active_size = optc1_get_otg_active_size,
 431                .set_early_control = optc1_set_early_control,
 432                /* used by enable_timing_synchronization. Not need for FPGA */
 433                .wait_for_state = optc1_wait_for_state,
 434                .set_blank = optc1_set_blank,
 435                .is_blanked = optc1_is_blanked,
 436                .set_blank_color = optc1_program_blank_color,
 437                .enable_reset_trigger = optc1_enable_reset_trigger,
 438                .enable_crtc_reset = optc1_enable_crtc_reset,
 439                .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
 440                .triplebuffer_lock = optc2_triplebuffer_lock,
 441                .triplebuffer_unlock = optc2_triplebuffer_unlock,
 442                .disable_reset_trigger = optc1_disable_reset_trigger,
 443                .lock = optc1_lock,
 444                .unlock = optc1_unlock,
 445                .lock_doublebuffer_enable = optc2_lock_doublebuffer_enable,
 446                .lock_doublebuffer_disable = optc2_lock_doublebuffer_disable,
 447                .enable_optc_clock = optc1_enable_optc_clock,
 448                .set_drr = optc1_set_drr,
 449                .set_static_screen_control = optc1_set_static_screen_control,
 450                .program_stereo = optc1_program_stereo,
 451                .is_stereo_left_eye = optc1_is_stereo_left_eye,
 452                .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,
 453                .tg_init = optc1_tg_init,
 454                .is_tg_enabled = optc1_is_tg_enabled,
 455                .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
 456                .clear_optc_underflow = optc1_clear_optc_underflow,
 457                .setup_global_swap_lock = NULL,
 458                .get_crc = optc1_get_crc,
 459                .configure_crc = optc2_configure_crc,
 460                .set_dsc_config = optc2_set_dsc_config,
 461                .set_dwb_source = optc2_set_dwb_source,
 462                .set_odm_bypass = optc2_set_odm_bypass,
 463                .set_odm_combine = optc2_set_odm_combine,
 464                .get_optc_source = optc2_get_optc_source,
 465                .set_gsl = optc2_set_gsl,
 466                .set_gsl_source_select = optc2_set_gsl_source_select,
 467                .set_vtg_params = optc1_set_vtg_params,
 468                .program_manual_trigger = optc2_program_manual_trigger,
 469                .setup_manual_trigger = optc2_setup_manual_trigger,
 470                .get_hw_timing = optc1_get_hw_timing,
 471};
 472
 473void dcn20_timing_generator_init(struct optc *optc1)
 474{
 475        optc1->base.funcs = &dcn20_tg_funcs;
 476
 477        optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
 478        optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
 479
 480        optc1->min_h_blank = 32;
 481        optc1->min_v_blank = 3;
 482        optc1->min_v_blank_interlace = 5;
 483        optc1->min_h_sync_width = 4;//  Minimum HSYNC = 8 pixels asked By HW in the first place for no actual reason. Oculus Rift S will not light up with 8 as it's hsyncWidth is 6. Changing it to 4 to fix that issue.
 484        optc1->min_v_sync_width = 1;
 485}
 486
 487