1/* 2 * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21#ifndef _gc_9_1_OFFSET_HEADER 22#define _gc_9_1_OFFSET_HEADER 23 24#define mmSQ_DEBUG_STS_GLOBAL 0x0309 25#define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0 26#define mmSQ_DEBUG_STS_GLOBAL2 0x0310 27#define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0 28#define mmSQ_DEBUG_STS_GLOBAL3 0x0311 29#define mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0 30 31// addressBlock: gc_grbmdec 32// base address: 0x8000 33#define mmGRBM_CNTL 0x0000 34#define mmGRBM_CNTL_BASE_IDX 0 35#define mmGRBM_SKEW_CNTL 0x0001 36#define mmGRBM_SKEW_CNTL_BASE_IDX 0 37#define mmGRBM_STATUS2 0x0002 38#define mmGRBM_STATUS2_BASE_IDX 0 39#define mmGRBM_PWR_CNTL 0x0003 40#define mmGRBM_PWR_CNTL_BASE_IDX 0 41#define mmGRBM_STATUS 0x0004 42#define mmGRBM_STATUS_BASE_IDX 0 43#define mmGRBM_STATUS_SE0 0x0005 44#define mmGRBM_STATUS_SE0_BASE_IDX 0 45#define mmGRBM_STATUS_SE1 0x0006 46#define mmGRBM_STATUS_SE1_BASE_IDX 0 47#define mmGRBM_SOFT_RESET 0x0008 48#define mmGRBM_SOFT_RESET_BASE_IDX 0 49#define mmGRBM_CGTT_CLK_CNTL 0x000b 50#define mmGRBM_CGTT_CLK_CNTL_BASE_IDX 0 51#define mmGRBM_GFX_CLKEN_CNTL 0x000c 52#define mmGRBM_GFX_CLKEN_CNTL_BASE_IDX 0 53#define mmGRBM_WAIT_IDLE_CLOCKS 0x000d 54#define mmGRBM_WAIT_IDLE_CLOCKS_BASE_IDX 0 55#define mmGRBM_STATUS_SE2 0x000e 56#define mmGRBM_STATUS_SE2_BASE_IDX 0 57#define mmGRBM_STATUS_SE3 0x000f 58#define mmGRBM_STATUS_SE3_BASE_IDX 0 59#define mmGRBM_READ_ERROR 0x0016 60#define mmGRBM_READ_ERROR_BASE_IDX 0 61#define mmGRBM_READ_ERROR2 0x0017 62#define mmGRBM_READ_ERROR2_BASE_IDX 0 63#define mmGRBM_INT_CNTL 0x0018 64#define mmGRBM_INT_CNTL_BASE_IDX 0 65#define mmGRBM_TRAP_OP 0x0019 66#define mmGRBM_TRAP_OP_BASE_IDX 0 67#define mmGRBM_TRAP_ADDR 0x001a 68#define mmGRBM_TRAP_ADDR_BASE_IDX 0 69#define mmGRBM_TRAP_ADDR_MSK 0x001b 70#define mmGRBM_TRAP_ADDR_MSK_BASE_IDX 0 71#define mmGRBM_TRAP_WD 0x001c 72#define mmGRBM_TRAP_WD_BASE_IDX 0 73#define mmGRBM_TRAP_WD_MSK 0x001d 74#define mmGRBM_TRAP_WD_MSK_BASE_IDX 0 75#define mmGRBM_DSM_BYPASS 0x001e 76#define mmGRBM_DSM_BYPASS_BASE_IDX 0 77#define mmGRBM_WRITE_ERROR 0x001f 78#define mmGRBM_WRITE_ERROR_BASE_IDX 0 79#define mmGRBM_IOV_ERROR 0x0020 80#define mmGRBM_IOV_ERROR_BASE_IDX 0 81#define mmGRBM_CHIP_REVISION 0x0021 82#define mmGRBM_CHIP_REVISION_BASE_IDX 0 83#define mmGRBM_GFX_CNTL 0x0022 84#define mmGRBM_GFX_CNTL_BASE_IDX 0 85#define mmGRBM_RSMU_CFG 0x0023 86#define mmGRBM_RSMU_CFG_BASE_IDX 0 87#define mmGRBM_IH_CREDIT 0x0024 88#define mmGRBM_IH_CREDIT_BASE_IDX 0 89#define mmGRBM_PWR_CNTL2 0x0025 90#define mmGRBM_PWR_CNTL2_BASE_IDX 0 91#define mmGRBM_UTCL2_INVAL_RANGE_START 0x0026 92#define mmGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX 0 93#define mmGRBM_UTCL2_INVAL_RANGE_END 0x0027 94#define mmGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX 0 95#define mmGRBM_RSMU_READ_ERROR 0x0028 96#define mmGRBM_RSMU_READ_ERROR_BASE_IDX 0 97#define mmGRBM_CHICKEN_BITS 0x0029 98#define mmGRBM_CHICKEN_BITS_BASE_IDX 0 99#define mmGRBM_NOWHERE 0x003f 100#define mmGRBM_NOWHERE_BASE_IDX 0 101#define mmGRBM_SCRATCH_REG0 0x0040 102#define mmGRBM_SCRATCH_REG0_BASE_IDX 0 103#define mmGRBM_SCRATCH_REG1 0x0041 104#define mmGRBM_SCRATCH_REG1_BASE_IDX 0 105#define mmGRBM_SCRATCH_REG2 0x0042 106#define mmGRBM_SCRATCH_REG2_BASE_IDX 0 107#define mmGRBM_SCRATCH_REG3 0x0043 108#define mmGRBM_SCRATCH_REG3_BASE_IDX 0 109#define mmGRBM_SCRATCH_REG4 0x0044 110#define mmGRBM_SCRATCH_REG4_BASE_IDX 0 111#define mmGRBM_SCRATCH_REG5 0x0045 112#define mmGRBM_SCRATCH_REG5_BASE_IDX 0 113#define mmGRBM_SCRATCH_REG6 0x0046 114#define mmGRBM_SCRATCH_REG6_BASE_IDX 0 115#define mmGRBM_SCRATCH_REG7 0x0047 116#define mmGRBM_SCRATCH_REG7_BASE_IDX 0 117 118 119// addressBlock: gc_cpdec 120// base address: 0x8200 121#define mmCP_CPC_STATUS 0x0084 122#define mmCP_CPC_STATUS_BASE_IDX 0 123#define mmCP_CPC_BUSY_STAT 0x0085 124#define mmCP_CPC_BUSY_STAT_BASE_IDX 0 125#define mmCP_CPC_STALLED_STAT1 0x0086 126#define mmCP_CPC_STALLED_STAT1_BASE_IDX 0 127#define mmCP_CPF_STATUS 0x0087 128#define mmCP_CPF_STATUS_BASE_IDX 0 129#define mmCP_CPF_BUSY_STAT 0x0088 130#define mmCP_CPF_BUSY_STAT_BASE_IDX 0 131#define mmCP_CPF_STALLED_STAT1 0x0089 132#define mmCP_CPF_STALLED_STAT1_BASE_IDX 0 133#define mmCP_CPC_GRBM_FREE_COUNT 0x008b 134#define mmCP_CPC_GRBM_FREE_COUNT_BASE_IDX 0 135#define mmCP_MEC_CNTL 0x008d 136#define mmCP_MEC_CNTL_BASE_IDX 0 137#define mmCP_MEC_ME1_HEADER_DUMP 0x008e 138#define mmCP_MEC_ME1_HEADER_DUMP_BASE_IDX 0 139#define mmCP_MEC_ME2_HEADER_DUMP 0x008f 140#define mmCP_MEC_ME2_HEADER_DUMP_BASE_IDX 0 141#define mmCP_CPC_SCRATCH_INDEX 0x0090 142#define mmCP_CPC_SCRATCH_INDEX_BASE_IDX 0 143#define mmCP_CPC_SCRATCH_DATA 0x0091 144#define mmCP_CPC_SCRATCH_DATA_BASE_IDX 0 145#define mmCP_CPF_GRBM_FREE_COUNT 0x0092 146#define mmCP_CPF_GRBM_FREE_COUNT_BASE_IDX 0 147#define mmCP_CPC_HALT_HYST_COUNT 0x00a7 148#define mmCP_CPC_HALT_HYST_COUNT_BASE_IDX 0 149#define mmCP_PRT_LOD_STATS_CNTL0 0x00ad 150#define mmCP_PRT_LOD_STATS_CNTL0_BASE_IDX 0 151#define mmCP_PRT_LOD_STATS_CNTL1 0x00ae 152#define mmCP_PRT_LOD_STATS_CNTL1_BASE_IDX 0 153#define mmCP_PRT_LOD_STATS_CNTL2 0x00af 154#define mmCP_PRT_LOD_STATS_CNTL2_BASE_IDX 0 155#define mmCP_PRT_LOD_STATS_CNTL3 0x00b0 156#define mmCP_PRT_LOD_STATS_CNTL3_BASE_IDX 0 157#define mmCP_CE_COMPARE_COUNT 0x00c0 158#define mmCP_CE_COMPARE_COUNT_BASE_IDX 0 159#define mmCP_CE_DE_COUNT 0x00c1 160#define mmCP_CE_DE_COUNT_BASE_IDX 0 161#define mmCP_DE_CE_COUNT 0x00c2 162#define mmCP_DE_CE_COUNT_BASE_IDX 0 163#define mmCP_DE_LAST_INVAL_COUNT 0x00c3 164#define mmCP_DE_LAST_INVAL_COUNT_BASE_IDX 0 165#define mmCP_DE_DE_COUNT 0x00c4 166#define mmCP_DE_DE_COUNT_BASE_IDX 0 167#define mmCP_STALLED_STAT3 0x019c 168#define mmCP_STALLED_STAT3_BASE_IDX 0 169#define mmCP_STALLED_STAT1 0x019d 170#define mmCP_STALLED_STAT1_BASE_IDX 0 171#define mmCP_STALLED_STAT2 0x019e 172#define mmCP_STALLED_STAT2_BASE_IDX 0 173#define mmCP_BUSY_STAT 0x019f 174#define mmCP_BUSY_STAT_BASE_IDX 0 175#define mmCP_STAT 0x01a0 176#define mmCP_STAT_BASE_IDX 0 177#define mmCP_ME_HEADER_DUMP 0x01a1 178#define mmCP_ME_HEADER_DUMP_BASE_IDX 0 179#define mmCP_PFP_HEADER_DUMP 0x01a2 180#define mmCP_PFP_HEADER_DUMP_BASE_IDX 0 181#define mmCP_GRBM_FREE_COUNT 0x01a3 182#define mmCP_GRBM_FREE_COUNT_BASE_IDX 0 183#define mmCP_CE_HEADER_DUMP 0x01a4 184#define mmCP_CE_HEADER_DUMP_BASE_IDX 0 185#define mmCP_PFP_INSTR_PNTR 0x01a5 186#define mmCP_PFP_INSTR_PNTR_BASE_IDX 0 187#define mmCP_ME_INSTR_PNTR 0x01a6 188#define mmCP_ME_INSTR_PNTR_BASE_IDX 0 189#define mmCP_CE_INSTR_PNTR 0x01a7 190#define mmCP_CE_INSTR_PNTR_BASE_IDX 0 191#define mmCP_MEC1_INSTR_PNTR 0x01a8 192#define mmCP_MEC1_INSTR_PNTR_BASE_IDX 0 193#define mmCP_MEC2_INSTR_PNTR 0x01a9 194#define mmCP_MEC2_INSTR_PNTR_BASE_IDX 0 195#define mmCP_CSF_STAT 0x01b4 196#define mmCP_CSF_STAT_BASE_IDX 0 197#define mmCP_ME_CNTL 0x01b6 198#define mmCP_ME_CNTL_BASE_IDX 0 199#define mmCP_CNTX_STAT 0x01b8 200#define mmCP_CNTX_STAT_BASE_IDX 0 201#define mmCP_ME_PREEMPTION 0x01b9 202#define mmCP_ME_PREEMPTION_BASE_IDX 0 203#define mmCP_ROQ_THRESHOLDS 0x01bc 204#define mmCP_ROQ_THRESHOLDS_BASE_IDX 0 205#define mmCP_MEQ_STQ_THRESHOLD 0x01bd 206#define mmCP_MEQ_STQ_THRESHOLD_BASE_IDX 0 207#define mmCP_RB2_RPTR 0x01be 208#define mmCP_RB2_RPTR_BASE_IDX 0 209#define mmCP_RB1_RPTR 0x01bf 210#define mmCP_RB1_RPTR_BASE_IDX 0 211#define mmCP_RB0_RPTR 0x01c0 212#define mmCP_RB0_RPTR_BASE_IDX 0 213#define mmCP_RB_RPTR 0x01c0 214#define mmCP_RB_RPTR_BASE_IDX 0 215#define mmCP_RB_WPTR_DELAY 0x01c1 216#define mmCP_RB_WPTR_DELAY_BASE_IDX 0 217#define mmCP_RB_WPTR_POLL_CNTL 0x01c2 218#define mmCP_RB_WPTR_POLL_CNTL_BASE_IDX 0 219#define mmCP_ROQ1_THRESHOLDS 0x01d5 220#define mmCP_ROQ1_THRESHOLDS_BASE_IDX 0 221#define mmCP_ROQ2_THRESHOLDS 0x01d6 222#define mmCP_ROQ2_THRESHOLDS_BASE_IDX 0 223#define mmCP_STQ_THRESHOLDS 0x01d7 224#define mmCP_STQ_THRESHOLDS_BASE_IDX 0 225#define mmCP_QUEUE_THRESHOLDS 0x01d8 226#define mmCP_QUEUE_THRESHOLDS_BASE_IDX 0 227#define mmCP_MEQ_THRESHOLDS 0x01d9 228#define mmCP_MEQ_THRESHOLDS_BASE_IDX 0 229#define mmCP_ROQ_AVAIL 0x01da 230#define mmCP_ROQ_AVAIL_BASE_IDX 0 231#define mmCP_STQ_AVAIL 0x01db 232#define mmCP_STQ_AVAIL_BASE_IDX 0 233#define mmCP_ROQ2_AVAIL 0x01dc 234#define mmCP_ROQ2_AVAIL_BASE_IDX 0 235#define mmCP_MEQ_AVAIL 0x01dd 236#define mmCP_MEQ_AVAIL_BASE_IDX 0 237#define mmCP_CMD_INDEX 0x01de 238#define mmCP_CMD_INDEX_BASE_IDX 0 239#define mmCP_CMD_DATA 0x01df 240#define mmCP_CMD_DATA_BASE_IDX 0 241#define mmCP_ROQ_RB_STAT 0x01e0 242#define mmCP_ROQ_RB_STAT_BASE_IDX 0 243#define mmCP_ROQ_IB1_STAT 0x01e1 244#define mmCP_ROQ_IB1_STAT_BASE_IDX 0 245#define mmCP_ROQ_IB2_STAT 0x01e2 246#define mmCP_ROQ_IB2_STAT_BASE_IDX 0 247#define mmCP_STQ_STAT 0x01e3 248#define mmCP_STQ_STAT_BASE_IDX 0 249#define mmCP_STQ_WR_STAT 0x01e4 250#define mmCP_STQ_WR_STAT_BASE_IDX 0 251#define mmCP_MEQ_STAT 0x01e5 252#define mmCP_MEQ_STAT_BASE_IDX 0 253#define mmCP_CEQ1_AVAIL 0x01e6 254#define mmCP_CEQ1_AVAIL_BASE_IDX 0 255#define mmCP_CEQ2_AVAIL 0x01e7 256#define mmCP_CEQ2_AVAIL_BASE_IDX 0 257#define mmCP_CE_ROQ_RB_STAT 0x01e8 258#define mmCP_CE_ROQ_RB_STAT_BASE_IDX 0 259#define mmCP_CE_ROQ_IB1_STAT 0x01e9 260#define mmCP_CE_ROQ_IB1_STAT_BASE_IDX 0 261#define mmCP_CE_ROQ_IB2_STAT 0x01ea 262#define mmCP_CE_ROQ_IB2_STAT_BASE_IDX 0 263 264 265// addressBlock: gc_padec 266// base address: 0x8800 267#define mmVGT_VTX_VECT_EJECT_REG 0x022c 268#define mmVGT_VTX_VECT_EJECT_REG_BASE_IDX 0 269#define mmVGT_DMA_DATA_FIFO_DEPTH 0x022d 270#define mmVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX 0 271#define mmVGT_DMA_REQ_FIFO_DEPTH 0x022e 272#define mmVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX 0 273#define mmVGT_DRAW_INIT_FIFO_DEPTH 0x022f 274#define mmVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX 0 275#define mmVGT_LAST_COPY_STATE 0x0230 276#define mmVGT_LAST_COPY_STATE_BASE_IDX 0 277#define mmVGT_CACHE_INVALIDATION 0x0231 278#define mmVGT_CACHE_INVALIDATION_BASE_IDX 0 279#define mmVGT_STRMOUT_DELAY 0x0233 280#define mmVGT_STRMOUT_DELAY_BASE_IDX 0 281#define mmVGT_FIFO_DEPTHS 0x0234 282#define mmVGT_FIFO_DEPTHS_BASE_IDX 0 283#define mmVGT_GS_VERTEX_REUSE 0x0235 284#define mmVGT_GS_VERTEX_REUSE_BASE_IDX 0 285#define mmVGT_MC_LAT_CNTL 0x0236 286#define mmVGT_MC_LAT_CNTL_BASE_IDX 0 287#define mmIA_CNTL_STATUS 0x0237 288#define mmIA_CNTL_STATUS_BASE_IDX 0 289#define mmVGT_CNTL_STATUS 0x023c 290#define mmVGT_CNTL_STATUS_BASE_IDX 0 291#define mmWD_CNTL_STATUS 0x023f 292#define mmWD_CNTL_STATUS_BASE_IDX 0 293#define mmCC_GC_PRIM_CONFIG 0x0240 294#define mmCC_GC_PRIM_CONFIG_BASE_IDX 0 295#define mmGC_USER_PRIM_CONFIG 0x0241 296#define mmGC_USER_PRIM_CONFIG_BASE_IDX 0 297#define mmWD_QOS 0x0242 298#define mmWD_QOS_BASE_IDX 0 299#define mmWD_UTCL1_CNTL 0x0243 300#define mmWD_UTCL1_CNTL_BASE_IDX 0 301#define mmWD_UTCL1_STATUS 0x0244 302#define mmWD_UTCL1_STATUS_BASE_IDX 0 303#define mmIA_UTCL1_CNTL 0x0246 304#define mmIA_UTCL1_CNTL_BASE_IDX 0 305#define mmIA_UTCL1_STATUS 0x0247 306#define mmIA_UTCL1_STATUS_BASE_IDX 0 307#define mmVGT_SYS_CONFIG 0x0263 308#define mmVGT_SYS_CONFIG_BASE_IDX 0 309#define mmVGT_VS_MAX_WAVE_ID 0x0268 310#define mmVGT_VS_MAX_WAVE_ID_BASE_IDX 0 311#define mmVGT_GS_MAX_WAVE_ID 0x0269 312#define mmVGT_GS_MAX_WAVE_ID_BASE_IDX 0 313#define mmGFX_PIPE_CONTROL 0x026d 314#define mmGFX_PIPE_CONTROL_BASE_IDX 0 315#define mmCC_GC_SHADER_ARRAY_CONFIG 0x026f 316#define mmCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX 0 317#define mmGC_USER_SHADER_ARRAY_CONFIG 0x0270 318#define mmGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX 0 319#define mmVGT_DMA_PRIMITIVE_TYPE 0x0271 320#define mmVGT_DMA_PRIMITIVE_TYPE_BASE_IDX 0 321#define mmVGT_DMA_CONTROL 0x0272 322#define mmVGT_DMA_CONTROL_BASE_IDX 0 323#define mmVGT_DMA_LS_HS_CONFIG 0x0273 324#define mmVGT_DMA_LS_HS_CONFIG_BASE_IDX 0 325#define mmWD_BUF_RESOURCE_1 0x0276 326#define mmWD_BUF_RESOURCE_1_BASE_IDX 0 327#define mmWD_BUF_RESOURCE_2 0x0277 328#define mmWD_BUF_RESOURCE_2_BASE_IDX 0 329#define mmPA_CL_CNTL_STATUS 0x0284 330#define mmPA_CL_CNTL_STATUS_BASE_IDX 0 331#define mmPA_CL_ENHANCE 0x0285 332#define mmPA_CL_ENHANCE_BASE_IDX 0 333#define mmPA_SU_CNTL_STATUS 0x0294 334#define mmPA_SU_CNTL_STATUS_BASE_IDX 0 335#define mmPA_SC_FIFO_DEPTH_CNTL 0x0295 336#define mmPA_SC_FIFO_DEPTH_CNTL_BASE_IDX 0 337#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x02c0 338#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 339#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x02c1 340#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 341#define mmPA_SC_TRAP_SCREEN_HV_LOCK 0x02c2 342#define mmPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 343#define mmPA_SC_FORCE_EOV_MAX_CNTS 0x02c9 344#define mmPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX 0 345#define mmPA_SC_BINNER_EVENT_CNTL_0 0x02cc 346#define mmPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX 0 347#define mmPA_SC_BINNER_EVENT_CNTL_1 0x02cd 348#define mmPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX 0 349#define mmPA_SC_BINNER_EVENT_CNTL_2 0x02ce 350#define mmPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX 0 351#define mmPA_SC_BINNER_EVENT_CNTL_3 0x02cf 352#define mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX 0 353#define mmPA_SC_BINNER_TIMEOUT_COUNTER 0x02d0 354#define mmPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX 0 355#define mmPA_SC_BINNER_PERF_CNTL_0 0x02d1 356#define mmPA_SC_BINNER_PERF_CNTL_0_BASE_IDX 0 357#define mmPA_SC_BINNER_PERF_CNTL_1 0x02d2 358#define mmPA_SC_BINNER_PERF_CNTL_1_BASE_IDX 0 359#define mmPA_SC_BINNER_PERF_CNTL_2 0x02d3 360#define mmPA_SC_BINNER_PERF_CNTL_2_BASE_IDX 0 361#define mmPA_SC_BINNER_PERF_CNTL_3 0x02d4 362#define mmPA_SC_BINNER_PERF_CNTL_3_BASE_IDX 0 363#define mmPA_SC_FIFO_SIZE 0x02f3 364#define mmPA_SC_FIFO_SIZE_BASE_IDX 0 365#define mmPA_SC_IF_FIFO_SIZE 0x02f5 366#define mmPA_SC_IF_FIFO_SIZE_BASE_IDX 0 367#define mmPA_SC_PKR_WAVE_TABLE_CNTL 0x02f8 368#define mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX 0 369#define mmPA_UTCL1_CNTL1 0x02f9 370#define mmPA_UTCL1_CNTL1_BASE_IDX 0 371#define mmPA_UTCL1_CNTL2 0x02fa 372#define mmPA_UTCL1_CNTL2_BASE_IDX 0 373#define mmPA_SIDEBAND_REQUEST_DELAYS 0x02fb 374#define mmPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX 0 375#define mmPA_SC_ENHANCE 0x02fc 376#define mmPA_SC_ENHANCE_BASE_IDX 0 377#define mmPA_SC_ENHANCE_1 0x02fd 378#define mmPA_SC_ENHANCE_1_BASE_IDX 0 379#define mmPA_SC_DSM_CNTL 0x02fe 380#define mmPA_SC_DSM_CNTL_BASE_IDX 0 381#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE 0x02ff 382#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX 0 383 384 385// addressBlock: gc_sqdec 386// base address: 0x8c00 387#define mmSQ_CONFIG 0x0300 388#define mmSQ_CONFIG_BASE_IDX 0 389#define mmSQC_CONFIG 0x0301 390#define mmSQC_CONFIG_BASE_IDX 0 391#define mmLDS_CONFIG 0x0302 392#define mmLDS_CONFIG_BASE_IDX 0 393#define mmSQ_RANDOM_WAVE_PRI 0x0303 394#define mmSQ_RANDOM_WAVE_PRI_BASE_IDX 0 395#define mmSQ_REG_CREDITS 0x0304 396#define mmSQ_REG_CREDITS_BASE_IDX 0 397#define mmSQ_FIFO_SIZES 0x0305 398#define mmSQ_FIFO_SIZES_BASE_IDX 0 399#define mmSQ_DSM_CNTL 0x0306 400#define mmSQ_DSM_CNTL_BASE_IDX 0 401#define mmSQ_DSM_CNTL2 0x0307 402#define mmSQ_DSM_CNTL2_BASE_IDX 0 403#define mmSQ_RUNTIME_CONFIG 0x0308 404#define mmSQ_RUNTIME_CONFIG_BASE_IDX 0 405#define mmSH_MEM_BASES 0x030a 406#define mmSH_MEM_BASES_BASE_IDX 0 407#define mmSH_MEM_CONFIG 0x030d 408#define mmSH_MEM_CONFIG_BASE_IDX 0 409#define mmCC_GC_SHADER_RATE_CONFIG 0x0312 410#define mmCC_GC_SHADER_RATE_CONFIG_BASE_IDX 0 411#define mmGC_USER_SHADER_RATE_CONFIG 0x0313 412#define mmGC_USER_SHADER_RATE_CONFIG_BASE_IDX 0 413#define mmSQ_INTERRUPT_AUTO_MASK 0x0314 414#define mmSQ_INTERRUPT_AUTO_MASK_BASE_IDX 0 415#define mmSQ_INTERRUPT_MSG_CTRL 0x0315 416#define mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX 0 417#define mmSQ_UTCL1_CNTL1 0x0317 418#define mmSQ_UTCL1_CNTL1_BASE_IDX 0 419#define mmSQ_UTCL1_CNTL2 0x0318 420#define mmSQ_UTCL1_CNTL2_BASE_IDX 0 421#define mmSQ_UTCL1_STATUS 0x0319 422#define mmSQ_UTCL1_STATUS_BASE_IDX 0 423#define mmSQ_SHADER_TBA_LO 0x031c 424#define mmSQ_SHADER_TBA_LO_BASE_IDX 0 425#define mmSQ_SHADER_TBA_HI 0x031d 426#define mmSQ_SHADER_TBA_HI_BASE_IDX 0 427#define mmSQ_SHADER_TMA_LO 0x031e 428#define mmSQ_SHADER_TMA_LO_BASE_IDX 0 429#define mmSQ_SHADER_TMA_HI 0x031f 430#define mmSQ_SHADER_TMA_HI_BASE_IDX 0 431#define mmSQC_DSM_CNTL 0x0320 432#define mmSQC_DSM_CNTL_BASE_IDX 0 433#define mmSQC_DSM_CNTLA 0x0321 434#define mmSQC_DSM_CNTLA_BASE_IDX 0 435#define mmSQC_DSM_CNTLB 0x0322 436#define mmSQC_DSM_CNTLB_BASE_IDX 0 437#define mmSQC_DSM_CNTL2 0x0325 438#define mmSQC_DSM_CNTL2_BASE_IDX 0 439#define mmSQC_DSM_CNTL2A 0x0326 440#define mmSQC_DSM_CNTL2A_BASE_IDX 0 441#define mmSQC_DSM_CNTL2B 0x0327 442#define mmSQC_DSM_CNTL2B_BASE_IDX 0 443#define mmSQC_EDC_FUE_CNTL 0x032b 444#define mmSQC_EDC_FUE_CNTL_BASE_IDX 0 445#define mmSQC_EDC_CNT2 0x032c 446#define mmSQC_EDC_CNT2_BASE_IDX 0 447#define mmSQC_EDC_CNT3 0x032d 448#define mmSQC_EDC_CNT3_BASE_IDX 0 449#define mmSQ_REG_TIMESTAMP 0x0374 450#define mmSQ_REG_TIMESTAMP_BASE_IDX 0 451#define mmSQ_CMD_TIMESTAMP 0x0375 452#define mmSQ_CMD_TIMESTAMP_BASE_IDX 0 453#define mmSQ_IND_INDEX 0x0378 454#define mmSQ_IND_INDEX_BASE_IDX 0 455#define mmSQ_IND_DATA 0x0379 456#define mmSQ_IND_DATA_BASE_IDX 0 457#define mmSQ_CMD 0x037b 458#define mmSQ_CMD_BASE_IDX 0 459#define mmSQ_TIME_HI 0x037c 460#define mmSQ_TIME_HI_BASE_IDX 0 461#define mmSQ_TIME_LO 0x037d 462#define mmSQ_TIME_LO_BASE_IDX 0 463#define mmSQ_DS_0 0x037f 464#define mmSQ_DS_0_BASE_IDX 0 465#define mmSQ_DS_1 0x037f 466#define mmSQ_DS_1_BASE_IDX 0 467#define mmSQ_EXP_0 0x037f 468#define mmSQ_EXP_0_BASE_IDX 0 469#define mmSQ_EXP_1 0x037f 470#define mmSQ_EXP_1_BASE_IDX 0 471#define mmSQ_FLAT_0 0x037f 472#define mmSQ_FLAT_0_BASE_IDX 0 473#define mmSQ_FLAT_1 0x037f 474#define mmSQ_FLAT_1_BASE_IDX 0 475#define mmSQ_GLBL_0 0x037f 476#define mmSQ_GLBL_0_BASE_IDX 0 477#define mmSQ_GLBL_1 0x037f 478#define mmSQ_GLBL_1_BASE_IDX 0 479#define mmSQ_INST 0x037f 480#define mmSQ_INST_BASE_IDX 0 481#define mmSQ_MIMG_0 0x037f 482#define mmSQ_MIMG_0_BASE_IDX 0 483#define mmSQ_MIMG_1 0x037f 484#define mmSQ_MIMG_1_BASE_IDX 0 485#define mmSQ_MTBUF_0 0x037f 486#define mmSQ_MTBUF_0_BASE_IDX 0 487#define mmSQ_MTBUF_1 0x037f 488#define mmSQ_MTBUF_1_BASE_IDX 0 489#define mmSQ_MUBUF_0 0x037f 490#define mmSQ_MUBUF_0_BASE_IDX 0 491#define mmSQ_MUBUF_1 0x037f 492#define mmSQ_MUBUF_1_BASE_IDX 0 493#define mmSQ_SCRATCH_0 0x037f 494#define mmSQ_SCRATCH_0_BASE_IDX 0 495#define mmSQ_SCRATCH_1 0x037f 496#define mmSQ_SCRATCH_1_BASE_IDX 0 497#define mmSQ_SMEM_0 0x037f 498#define mmSQ_SMEM_0_BASE_IDX 0 499#define mmSQ_SMEM_1 0x037f 500#define mmSQ_SMEM_1_BASE_IDX 0 501#define mmSQ_SOP1 0x037f 502#define mmSQ_SOP1_BASE_IDX 0 503#define mmSQ_SOP2 0x037f 504#define mmSQ_SOP2_BASE_IDX 0 505#define mmSQ_SOPC 0x037f 506#define mmSQ_SOPC_BASE_IDX 0 507#define mmSQ_SOPK 0x037f 508#define mmSQ_SOPK_BASE_IDX 0 509#define mmSQ_SOPP 0x037f 510#define mmSQ_SOPP_BASE_IDX 0 511#define mmSQ_VINTRP 0x037f 512#define mmSQ_VINTRP_BASE_IDX 0 513#define mmSQ_VOP1 0x037f 514#define mmSQ_VOP1_BASE_IDX 0 515#define mmSQ_VOP2 0x037f 516#define mmSQ_VOP2_BASE_IDX 0 517#define mmSQ_VOP3P_0 0x037f 518#define mmSQ_VOP3P_0_BASE_IDX 0 519#define mmSQ_VOP3P_1 0x037f 520#define mmSQ_VOP3P_1_BASE_IDX 0 521#define mmSQ_VOP3_0 0x037f 522#define mmSQ_VOP3_0_BASE_IDX 0 523#define mmSQ_VOP3_0_SDST_ENC 0x037f 524#define mmSQ_VOP3_0_SDST_ENC_BASE_IDX 0 525#define mmSQ_VOP3_1 0x037f 526#define mmSQ_VOP3_1_BASE_IDX 0 527#define mmSQ_VOPC 0x037f 528#define mmSQ_VOPC_BASE_IDX 0 529#define mmSQ_VOP_DPP 0x037f 530#define mmSQ_VOP_DPP_BASE_IDX 0 531#define mmSQ_VOP_SDWA 0x037f 532#define mmSQ_VOP_SDWA_BASE_IDX 0 533#define mmSQ_VOP_SDWA_SDST_ENC 0x037f 534#define mmSQ_VOP_SDWA_SDST_ENC_BASE_IDX 0 535#define mmSQ_LB_CTR_CTRL 0x0398 536#define mmSQ_LB_CTR_CTRL_BASE_IDX 0 537#define mmSQ_LB_DATA0 0x0399 538#define mmSQ_LB_DATA0_BASE_IDX 0 539#define mmSQ_LB_DATA1 0x039a 540#define mmSQ_LB_DATA1_BASE_IDX 0 541#define mmSQ_LB_DATA2 0x039b 542#define mmSQ_LB_DATA2_BASE_IDX 0 543#define mmSQ_LB_DATA3 0x039c 544#define mmSQ_LB_DATA3_BASE_IDX 0 545#define mmSQ_LB_CTR_SEL 0x039d 546#define mmSQ_LB_CTR_SEL_BASE_IDX 0 547#define mmSQ_LB_CTR0_CU 0x039e 548#define mmSQ_LB_CTR0_CU_BASE_IDX 0 549#define mmSQ_LB_CTR1_CU 0x039f 550#define mmSQ_LB_CTR1_CU_BASE_IDX 0 551#define mmSQ_LB_CTR2_CU 0x03a0 552#define mmSQ_LB_CTR2_CU_BASE_IDX 0 553#define mmSQ_LB_CTR3_CU 0x03a1 554#define mmSQ_LB_CTR3_CU_BASE_IDX 0 555#define mmSQC_EDC_CNT 0x03a2 556#define mmSQC_EDC_CNT_BASE_IDX 0 557#define mmSQ_EDC_SEC_CNT 0x03a3 558#define mmSQ_EDC_SEC_CNT_BASE_IDX 0 559#define mmSQ_EDC_DED_CNT 0x03a4 560#define mmSQ_EDC_DED_CNT_BASE_IDX 0 561#define mmSQ_EDC_INFO 0x03a5 562#define mmSQ_EDC_INFO_BASE_IDX 0 563#define mmSQ_EDC_CNT 0x03a6 564#define mmSQ_EDC_CNT_BASE_IDX 0 565#define mmSQ_EDC_FUE_CNTL 0x03a7 566#define mmSQ_EDC_FUE_CNTL_BASE_IDX 0 567#define mmSQ_THREAD_TRACE_WORD_CMN 0x03b0 568#define mmSQ_THREAD_TRACE_WORD_CMN_BASE_IDX 0 569#define mmSQ_THREAD_TRACE_WORD_EVENT 0x03b0 570#define mmSQ_THREAD_TRACE_WORD_EVENT_BASE_IDX 0 571#define mmSQ_THREAD_TRACE_WORD_INST 0x03b0 572#define mmSQ_THREAD_TRACE_WORD_INST_BASE_IDX 0 573#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x03b0 574#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_BASE_IDX 0 575#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x03b0 576#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_BASE_IDX 0 577#define mmSQ_THREAD_TRACE_WORD_ISSUE 0x03b0 578#define mmSQ_THREAD_TRACE_WORD_ISSUE_BASE_IDX 0 579#define mmSQ_THREAD_TRACE_WORD_MISC 0x03b0 580#define mmSQ_THREAD_TRACE_WORD_MISC_BASE_IDX 0 581#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x03b0 582#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2_BASE_IDX 0 583#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x03b0 584#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2_BASE_IDX 0 585#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x03b0 586#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2_BASE_IDX 0 587#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x03b0 588#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_BASE_IDX 0 589#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x03b0 590#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_BASE_IDX 0 591#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x03b0 592#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_BASE_IDX 0 593#define mmSQ_THREAD_TRACE_WORD_WAVE 0x03b0 594#define mmSQ_THREAD_TRACE_WORD_WAVE_BASE_IDX 0 595#define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x03b0 596#define mmSQ_THREAD_TRACE_WORD_WAVE_START_BASE_IDX 0 597#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x03b1 598#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_BASE_IDX 0 599#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x03b1 600#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_BASE_IDX 0 601#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x03b1 602#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2_BASE_IDX 0 603#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x03b1 604#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_BASE_IDX 0 605#define mmSQ_WREXEC_EXEC_HI 0x03b1 606#define mmSQ_WREXEC_EXEC_HI_BASE_IDX 0 607#define mmSQ_WREXEC_EXEC_LO 0x03b1 608#define mmSQ_WREXEC_EXEC_LO_BASE_IDX 0 609#define mmSQ_BUF_RSRC_WORD0 0x03c0 610#define mmSQ_BUF_RSRC_WORD0_BASE_IDX 0 611#define mmSQ_BUF_RSRC_WORD1 0x03c1 612#define mmSQ_BUF_RSRC_WORD1_BASE_IDX 0 613#define mmSQ_BUF_RSRC_WORD2 0x03c2 614#define mmSQ_BUF_RSRC_WORD2_BASE_IDX 0 615#define mmSQ_BUF_RSRC_WORD3 0x03c3 616#define mmSQ_BUF_RSRC_WORD3_BASE_IDX 0 617#define mmSQ_IMG_RSRC_WORD0 0x03c4 618#define mmSQ_IMG_RSRC_WORD0_BASE_IDX 0 619#define mmSQ_IMG_RSRC_WORD1 0x03c5 620#define mmSQ_IMG_RSRC_WORD1_BASE_IDX 0 621#define mmSQ_IMG_RSRC_WORD2 0x03c6 622#define mmSQ_IMG_RSRC_WORD2_BASE_IDX 0 623#define mmSQ_IMG_RSRC_WORD3 0x03c7 624#define mmSQ_IMG_RSRC_WORD3_BASE_IDX 0 625#define mmSQ_IMG_RSRC_WORD4 0x03c8 626#define mmSQ_IMG_RSRC_WORD4_BASE_IDX 0 627#define mmSQ_IMG_RSRC_WORD5 0x03c9 628#define mmSQ_IMG_RSRC_WORD5_BASE_IDX 0 629#define mmSQ_IMG_RSRC_WORD6 0x03ca 630#define mmSQ_IMG_RSRC_WORD6_BASE_IDX 0 631#define mmSQ_IMG_RSRC_WORD7 0x03cb 632#define mmSQ_IMG_RSRC_WORD7_BASE_IDX 0 633#define mmSQ_IMG_SAMP_WORD0 0x03cc 634#define mmSQ_IMG_SAMP_WORD0_BASE_IDX 0 635#define mmSQ_IMG_SAMP_WORD1 0x03cd 636#define mmSQ_IMG_SAMP_WORD1_BASE_IDX 0 637#define mmSQ_IMG_SAMP_WORD2 0x03ce 638#define mmSQ_IMG_SAMP_WORD2_BASE_IDX 0 639#define mmSQ_IMG_SAMP_WORD3 0x03cf 640#define mmSQ_IMG_SAMP_WORD3_BASE_IDX 0 641#define mmSQ_FLAT_SCRATCH_WORD0 0x03d0 642#define mmSQ_FLAT_SCRATCH_WORD0_BASE_IDX 0 643#define mmSQ_FLAT_SCRATCH_WORD1 0x03d1 644#define mmSQ_FLAT_SCRATCH_WORD1_BASE_IDX 0 645#define mmSQ_M0_GPR_IDX_WORD 0x03d2 646#define mmSQ_M0_GPR_IDX_WORD_BASE_IDX 0 647#define mmSQC_ICACHE_UTCL1_CNTL1 0x03d3 648#define mmSQC_ICACHE_UTCL1_CNTL1_BASE_IDX 0 649#define mmSQC_ICACHE_UTCL1_CNTL2 0x03d4 650#define mmSQC_ICACHE_UTCL1_CNTL2_BASE_IDX 0 651#define mmSQC_DCACHE_UTCL1_CNTL1 0x03d5 652#define mmSQC_DCACHE_UTCL1_CNTL1_BASE_IDX 0 653#define mmSQC_DCACHE_UTCL1_CNTL2 0x03d6 654#define mmSQC_DCACHE_UTCL1_CNTL2_BASE_IDX 0 655#define mmSQC_ICACHE_UTCL1_STATUS 0x03d7 656#define mmSQC_ICACHE_UTCL1_STATUS_BASE_IDX 0 657#define mmSQC_DCACHE_UTCL1_STATUS 0x03d8 658#define mmSQC_DCACHE_UTCL1_STATUS_BASE_IDX 0 659 660 661// addressBlock: gc_shsdec 662// base address: 0x9000 663#define mmSX_DEBUG_1 0x0419 664#define mmSX_DEBUG_1_BASE_IDX 0 665#define mmSPI_PS_MAX_WAVE_ID 0x043a 666#define mmSPI_PS_MAX_WAVE_ID_BASE_IDX 0 667#define mmSPI_START_PHASE 0x043b 668#define mmSPI_START_PHASE_BASE_IDX 0 669#define mmSPI_GFX_CNTL 0x043c 670#define mmSPI_GFX_CNTL_BASE_IDX 0 671#define mmSPI_DSM_CNTL 0x0443 672#define mmSPI_DSM_CNTL_BASE_IDX 0 673#define mmSPI_DSM_CNTL2 0x0444 674#define mmSPI_DSM_CNTL2_BASE_IDX 0 675#define mmSPI_EDC_CNT 0x0445 676#define mmSPI_EDC_CNT_BASE_IDX 0 677#define mmSPI_CONFIG_PS_CU_EN 0x0452 678#define mmSPI_CONFIG_PS_CU_EN_BASE_IDX 0 679#define mmSPI_WF_LIFETIME_CNTL 0x04aa 680#define mmSPI_WF_LIFETIME_CNTL_BASE_IDX 0 681#define mmSPI_WF_LIFETIME_LIMIT_0 0x04ab 682#define mmSPI_WF_LIFETIME_LIMIT_0_BASE_IDX 0 683#define mmSPI_WF_LIFETIME_LIMIT_1 0x04ac 684#define mmSPI_WF_LIFETIME_LIMIT_1_BASE_IDX 0 685#define mmSPI_WF_LIFETIME_LIMIT_2 0x04ad 686#define mmSPI_WF_LIFETIME_LIMIT_2_BASE_IDX 0 687#define mmSPI_WF_LIFETIME_LIMIT_3 0x04ae 688#define mmSPI_WF_LIFETIME_LIMIT_3_BASE_IDX 0 689#define mmSPI_WF_LIFETIME_LIMIT_4 0x04af 690#define mmSPI_WF_LIFETIME_LIMIT_4_BASE_IDX 0 691#define mmSPI_WF_LIFETIME_LIMIT_5 0x04b0 692#define mmSPI_WF_LIFETIME_LIMIT_5_BASE_IDX 0 693#define mmSPI_WF_LIFETIME_LIMIT_6 0x04b1 694#define mmSPI_WF_LIFETIME_LIMIT_6_BASE_IDX 0 695#define mmSPI_WF_LIFETIME_LIMIT_7 0x04b2 696#define mmSPI_WF_LIFETIME_LIMIT_7_BASE_IDX 0 697#define mmSPI_WF_LIFETIME_LIMIT_8 0x04b3 698#define mmSPI_WF_LIFETIME_LIMIT_8_BASE_IDX 0 699#define mmSPI_WF_LIFETIME_LIMIT_9 0x04b4 700#define mmSPI_WF_LIFETIME_LIMIT_9_BASE_IDX 0 701#define mmSPI_WF_LIFETIME_STATUS_0 0x04b5 702#define mmSPI_WF_LIFETIME_STATUS_0_BASE_IDX 0 703#define mmSPI_WF_LIFETIME_STATUS_1 0x04b6 704#define mmSPI_WF_LIFETIME_STATUS_1_BASE_IDX 0 705#define mmSPI_WF_LIFETIME_STATUS_2 0x04b7 706#define mmSPI_WF_LIFETIME_STATUS_2_BASE_IDX 0 707#define mmSPI_WF_LIFETIME_STATUS_3 0x04b8 708#define mmSPI_WF_LIFETIME_STATUS_3_BASE_IDX 0 709#define mmSPI_WF_LIFETIME_STATUS_4 0x04b9 710#define mmSPI_WF_LIFETIME_STATUS_4_BASE_IDX 0 711#define mmSPI_WF_LIFETIME_STATUS_5 0x04ba 712#define mmSPI_WF_LIFETIME_STATUS_5_BASE_IDX 0 713#define mmSPI_WF_LIFETIME_STATUS_6 0x04bb 714#define mmSPI_WF_LIFETIME_STATUS_6_BASE_IDX 0 715#define mmSPI_WF_LIFETIME_STATUS_7 0x04bc 716#define mmSPI_WF_LIFETIME_STATUS_7_BASE_IDX 0 717#define mmSPI_WF_LIFETIME_STATUS_8 0x04bd 718#define mmSPI_WF_LIFETIME_STATUS_8_BASE_IDX 0 719#define mmSPI_WF_LIFETIME_STATUS_9 0x04be 720#define mmSPI_WF_LIFETIME_STATUS_9_BASE_IDX 0 721#define mmSPI_WF_LIFETIME_STATUS_10 0x04bf 722#define mmSPI_WF_LIFETIME_STATUS_10_BASE_IDX 0 723#define mmSPI_WF_LIFETIME_STATUS_11 0x04c0 724#define mmSPI_WF_LIFETIME_STATUS_11_BASE_IDX 0 725#define mmSPI_WF_LIFETIME_STATUS_12 0x04c1 726#define mmSPI_WF_LIFETIME_STATUS_12_BASE_IDX 0 727#define mmSPI_WF_LIFETIME_STATUS_13 0x04c2 728#define mmSPI_WF_LIFETIME_STATUS_13_BASE_IDX 0 729#define mmSPI_WF_LIFETIME_STATUS_14 0x04c3 730#define mmSPI_WF_LIFETIME_STATUS_14_BASE_IDX 0 731#define mmSPI_WF_LIFETIME_STATUS_15 0x04c4 732#define mmSPI_WF_LIFETIME_STATUS_15_BASE_IDX 0 733#define mmSPI_WF_LIFETIME_STATUS_16 0x04c5 734#define mmSPI_WF_LIFETIME_STATUS_16_BASE_IDX 0 735#define mmSPI_WF_LIFETIME_STATUS_17 0x04c6 736#define mmSPI_WF_LIFETIME_STATUS_17_BASE_IDX 0 737#define mmSPI_WF_LIFETIME_STATUS_18 0x04c7 738#define mmSPI_WF_LIFETIME_STATUS_18_BASE_IDX 0 739#define mmSPI_WF_LIFETIME_STATUS_19 0x04c8 740#define mmSPI_WF_LIFETIME_STATUS_19_BASE_IDX 0 741#define mmSPI_WF_LIFETIME_STATUS_20 0x04c9 742#define mmSPI_WF_LIFETIME_STATUS_20_BASE_IDX 0 743#define mmSPI_LB_CTR_CTRL 0x04d4 744#define mmSPI_LB_CTR_CTRL_BASE_IDX 0 745#define mmSPI_LB_CU_MASK 0x04d5 746#define mmSPI_LB_CU_MASK_BASE_IDX 0 747#define mmSPI_LB_DATA_REG 0x04d6 748#define mmSPI_LB_DATA_REG_BASE_IDX 0 749#define mmSPI_PG_ENABLE_STATIC_CU_MASK 0x04d7 750#define mmSPI_PG_ENABLE_STATIC_CU_MASK_BASE_IDX 0 751#define mmSPI_GDS_CREDITS 0x04d8 752#define mmSPI_GDS_CREDITS_BASE_IDX 0 753#define mmSPI_SX_EXPORT_BUFFER_SIZES 0x04d9 754#define mmSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX 0 755#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x04da 756#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX 0 757#define mmSPI_CSQ_WF_ACTIVE_STATUS 0x04db 758#define mmSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX 0 759#define mmSPI_CSQ_WF_ACTIVE_COUNT_0 0x04dc 760#define mmSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX 0 761#define mmSPI_CSQ_WF_ACTIVE_COUNT_1 0x04dd 762#define mmSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX 0 763#define mmSPI_CSQ_WF_ACTIVE_COUNT_2 0x04de 764#define mmSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX 0 765#define mmSPI_CSQ_WF_ACTIVE_COUNT_3 0x04df 766#define mmSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX 0 767#define mmSPI_CSQ_WF_ACTIVE_COUNT_4 0x04e0 768#define mmSPI_CSQ_WF_ACTIVE_COUNT_4_BASE_IDX 0 769#define mmSPI_CSQ_WF_ACTIVE_COUNT_5 0x04e1 770#define mmSPI_CSQ_WF_ACTIVE_COUNT_5_BASE_IDX 0 771#define mmSPI_CSQ_WF_ACTIVE_COUNT_6 0x04e2 772#define mmSPI_CSQ_WF_ACTIVE_COUNT_6_BASE_IDX 0 773#define mmSPI_CSQ_WF_ACTIVE_COUNT_7 0x04e3 774#define mmSPI_CSQ_WF_ACTIVE_COUNT_7_BASE_IDX 0 775#define mmSPI_LB_DATA_WAVES 0x04e4 776#define mmSPI_LB_DATA_WAVES_BASE_IDX 0 777#define mmSPI_LB_DATA_PERCU_WAVE_HSGS 0x04e5 778#define mmSPI_LB_DATA_PERCU_WAVE_HSGS_BASE_IDX 0 779#define mmSPI_LB_DATA_PERCU_WAVE_VSPS 0x04e6 780#define mmSPI_LB_DATA_PERCU_WAVE_VSPS_BASE_IDX 0 781#define mmSPI_LB_DATA_PERCU_WAVE_CS 0x04e7 782#define mmSPI_LB_DATA_PERCU_WAVE_CS_BASE_IDX 0 783#define mmSPI_P0_TRAP_SCREEN_PSBA_LO 0x04ec 784#define mmSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 785#define mmSPI_P0_TRAP_SCREEN_PSBA_HI 0x04ed 786#define mmSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 787#define mmSPI_P0_TRAP_SCREEN_PSMA_LO 0x04ee 788#define mmSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 789#define mmSPI_P0_TRAP_SCREEN_PSMA_HI 0x04ef 790#define mmSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 791#define mmSPI_P0_TRAP_SCREEN_GPR_MIN 0x04f0 792#define mmSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 793#define mmSPI_P1_TRAP_SCREEN_PSBA_LO 0x04f1 794#define mmSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 795#define mmSPI_P1_TRAP_SCREEN_PSBA_HI 0x04f2 796#define mmSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 797#define mmSPI_P1_TRAP_SCREEN_PSMA_LO 0x04f3 798#define mmSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 799#define mmSPI_P1_TRAP_SCREEN_PSMA_HI 0x04f4 800#define mmSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 801#define mmSPI_P1_TRAP_SCREEN_GPR_MIN 0x04f5 802#define mmSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 803 804 805// addressBlock: gc_tpdec 806// base address: 0x9400 807#define mmTD_CNTL 0x0525 808#define mmTD_CNTL_BASE_IDX 0 809#define mmTD_STATUS 0x0526 810#define mmTD_STATUS_BASE_IDX 0 811#define mmTD_DSM_CNTL 0x052f 812#define mmTD_DSM_CNTL_BASE_IDX 0 813#define mmTD_DSM_CNTL2 0x0530 814#define mmTD_DSM_CNTL2_BASE_IDX 0 815#define mmTD_SCRATCH 0x0533 816#define mmTD_SCRATCH_BASE_IDX 0 817#define mmTA_CNTL 0x0541 818#define mmTA_CNTL_BASE_IDX 0 819#define mmTA_CNTL_AUX 0x0542 820#define mmTA_CNTL_AUX_BASE_IDX 0 821#define mmTA_RESERVED_010C 0x0543 822#define mmTA_RESERVED_010C_BASE_IDX 0 823#define mmTA_STATUS 0x0548 824#define mmTA_STATUS_BASE_IDX 0 825#define mmTA_SCRATCH 0x0564 826#define mmTA_SCRATCH_BASE_IDX 0 827 828 829// addressBlock: gc_gdsdec 830// base address: 0x9700 831#define mmGDS_CONFIG 0x05c0 832#define mmGDS_CONFIG_BASE_IDX 0 833#define mmGDS_CNTL_STATUS 0x05c1 834#define mmGDS_CNTL_STATUS_BASE_IDX 0 835#define mmGDS_ENHANCE2 0x05c2 836#define mmGDS_ENHANCE2_BASE_IDX 0 837#define mmGDS_PROTECTION_FAULT 0x05c3 838#define mmGDS_PROTECTION_FAULT_BASE_IDX 0 839#define mmGDS_VM_PROTECTION_FAULT 0x05c4 840#define mmGDS_VM_PROTECTION_FAULT_BASE_IDX 0 841#define mmGDS_EDC_CNT 0x05c5 842#define mmGDS_EDC_CNT_BASE_IDX 0 843#define mmGDS_EDC_GRBM_CNT 0x05c6 844#define mmGDS_EDC_GRBM_CNT_BASE_IDX 0 845#define mmGDS_EDC_OA_DED 0x05c7 846#define mmGDS_EDC_OA_DED_BASE_IDX 0 847#define mmGDS_DSM_CNTL 0x05ca 848#define mmGDS_DSM_CNTL_BASE_IDX 0 849#define mmGDS_EDC_OA_PHY_CNT 0x05cb 850#define mmGDS_EDC_OA_PHY_CNT_BASE_IDX 0 851#define mmGDS_EDC_OA_PIPE_CNT 0x05cc 852#define mmGDS_EDC_OA_PIPE_CNT_BASE_IDX 0 853#define mmGDS_DSM_CNTL2 0x05cd 854#define mmGDS_DSM_CNTL2_BASE_IDX 0 855#define mmGDS_WD_GDS_CSB 0x05ce 856#define mmGDS_WD_GDS_CSB_BASE_IDX 0 857 858 859// addressBlock: gc_rbdec 860// base address: 0x9800 861#define mmDB_DEBUG 0x060c 862#define mmDB_DEBUG_BASE_IDX 0 863#define mmDB_DEBUG2 0x060d 864#define mmDB_DEBUG2_BASE_IDX 0 865#define mmDB_DEBUG3 0x060e 866#define mmDB_DEBUG3_BASE_IDX 0 867#define mmDB_DEBUG4 0x060f 868#define mmDB_DEBUG4_BASE_IDX 0 869#define mmDB_CREDIT_LIMIT 0x0614 870#define mmDB_CREDIT_LIMIT_BASE_IDX 0 871#define mmDB_WATERMARKS 0x0615 872#define mmDB_WATERMARKS_BASE_IDX 0 873#define mmDB_SUBTILE_CONTROL 0x0616 874#define mmDB_SUBTILE_CONTROL_BASE_IDX 0 875#define mmDB_FREE_CACHELINES 0x0617 876#define mmDB_FREE_CACHELINES_BASE_IDX 0 877#define mmDB_FIFO_DEPTH1 0x0618 878#define mmDB_FIFO_DEPTH1_BASE_IDX 0 879#define mmDB_FIFO_DEPTH2 0x0619 880#define mmDB_FIFO_DEPTH2_BASE_IDX 0 881#define mmDB_EXCEPTION_CONTROL 0x061a 882#define mmDB_EXCEPTION_CONTROL_BASE_IDX 0 883#define mmDB_RING_CONTROL 0x061b 884#define mmDB_RING_CONTROL_BASE_IDX 0 885#define mmDB_MEM_ARB_WATERMARKS 0x061c 886#define mmDB_MEM_ARB_WATERMARKS_BASE_IDX 0 887#define mmDB_RMI_CACHE_POLICY 0x061e 888#define mmDB_RMI_CACHE_POLICY_BASE_IDX 0 889#define mmDB_DFSM_CONFIG 0x0630 890#define mmDB_DFSM_CONFIG_BASE_IDX 0 891#define mmDB_DFSM_WATERMARK 0x0631 892#define mmDB_DFSM_WATERMARK_BASE_IDX 0 893#define mmDB_DFSM_TILES_IN_FLIGHT 0x0632 894#define mmDB_DFSM_TILES_IN_FLIGHT_BASE_IDX 0 895#define mmDB_DFSM_PRIMS_IN_FLIGHT 0x0633 896#define mmDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX 0 897#define mmDB_DFSM_WATCHDOG 0x0634 898#define mmDB_DFSM_WATCHDOG_BASE_IDX 0 899#define mmDB_DFSM_FLUSH_ENABLE 0x0635 900#define mmDB_DFSM_FLUSH_ENABLE_BASE_IDX 0 901#define mmDB_DFSM_FLUSH_AUX_EVENT 0x0636 902#define mmDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX 0 903#define mmCC_RB_REDUNDANCY 0x063c 904#define mmCC_RB_REDUNDANCY_BASE_IDX 0 905#define mmCC_RB_BACKEND_DISABLE 0x063d 906#define mmCC_RB_BACKEND_DISABLE_BASE_IDX 0 907#define mmGB_ADDR_CONFIG 0x063e 908#define mmGB_ADDR_CONFIG_BASE_IDX 0 909#define mmGB_BACKEND_MAP 0x063f 910#define mmGB_BACKEND_MAP_BASE_IDX 0 911#define mmGB_GPU_ID 0x0640 912#define mmGB_GPU_ID_BASE_IDX 0 913#define mmCC_RB_DAISY_CHAIN 0x0641 914#define mmCC_RB_DAISY_CHAIN_BASE_IDX 0 915#define mmGB_ADDR_CONFIG_READ 0x0642 916#define mmGB_ADDR_CONFIG_READ_BASE_IDX 0 917#define mmGB_TILE_MODE0 0x0644 918#define mmGB_TILE_MODE0_BASE_IDX 0 919#define mmGB_TILE_MODE1 0x0645 920#define mmGB_TILE_MODE1_BASE_IDX 0 921#define mmGB_TILE_MODE2 0x0646 922#define mmGB_TILE_MODE2_BASE_IDX 0 923#define mmGB_TILE_MODE3 0x0647 924#define mmGB_TILE_MODE3_BASE_IDX 0 925#define mmGB_TILE_MODE4 0x0648 926#define mmGB_TILE_MODE4_BASE_IDX 0 927#define mmGB_TILE_MODE5 0x0649 928#define mmGB_TILE_MODE5_BASE_IDX 0 929#define mmGB_TILE_MODE6 0x064a 930#define mmGB_TILE_MODE6_BASE_IDX 0 931#define mmGB_TILE_MODE7 0x064b 932#define mmGB_TILE_MODE7_BASE_IDX 0 933#define mmGB_TILE_MODE8 0x064c 934#define mmGB_TILE_MODE8_BASE_IDX 0 935#define mmGB_TILE_MODE9 0x064d 936#define mmGB_TILE_MODE9_BASE_IDX 0 937#define mmGB_TILE_MODE10 0x064e 938#define mmGB_TILE_MODE10_BASE_IDX 0 939#define mmGB_TILE_MODE11 0x064f 940#define mmGB_TILE_MODE11_BASE_IDX 0 941#define mmGB_TILE_MODE12 0x0650 942#define mmGB_TILE_MODE12_BASE_IDX 0 943#define mmGB_TILE_MODE13 0x0651 944#define mmGB_TILE_MODE13_BASE_IDX 0 945#define mmGB_TILE_MODE14 0x0652 946#define mmGB_TILE_MODE14_BASE_IDX 0 947#define mmGB_TILE_MODE15 0x0653 948#define mmGB_TILE_MODE15_BASE_IDX 0 949#define mmGB_TILE_MODE16 0x0654 950#define mmGB_TILE_MODE16_BASE_IDX 0 951#define mmGB_TILE_MODE17 0x0655 952#define mmGB_TILE_MODE17_BASE_IDX 0 953#define mmGB_TILE_MODE18 0x0656 954#define mmGB_TILE_MODE18_BASE_IDX 0 955#define mmGB_TILE_MODE19 0x0657 956#define mmGB_TILE_MODE19_BASE_IDX 0 957#define mmGB_TILE_MODE20 0x0658 958#define mmGB_TILE_MODE20_BASE_IDX 0 959#define mmGB_TILE_MODE21 0x0659 960#define mmGB_TILE_MODE21_BASE_IDX 0 961#define mmGB_TILE_MODE22 0x065a 962#define mmGB_TILE_MODE22_BASE_IDX 0 963#define mmGB_TILE_MODE23 0x065b 964#define mmGB_TILE_MODE23_BASE_IDX 0 965#define mmGB_TILE_MODE24 0x065c 966#define mmGB_TILE_MODE24_BASE_IDX 0 967#define mmGB_TILE_MODE25 0x065d 968#define mmGB_TILE_MODE25_BASE_IDX 0 969#define mmGB_TILE_MODE26 0x065e 970#define mmGB_TILE_MODE26_BASE_IDX 0 971#define mmGB_TILE_MODE27 0x065f 972#define mmGB_TILE_MODE27_BASE_IDX 0 973#define mmGB_TILE_MODE28 0x0660 974#define mmGB_TILE_MODE28_BASE_IDX 0 975#define mmGB_TILE_MODE29 0x0661 976#define mmGB_TILE_MODE29_BASE_IDX 0 977#define mmGB_TILE_MODE30 0x0662 978#define mmGB_TILE_MODE30_BASE_IDX 0 979#define mmGB_TILE_MODE31 0x0663 980#define mmGB_TILE_MODE31_BASE_IDX 0 981#define mmGB_MACROTILE_MODE0 0x0664 982#define mmGB_MACROTILE_MODE0_BASE_IDX 0 983#define mmGB_MACROTILE_MODE1 0x0665 984#define mmGB_MACROTILE_MODE1_BASE_IDX 0 985#define mmGB_MACROTILE_MODE2 0x0666 986#define mmGB_MACROTILE_MODE2_BASE_IDX 0 987#define mmGB_MACROTILE_MODE3 0x0667 988#define mmGB_MACROTILE_MODE3_BASE_IDX 0 989#define mmGB_MACROTILE_MODE4 0x0668 990#define mmGB_MACROTILE_MODE4_BASE_IDX 0 991#define mmGB_MACROTILE_MODE5 0x0669 992#define mmGB_MACROTILE_MODE5_BASE_IDX 0 993#define mmGB_MACROTILE_MODE6 0x066a 994#define mmGB_MACROTILE_MODE6_BASE_IDX 0 995#define mmGB_MACROTILE_MODE7 0x066b 996#define mmGB_MACROTILE_MODE7_BASE_IDX 0 997#define mmGB_MACROTILE_MODE8 0x066c 998#define mmGB_MACROTILE_MODE8_BASE_IDX 0 999#define mmGB_MACROTILE_MODE9 0x066d 1000#define mmGB_MACROTILE_MODE9_BASE_IDX 0
1001#define mmGB_MACROTILE_MODE10 0x066e 1002#define mmGB_MACROTILE_MODE10_BASE_IDX 0 1003#define mmGB_MACROTILE_MODE11 0x066f 1004#define mmGB_MACROTILE_MODE11_BASE_IDX 0 1005#define mmGB_MACROTILE_MODE12 0x0670 1006#define mmGB_MACROTILE_MODE12_BASE_IDX 0 1007#define mmGB_MACROTILE_MODE13 0x0671 1008#define mmGB_MACROTILE_MODE13_BASE_IDX 0 1009#define mmGB_MACROTILE_MODE14 0x0672 1010#define mmGB_MACROTILE_MODE14_BASE_IDX 0 1011#define mmGB_MACROTILE_MODE15 0x0673 1012#define mmGB_MACROTILE_MODE15_BASE_IDX 0 1013#define mmCB_HW_CONTROL 0x0680 1014#define mmCB_HW_CONTROL_BASE_IDX 0 1015#define mmCB_HW_CONTROL_1 0x0681 1016#define mmCB_HW_CONTROL_1_BASE_IDX 0 1017#define mmCB_HW_CONTROL_2 0x0682 1018#define mmCB_HW_CONTROL_2_BASE_IDX 0 1019#define mmCB_HW_CONTROL_3 0x0683 1020#define mmCB_HW_CONTROL_3_BASE_IDX 0 1021#define mmCB_HW_MEM_ARBITER_RD 0x0686 1022#define mmCB_HW_MEM_ARBITER_RD_BASE_IDX 0 1023#define mmCB_HW_MEM_ARBITER_WR 0x0687 1024#define mmCB_HW_MEM_ARBITER_WR_BASE_IDX 0 1025#define mmCB_DCC_CONFIG 0x0688 1026#define mmCB_DCC_CONFIG_BASE_IDX 0 1027#define mmGC_USER_RB_REDUNDANCY 0x06de 1028#define mmGC_USER_RB_REDUNDANCY_BASE_IDX 0 1029#define mmGC_USER_RB_BACKEND_DISABLE 0x06df 1030#define mmGC_USER_RB_BACKEND_DISABLE_BASE_IDX 0 1031 1032 1033// addressBlock: gc_ea_gceadec2 1034// base address: 0x9c00 1035#define mmGCEA_EDC_CNT 0x0701 1036#define mmGCEA_EDC_CNT_BASE_IDX 0 1037#define mmGCEA_EDC_CNT2 0x0702 1038#define mmGCEA_EDC_CNT2_BASE_IDX 0 1039#define mmGCEA_DSM_CNTL 0x0703 1040#define mmGCEA_DSM_CNTL_BASE_IDX 0 1041#define mmGCEA_DSM_CNTLA 0x0704 1042#define mmGCEA_DSM_CNTLA_BASE_IDX 0 1043#define mmGCEA_DSM_CNTLB 0x0705 1044#define mmGCEA_DSM_CNTLB_BASE_IDX 0 1045#define mmGCEA_DSM_CNTL2 0x0706 1046#define mmGCEA_DSM_CNTL2_BASE_IDX 0 1047#define mmGCEA_DSM_CNTL2A 0x0707 1048#define mmGCEA_DSM_CNTL2A_BASE_IDX 0 1049#define mmGCEA_DSM_CNTL2B 0x0708 1050#define mmGCEA_DSM_CNTL2B_BASE_IDX 0 1051#define mmGCEA_TCC_XBR_CREDITS 0x0709 1052#define mmGCEA_TCC_XBR_CREDITS_BASE_IDX 0 1053#define mmGCEA_TCC_XBR_MAXBURST 0x070a 1054#define mmGCEA_TCC_XBR_MAXBURST_BASE_IDX 0 1055#define mmGCEA_PROBE_CNTL 0x070b 1056#define mmGCEA_PROBE_CNTL_BASE_IDX 0 1057#define mmGCEA_PROBE_MAP 0x070c 1058#define mmGCEA_PROBE_MAP_BASE_IDX 0 1059#define mmGCEA_ERR_STATUS 0x070d 1060#define mmGCEA_ERR_STATUS_BASE_IDX 0 1061#define mmGCEA_MISC2 0x070e 1062#define mmGCEA_MISC2_BASE_IDX 0 1063#define mmGCEA_SDP_BACKDOOR_CMDCREDITS0 0x070f 1064#define mmGCEA_SDP_BACKDOOR_CMDCREDITS0_BASE_IDX 0 1065#define mmGCEA_SDP_BACKDOOR_CMDCREDITS1 0x0710 1066#define mmGCEA_SDP_BACKDOOR_CMDCREDITS1_BASE_IDX 0 1067#define mmGCEA_SDP_BACKDOOR_DATACREDITS0 0x0711 1068#define mmGCEA_SDP_BACKDOOR_DATACREDITS0_BASE_IDX 0 1069#define mmGCEA_SDP_BACKDOOR_DATACREDITS1 0x0712 1070#define mmGCEA_SDP_BACKDOOR_DATACREDITS1_BASE_IDX 0 1071#define mmGCEA_SDP_BACKDOOR_MISCCREDITS 0x0713 1072#define mmGCEA_SDP_BACKDOOR_MISCCREDITS_BASE_IDX 0 1073#define mmGCEA_SDP_ENABLE 0x0714 1074#define mmGCEA_SDP_ENABLE_BASE_IDX 0 1075 1076 1077// addressBlock: gc_rmi_rmidec 1078// base address: 0x9e00 1079#define mmRMI_GENERAL_CNTL 0x0780 1080#define mmRMI_GENERAL_CNTL_BASE_IDX 0 1081#define mmRMI_GENERAL_CNTL1 0x0781 1082#define mmRMI_GENERAL_CNTL1_BASE_IDX 0 1083#define mmRMI_GENERAL_STATUS 0x0782 1084#define mmRMI_GENERAL_STATUS_BASE_IDX 0 1085#define mmRMI_SUBBLOCK_STATUS0 0x0783 1086#define mmRMI_SUBBLOCK_STATUS0_BASE_IDX 0 1087#define mmRMI_SUBBLOCK_STATUS1 0x0784 1088#define mmRMI_SUBBLOCK_STATUS1_BASE_IDX 0 1089#define mmRMI_SUBBLOCK_STATUS2 0x0785 1090#define mmRMI_SUBBLOCK_STATUS2_BASE_IDX 0 1091#define mmRMI_SUBBLOCK_STATUS3 0x0786 1092#define mmRMI_SUBBLOCK_STATUS3_BASE_IDX 0 1093#define mmRMI_XBAR_CONFIG 0x0787 1094#define mmRMI_XBAR_CONFIG_BASE_IDX 0 1095#define mmRMI_PROBE_POP_LOGIC_CNTL 0x0788 1096#define mmRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX 0 1097#define mmRMI_UTC_XNACK_N_MISC_CNTL 0x0789 1098#define mmRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX 0 1099#define mmRMI_DEMUX_CNTL 0x078a 1100#define mmRMI_DEMUX_CNTL_BASE_IDX 0 1101#define mmRMI_UTCL1_CNTL1 0x078b 1102#define mmRMI_UTCL1_CNTL1_BASE_IDX 0 1103#define mmRMI_UTCL1_CNTL2 0x078c 1104#define mmRMI_UTCL1_CNTL2_BASE_IDX 0 1105#define mmRMI_UTC_UNIT_CONFIG 0x078d 1106#define mmRMI_UTC_UNIT_CONFIG_BASE_IDX 0 1107#define mmRMI_TCIW_FORMATTER0_CNTL 0x078e 1108#define mmRMI_TCIW_FORMATTER0_CNTL_BASE_IDX 0 1109#define mmRMI_TCIW_FORMATTER1_CNTL 0x078f 1110#define mmRMI_TCIW_FORMATTER1_CNTL_BASE_IDX 0 1111#define mmRMI_SCOREBOARD_CNTL 0x0790 1112#define mmRMI_SCOREBOARD_CNTL_BASE_IDX 0 1113#define mmRMI_SCOREBOARD_STATUS0 0x0791 1114#define mmRMI_SCOREBOARD_STATUS0_BASE_IDX 0 1115#define mmRMI_SCOREBOARD_STATUS1 0x0792 1116#define mmRMI_SCOREBOARD_STATUS1_BASE_IDX 0 1117#define mmRMI_SCOREBOARD_STATUS2 0x0793 1118#define mmRMI_SCOREBOARD_STATUS2_BASE_IDX 0 1119#define mmRMI_XBAR_ARBITER_CONFIG 0x0794 1120#define mmRMI_XBAR_ARBITER_CONFIG_BASE_IDX 0 1121#define mmRMI_XBAR_ARBITER_CONFIG_1 0x0795 1122#define mmRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX 0 1123#define mmRMI_CLOCK_CNTRL 0x0796 1124#define mmRMI_CLOCK_CNTRL_BASE_IDX 0 1125#define mmRMI_UTCL1_STATUS 0x0797 1126#define mmRMI_UTCL1_STATUS_BASE_IDX 0 1127#define mmRMI_SPARE 0x079e 1128#define mmRMI_SPARE_BASE_IDX 0 1129#define mmRMI_SPARE_1 0x079f 1130#define mmRMI_SPARE_1_BASE_IDX 0 1131#define mmRMI_SPARE_2 0x07a0 1132#define mmRMI_SPARE_2_BASE_IDX 0 1133 1134 1135// addressBlock: gc_dbgu_gfx_dbgudec 1136// base address: 0x9f00 1137#define mmport_a_addr 0x07c0 1138#define mmport_a_addr_BASE_IDX 0 1139#define mmport_a_data_lo 0x07c1 1140#define mmport_a_data_lo_BASE_IDX 0 1141#define mmport_a_data_hi 0x07c2 1142#define mmport_a_data_hi_BASE_IDX 0 1143#define mmport_b_addr 0x07c3 1144#define mmport_b_addr_BASE_IDX 0 1145#define mmport_b_data_lo 0x07c4 1146#define mmport_b_data_lo_BASE_IDX 0 1147#define mmport_b_data_hi 0x07c5 1148#define mmport_b_data_hi_BASE_IDX 0 1149#define mmport_c_addr 0x07c6 1150#define mmport_c_addr_BASE_IDX 0 1151#define mmport_c_data_lo 0x07c7 1152#define mmport_c_data_lo_BASE_IDX 0 1153#define mmport_c_data_hi 0x07c8 1154#define mmport_c_data_hi_BASE_IDX 0 1155#define mmport_d_addr 0x07c9 1156#define mmport_d_addr_BASE_IDX 0 1157#define mmport_d_data_lo 0x07ca 1158#define mmport_d_data_lo_BASE_IDX 0 1159#define mmport_d_data_hi 0x07cb 1160#define mmport_d_data_hi_BASE_IDX 0 1161 1162 1163// addressBlock: gc_utcl2_atcl2dec 1164// base address: 0xa000 1165#define mmATC_L2_CNTL 0x0800 1166#define mmATC_L2_CNTL_BASE_IDX 0 1167#define mmATC_L2_CNTL2 0x0801 1168#define mmATC_L2_CNTL2_BASE_IDX 0 1169#define mmATC_L2_CACHE_DATA0 0x0804 1170#define mmATC_L2_CACHE_DATA0_BASE_IDX 0 1171#define mmATC_L2_CACHE_DATA1 0x0805 1172#define mmATC_L2_CACHE_DATA1_BASE_IDX 0 1173#define mmATC_L2_CACHE_DATA2 0x0806 1174#define mmATC_L2_CACHE_DATA2_BASE_IDX 0 1175#define mmATC_L2_CNTL3 0x0807 1176#define mmATC_L2_CNTL3_BASE_IDX 0 1177#define mmATC_L2_STATUS 0x0808 1178#define mmATC_L2_STATUS_BASE_IDX 0 1179#define mmATC_L2_STATUS2 0x0809 1180#define mmATC_L2_STATUS2_BASE_IDX 0 1181#define mmATC_L2_MISC_CG 0x080a 1182#define mmATC_L2_MISC_CG_BASE_IDX 0 1183#define mmATC_L2_MEM_POWER_LS 0x080b 1184#define mmATC_L2_MEM_POWER_LS_BASE_IDX 0 1185#define mmATC_L2_CGTT_CLK_CTRL 0x080c 1186#define mmATC_L2_CGTT_CLK_CTRL_BASE_IDX 0 1187 1188 1189// addressBlock: gc_utcl2_vml2pfdec 1190// base address: 0xa100 1191#define mmVM_L2_CNTL 0x0840 1192#define mmVM_L2_CNTL_BASE_IDX 0 1193#define mmVM_L2_CNTL2 0x0841 1194#define mmVM_L2_CNTL2_BASE_IDX 0 1195#define mmVM_L2_CNTL3 0x0842 1196#define mmVM_L2_CNTL3_BASE_IDX 0 1197#define mmVM_L2_STATUS 0x0843 1198#define mmVM_L2_STATUS_BASE_IDX 0 1199#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x0844 1200#define mmVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 1201#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0845 1202#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 1203#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0846 1204#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 1205#define mmVM_L2_PROTECTION_FAULT_CNTL 0x0847 1206#define mmVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 1207#define mmVM_L2_PROTECTION_FAULT_CNTL2 0x0848 1208#define mmVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 1209#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3 0x0849 1210#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 1211#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4 0x084a 1212#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 1213#define mmVM_L2_PROTECTION_FAULT_STATUS 0x084b 1214#define mmVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 1215#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32 0x084c 1216#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 1217#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32 0x084d 1218#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 1219#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x084e 1220#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 1221#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x084f 1222#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 1223#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0851 1224#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 1225#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0852 1226#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 1227#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0853 1228#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 1229#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0854 1230#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 1231#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0855 1232#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 1233#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0856 1234#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 1235#define mmVM_L2_CNTL4 0x0857 1236#define mmVM_L2_CNTL4_BASE_IDX 0 1237#define mmVM_L2_MM_GROUP_RT_CLASSES 0x0858 1238#define mmVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 1239#define mmVM_L2_BANK_SELECT_RESERVED_CID 0x0859 1240#define mmVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 1241#define mmVM_L2_BANK_SELECT_RESERVED_CID2 0x085a 1242#define mmVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 1243#define mmVM_L2_CACHE_PARITY_CNTL 0x085b 1244#define mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 1245#define mmVM_L2_CGTT_CLK_CTRL 0x085e 1246#define mmVM_L2_CGTT_CLK_CTRL_BASE_IDX 0 1247 1248 1249// addressBlock: gc_utcl2_vml2vcdec 1250// base address: 0xa200 1251#define mmVM_CONTEXT0_CNTL 0x0880 1252#define mmVM_CONTEXT0_CNTL_BASE_IDX 0 1253#define mmVM_CONTEXT1_CNTL 0x0881 1254#define mmVM_CONTEXT1_CNTL_BASE_IDX 0 1255#define mmVM_CONTEXT2_CNTL 0x0882 1256#define mmVM_CONTEXT2_CNTL_BASE_IDX 0 1257#define mmVM_CONTEXT3_CNTL 0x0883 1258#define mmVM_CONTEXT3_CNTL_BASE_IDX 0 1259#define mmVM_CONTEXT4_CNTL 0x0884 1260#define mmVM_CONTEXT4_CNTL_BASE_IDX 0 1261#define mmVM_CONTEXT5_CNTL 0x0885 1262#define mmVM_CONTEXT5_CNTL_BASE_IDX 0 1263#define mmVM_CONTEXT6_CNTL 0x0886 1264#define mmVM_CONTEXT6_CNTL_BASE_IDX 0 1265#define mmVM_CONTEXT7_CNTL 0x0887 1266#define mmVM_CONTEXT7_CNTL_BASE_IDX 0 1267#define mmVM_CONTEXT8_CNTL 0x0888 1268#define mmVM_CONTEXT8_CNTL_BASE_IDX 0 1269#define mmVM_CONTEXT9_CNTL 0x0889 1270#define mmVM_CONTEXT9_CNTL_BASE_IDX 0 1271#define mmVM_CONTEXT10_CNTL 0x088a 1272#define mmVM_CONTEXT10_CNTL_BASE_IDX 0 1273#define mmVM_CONTEXT11_CNTL 0x088b 1274#define mmVM_CONTEXT11_CNTL_BASE_IDX 0 1275#define mmVM_CONTEXT12_CNTL 0x088c 1276#define mmVM_CONTEXT12_CNTL_BASE_IDX 0 1277#define mmVM_CONTEXT13_CNTL 0x088d 1278#define mmVM_CONTEXT13_CNTL_BASE_IDX 0 1279#define mmVM_CONTEXT14_CNTL 0x088e 1280#define mmVM_CONTEXT14_CNTL_BASE_IDX 0 1281#define mmVM_CONTEXT15_CNTL 0x088f 1282#define mmVM_CONTEXT15_CNTL_BASE_IDX 0 1283#define mmVM_CONTEXTS_DISABLE 0x0890 1284#define mmVM_CONTEXTS_DISABLE_BASE_IDX 0 1285#define mmVM_INVALIDATE_ENG0_SEM 0x0891 1286#define mmVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 1287#define mmVM_INVALIDATE_ENG1_SEM 0x0892 1288#define mmVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 1289#define mmVM_INVALIDATE_ENG2_SEM 0x0893 1290#define mmVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 1291#define mmVM_INVALIDATE_ENG3_SEM 0x0894 1292#define mmVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 1293#define mmVM_INVALIDATE_ENG4_SEM 0x0895 1294#define mmVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 1295#define mmVM_INVALIDATE_ENG5_SEM 0x0896 1296#define mmVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 1297#define mmVM_INVALIDATE_ENG6_SEM 0x0897 1298#define mmVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 1299#define mmVM_INVALIDATE_ENG7_SEM 0x0898 1300#define mmVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 1301#define mmVM_INVALIDATE_ENG8_SEM 0x0899 1302#define mmVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 1303#define mmVM_INVALIDATE_ENG9_SEM 0x089a 1304#define mmVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 1305#define mmVM_INVALIDATE_ENG10_SEM 0x089b 1306#define mmVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 1307#define mmVM_INVALIDATE_ENG11_SEM 0x089c 1308#define mmVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 1309#define mmVM_INVALIDATE_ENG12_SEM 0x089d 1310#define mmVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 1311#define mmVM_INVALIDATE_ENG13_SEM 0x089e 1312#define mmVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 1313#define mmVM_INVALIDATE_ENG14_SEM 0x089f 1314#define mmVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 1315#define mmVM_INVALIDATE_ENG15_SEM 0x08a0 1316#define mmVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 1317#define mmVM_INVALIDATE_ENG16_SEM 0x08a1 1318#define mmVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 1319#define mmVM_INVALIDATE_ENG17_SEM 0x08a2 1320#define mmVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 1321#define mmVM_INVALIDATE_ENG0_REQ 0x08a3 1322#define mmVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 1323#define mmVM_INVALIDATE_ENG1_REQ 0x08a4 1324#define mmVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 1325#define mmVM_INVALIDATE_ENG2_REQ 0x08a5 1326#define mmVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 1327#define mmVM_INVALIDATE_ENG3_REQ 0x08a6 1328#define mmVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 1329#define mmVM_INVALIDATE_ENG4_REQ 0x08a7 1330#define mmVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 1331#define mmVM_INVALIDATE_ENG5_REQ 0x08a8 1332#define mmVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 1333#define mmVM_INVALIDATE_ENG6_REQ 0x08a9 1334#define mmVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 1335#define mmVM_INVALIDATE_ENG7_REQ 0x08aa 1336#define mmVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 1337#define mmVM_INVALIDATE_ENG8_REQ 0x08ab 1338#define mmVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 1339#define mmVM_INVALIDATE_ENG9_REQ 0x08ac 1340#define mmVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 1341#define mmVM_INVALIDATE_ENG10_REQ 0x08ad 1342#define mmVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 1343#define mmVM_INVALIDATE_ENG11_REQ 0x08ae 1344#define mmVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 1345#define mmVM_INVALIDATE_ENG12_REQ 0x08af 1346#define mmVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 1347#define mmVM_INVALIDATE_ENG13_REQ 0x08b0 1348#define mmVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 1349#define mmVM_INVALIDATE_ENG14_REQ 0x08b1 1350#define mmVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 1351#define mmVM_INVALIDATE_ENG15_REQ 0x08b2 1352#define mmVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 1353#define mmVM_INVALIDATE_ENG16_REQ 0x08b3 1354#define mmVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 1355#define mmVM_INVALIDATE_ENG17_REQ 0x08b4 1356#define mmVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 1357#define mmVM_INVALIDATE_ENG0_ACK 0x08b5 1358#define mmVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 1359#define mmVM_INVALIDATE_ENG1_ACK 0x08b6 1360#define mmVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 1361#define mmVM_INVALIDATE_ENG2_ACK 0x08b7 1362#define mmVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 1363#define mmVM_INVALIDATE_ENG3_ACK 0x08b8 1364#define mmVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 1365#define mmVM_INVALIDATE_ENG4_ACK 0x08b9 1366#define mmVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 1367#define mmVM_INVALIDATE_ENG5_ACK 0x08ba 1368#define mmVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 1369#define mmVM_INVALIDATE_ENG6_ACK 0x08bb 1370#define mmVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 1371#define mmVM_INVALIDATE_ENG7_ACK 0x08bc 1372#define mmVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 1373#define mmVM_INVALIDATE_ENG8_ACK 0x08bd 1374#define mmVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 1375#define mmVM_INVALIDATE_ENG9_ACK 0x08be 1376#define mmVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 1377#define mmVM_INVALIDATE_ENG10_ACK 0x08bf 1378#define mmVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 1379#define mmVM_INVALIDATE_ENG11_ACK 0x08c0 1380#define mmVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 1381#define mmVM_INVALIDATE_ENG12_ACK 0x08c1 1382#define mmVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 1383#define mmVM_INVALIDATE_ENG13_ACK 0x08c2 1384#define mmVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 1385#define mmVM_INVALIDATE_ENG14_ACK 0x08c3 1386#define mmVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 1387#define mmVM_INVALIDATE_ENG15_ACK 0x08c4 1388#define mmVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 1389#define mmVM_INVALIDATE_ENG16_ACK 0x08c5 1390#define mmVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 1391#define mmVM_INVALIDATE_ENG17_ACK 0x08c6 1392#define mmVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 1393#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x08c7 1394#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 1395#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x08c8 1396#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 1397#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x08c9 1398#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 1399#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x08ca 1400#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 1401#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x08cb 1402#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 1403#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x08cc 1404#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 1405#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x08cd 1406#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 1407#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x08ce 1408#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 1409#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x08cf 1410#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 1411#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x08d0 1412#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 1413#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x08d1 1414#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 1415#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x08d2 1416#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 1417#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x08d3 1418#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 1419#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x08d4 1420#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 1421#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x08d5 1422#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 1423#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x08d6 1424#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 1425#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x08d7 1426#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 1427#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x08d8 1428#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 1429#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x08d9 1430#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 1431#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x08da 1432#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 1433#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x08db 1434#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 1435#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x08dc 1436#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 1437#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x08dd 1438#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 1439#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x08de 1440#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 1441#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x08df 1442#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 1443#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x08e0 1444#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 1445#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x08e1 1446#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 1447#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x08e2 1448#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 1449#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x08e3 1450#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 1451#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x08e4 1452#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 1453#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x08e5 1454#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 1455#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x08e6 1456#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 1457#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x08e7 1458#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 1459#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x08e8 1460#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 1461#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x08e9 1462#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 1463#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x08ea 1464#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 1465#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x08eb 1466#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1467#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x08ec 1468#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1469#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x08ed 1470#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1471#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x08ee 1472#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1473#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x08ef 1474#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1475#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x08f0 1476#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1477#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x08f1 1478#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1479#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x08f2 1480#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1481#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x08f3 1482#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1483#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x08f4 1484#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1485#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x08f5 1486#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1487#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x08f6 1488#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1489#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x08f7 1490#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1491#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x08f8 1492#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1493#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x08f9 1494#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1495#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x08fa 1496#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1497#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x08fb 1498#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1499#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x08fc 1500#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1501#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x08fd 1502#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1503#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x08fe 1504#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1505#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x08ff 1506#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1507#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0900 1508#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1509#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0901 1510#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1511#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0902 1512#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1513#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0903 1514#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1515#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0904 1516#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1517#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0905 1518#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1519#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0906 1520#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1521#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0907 1522#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1523#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0908 1524#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1525#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0909 1526#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1527#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x090a 1528#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1529#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x090b 1530#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1531#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x090c 1532#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1533#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x090d 1534#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1535#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x090e 1536#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1537#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x090f 1538#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1539#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0910 1540#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1541#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0911 1542#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1543#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0912 1544#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1545#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0913 1546#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1547#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0914 1548#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1549#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0915 1550#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1551#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0916 1552#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1553#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0917 1554#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1555#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0918 1556#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1557#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0919 1558#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1559#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x091a 1560#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1561#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x091b 1562#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1563#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x091c 1564#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1565#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x091d 1566#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1567#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x091e 1568#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1569#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x091f 1570#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1571#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0920 1572#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1573#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0921 1574#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1575#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0922 1576#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1577#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0923 1578#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1579#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0924 1580#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1581#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0925 1582#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1583#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0926 1584#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1585#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0927 1586#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1587#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0928 1588#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1589#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0929 1590#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1591#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x092a 1592#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1593#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x092b 1594#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1595#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x092c 1596#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1597#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x092d 1598#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1599#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x092e 1600#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1601#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x092f 1602#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1603#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0930 1604#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1605#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0931 1606#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1607#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0932 1608#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1609#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0933 1610#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1611#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0934 1612#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1613#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0935 1614#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1615#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0936 1616#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1617#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0937 1618#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1619#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0938 1620#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1621#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0939 1622#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1623#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x093a 1624#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1625#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x093b 1626#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1627#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x093c 1628#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1629#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x093d 1630#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1631#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x093e 1632#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1633#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x093f 1634#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1635#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0940 1636#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1637#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0941 1638#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1639#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0942 1640#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1641#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0943 1642#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1643#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0944 1644#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1645#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0945 1646#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1647#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0946 1648#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1649#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0947 1650#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1651#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0948 1652#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1653#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0949 1654#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1655#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x094a 1656#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1657 1658 1659// addressBlock: gc_utcl2_vmsharedpfdec 1660// base address: 0xa590 1661#define mmMC_VM_NB_MMIOBASE 0x0964 1662#define mmMC_VM_NB_MMIOBASE_BASE_IDX 0 1663#define mmMC_VM_NB_MMIOLIMIT 0x0965 1664#define mmMC_VM_NB_MMIOLIMIT_BASE_IDX 0 1665#define mmMC_VM_NB_PCI_CTRL 0x0966 1666#define mmMC_VM_NB_PCI_CTRL_BASE_IDX 0 1667#define mmMC_VM_NB_PCI_ARB 0x0967 1668#define mmMC_VM_NB_PCI_ARB_BASE_IDX 0 1669#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1 0x0968 1670#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0 1671#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2 0x0969 1672#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0 1673#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2 0x096a 1674#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0 1675#define mmMC_VM_FB_OFFSET 0x096b 1676#define mmMC_VM_FB_OFFSET_BASE_IDX 0 1677#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x096c 1678#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 1679#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x096d 1680#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 1681#define mmMC_VM_STEERING 0x096e 1682#define mmMC_VM_STEERING_BASE_IDX 0 1683#define mmMC_SHARED_VIRT_RESET_REQ 0x096f 1684#define mmMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0 1685#define mmMC_MEM_POWER_LS 0x0970 1686#define mmMC_MEM_POWER_LS_BASE_IDX 0 1687#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x0971 1688#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 1689#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x0972 1690#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 1691#define mmMC_VM_APT_CNTL 0x0973 1692#define mmMC_VM_APT_CNTL_BASE_IDX 0 1693#define mmMC_VM_LOCAL_HBM_ADDRESS_START 0x0974 1694#define mmMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0 1695#define mmMC_VM_LOCAL_HBM_ADDRESS_END 0x0975 1696#define mmMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0 1697#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0976 1698#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0 1699 1700 1701// addressBlock: gc_utcl2_vmsharedvcdec 1702// base address: 0xa600 1703#define mmMC_VM_FB_LOCATION_BASE 0x0980 1704#define mmMC_VM_FB_LOCATION_BASE_BASE_IDX 0 1705#define mmMC_VM_FB_LOCATION_TOP 0x0981 1706#define mmMC_VM_FB_LOCATION_TOP_BASE_IDX 0 1707#define mmMC_VM_AGP_TOP 0x0982 1708#define mmMC_VM_AGP_TOP_BASE_IDX 0 1709#define mmMC_VM_AGP_BOT 0x0983 1710#define mmMC_VM_AGP_BOT_BASE_IDX 0 1711#define mmMC_VM_AGP_BASE 0x0984 1712#define mmMC_VM_AGP_BASE_BASE_IDX 0 1713#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0985 1714#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 1715#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0986 1716#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 1717#define mmMC_VM_MX_L1_TLB_CNTL 0x0987 1718#define mmMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 1719 1720 1721// addressBlock: gc_ea_gceadec 1722// base address: 0xa800 1723#define mmGCEA_DRAM_RD_CLI2GRP_MAP0 0x0a00 1724#define mmGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 1725#define mmGCEA_DRAM_RD_CLI2GRP_MAP1 0x0a01 1726#define mmGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 1727#define mmGCEA_DRAM_WR_CLI2GRP_MAP0 0x0a02 1728#define mmGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 1729#define mmGCEA_DRAM_WR_CLI2GRP_MAP1 0x0a03 1730#define mmGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 1731#define mmGCEA_DRAM_RD_GRP2VC_MAP 0x0a04 1732#define mmGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 1733#define mmGCEA_DRAM_WR_GRP2VC_MAP 0x0a05 1734#define mmGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 1735#define mmGCEA_DRAM_RD_LAZY 0x0a06 1736#define mmGCEA_DRAM_RD_LAZY_BASE_IDX 0 1737#define mmGCEA_DRAM_WR_LAZY 0x0a07 1738#define mmGCEA_DRAM_WR_LAZY_BASE_IDX 0 1739#define mmGCEA_DRAM_RD_CAM_CNTL 0x0a08 1740#define mmGCEA_DRAM_RD_CAM_CNTL_BASE_IDX 0 1741#define mmGCEA_DRAM_WR_CAM_CNTL 0x0a09 1742#define mmGCEA_DRAM_WR_CAM_CNTL_BASE_IDX 0 1743#define mmGCEA_DRAM_PAGE_BURST 0x0a0a 1744#define mmGCEA_DRAM_PAGE_BURST_BASE_IDX 0 1745#define mmGCEA_DRAM_RD_PRI_AGE 0x0a0b 1746#define mmGCEA_DRAM_RD_PRI_AGE_BASE_IDX 0 1747#define mmGCEA_DRAM_WR_PRI_AGE 0x0a0c 1748#define mmGCEA_DRAM_WR_PRI_AGE_BASE_IDX 0 1749#define mmGCEA_DRAM_RD_PRI_QUEUING 0x0a0d 1750#define mmGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX 0 1751#define mmGCEA_DRAM_WR_PRI_QUEUING 0x0a0e 1752#define mmGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX 0 1753#define mmGCEA_DRAM_RD_PRI_FIXED 0x0a0f 1754#define mmGCEA_DRAM_RD_PRI_FIXED_BASE_IDX 0 1755#define mmGCEA_DRAM_WR_PRI_FIXED 0x0a10 1756#define mmGCEA_DRAM_WR_PRI_FIXED_BASE_IDX 0 1757#define mmGCEA_DRAM_RD_PRI_URGENCY 0x0a11 1758#define mmGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX 0 1759#define mmGCEA_DRAM_WR_PRI_URGENCY 0x0a12 1760#define mmGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX 0 1761#define mmGCEA_DRAM_RD_PRI_QUANT_PRI1 0x0a13 1762#define mmGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 1763#define mmGCEA_DRAM_RD_PRI_QUANT_PRI2 0x0a14 1764#define mmGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 1765#define mmGCEA_DRAM_RD_PRI_QUANT_PRI3 0x0a15 1766#define mmGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 1767#define mmGCEA_DRAM_WR_PRI_QUANT_PRI1 0x0a16 1768#define mmGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 1769#define mmGCEA_DRAM_WR_PRI_QUANT_PRI2 0x0a17 1770#define mmGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 1771#define mmGCEA_DRAM_WR_PRI_QUANT_PRI3 0x0a18 1772#define mmGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 1773#define mmGCEA_ADDRNORM_BASE_ADDR0 0x0a32 1774#define mmGCEA_ADDRNORM_BASE_ADDR0_BASE_IDX 0 1775#define mmGCEA_ADDRNORM_LIMIT_ADDR0 0x0a33 1776#define mmGCEA_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 1777#define mmGCEA_ADDRNORM_BASE_ADDR1 0x0a34 1778#define mmGCEA_ADDRNORM_BASE_ADDR1_BASE_IDX 0 1779#define mmGCEA_ADDRNORM_LIMIT_ADDR1 0x0a35 1780#define mmGCEA_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 1781#define mmGCEA_ADDRNORM_OFFSET_ADDR1 0x0a36 1782#define mmGCEA_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 1783#define mmGCEA_ADDRNORM_HOLE_CNTL 0x0a41 1784#define mmGCEA_ADDRNORM_HOLE_CNTL_BASE_IDX 0 1785#define mmGCEA_ADDRDEC_BANK_CFG 0x0a42 1786#define mmGCEA_ADDRDEC_BANK_CFG_BASE_IDX 0 1787#define mmGCEA_ADDRDEC_MISC_CFG 0x0a43 1788#define mmGCEA_ADDRDEC_MISC_CFG_BASE_IDX 0 1789#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0 0x0a44 1790#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 0 1791#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1 0x0a45 1792#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 0 1793#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2 0x0a46 1794#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 0 1795#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3 0x0a47 1796#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 0 1797#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4 0x0a48 1798#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 0 1799#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC 0x0a49 1800#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 0 1801#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2 0x0a4a 1802#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 0 1803#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0 0x0a4b 1804#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 0 1805#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1 0x0a4c 1806#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 0 1807#define mmGCEA_ADDRDECDRAM_HARVEST_ENABLE 0x0a4d 1808#define mmGCEA_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 1809#define mmGCEA_ADDRDEC0_BASE_ADDR_CS0 0x0a58 1810#define mmGCEA_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 1811#define mmGCEA_ADDRDEC0_BASE_ADDR_CS1 0x0a59 1812#define mmGCEA_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 1813#define mmGCEA_ADDRDEC0_BASE_ADDR_CS2 0x0a5a 1814#define mmGCEA_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 1815#define mmGCEA_ADDRDEC0_BASE_ADDR_CS3 0x0a5b 1816#define mmGCEA_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 1817#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0 0x0a5c 1818#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 1819#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1 0x0a5d 1820#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 1821#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2 0x0a5e 1822#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 1823#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3 0x0a5f 1824#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 1825#define mmGCEA_ADDRDEC0_ADDR_MASK_CS01 0x0a60 1826#define mmGCEA_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 1827#define mmGCEA_ADDRDEC0_ADDR_MASK_CS23 0x0a61 1828#define mmGCEA_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 1829#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01 0x0a62 1830#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 1831#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23 0x0a63 1832#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 1833#define mmGCEA_ADDRDEC0_ADDR_CFG_CS01 0x0a64 1834#define mmGCEA_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 1835#define mmGCEA_ADDRDEC0_ADDR_CFG_CS23 0x0a65 1836#define mmGCEA_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 1837#define mmGCEA_ADDRDEC0_ADDR_SEL_CS01 0x0a66 1838#define mmGCEA_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 1839#define mmGCEA_ADDRDEC0_ADDR_SEL_CS23 0x0a67 1840#define mmGCEA_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 1841#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS01 0x0a68 1842#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 1843#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS23 0x0a69 1844#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 1845#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS01 0x0a6a 1846#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 1847#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS23 0x0a6b 1848#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 1849#define mmGCEA_ADDRDEC0_RM_SEL_CS01 0x0a6c 1850#define mmGCEA_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 1851#define mmGCEA_ADDRDEC0_RM_SEL_CS23 0x0a6d 1852#define mmGCEA_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 1853#define mmGCEA_ADDRDEC0_RM_SEL_SECCS01 0x0a6e 1854#define mmGCEA_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 1855#define mmGCEA_ADDRDEC0_RM_SEL_SECCS23 0x0a6f 1856#define mmGCEA_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 1857#define mmGCEA_ADDRDEC1_BASE_ADDR_CS0 0x0a70 1858#define mmGCEA_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 1859#define mmGCEA_ADDRDEC1_BASE_ADDR_CS1 0x0a71 1860#define mmGCEA_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 1861#define mmGCEA_ADDRDEC1_BASE_ADDR_CS2 0x0a72 1862#define mmGCEA_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 1863#define mmGCEA_ADDRDEC1_BASE_ADDR_CS3 0x0a73 1864#define mmGCEA_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 1865#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0 0x0a74 1866#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 1867#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1 0x0a75 1868#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 1869#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2 0x0a76 1870#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 1871#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3 0x0a77 1872#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 1873#define mmGCEA_ADDRDEC1_ADDR_MASK_CS01 0x0a78 1874#define mmGCEA_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 1875#define mmGCEA_ADDRDEC1_ADDR_MASK_CS23 0x0a79 1876#define mmGCEA_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 1877#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01 0x0a7a 1878#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 1879#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23 0x0a7b 1880#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 1881#define mmGCEA_ADDRDEC1_ADDR_CFG_CS01 0x0a7c 1882#define mmGCEA_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 1883#define mmGCEA_ADDRDEC1_ADDR_CFG_CS23 0x0a7d 1884#define mmGCEA_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 1885#define mmGCEA_ADDRDEC1_ADDR_SEL_CS01 0x0a7e 1886#define mmGCEA_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 1887#define mmGCEA_ADDRDEC1_ADDR_SEL_CS23 0x0a7f 1888#define mmGCEA_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 1889#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS01 0x0a80 1890#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 1891#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS23 0x0a81 1892#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 1893#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS01 0x0a82 1894#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 1895#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS23 0x0a83 1896#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 1897#define mmGCEA_ADDRDEC1_RM_SEL_CS01 0x0a84 1898#define mmGCEA_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 1899#define mmGCEA_ADDRDEC1_RM_SEL_CS23 0x0a85 1900#define mmGCEA_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 1901#define mmGCEA_ADDRDEC1_RM_SEL_SECCS01 0x0a86 1902#define mmGCEA_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 1903#define mmGCEA_ADDRDEC1_RM_SEL_SECCS23 0x0a87 1904#define mmGCEA_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 1905#define mmGCEA_IO_RD_CLI2GRP_MAP0 0x0ad0 1906#define mmGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 1907#define mmGCEA_IO_RD_CLI2GRP_MAP1 0x0ad1 1908#define mmGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 1909#define mmGCEA_IO_WR_CLI2GRP_MAP0 0x0ad2 1910#define mmGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 1911#define mmGCEA_IO_WR_CLI2GRP_MAP1 0x0ad3 1912#define mmGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 1913#define mmGCEA_IO_RD_COMBINE_FLUSH 0x0ad4 1914#define mmGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX 0 1915#define mmGCEA_IO_WR_COMBINE_FLUSH 0x0ad5 1916#define mmGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX 0 1917#define mmGCEA_IO_GROUP_BURST 0x0ad6 1918#define mmGCEA_IO_GROUP_BURST_BASE_IDX 0 1919#define mmGCEA_IO_RD_PRI_AGE 0x0ad7 1920#define mmGCEA_IO_RD_PRI_AGE_BASE_IDX 0 1921#define mmGCEA_IO_WR_PRI_AGE 0x0ad8 1922#define mmGCEA_IO_WR_PRI_AGE_BASE_IDX 0 1923#define mmGCEA_IO_RD_PRI_QUEUING 0x0ad9 1924#define mmGCEA_IO_RD_PRI_QUEUING_BASE_IDX 0 1925#define mmGCEA_IO_WR_PRI_QUEUING 0x0ada 1926#define mmGCEA_IO_WR_PRI_QUEUING_BASE_IDX 0 1927#define mmGCEA_IO_RD_PRI_FIXED 0x0adb 1928#define mmGCEA_IO_RD_PRI_FIXED_BASE_IDX 0 1929#define mmGCEA_IO_WR_PRI_FIXED 0x0adc 1930#define mmGCEA_IO_WR_PRI_FIXED_BASE_IDX 0 1931#define mmGCEA_IO_RD_PRI_URGENCY 0x0add 1932#define mmGCEA_IO_RD_PRI_URGENCY_BASE_IDX 0 1933#define mmGCEA_IO_WR_PRI_URGENCY 0x0ade 1934#define mmGCEA_IO_WR_PRI_URGENCY_BASE_IDX 0 1935#define mmGCEA_IO_RD_PRI_URGENCY_MASK 0x0adf 1936#define mmGCEA_IO_RD_PRI_URGENCY_MASK_BASE_IDX 0 1937#define mmGCEA_IO_WR_PRI_URGENCY_MASK 0x0ae0 1938#define mmGCEA_IO_WR_PRI_URGENCY_MASK_BASE_IDX 0 1939#define mmGCEA_IO_RD_PRI_QUANT_PRI1 0x0ae1 1940#define mmGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 1941#define mmGCEA_IO_RD_PRI_QUANT_PRI2 0x0ae2 1942#define mmGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 1943#define mmGCEA_IO_RD_PRI_QUANT_PRI3 0x0ae3 1944#define mmGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 1945#define mmGCEA_IO_WR_PRI_QUANT_PRI1 0x0ae4 1946#define mmGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 1947#define mmGCEA_IO_WR_PRI_QUANT_PRI2 0x0ae5 1948#define mmGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 1949#define mmGCEA_IO_WR_PRI_QUANT_PRI3 0x0ae6 1950#define mmGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 1951#define mmGCEA_SDP_ARB_DRAM 0x0ae7 1952#define mmGCEA_SDP_ARB_DRAM_BASE_IDX 0 1953#define mmGCEA_SDP_ARB_FINAL 0x0ae9 1954#define mmGCEA_SDP_ARB_FINAL_BASE_IDX 0 1955#define mmGCEA_SDP_DRAM_PRIORITY 0x0aea 1956#define mmGCEA_SDP_DRAM_PRIORITY_BASE_IDX 0 1957#define mmGCEA_SDP_IO_PRIORITY 0x0aec 1958#define mmGCEA_SDP_IO_PRIORITY_BASE_IDX 0 1959#define mmGCEA_SDP_CREDITS 0x0aed 1960#define mmGCEA_SDP_CREDITS_BASE_IDX 0 1961#define mmGCEA_SDP_TAG_RESERVE0 0x0aee 1962#define mmGCEA_SDP_TAG_RESERVE0_BASE_IDX 0 1963#define mmGCEA_SDP_TAG_RESERVE1 0x0aef 1964#define mmGCEA_SDP_TAG_RESERVE1_BASE_IDX 0 1965#define mmGCEA_SDP_VCC_RESERVE0 0x0af0 1966#define mmGCEA_SDP_VCC_RESERVE0_BASE_IDX 0 1967#define mmGCEA_SDP_VCC_RESERVE1 0x0af1 1968#define mmGCEA_SDP_VCC_RESERVE1_BASE_IDX 0 1969#define mmGCEA_SDP_VCD_RESERVE0 0x0af2 1970#define mmGCEA_SDP_VCD_RESERVE0_BASE_IDX 0 1971#define mmGCEA_SDP_VCD_RESERVE1 0x0af3 1972#define mmGCEA_SDP_VCD_RESERVE1_BASE_IDX 0 1973#define mmGCEA_SDP_REQ_CNTL 0x0af4 1974#define mmGCEA_SDP_REQ_CNTL_BASE_IDX 0 1975#define mmGCEA_MISC 0x0af5 1976#define mmGCEA_MISC_BASE_IDX 0 1977#define mmGCEA_LATENCY_SAMPLING 0x0af6 1978#define mmGCEA_LATENCY_SAMPLING_BASE_IDX 0 1979#define mmGCEA_PERFCOUNTER_LO 0x0af7 1980#define mmGCEA_PERFCOUNTER_LO_BASE_IDX 0 1981#define mmGCEA_PERFCOUNTER_HI 0x0af8 1982#define mmGCEA_PERFCOUNTER_HI_BASE_IDX 0 1983#define mmGCEA_PERFCOUNTER0_CFG 0x0af9 1984#define mmGCEA_PERFCOUNTER0_CFG_BASE_IDX 0 1985#define mmGCEA_PERFCOUNTER1_CFG 0x0afa 1986#define mmGCEA_PERFCOUNTER1_CFG_BASE_IDX 0 1987#define mmGCEA_PERFCOUNTER_RSLT_CNTL 0x0afb 1988#define mmGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 1989 1990 1991// addressBlock: gc_tcdec 1992// base address: 0xac00 1993#define mmTCP_INVALIDATE 0x0b00 1994#define mmTCP_INVALIDATE_BASE_IDX 0 1995#define mmTCP_STATUS 0x0b01 1996#define mmTCP_STATUS_BASE_IDX 0 1997#define mmTCP_CNTL 0x0b02 1998#define mmTCP_CNTL_BASE_IDX 0 1999#define mmTCP_CHAN_STEER_LO 0x0b03 2000#define mmTCP_CHAN_STEER_LO_BASE_IDX 0
2001#define mmTCP_CHAN_STEER_HI 0x0b04 2002#define mmTCP_CHAN_STEER_HI_BASE_IDX 0 2003#define mmTCP_ADDR_CONFIG 0x0b05 2004#define mmTCP_ADDR_CONFIG_BASE_IDX 0 2005#define mmTCP_CREDIT 0x0b06 2006#define mmTCP_CREDIT_BASE_IDX 0 2007#define mmTCP_BUFFER_ADDR_HASH_CNTL 0x0b16 2008#define mmTCP_BUFFER_ADDR_HASH_CNTL_BASE_IDX 0 2009#define mmTCP_EDC_CNT 0x0b17 2010#define mmTCP_EDC_CNT_BASE_IDX 0 2011#define mmTC_CFG_L1_LOAD_POLICY0 0x0b1a 2012#define mmTC_CFG_L1_LOAD_POLICY0_BASE_IDX 0 2013#define mmTC_CFG_L1_LOAD_POLICY1 0x0b1b 2014#define mmTC_CFG_L1_LOAD_POLICY1_BASE_IDX 0 2015#define mmTC_CFG_L1_STORE_POLICY 0x0b1c 2016#define mmTC_CFG_L1_STORE_POLICY_BASE_IDX 0 2017#define mmTC_CFG_L2_LOAD_POLICY0 0x0b1d 2018#define mmTC_CFG_L2_LOAD_POLICY0_BASE_IDX 0 2019#define mmTC_CFG_L2_LOAD_POLICY1 0x0b1e 2020#define mmTC_CFG_L2_LOAD_POLICY1_BASE_IDX 0 2021#define mmTC_CFG_L2_STORE_POLICY0 0x0b1f 2022#define mmTC_CFG_L2_STORE_POLICY0_BASE_IDX 0 2023#define mmTC_CFG_L2_STORE_POLICY1 0x0b20 2024#define mmTC_CFG_L2_STORE_POLICY1_BASE_IDX 0 2025#define mmTC_CFG_L2_ATOMIC_POLICY 0x0b21 2026#define mmTC_CFG_L2_ATOMIC_POLICY_BASE_IDX 0 2027#define mmTC_CFG_L1_VOLATILE 0x0b22 2028#define mmTC_CFG_L1_VOLATILE_BASE_IDX 0 2029#define mmTC_CFG_L2_VOLATILE 0x0b23 2030#define mmTC_CFG_L2_VOLATILE_BASE_IDX 0 2031#define mmTCI_STATUS 0x0b61 2032#define mmTCI_STATUS_BASE_IDX 0 2033#define mmTCI_CNTL_1 0x0b62 2034#define mmTCI_CNTL_1_BASE_IDX 0 2035#define mmTCI_CNTL_2 0x0b63 2036#define mmTCI_CNTL_2_BASE_IDX 0 2037#define mmTCC_CTRL 0x0b80 2038#define mmTCC_CTRL_BASE_IDX 0 2039#define mmTCC_CTRL2 0x0b81 2040#define mmTCC_CTRL2_BASE_IDX 0 2041#define mmTCC_EDC_CNT 0x0b82 2042#define mmTCC_EDC_CNT_BASE_IDX 0 2043#define mmTCC_EDC_CNT2 0x0b83 2044#define mmTCC_EDC_CNT2_BASE_IDX 0 2045#define mmTCC_REDUNDANCY 0x0b84 2046#define mmTCC_REDUNDANCY_BASE_IDX 0 2047#define mmTCC_EXE_DISABLE 0x0b85 2048#define mmTCC_EXE_DISABLE_BASE_IDX 0 2049#define mmTCC_DSM_CNTL 0x0b86 2050#define mmTCC_DSM_CNTL_BASE_IDX 0 2051#define mmTCC_DSM_CNTLA 0x0b87 2052#define mmTCC_DSM_CNTLA_BASE_IDX 0 2053#define mmTCC_DSM_CNTL2 0x0b88 2054#define mmTCC_DSM_CNTL2_BASE_IDX 0 2055#define mmTCC_DSM_CNTL2A 0x0b89 2056#define mmTCC_DSM_CNTL2A_BASE_IDX 0 2057#define mmTCC_DSM_CNTL2B 0x0b8a 2058#define mmTCC_DSM_CNTL2B_BASE_IDX 0 2059#define mmTCC_WBINVL2 0x0b8b 2060#define mmTCC_WBINVL2_BASE_IDX 0 2061#define mmTCC_SOFT_RESET 0x0b8c 2062#define mmTCC_SOFT_RESET_BASE_IDX 0 2063#define mmTCA_CTRL 0x0bc0 2064#define mmTCA_CTRL_BASE_IDX 0 2065#define mmTCA_BURST_MASK 0x0bc1 2066#define mmTCA_BURST_MASK_BASE_IDX 0 2067#define mmTCA_BURST_CTRL 0x0bc2 2068#define mmTCA_BURST_CTRL_BASE_IDX 0 2069#define mmTCA_DSM_CNTL 0x0bc3 2070#define mmTCA_DSM_CNTL_BASE_IDX 0 2071#define mmTCA_DSM_CNTL2 0x0bc4 2072#define mmTCA_DSM_CNTL2_BASE_IDX 0 2073#define mmTCA_EDC_CNT 0x0bc5 2074#define mmTCA_EDC_CNT_BASE_IDX 0 2075 2076 2077// addressBlock: gc_shdec 2078// base address: 0xb000 2079#define mmSPI_SHADER_PGM_RSRC3_PS 0x0c07 2080#define mmSPI_SHADER_PGM_RSRC3_PS_BASE_IDX 0 2081#define mmSPI_SHADER_PGM_LO_PS 0x0c08 2082#define mmSPI_SHADER_PGM_LO_PS_BASE_IDX 0 2083#define mmSPI_SHADER_PGM_HI_PS 0x0c09 2084#define mmSPI_SHADER_PGM_HI_PS_BASE_IDX 0 2085#define mmSPI_SHADER_PGM_RSRC1_PS 0x0c0a 2086#define mmSPI_SHADER_PGM_RSRC1_PS_BASE_IDX 0 2087#define mmSPI_SHADER_PGM_RSRC2_PS 0x0c0b 2088#define mmSPI_SHADER_PGM_RSRC2_PS_BASE_IDX 0 2089#define mmSPI_SHADER_USER_DATA_PS_0 0x0c0c 2090#define mmSPI_SHADER_USER_DATA_PS_0_BASE_IDX 0 2091#define mmSPI_SHADER_USER_DATA_PS_1 0x0c0d 2092#define mmSPI_SHADER_USER_DATA_PS_1_BASE_IDX 0 2093#define mmSPI_SHADER_USER_DATA_PS_2 0x0c0e 2094#define mmSPI_SHADER_USER_DATA_PS_2_BASE_IDX 0 2095#define mmSPI_SHADER_USER_DATA_PS_3 0x0c0f 2096#define mmSPI_SHADER_USER_DATA_PS_3_BASE_IDX 0 2097#define mmSPI_SHADER_USER_DATA_PS_4 0x0c10 2098#define mmSPI_SHADER_USER_DATA_PS_4_BASE_IDX 0 2099#define mmSPI_SHADER_USER_DATA_PS_5 0x0c11 2100#define mmSPI_SHADER_USER_DATA_PS_5_BASE_IDX 0 2101#define mmSPI_SHADER_USER_DATA_PS_6 0x0c12 2102#define mmSPI_SHADER_USER_DATA_PS_6_BASE_IDX 0 2103#define mmSPI_SHADER_USER_DATA_PS_7 0x0c13 2104#define mmSPI_SHADER_USER_DATA_PS_7_BASE_IDX 0 2105#define mmSPI_SHADER_USER_DATA_PS_8 0x0c14 2106#define mmSPI_SHADER_USER_DATA_PS_8_BASE_IDX 0 2107#define mmSPI_SHADER_USER_DATA_PS_9 0x0c15 2108#define mmSPI_SHADER_USER_DATA_PS_9_BASE_IDX 0 2109#define mmSPI_SHADER_USER_DATA_PS_10 0x0c16 2110#define mmSPI_SHADER_USER_DATA_PS_10_BASE_IDX 0 2111#define mmSPI_SHADER_USER_DATA_PS_11 0x0c17 2112#define mmSPI_SHADER_USER_DATA_PS_11_BASE_IDX 0 2113#define mmSPI_SHADER_USER_DATA_PS_12 0x0c18 2114#define mmSPI_SHADER_USER_DATA_PS_12_BASE_IDX 0 2115#define mmSPI_SHADER_USER_DATA_PS_13 0x0c19 2116#define mmSPI_SHADER_USER_DATA_PS_13_BASE_IDX 0 2117#define mmSPI_SHADER_USER_DATA_PS_14 0x0c1a 2118#define mmSPI_SHADER_USER_DATA_PS_14_BASE_IDX 0 2119#define mmSPI_SHADER_USER_DATA_PS_15 0x0c1b 2120#define mmSPI_SHADER_USER_DATA_PS_15_BASE_IDX 0 2121#define mmSPI_SHADER_USER_DATA_PS_16 0x0c1c 2122#define mmSPI_SHADER_USER_DATA_PS_16_BASE_IDX 0 2123#define mmSPI_SHADER_USER_DATA_PS_17 0x0c1d 2124#define mmSPI_SHADER_USER_DATA_PS_17_BASE_IDX 0 2125#define mmSPI_SHADER_USER_DATA_PS_18 0x0c1e 2126#define mmSPI_SHADER_USER_DATA_PS_18_BASE_IDX 0 2127#define mmSPI_SHADER_USER_DATA_PS_19 0x0c1f 2128#define mmSPI_SHADER_USER_DATA_PS_19_BASE_IDX 0 2129#define mmSPI_SHADER_USER_DATA_PS_20 0x0c20 2130#define mmSPI_SHADER_USER_DATA_PS_20_BASE_IDX 0 2131#define mmSPI_SHADER_USER_DATA_PS_21 0x0c21 2132#define mmSPI_SHADER_USER_DATA_PS_21_BASE_IDX 0 2133#define mmSPI_SHADER_USER_DATA_PS_22 0x0c22 2134#define mmSPI_SHADER_USER_DATA_PS_22_BASE_IDX 0 2135#define mmSPI_SHADER_USER_DATA_PS_23 0x0c23 2136#define mmSPI_SHADER_USER_DATA_PS_23_BASE_IDX 0 2137#define mmSPI_SHADER_USER_DATA_PS_24 0x0c24 2138#define mmSPI_SHADER_USER_DATA_PS_24_BASE_IDX 0 2139#define mmSPI_SHADER_USER_DATA_PS_25 0x0c25 2140#define mmSPI_SHADER_USER_DATA_PS_25_BASE_IDX 0 2141#define mmSPI_SHADER_USER_DATA_PS_26 0x0c26 2142#define mmSPI_SHADER_USER_DATA_PS_26_BASE_IDX 0 2143#define mmSPI_SHADER_USER_DATA_PS_27 0x0c27 2144#define mmSPI_SHADER_USER_DATA_PS_27_BASE_IDX 0 2145#define mmSPI_SHADER_USER_DATA_PS_28 0x0c28 2146#define mmSPI_SHADER_USER_DATA_PS_28_BASE_IDX 0 2147#define mmSPI_SHADER_USER_DATA_PS_29 0x0c29 2148#define mmSPI_SHADER_USER_DATA_PS_29_BASE_IDX 0 2149#define mmSPI_SHADER_USER_DATA_PS_30 0x0c2a 2150#define mmSPI_SHADER_USER_DATA_PS_30_BASE_IDX 0 2151#define mmSPI_SHADER_USER_DATA_PS_31 0x0c2b 2152#define mmSPI_SHADER_USER_DATA_PS_31_BASE_IDX 0 2153#define mmSPI_SHADER_PGM_RSRC3_VS 0x0c46 2154#define mmSPI_SHADER_PGM_RSRC3_VS_BASE_IDX 0 2155#define mmSPI_SHADER_LATE_ALLOC_VS 0x0c47 2156#define mmSPI_SHADER_LATE_ALLOC_VS_BASE_IDX 0 2157#define mmSPI_SHADER_PGM_LO_VS 0x0c48 2158#define mmSPI_SHADER_PGM_LO_VS_BASE_IDX 0 2159#define mmSPI_SHADER_PGM_HI_VS 0x0c49 2160#define mmSPI_SHADER_PGM_HI_VS_BASE_IDX 0 2161#define mmSPI_SHADER_PGM_RSRC1_VS 0x0c4a 2162#define mmSPI_SHADER_PGM_RSRC1_VS_BASE_IDX 0 2163#define mmSPI_SHADER_PGM_RSRC2_VS 0x0c4b 2164#define mmSPI_SHADER_PGM_RSRC2_VS_BASE_IDX 0 2165#define mmSPI_SHADER_USER_DATA_VS_0 0x0c4c 2166#define mmSPI_SHADER_USER_DATA_VS_0_BASE_IDX 0 2167#define mmSPI_SHADER_USER_DATA_VS_1 0x0c4d 2168#define mmSPI_SHADER_USER_DATA_VS_1_BASE_IDX 0 2169#define mmSPI_SHADER_USER_DATA_VS_2 0x0c4e 2170#define mmSPI_SHADER_USER_DATA_VS_2_BASE_IDX 0 2171#define mmSPI_SHADER_USER_DATA_VS_3 0x0c4f 2172#define mmSPI_SHADER_USER_DATA_VS_3_BASE_IDX 0 2173#define mmSPI_SHADER_USER_DATA_VS_4 0x0c50 2174#define mmSPI_SHADER_USER_DATA_VS_4_BASE_IDX 0 2175#define mmSPI_SHADER_USER_DATA_VS_5 0x0c51 2176#define mmSPI_SHADER_USER_DATA_VS_5_BASE_IDX 0 2177#define mmSPI_SHADER_USER_DATA_VS_6 0x0c52 2178#define mmSPI_SHADER_USER_DATA_VS_6_BASE_IDX 0 2179#define mmSPI_SHADER_USER_DATA_VS_7 0x0c53 2180#define mmSPI_SHADER_USER_DATA_VS_7_BASE_IDX 0 2181#define mmSPI_SHADER_USER_DATA_VS_8 0x0c54 2182#define mmSPI_SHADER_USER_DATA_VS_8_BASE_IDX 0 2183#define mmSPI_SHADER_USER_DATA_VS_9 0x0c55 2184#define mmSPI_SHADER_USER_DATA_VS_9_BASE_IDX 0 2185#define mmSPI_SHADER_USER_DATA_VS_10 0x0c56 2186#define mmSPI_SHADER_USER_DATA_VS_10_BASE_IDX 0 2187#define mmSPI_SHADER_USER_DATA_VS_11 0x0c57 2188#define mmSPI_SHADER_USER_DATA_VS_11_BASE_IDX 0 2189#define mmSPI_SHADER_USER_DATA_VS_12 0x0c58 2190#define mmSPI_SHADER_USER_DATA_VS_12_BASE_IDX 0 2191#define mmSPI_SHADER_USER_DATA_VS_13 0x0c59 2192#define mmSPI_SHADER_USER_DATA_VS_13_BASE_IDX 0 2193#define mmSPI_SHADER_USER_DATA_VS_14 0x0c5a 2194#define mmSPI_SHADER_USER_DATA_VS_14_BASE_IDX 0 2195#define mmSPI_SHADER_USER_DATA_VS_15 0x0c5b 2196#define mmSPI_SHADER_USER_DATA_VS_15_BASE_IDX 0 2197#define mmSPI_SHADER_USER_DATA_VS_16 0x0c5c 2198#define mmSPI_SHADER_USER_DATA_VS_16_BASE_IDX 0 2199#define mmSPI_SHADER_USER_DATA_VS_17 0x0c5d 2200#define mmSPI_SHADER_USER_DATA_VS_17_BASE_IDX 0 2201#define mmSPI_SHADER_USER_DATA_VS_18 0x0c5e 2202#define mmSPI_SHADER_USER_DATA_VS_18_BASE_IDX 0 2203#define mmSPI_SHADER_USER_DATA_VS_19 0x0c5f 2204#define mmSPI_SHADER_USER_DATA_VS_19_BASE_IDX 0 2205#define mmSPI_SHADER_USER_DATA_VS_20 0x0c60 2206#define mmSPI_SHADER_USER_DATA_VS_20_BASE_IDX 0 2207#define mmSPI_SHADER_USER_DATA_VS_21 0x0c61 2208#define mmSPI_SHADER_USER_DATA_VS_21_BASE_IDX 0 2209#define mmSPI_SHADER_USER_DATA_VS_22 0x0c62 2210#define mmSPI_SHADER_USER_DATA_VS_22_BASE_IDX 0 2211#define mmSPI_SHADER_USER_DATA_VS_23 0x0c63 2212#define mmSPI_SHADER_USER_DATA_VS_23_BASE_IDX 0 2213#define mmSPI_SHADER_USER_DATA_VS_24 0x0c64 2214#define mmSPI_SHADER_USER_DATA_VS_24_BASE_IDX 0 2215#define mmSPI_SHADER_USER_DATA_VS_25 0x0c65 2216#define mmSPI_SHADER_USER_DATA_VS_25_BASE_IDX 0 2217#define mmSPI_SHADER_USER_DATA_VS_26 0x0c66 2218#define mmSPI_SHADER_USER_DATA_VS_26_BASE_IDX 0 2219#define mmSPI_SHADER_USER_DATA_VS_27 0x0c67 2220#define mmSPI_SHADER_USER_DATA_VS_27_BASE_IDX 0 2221#define mmSPI_SHADER_USER_DATA_VS_28 0x0c68 2222#define mmSPI_SHADER_USER_DATA_VS_28_BASE_IDX 0 2223#define mmSPI_SHADER_USER_DATA_VS_29 0x0c69 2224#define mmSPI_SHADER_USER_DATA_VS_29_BASE_IDX 0 2225#define mmSPI_SHADER_USER_DATA_VS_30 0x0c6a 2226#define mmSPI_SHADER_USER_DATA_VS_30_BASE_IDX 0 2227#define mmSPI_SHADER_USER_DATA_VS_31 0x0c6b 2228#define mmSPI_SHADER_USER_DATA_VS_31_BASE_IDX 0 2229#define mmSPI_SHADER_PGM_RSRC2_GS_VS 0x0c7c 2230#define mmSPI_SHADER_PGM_RSRC2_GS_VS_BASE_IDX 0 2231#define mmSPI_SHADER_PGM_RSRC4_GS 0x0c81 2232#define mmSPI_SHADER_PGM_RSRC4_GS_BASE_IDX 0 2233#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS 0x0c82 2234#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX 0 2235#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS 0x0c83 2236#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX 0 2237#define mmSPI_SHADER_PGM_LO_ES 0x0c84 2238#define mmSPI_SHADER_PGM_LO_ES_BASE_IDX 0 2239#define mmSPI_SHADER_PGM_HI_ES 0x0c85 2240#define mmSPI_SHADER_PGM_HI_ES_BASE_IDX 0 2241#define mmSPI_SHADER_PGM_RSRC3_GS 0x0c87 2242#define mmSPI_SHADER_PGM_RSRC3_GS_BASE_IDX 0 2243#define mmSPI_SHADER_PGM_LO_GS 0x0c88 2244#define mmSPI_SHADER_PGM_LO_GS_BASE_IDX 0 2245#define mmSPI_SHADER_PGM_HI_GS 0x0c89 2246#define mmSPI_SHADER_PGM_HI_GS_BASE_IDX 0 2247#define mmSPI_SHADER_PGM_RSRC1_GS 0x0c8a 2248#define mmSPI_SHADER_PGM_RSRC1_GS_BASE_IDX 0 2249#define mmSPI_SHADER_PGM_RSRC2_GS 0x0c8b 2250#define mmSPI_SHADER_PGM_RSRC2_GS_BASE_IDX 0 2251#define mmSPI_SHADER_USER_DATA_ES_0 0x0ccc 2252#define mmSPI_SHADER_USER_DATA_ES_0_BASE_IDX 0 2253#define mmSPI_SHADER_USER_DATA_ES_1 0x0ccd 2254#define mmSPI_SHADER_USER_DATA_ES_1_BASE_IDX 0 2255#define mmSPI_SHADER_USER_DATA_ES_2 0x0cce 2256#define mmSPI_SHADER_USER_DATA_ES_2_BASE_IDX 0 2257#define mmSPI_SHADER_USER_DATA_ES_3 0x0ccf 2258#define mmSPI_SHADER_USER_DATA_ES_3_BASE_IDX 0 2259#define mmSPI_SHADER_USER_DATA_ES_4 0x0cd0 2260#define mmSPI_SHADER_USER_DATA_ES_4_BASE_IDX 0 2261#define mmSPI_SHADER_USER_DATA_ES_5 0x0cd1 2262#define mmSPI_SHADER_USER_DATA_ES_5_BASE_IDX 0 2263#define mmSPI_SHADER_USER_DATA_ES_6 0x0cd2 2264#define mmSPI_SHADER_USER_DATA_ES_6_BASE_IDX 0 2265#define mmSPI_SHADER_USER_DATA_ES_7 0x0cd3 2266#define mmSPI_SHADER_USER_DATA_ES_7_BASE_IDX 0 2267#define mmSPI_SHADER_USER_DATA_ES_8 0x0cd4 2268#define mmSPI_SHADER_USER_DATA_ES_8_BASE_IDX 0 2269#define mmSPI_SHADER_USER_DATA_ES_9 0x0cd5 2270#define mmSPI_SHADER_USER_DATA_ES_9_BASE_IDX 0 2271#define mmSPI_SHADER_USER_DATA_ES_10 0x0cd6 2272#define mmSPI_SHADER_USER_DATA_ES_10_BASE_IDX 0 2273#define mmSPI_SHADER_USER_DATA_ES_11 0x0cd7 2274#define mmSPI_SHADER_USER_DATA_ES_11_BASE_IDX 0 2275#define mmSPI_SHADER_USER_DATA_ES_12 0x0cd8 2276#define mmSPI_SHADER_USER_DATA_ES_12_BASE_IDX 0 2277#define mmSPI_SHADER_USER_DATA_ES_13 0x0cd9 2278#define mmSPI_SHADER_USER_DATA_ES_13_BASE_IDX 0 2279#define mmSPI_SHADER_USER_DATA_ES_14 0x0cda 2280#define mmSPI_SHADER_USER_DATA_ES_14_BASE_IDX 0 2281#define mmSPI_SHADER_USER_DATA_ES_15 0x0cdb 2282#define mmSPI_SHADER_USER_DATA_ES_15_BASE_IDX 0 2283#define mmSPI_SHADER_USER_DATA_ES_16 0x0cdc 2284#define mmSPI_SHADER_USER_DATA_ES_16_BASE_IDX 0 2285#define mmSPI_SHADER_USER_DATA_ES_17 0x0cdd 2286#define mmSPI_SHADER_USER_DATA_ES_17_BASE_IDX 0 2287#define mmSPI_SHADER_USER_DATA_ES_18 0x0cde 2288#define mmSPI_SHADER_USER_DATA_ES_18_BASE_IDX 0 2289#define mmSPI_SHADER_USER_DATA_ES_19 0x0cdf 2290#define mmSPI_SHADER_USER_DATA_ES_19_BASE_IDX 0 2291#define mmSPI_SHADER_USER_DATA_ES_20 0x0ce0 2292#define mmSPI_SHADER_USER_DATA_ES_20_BASE_IDX 0 2293#define mmSPI_SHADER_USER_DATA_ES_21 0x0ce1 2294#define mmSPI_SHADER_USER_DATA_ES_21_BASE_IDX 0 2295#define mmSPI_SHADER_USER_DATA_ES_22 0x0ce2 2296#define mmSPI_SHADER_USER_DATA_ES_22_BASE_IDX 0 2297#define mmSPI_SHADER_USER_DATA_ES_23 0x0ce3 2298#define mmSPI_SHADER_USER_DATA_ES_23_BASE_IDX 0 2299#define mmSPI_SHADER_USER_DATA_ES_24 0x0ce4 2300#define mmSPI_SHADER_USER_DATA_ES_24_BASE_IDX 0 2301#define mmSPI_SHADER_USER_DATA_ES_25 0x0ce5 2302#define mmSPI_SHADER_USER_DATA_ES_25_BASE_IDX 0 2303#define mmSPI_SHADER_USER_DATA_ES_26 0x0ce6 2304#define mmSPI_SHADER_USER_DATA_ES_26_BASE_IDX 0 2305#define mmSPI_SHADER_USER_DATA_ES_27 0x0ce7 2306#define mmSPI_SHADER_USER_DATA_ES_27_BASE_IDX 0 2307#define mmSPI_SHADER_USER_DATA_ES_28 0x0ce8 2308#define mmSPI_SHADER_USER_DATA_ES_28_BASE_IDX 0 2309#define mmSPI_SHADER_USER_DATA_ES_29 0x0ce9 2310#define mmSPI_SHADER_USER_DATA_ES_29_BASE_IDX 0 2311#define mmSPI_SHADER_USER_DATA_ES_30 0x0cea 2312#define mmSPI_SHADER_USER_DATA_ES_30_BASE_IDX 0 2313#define mmSPI_SHADER_USER_DATA_ES_31 0x0ceb 2314#define mmSPI_SHADER_USER_DATA_ES_31_BASE_IDX 0 2315#define mmSPI_SHADER_PGM_RSRC4_HS 0x0d01 2316#define mmSPI_SHADER_PGM_RSRC4_HS_BASE_IDX 0 2317#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS 0x0d02 2318#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX 0 2319#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS 0x0d03 2320#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX 0 2321#define mmSPI_SHADER_PGM_LO_LS 0x0d04 2322#define mmSPI_SHADER_PGM_LO_LS_BASE_IDX 0 2323#define mmSPI_SHADER_PGM_HI_LS 0x0d05 2324#define mmSPI_SHADER_PGM_HI_LS_BASE_IDX 0 2325#define mmSPI_SHADER_PGM_RSRC3_HS 0x0d07 2326#define mmSPI_SHADER_PGM_RSRC3_HS_BASE_IDX 0 2327#define mmSPI_SHADER_PGM_LO_HS 0x0d08 2328#define mmSPI_SHADER_PGM_LO_HS_BASE_IDX 0 2329#define mmSPI_SHADER_PGM_HI_HS 0x0d09 2330#define mmSPI_SHADER_PGM_HI_HS_BASE_IDX 0 2331#define mmSPI_SHADER_PGM_RSRC1_HS 0x0d0a 2332#define mmSPI_SHADER_PGM_RSRC1_HS_BASE_IDX 0 2333#define mmSPI_SHADER_PGM_RSRC2_HS 0x0d0b 2334#define mmSPI_SHADER_PGM_RSRC2_HS_BASE_IDX 0 2335#define mmSPI_SHADER_USER_DATA_LS_0 0x0d0c 2336#define mmSPI_SHADER_USER_DATA_LS_0_BASE_IDX 0 2337#define mmSPI_SHADER_USER_DATA_LS_1 0x0d0d 2338#define mmSPI_SHADER_USER_DATA_LS_1_BASE_IDX 0 2339#define mmSPI_SHADER_USER_DATA_LS_2 0x0d0e 2340#define mmSPI_SHADER_USER_DATA_LS_2_BASE_IDX 0 2341#define mmSPI_SHADER_USER_DATA_LS_3 0x0d0f 2342#define mmSPI_SHADER_USER_DATA_LS_3_BASE_IDX 0 2343#define mmSPI_SHADER_USER_DATA_LS_4 0x0d10 2344#define mmSPI_SHADER_USER_DATA_LS_4_BASE_IDX 0 2345#define mmSPI_SHADER_USER_DATA_LS_5 0x0d11 2346#define mmSPI_SHADER_USER_DATA_LS_5_BASE_IDX 0 2347#define mmSPI_SHADER_USER_DATA_LS_6 0x0d12 2348#define mmSPI_SHADER_USER_DATA_LS_6_BASE_IDX 0 2349#define mmSPI_SHADER_USER_DATA_LS_7 0x0d13 2350#define mmSPI_SHADER_USER_DATA_LS_7_BASE_IDX 0 2351#define mmSPI_SHADER_USER_DATA_LS_8 0x0d14 2352#define mmSPI_SHADER_USER_DATA_LS_8_BASE_IDX 0 2353#define mmSPI_SHADER_USER_DATA_LS_9 0x0d15 2354#define mmSPI_SHADER_USER_DATA_LS_9_BASE_IDX 0 2355#define mmSPI_SHADER_USER_DATA_LS_10 0x0d16 2356#define mmSPI_SHADER_USER_DATA_LS_10_BASE_IDX 0 2357#define mmSPI_SHADER_USER_DATA_LS_11 0x0d17 2358#define mmSPI_SHADER_USER_DATA_LS_11_BASE_IDX 0 2359#define mmSPI_SHADER_USER_DATA_LS_12 0x0d18 2360#define mmSPI_SHADER_USER_DATA_LS_12_BASE_IDX 0 2361#define mmSPI_SHADER_USER_DATA_LS_13 0x0d19 2362#define mmSPI_SHADER_USER_DATA_LS_13_BASE_IDX 0 2363#define mmSPI_SHADER_USER_DATA_LS_14 0x0d1a 2364#define mmSPI_SHADER_USER_DATA_LS_14_BASE_IDX 0 2365#define mmSPI_SHADER_USER_DATA_LS_15 0x0d1b 2366#define mmSPI_SHADER_USER_DATA_LS_15_BASE_IDX 0 2367#define mmSPI_SHADER_USER_DATA_LS_16 0x0d1c 2368#define mmSPI_SHADER_USER_DATA_LS_16_BASE_IDX 0 2369#define mmSPI_SHADER_USER_DATA_LS_17 0x0d1d 2370#define mmSPI_SHADER_USER_DATA_LS_17_BASE_IDX 0 2371#define mmSPI_SHADER_USER_DATA_LS_18 0x0d1e 2372#define mmSPI_SHADER_USER_DATA_LS_18_BASE_IDX 0 2373#define mmSPI_SHADER_USER_DATA_LS_19 0x0d1f 2374#define mmSPI_SHADER_USER_DATA_LS_19_BASE_IDX 0 2375#define mmSPI_SHADER_USER_DATA_LS_20 0x0d20 2376#define mmSPI_SHADER_USER_DATA_LS_20_BASE_IDX 0 2377#define mmSPI_SHADER_USER_DATA_LS_21 0x0d21 2378#define mmSPI_SHADER_USER_DATA_LS_21_BASE_IDX 0 2379#define mmSPI_SHADER_USER_DATA_LS_22 0x0d22 2380#define mmSPI_SHADER_USER_DATA_LS_22_BASE_IDX 0 2381#define mmSPI_SHADER_USER_DATA_LS_23 0x0d23 2382#define mmSPI_SHADER_USER_DATA_LS_23_BASE_IDX 0 2383#define mmSPI_SHADER_USER_DATA_LS_24 0x0d24 2384#define mmSPI_SHADER_USER_DATA_LS_24_BASE_IDX 0 2385#define mmSPI_SHADER_USER_DATA_LS_25 0x0d25 2386#define mmSPI_SHADER_USER_DATA_LS_25_BASE_IDX 0 2387#define mmSPI_SHADER_USER_DATA_LS_26 0x0d26 2388#define mmSPI_SHADER_USER_DATA_LS_26_BASE_IDX 0 2389#define mmSPI_SHADER_USER_DATA_LS_27 0x0d27 2390#define mmSPI_SHADER_USER_DATA_LS_27_BASE_IDX 0 2391#define mmSPI_SHADER_USER_DATA_LS_28 0x0d28 2392#define mmSPI_SHADER_USER_DATA_LS_28_BASE_IDX 0 2393#define mmSPI_SHADER_USER_DATA_LS_29 0x0d29 2394#define mmSPI_SHADER_USER_DATA_LS_29_BASE_IDX 0 2395#define mmSPI_SHADER_USER_DATA_LS_30 0x0d2a 2396#define mmSPI_SHADER_USER_DATA_LS_30_BASE_IDX 0 2397#define mmSPI_SHADER_USER_DATA_LS_31 0x0d2b 2398#define mmSPI_SHADER_USER_DATA_LS_31_BASE_IDX 0 2399#define mmSPI_SHADER_USER_DATA_COMMON_0 0x0d4c 2400#define mmSPI_SHADER_USER_DATA_COMMON_0_BASE_IDX 0 2401#define mmSPI_SHADER_USER_DATA_COMMON_1 0x0d4d 2402#define mmSPI_SHADER_USER_DATA_COMMON_1_BASE_IDX 0 2403#define mmSPI_SHADER_USER_DATA_COMMON_2 0x0d4e 2404#define mmSPI_SHADER_USER_DATA_COMMON_2_BASE_IDX 0 2405#define mmSPI_SHADER_USER_DATA_COMMON_3 0x0d4f 2406#define mmSPI_SHADER_USER_DATA_COMMON_3_BASE_IDX 0 2407#define mmSPI_SHADER_USER_DATA_COMMON_4 0x0d50 2408#define mmSPI_SHADER_USER_DATA_COMMON_4_BASE_IDX 0 2409#define mmSPI_SHADER_USER_DATA_COMMON_5 0x0d51 2410#define mmSPI_SHADER_USER_DATA_COMMON_5_BASE_IDX 0 2411#define mmSPI_SHADER_USER_DATA_COMMON_6 0x0d52 2412#define mmSPI_SHADER_USER_DATA_COMMON_6_BASE_IDX 0 2413#define mmSPI_SHADER_USER_DATA_COMMON_7 0x0d53 2414#define mmSPI_SHADER_USER_DATA_COMMON_7_BASE_IDX 0 2415#define mmSPI_SHADER_USER_DATA_COMMON_8 0x0d54 2416#define mmSPI_SHADER_USER_DATA_COMMON_8_BASE_IDX 0 2417#define mmSPI_SHADER_USER_DATA_COMMON_9 0x0d55 2418#define mmSPI_SHADER_USER_DATA_COMMON_9_BASE_IDX 0 2419#define mmSPI_SHADER_USER_DATA_COMMON_10 0x0d56 2420#define mmSPI_SHADER_USER_DATA_COMMON_10_BASE_IDX 0 2421#define mmSPI_SHADER_USER_DATA_COMMON_11 0x0d57 2422#define mmSPI_SHADER_USER_DATA_COMMON_11_BASE_IDX 0 2423#define mmSPI_SHADER_USER_DATA_COMMON_12 0x0d58 2424#define mmSPI_SHADER_USER_DATA_COMMON_12_BASE_IDX 0 2425#define mmSPI_SHADER_USER_DATA_COMMON_13 0x0d59 2426#define mmSPI_SHADER_USER_DATA_COMMON_13_BASE_IDX 0 2427#define mmSPI_SHADER_USER_DATA_COMMON_14 0x0d5a 2428#define mmSPI_SHADER_USER_DATA_COMMON_14_BASE_IDX 0 2429#define mmSPI_SHADER_USER_DATA_COMMON_15 0x0d5b 2430#define mmSPI_SHADER_USER_DATA_COMMON_15_BASE_IDX 0 2431#define mmSPI_SHADER_USER_DATA_COMMON_16 0x0d5c 2432#define mmSPI_SHADER_USER_DATA_COMMON_16_BASE_IDX 0 2433#define mmSPI_SHADER_USER_DATA_COMMON_17 0x0d5d 2434#define mmSPI_SHADER_USER_DATA_COMMON_17_BASE_IDX 0 2435#define mmSPI_SHADER_USER_DATA_COMMON_18 0x0d5e 2436#define mmSPI_SHADER_USER_DATA_COMMON_18_BASE_IDX 0 2437#define mmSPI_SHADER_USER_DATA_COMMON_19 0x0d5f 2438#define mmSPI_SHADER_USER_DATA_COMMON_19_BASE_IDX 0 2439#define mmSPI_SHADER_USER_DATA_COMMON_20 0x0d60 2440#define mmSPI_SHADER_USER_DATA_COMMON_20_BASE_IDX 0 2441#define mmSPI_SHADER_USER_DATA_COMMON_21 0x0d61 2442#define mmSPI_SHADER_USER_DATA_COMMON_21_BASE_IDX 0 2443#define mmSPI_SHADER_USER_DATA_COMMON_22 0x0d62 2444#define mmSPI_SHADER_USER_DATA_COMMON_22_BASE_IDX 0 2445#define mmSPI_SHADER_USER_DATA_COMMON_23 0x0d63 2446#define mmSPI_SHADER_USER_DATA_COMMON_23_BASE_IDX 0 2447#define mmSPI_SHADER_USER_DATA_COMMON_24 0x0d64 2448#define mmSPI_SHADER_USER_DATA_COMMON_24_BASE_IDX 0 2449#define mmSPI_SHADER_USER_DATA_COMMON_25 0x0d65 2450#define mmSPI_SHADER_USER_DATA_COMMON_25_BASE_IDX 0 2451#define mmSPI_SHADER_USER_DATA_COMMON_26 0x0d66 2452#define mmSPI_SHADER_USER_DATA_COMMON_26_BASE_IDX 0 2453#define mmSPI_SHADER_USER_DATA_COMMON_27 0x0d67 2454#define mmSPI_SHADER_USER_DATA_COMMON_27_BASE_IDX 0 2455#define mmSPI_SHADER_USER_DATA_COMMON_28 0x0d68 2456#define mmSPI_SHADER_USER_DATA_COMMON_28_BASE_IDX 0 2457#define mmSPI_SHADER_USER_DATA_COMMON_29 0x0d69 2458#define mmSPI_SHADER_USER_DATA_COMMON_29_BASE_IDX 0 2459#define mmSPI_SHADER_USER_DATA_COMMON_30 0x0d6a 2460#define mmSPI_SHADER_USER_DATA_COMMON_30_BASE_IDX 0 2461#define mmSPI_SHADER_USER_DATA_COMMON_31 0x0d6b 2462#define mmSPI_SHADER_USER_DATA_COMMON_31_BASE_IDX 0 2463#define mmCOMPUTE_DISPATCH_INITIATOR 0x0e00 2464#define mmCOMPUTE_DISPATCH_INITIATOR_BASE_IDX 0 2465#define mmCOMPUTE_DIM_X 0x0e01 2466#define mmCOMPUTE_DIM_X_BASE_IDX 0 2467#define mmCOMPUTE_DIM_Y 0x0e02 2468#define mmCOMPUTE_DIM_Y_BASE_IDX 0 2469#define mmCOMPUTE_DIM_Z 0x0e03 2470#define mmCOMPUTE_DIM_Z_BASE_IDX 0 2471#define mmCOMPUTE_START_X 0x0e04 2472#define mmCOMPUTE_START_X_BASE_IDX 0 2473#define mmCOMPUTE_START_Y 0x0e05 2474#define mmCOMPUTE_START_Y_BASE_IDX 0 2475#define mmCOMPUTE_START_Z 0x0e06 2476#define mmCOMPUTE_START_Z_BASE_IDX 0 2477#define mmCOMPUTE_NUM_THREAD_X 0x0e07 2478#define mmCOMPUTE_NUM_THREAD_X_BASE_IDX 0 2479#define mmCOMPUTE_NUM_THREAD_Y 0x0e08 2480#define mmCOMPUTE_NUM_THREAD_Y_BASE_IDX 0 2481#define mmCOMPUTE_NUM_THREAD_Z 0x0e09 2482#define mmCOMPUTE_NUM_THREAD_Z_BASE_IDX 0 2483#define mmCOMPUTE_PIPELINESTAT_ENABLE 0x0e0a 2484#define mmCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX 0 2485#define mmCOMPUTE_PERFCOUNT_ENABLE 0x0e0b 2486#define mmCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX 0 2487#define mmCOMPUTE_PGM_LO 0x0e0c 2488#define mmCOMPUTE_PGM_LO_BASE_IDX 0 2489#define mmCOMPUTE_PGM_HI 0x0e0d 2490#define mmCOMPUTE_PGM_HI_BASE_IDX 0 2491#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO 0x0e0e 2492#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX 0 2493#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI 0x0e0f 2494#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX 0 2495#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO 0x0e10 2496#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX 0 2497#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI 0x0e11 2498#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX 0 2499#define mmCOMPUTE_PGM_RSRC1 0x0e12 2500#define mmCOMPUTE_PGM_RSRC1_BASE_IDX 0 2501#define mmCOMPUTE_PGM_RSRC2 0x0e13 2502#define mmCOMPUTE_PGM_RSRC2_BASE_IDX 0 2503#define mmCOMPUTE_VMID 0x0e14 2504#define mmCOMPUTE_VMID_BASE_IDX 0 2505#define mmCOMPUTE_RESOURCE_LIMITS 0x0e15 2506#define mmCOMPUTE_RESOURCE_LIMITS_BASE_IDX 0 2507#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x0e16 2508#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX 0 2509#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x0e17 2510#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX 0 2511#define mmCOMPUTE_TMPRING_SIZE 0x0e18 2512#define mmCOMPUTE_TMPRING_SIZE_BASE_IDX 0 2513#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2 0x0e19 2514#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX 0 2515#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0x0e1a 2516#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX 0 2517#define mmCOMPUTE_RESTART_X 0x0e1b 2518#define mmCOMPUTE_RESTART_X_BASE_IDX 0 2519#define mmCOMPUTE_RESTART_Y 0x0e1c 2520#define mmCOMPUTE_RESTART_Y_BASE_IDX 0 2521#define mmCOMPUTE_RESTART_Z 0x0e1d 2522#define mmCOMPUTE_RESTART_Z_BASE_IDX 0 2523#define mmCOMPUTE_THREAD_TRACE_ENABLE 0x0e1e 2524#define mmCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX 0 2525#define mmCOMPUTE_MISC_RESERVED 0x0e1f 2526#define mmCOMPUTE_MISC_RESERVED_BASE_IDX 0 2527#define mmCOMPUTE_DISPATCH_ID 0x0e20 2528#define mmCOMPUTE_DISPATCH_ID_BASE_IDX 0 2529#define mmCOMPUTE_THREADGROUP_ID 0x0e21 2530#define mmCOMPUTE_THREADGROUP_ID_BASE_IDX 0 2531#define mmCOMPUTE_RELAUNCH 0x0e22 2532#define mmCOMPUTE_RELAUNCH_BASE_IDX 0 2533#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO 0x0e23 2534#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX 0 2535#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI 0x0e24 2536#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX 0 2537#define mmCOMPUTE_USER_DATA_0 0x0e40 2538#define mmCOMPUTE_USER_DATA_0_BASE_IDX 0 2539#define mmCOMPUTE_USER_DATA_1 0x0e41 2540#define mmCOMPUTE_USER_DATA_1_BASE_IDX 0 2541#define mmCOMPUTE_USER_DATA_2 0x0e42 2542#define mmCOMPUTE_USER_DATA_2_BASE_IDX 0 2543#define mmCOMPUTE_USER_DATA_3 0x0e43 2544#define mmCOMPUTE_USER_DATA_3_BASE_IDX 0 2545#define mmCOMPUTE_USER_DATA_4 0x0e44 2546#define mmCOMPUTE_USER_DATA_4_BASE_IDX 0 2547#define mmCOMPUTE_USER_DATA_5 0x0e45 2548#define mmCOMPUTE_USER_DATA_5_BASE_IDX 0 2549#define mmCOMPUTE_USER_DATA_6 0x0e46 2550#define mmCOMPUTE_USER_DATA_6_BASE_IDX 0 2551#define mmCOMPUTE_USER_DATA_7 0x0e47 2552#define mmCOMPUTE_USER_DATA_7_BASE_IDX 0 2553#define mmCOMPUTE_USER_DATA_8 0x0e48 2554#define mmCOMPUTE_USER_DATA_8_BASE_IDX 0 2555#define mmCOMPUTE_USER_DATA_9 0x0e49 2556#define mmCOMPUTE_USER_DATA_9_BASE_IDX 0 2557#define mmCOMPUTE_USER_DATA_10 0x0e4a 2558#define mmCOMPUTE_USER_DATA_10_BASE_IDX 0 2559#define mmCOMPUTE_USER_DATA_11 0x0e4b 2560#define mmCOMPUTE_USER_DATA_11_BASE_IDX 0 2561#define mmCOMPUTE_USER_DATA_12 0x0e4c 2562#define mmCOMPUTE_USER_DATA_12_BASE_IDX 0 2563#define mmCOMPUTE_USER_DATA_13 0x0e4d 2564#define mmCOMPUTE_USER_DATA_13_BASE_IDX 0 2565#define mmCOMPUTE_USER_DATA_14 0x0e4e 2566#define mmCOMPUTE_USER_DATA_14_BASE_IDX 0 2567#define mmCOMPUTE_USER_DATA_15 0x0e4f 2568#define mmCOMPUTE_USER_DATA_15_BASE_IDX 0 2569#define mmCOMPUTE_NOWHERE 0x0e7f 2570#define mmCOMPUTE_NOWHERE_BASE_IDX 0 2571 2572 2573// addressBlock: gc_cppdec 2574// base address: 0xc080 2575#define mmCP_DFY_CNTL 0x1020 2576#define mmCP_DFY_CNTL_BASE_IDX 0 2577#define mmCP_DFY_STAT 0x1021 2578#define mmCP_DFY_STAT_BASE_IDX 0 2579#define mmCP_DFY_ADDR_HI 0x1022 2580#define mmCP_DFY_ADDR_HI_BASE_IDX 0 2581#define mmCP_DFY_ADDR_LO 0x1023 2582#define mmCP_DFY_ADDR_LO_BASE_IDX 0 2583#define mmCP_DFY_DATA_0 0x1024 2584#define mmCP_DFY_DATA_0_BASE_IDX 0 2585#define mmCP_DFY_DATA_1 0x1025 2586#define mmCP_DFY_DATA_1_BASE_IDX 0 2587#define mmCP_DFY_DATA_2 0x1026 2588#define mmCP_DFY_DATA_2_BASE_IDX 0 2589#define mmCP_DFY_DATA_3 0x1027 2590#define mmCP_DFY_DATA_3_BASE_IDX 0 2591#define mmCP_DFY_DATA_4 0x1028 2592#define mmCP_DFY_DATA_4_BASE_IDX 0 2593#define mmCP_DFY_DATA_5 0x1029 2594#define mmCP_DFY_DATA_5_BASE_IDX 0 2595#define mmCP_DFY_DATA_6 0x102a 2596#define mmCP_DFY_DATA_6_BASE_IDX 0 2597#define mmCP_DFY_DATA_7 0x102b 2598#define mmCP_DFY_DATA_7_BASE_IDX 0 2599#define mmCP_DFY_DATA_8 0x102c 2600#define mmCP_DFY_DATA_8_BASE_IDX 0 2601#define mmCP_DFY_DATA_9 0x102d 2602#define mmCP_DFY_DATA_9_BASE_IDX 0 2603#define mmCP_DFY_DATA_10 0x102e 2604#define mmCP_DFY_DATA_10_BASE_IDX 0 2605#define mmCP_DFY_DATA_11 0x102f 2606#define mmCP_DFY_DATA_11_BASE_IDX 0 2607#define mmCP_DFY_DATA_12 0x1030 2608#define mmCP_DFY_DATA_12_BASE_IDX 0 2609#define mmCP_DFY_DATA_13 0x1031 2610#define mmCP_DFY_DATA_13_BASE_IDX 0 2611#define mmCP_DFY_DATA_14 0x1032 2612#define mmCP_DFY_DATA_14_BASE_IDX 0 2613#define mmCP_DFY_DATA_15 0x1033 2614#define mmCP_DFY_DATA_15_BASE_IDX 0 2615#define mmCP_DFY_CMD 0x1034 2616#define mmCP_DFY_CMD_BASE_IDX 0 2617#define mmCP_EOPQ_WAIT_TIME 0x1035 2618#define mmCP_EOPQ_WAIT_TIME_BASE_IDX 0 2619#define mmCP_CPC_MGCG_SYNC_CNTL 0x1036 2620#define mmCP_CPC_MGCG_SYNC_CNTL_BASE_IDX 0 2621#define mmCPC_INT_INFO 0x1037 2622#define mmCPC_INT_INFO_BASE_IDX 0 2623#define mmCP_VIRT_STATUS 0x1038 2624#define mmCP_VIRT_STATUS_BASE_IDX 0 2625#define mmCPC_INT_ADDR 0x1039 2626#define mmCPC_INT_ADDR_BASE_IDX 0 2627#define mmCPC_INT_PASID 0x103a 2628#define mmCPC_INT_PASID_BASE_IDX 0 2629#define mmCP_GFX_ERROR 0x103b 2630#define mmCP_GFX_ERROR_BASE_IDX 0 2631#define mmCPG_UTCL1_CNTL 0x103c 2632#define mmCPG_UTCL1_CNTL_BASE_IDX 0 2633#define mmCPC_UTCL1_CNTL 0x103d 2634#define mmCPC_UTCL1_CNTL_BASE_IDX 0 2635#define mmCPF_UTCL1_CNTL 0x103e 2636#define mmCPF_UTCL1_CNTL_BASE_IDX 0 2637#define mmCP_AQL_SMM_STATUS 0x103f 2638#define mmCP_AQL_SMM_STATUS_BASE_IDX 0 2639#define mmCP_RB0_BASE 0x1040 2640#define mmCP_RB0_BASE_BASE_IDX 0 2641#define mmCP_RB_BASE 0x1040 2642#define mmCP_RB_BASE_BASE_IDX 0 2643#define mmCP_RB0_CNTL 0x1041 2644#define mmCP_RB0_CNTL_BASE_IDX 0 2645#define mmCP_RB_CNTL 0x1041 2646#define mmCP_RB_CNTL_BASE_IDX 0 2647#define mmCP_RB_RPTR_WR 0x1042 2648#define mmCP_RB_RPTR_WR_BASE_IDX 0 2649#define mmCP_RB0_RPTR_ADDR 0x1043 2650#define mmCP_RB0_RPTR_ADDR_BASE_IDX 0 2651#define mmCP_RB_RPTR_ADDR 0x1043 2652#define mmCP_RB_RPTR_ADDR_BASE_IDX 0 2653#define mmCP_RB0_RPTR_ADDR_HI 0x1044 2654#define mmCP_RB0_RPTR_ADDR_HI_BASE_IDX 0 2655#define mmCP_RB_RPTR_ADDR_HI 0x1044 2656#define mmCP_RB_RPTR_ADDR_HI_BASE_IDX 0 2657#define mmCP_RB0_BUFSZ_MASK 0x1045 2658#define mmCP_RB0_BUFSZ_MASK_BASE_IDX 0 2659#define mmCP_RB_BUFSZ_MASK 0x1045 2660#define mmCP_RB_BUFSZ_MASK_BASE_IDX 0 2661#define mmCP_RB_WPTR_POLL_ADDR_LO 0x1046 2662#define mmCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 2663#define mmCP_RB_WPTR_POLL_ADDR_HI 0x1047 2664#define mmCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 2665#define mmGC_PRIV_MODE 0x1048 2666#define mmGC_PRIV_MODE_BASE_IDX 0 2667#define mmCP_INT_CNTL 0x1049 2668#define mmCP_INT_CNTL_BASE_IDX 0 2669#define mmCP_INT_STATUS 0x104a 2670#define mmCP_INT_STATUS_BASE_IDX 0 2671#define mmCP_DEVICE_ID 0x104b 2672#define mmCP_DEVICE_ID_BASE_IDX 0 2673#define mmCP_ME0_PIPE_PRIORITY_CNTS 0x104c 2674#define mmCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX 0 2675#define mmCP_RING_PRIORITY_CNTS 0x104c 2676#define mmCP_RING_PRIORITY_CNTS_BASE_IDX 0 2677#define mmCP_ME0_PIPE0_PRIORITY 0x104d 2678#define mmCP_ME0_PIPE0_PRIORITY_BASE_IDX 0 2679#define mmCP_RING0_PRIORITY 0x104d 2680#define mmCP_RING0_PRIORITY_BASE_IDX 0 2681#define mmCP_ME0_PIPE1_PRIORITY 0x104e 2682#define mmCP_ME0_PIPE1_PRIORITY_BASE_IDX 0 2683#define mmCP_RING1_PRIORITY 0x104e 2684#define mmCP_RING1_PRIORITY_BASE_IDX 0 2685#define mmCP_ME0_PIPE2_PRIORITY 0x104f 2686#define mmCP_ME0_PIPE2_PRIORITY_BASE_IDX 0 2687#define mmCP_RING2_PRIORITY 0x104f 2688#define mmCP_RING2_PRIORITY_BASE_IDX 0 2689#define mmCP_FATAL_ERROR 0x1050 2690#define mmCP_FATAL_ERROR_BASE_IDX 0 2691#define mmCP_RB_VMID 0x1051 2692#define mmCP_RB_VMID_BASE_IDX 0 2693#define mmCP_ME0_PIPE0_VMID 0x1052 2694#define mmCP_ME0_PIPE0_VMID_BASE_IDX 0 2695#define mmCP_ME0_PIPE1_VMID 0x1053 2696#define mmCP_ME0_PIPE1_VMID_BASE_IDX 0 2697#define mmCP_RB0_WPTR 0x1054 2698#define mmCP_RB0_WPTR_BASE_IDX 0 2699#define mmCP_RB_WPTR 0x1054 2700#define mmCP_RB_WPTR_BASE_IDX 0 2701#define mmCP_RB0_WPTR_HI 0x1055 2702#define mmCP_RB0_WPTR_HI_BASE_IDX 0 2703#define mmCP_RB_WPTR_HI 0x1055 2704#define mmCP_RB_WPTR_HI_BASE_IDX 0 2705#define mmCP_RB1_WPTR 0x1056 2706#define mmCP_RB1_WPTR_BASE_IDX 0 2707#define mmCP_RB1_WPTR_HI 0x1057 2708#define mmCP_RB1_WPTR_HI_BASE_IDX 0 2709#define mmCP_RB2_WPTR 0x1058 2710#define mmCP_RB2_WPTR_BASE_IDX 0 2711#define mmCP_RB_DOORBELL_CONTROL 0x1059 2712#define mmCP_RB_DOORBELL_CONTROL_BASE_IDX 0 2713#define mmCP_RB_DOORBELL_RANGE_LOWER 0x105a 2714#define mmCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX 0 2715#define mmCP_RB_DOORBELL_RANGE_UPPER 0x105b 2716#define mmCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX 0 2717#define mmCP_MEC_DOORBELL_RANGE_LOWER 0x105c 2718#define mmCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX 0 2719#define mmCP_MEC_DOORBELL_RANGE_UPPER 0x105d 2720#define mmCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX 0 2721#define mmCPG_UTCL1_ERROR 0x105e 2722#define mmCPG_UTCL1_ERROR_BASE_IDX 0 2723#define mmCPC_UTCL1_ERROR 0x105f 2724#define mmCPC_UTCL1_ERROR_BASE_IDX 0 2725#define mmCP_RB1_BASE 0x1060 2726#define mmCP_RB1_BASE_BASE_IDX 0 2727#define mmCP_RB1_CNTL 0x1061 2728#define mmCP_RB1_CNTL_BASE_IDX 0 2729#define mmCP_RB1_RPTR_ADDR 0x1062 2730#define mmCP_RB1_RPTR_ADDR_BASE_IDX 0 2731#define mmCP_RB1_RPTR_ADDR_HI 0x1063 2732#define mmCP_RB1_RPTR_ADDR_HI_BASE_IDX 0 2733#define mmCP_RB2_BASE 0x1065 2734#define mmCP_RB2_BASE_BASE_IDX 0 2735#define mmCP_RB2_CNTL 0x1066 2736#define mmCP_RB2_CNTL_BASE_IDX 0 2737#define mmCP_RB2_RPTR_ADDR 0x1067 2738#define mmCP_RB2_RPTR_ADDR_BASE_IDX 0 2739#define mmCP_RB2_RPTR_ADDR_HI 0x1068 2740#define mmCP_RB2_RPTR_ADDR_HI_BASE_IDX 0 2741#define mmCP_RB0_ACTIVE 0x1069 2742#define mmCP_RB0_ACTIVE_BASE_IDX 0 2743#define mmCP_RB_ACTIVE 0x1069 2744#define mmCP_RB_ACTIVE_BASE_IDX 0 2745#define mmCP_INT_CNTL_RING0 0x106a 2746#define mmCP_INT_CNTL_RING0_BASE_IDX 0 2747#define mmCP_INT_CNTL_RING1 0x106b 2748#define mmCP_INT_CNTL_RING1_BASE_IDX 0 2749#define mmCP_INT_CNTL_RING2 0x106c 2750#define mmCP_INT_CNTL_RING2_BASE_IDX 0 2751#define mmCP_INT_STATUS_RING0 0x106d 2752#define mmCP_INT_STATUS_RING0_BASE_IDX 0 2753#define mmCP_INT_STATUS_RING1 0x106e 2754#define mmCP_INT_STATUS_RING1_BASE_IDX 0 2755#define mmCP_INT_STATUS_RING2 0x106f 2756#define mmCP_INT_STATUS_RING2_BASE_IDX 0 2757#define mmCP_PWR_CNTL 0x1078 2758#define mmCP_PWR_CNTL_BASE_IDX 0 2759#define mmCP_MEM_SLP_CNTL 0x1079 2760#define mmCP_MEM_SLP_CNTL_BASE_IDX 0 2761#define mmCP_ECC_FIRSTOCCURRENCE 0x107a 2762#define mmCP_ECC_FIRSTOCCURRENCE_BASE_IDX 0 2763#define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x107b 2764#define mmCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX 0 2765#define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x107c 2766#define mmCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX 0 2767#define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x107d 2768#define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0 2769#define mmGB_EDC_MODE 0x107e 2770#define mmGB_EDC_MODE_BASE_IDX 0 2771#define mmCP_PQ_WPTR_POLL_CNTL 0x1083 2772#define mmCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0 2773#define mmCP_PQ_WPTR_POLL_CNTL1 0x1084 2774#define mmCP_PQ_WPTR_POLL_CNTL1_BASE_IDX 0 2775#define mmCP_ME1_PIPE0_INT_CNTL 0x1085 2776#define mmCP_ME1_PIPE0_INT_CNTL_BASE_IDX 0 2777#define mmCP_ME1_PIPE1_INT_CNTL 0x1086 2778#define mmCP_ME1_PIPE1_INT_CNTL_BASE_IDX 0 2779#define mmCP_ME1_PIPE2_INT_CNTL 0x1087 2780#define mmCP_ME1_PIPE2_INT_CNTL_BASE_IDX 0 2781#define mmCP_ME1_PIPE3_INT_CNTL 0x1088 2782#define mmCP_ME1_PIPE3_INT_CNTL_BASE_IDX 0 2783#define mmCP_ME2_PIPE0_INT_CNTL 0x1089 2784#define mmCP_ME2_PIPE0_INT_CNTL_BASE_IDX 0 2785#define mmCP_ME2_PIPE1_INT_CNTL 0x108a 2786#define mmCP_ME2_PIPE1_INT_CNTL_BASE_IDX 0 2787#define mmCP_ME2_PIPE2_INT_CNTL 0x108b 2788#define mmCP_ME2_PIPE2_INT_CNTL_BASE_IDX 0 2789#define mmCP_ME2_PIPE3_INT_CNTL 0x108c 2790#define mmCP_ME2_PIPE3_INT_CNTL_BASE_IDX 0 2791#define mmCP_ME1_PIPE0_INT_STATUS 0x108d 2792#define mmCP_ME1_PIPE0_INT_STATUS_BASE_IDX 0 2793#define mmCP_ME1_PIPE1_INT_STATUS 0x108e 2794#define mmCP_ME1_PIPE1_INT_STATUS_BASE_IDX 0 2795#define mmCP_ME1_PIPE2_INT_STATUS 0x108f 2796#define mmCP_ME1_PIPE2_INT_STATUS_BASE_IDX 0 2797#define mmCP_ME1_PIPE3_INT_STATUS 0x1090 2798#define mmCP_ME1_PIPE3_INT_STATUS_BASE_IDX 0 2799#define mmCP_ME2_PIPE0_INT_STATUS 0x1091 2800#define mmCP_ME2_PIPE0_INT_STATUS_BASE_IDX 0 2801#define mmCP_ME2_PIPE1_INT_STATUS 0x1092 2802#define mmCP_ME2_PIPE1_INT_STATUS_BASE_IDX 0 2803#define mmCP_ME2_PIPE2_INT_STATUS 0x1093 2804#define mmCP_ME2_PIPE2_INT_STATUS_BASE_IDX 0 2805#define mmCP_ME2_PIPE3_INT_STATUS 0x1094 2806#define mmCP_ME2_PIPE3_INT_STATUS_BASE_IDX 0 2807#define mmCC_GC_EDC_CONFIG 0x1098 2808#define mmCC_GC_EDC_CONFIG_BASE_IDX 0 2809#define mmCP_ME1_PIPE_PRIORITY_CNTS 0x1099 2810#define mmCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX 0 2811#define mmCP_ME1_PIPE0_PRIORITY 0x109a 2812#define mmCP_ME1_PIPE0_PRIORITY_BASE_IDX 0 2813#define mmCP_ME1_PIPE1_PRIORITY 0x109b 2814#define mmCP_ME1_PIPE1_PRIORITY_BASE_IDX 0 2815#define mmCP_ME1_PIPE2_PRIORITY 0x109c 2816#define mmCP_ME1_PIPE2_PRIORITY_BASE_IDX 0 2817#define mmCP_ME1_PIPE3_PRIORITY 0x109d 2818#define mmCP_ME1_PIPE3_PRIORITY_BASE_IDX 0 2819#define mmCP_ME2_PIPE_PRIORITY_CNTS 0x109e 2820#define mmCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX 0 2821#define mmCP_ME2_PIPE0_PRIORITY 0x109f 2822#define mmCP_ME2_PIPE0_PRIORITY_BASE_IDX 0 2823#define mmCP_ME2_PIPE1_PRIORITY 0x10a0 2824#define mmCP_ME2_PIPE1_PRIORITY_BASE_IDX 0 2825#define mmCP_ME2_PIPE2_PRIORITY 0x10a1 2826#define mmCP_ME2_PIPE2_PRIORITY_BASE_IDX 0 2827#define mmCP_ME2_PIPE3_PRIORITY 0x10a2 2828#define mmCP_ME2_PIPE3_PRIORITY_BASE_IDX 0 2829#define mmCP_CE_PRGRM_CNTR_START 0x10a3 2830#define mmCP_CE_PRGRM_CNTR_START_BASE_IDX 0 2831#define mmCP_PFP_PRGRM_CNTR_START 0x10a4 2832#define mmCP_PFP_PRGRM_CNTR_START_BASE_IDX 0 2833#define mmCP_ME_PRGRM_CNTR_START 0x10a5 2834#define mmCP_ME_PRGRM_CNTR_START_BASE_IDX 0 2835#define mmCP_MEC1_PRGRM_CNTR_START 0x10a6 2836#define mmCP_MEC1_PRGRM_CNTR_START_BASE_IDX 0 2837#define mmCP_MEC2_PRGRM_CNTR_START 0x10a7 2838#define mmCP_MEC2_PRGRM_CNTR_START_BASE_IDX 0 2839#define mmCP_CE_INTR_ROUTINE_START 0x10a8 2840#define mmCP_CE_INTR_ROUTINE_START_BASE_IDX 0 2841#define mmCP_PFP_INTR_ROUTINE_START 0x10a9 2842#define mmCP_PFP_INTR_ROUTINE_START_BASE_IDX 0 2843#define mmCP_ME_INTR_ROUTINE_START 0x10aa 2844#define mmCP_ME_INTR_ROUTINE_START_BASE_IDX 0 2845#define mmCP_MEC1_INTR_ROUTINE_START 0x10ab 2846#define mmCP_MEC1_INTR_ROUTINE_START_BASE_IDX 0 2847#define mmCP_MEC2_INTR_ROUTINE_START 0x10ac 2848#define mmCP_MEC2_INTR_ROUTINE_START_BASE_IDX 0 2849#define mmCP_CONTEXT_CNTL 0x10ad 2850#define mmCP_CONTEXT_CNTL_BASE_IDX 0 2851#define mmCP_MAX_CONTEXT 0x10ae 2852#define mmCP_MAX_CONTEXT_BASE_IDX 0 2853#define mmCP_IQ_WAIT_TIME1 0x10af 2854#define mmCP_IQ_WAIT_TIME1_BASE_IDX 0 2855#define mmCP_IQ_WAIT_TIME2 0x10b0 2856#define mmCP_IQ_WAIT_TIME2_BASE_IDX 0 2857#define mmCP_RB0_BASE_HI 0x10b1 2858#define mmCP_RB0_BASE_HI_BASE_IDX 0 2859#define mmCP_RB1_BASE_HI 0x10b2 2860#define mmCP_RB1_BASE_HI_BASE_IDX 0 2861#define mmCP_VMID_RESET 0x10b3 2862#define mmCP_VMID_RESET_BASE_IDX 0 2863#define mmCPC_INT_CNTL 0x10b4 2864#define mmCPC_INT_CNTL_BASE_IDX 0 2865#define mmCPC_INT_STATUS 0x10b5 2866#define mmCPC_INT_STATUS_BASE_IDX 0 2867#define mmCP_VMID_PREEMPT 0x10b6 2868#define mmCP_VMID_PREEMPT_BASE_IDX 0 2869#define mmCPC_INT_CNTX_ID 0x10b7 2870#define mmCPC_INT_CNTX_ID_BASE_IDX 0 2871#define mmCP_PQ_STATUS 0x10b8 2872#define mmCP_PQ_STATUS_BASE_IDX 0 2873#define mmCP_CPC_IC_BASE_LO 0x10b9 2874#define mmCP_CPC_IC_BASE_LO_BASE_IDX 0 2875#define mmCP_CPC_IC_BASE_HI 0x10ba 2876#define mmCP_CPC_IC_BASE_HI_BASE_IDX 0 2877#define mmCP_CPC_IC_BASE_CNTL 0x10bb 2878#define mmCP_CPC_IC_BASE_CNTL_BASE_IDX 0 2879#define mmCP_CPC_IC_OP_CNTL 0x10bc 2880#define mmCP_CPC_IC_OP_CNTL_BASE_IDX 0 2881#define mmCP_MEC1_F32_INT_DIS 0x10bd 2882#define mmCP_MEC1_F32_INT_DIS_BASE_IDX 0 2883#define mmCP_MEC2_F32_INT_DIS 0x10be 2884#define mmCP_MEC2_F32_INT_DIS_BASE_IDX 0 2885#define mmCP_VMID_STATUS 0x10bf 2886#define mmCP_VMID_STATUS_BASE_IDX 0 2887 2888 2889// addressBlock: gc_cppdec2 2890// base address: 0xc600 2891#define mmCP_RB_DOORBELL_CONTROL_SCH_0 0x1180 2892#define mmCP_RB_DOORBELL_CONTROL_SCH_0_BASE_IDX 0 2893#define mmCP_RB_DOORBELL_CONTROL_SCH_1 0x1181 2894#define mmCP_RB_DOORBELL_CONTROL_SCH_1_BASE_IDX 0 2895#define mmCP_RB_DOORBELL_CONTROL_SCH_2 0x1182 2896#define mmCP_RB_DOORBELL_CONTROL_SCH_2_BASE_IDX 0 2897#define mmCP_RB_DOORBELL_CONTROL_SCH_3 0x1183 2898#define mmCP_RB_DOORBELL_CONTROL_SCH_3_BASE_IDX 0 2899#define mmCP_RB_DOORBELL_CONTROL_SCH_4 0x1184 2900#define mmCP_RB_DOORBELL_CONTROL_SCH_4_BASE_IDX 0 2901#define mmCP_RB_DOORBELL_CONTROL_SCH_5 0x1185 2902#define mmCP_RB_DOORBELL_CONTROL_SCH_5_BASE_IDX 0 2903#define mmCP_RB_DOORBELL_CONTROL_SCH_6 0x1186 2904#define mmCP_RB_DOORBELL_CONTROL_SCH_6_BASE_IDX 0 2905#define mmCP_RB_DOORBELL_CONTROL_SCH_7 0x1187 2906#define mmCP_RB_DOORBELL_CONTROL_SCH_7_BASE_IDX 0 2907#define mmCP_RB_DOORBELL_CLEAR 0x1188 2908#define mmCP_RB_DOORBELL_CLEAR_BASE_IDX 0 2909#define mmCP_GFX_MQD_CONTROL 0x11a0 2910#define mmCP_GFX_MQD_CONTROL_BASE_IDX 0 2911#define mmCP_GFX_MQD_BASE_ADDR 0x11a1 2912#define mmCP_GFX_MQD_BASE_ADDR_BASE_IDX 0 2913#define mmCP_GFX_MQD_BASE_ADDR_HI 0x11a2 2914#define mmCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX 0 2915#define mmCP_RB_STATUS 0x11a3 2916#define mmCP_RB_STATUS_BASE_IDX 0 2917#define mmCPG_UTCL1_STATUS 0x11b4 2918#define mmCPG_UTCL1_STATUS_BASE_IDX 0 2919#define mmCPC_UTCL1_STATUS 0x11b5 2920#define mmCPC_UTCL1_STATUS_BASE_IDX 0 2921#define mmCPF_UTCL1_STATUS 0x11b6 2922#define mmCPF_UTCL1_STATUS_BASE_IDX 0 2923#define mmCP_SD_CNTL 0x11b7 2924#define mmCP_SD_CNTL_BASE_IDX 0 2925#define mmCP_SOFT_RESET_CNTL 0x11b9 2926#define mmCP_SOFT_RESET_CNTL_BASE_IDX 0 2927#define mmCP_CPC_GFX_CNTL 0x11ba 2928#define mmCP_CPC_GFX_CNTL_BASE_IDX 0 2929 2930 2931// addressBlock: gc_spipdec 2932// base address: 0xc700 2933#define mmSPI_ARB_PRIORITY 0x11c0 2934#define mmSPI_ARB_PRIORITY_BASE_IDX 0 2935#define mmSPI_ARB_CYCLES_0 0x11c1 2936#define mmSPI_ARB_CYCLES_0_BASE_IDX 0 2937#define mmSPI_ARB_CYCLES_1 0x11c2 2938#define mmSPI_ARB_CYCLES_1_BASE_IDX 0 2939#define mmSPI_WCL_PIPE_PERCENT_GFX 0x11c7 2940#define mmSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX 0 2941#define mmSPI_WCL_PIPE_PERCENT_HP3D 0x11c8 2942#define mmSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX 0 2943#define mmSPI_WCL_PIPE_PERCENT_CS0 0x11c9 2944#define mmSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX 0 2945#define mmSPI_WCL_PIPE_PERCENT_CS1 0x11ca 2946#define mmSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX 0 2947#define mmSPI_WCL_PIPE_PERCENT_CS2 0x11cb 2948#define mmSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX 0 2949#define mmSPI_WCL_PIPE_PERCENT_CS3 0x11cc 2950#define mmSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX 0 2951#define mmSPI_WCL_PIPE_PERCENT_CS4 0x11cd 2952#define mmSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX 0 2953#define mmSPI_WCL_PIPE_PERCENT_CS5 0x11ce 2954#define mmSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX 0 2955#define mmSPI_WCL_PIPE_PERCENT_CS6 0x11cf 2956#define mmSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX 0 2957#define mmSPI_WCL_PIPE_PERCENT_CS7 0x11d0 2958#define mmSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX 0 2959#define mmSPI_COMPUTE_QUEUE_RESET 0x11db 2960#define mmSPI_COMPUTE_QUEUE_RESET_BASE_IDX 0 2961#define mmSPI_RESOURCE_RESERVE_CU_0 0x11dc 2962#define mmSPI_RESOURCE_RESERVE_CU_0_BASE_IDX 0 2963#define mmSPI_RESOURCE_RESERVE_CU_1 0x11dd 2964#define mmSPI_RESOURCE_RESERVE_CU_1_BASE_IDX 0 2965#define mmSPI_RESOURCE_RESERVE_CU_2 0x11de 2966#define mmSPI_RESOURCE_RESERVE_CU_2_BASE_IDX 0 2967#define mmSPI_RESOURCE_RESERVE_CU_3 0x11df 2968#define mmSPI_RESOURCE_RESERVE_CU_3_BASE_IDX 0 2969#define mmSPI_RESOURCE_RESERVE_CU_4 0x11e0 2970#define mmSPI_RESOURCE_RESERVE_CU_4_BASE_IDX 0 2971#define mmSPI_RESOURCE_RESERVE_CU_5 0x11e1 2972#define mmSPI_RESOURCE_RESERVE_CU_5_BASE_IDX 0 2973#define mmSPI_RESOURCE_RESERVE_CU_6 0x11e2 2974#define mmSPI_RESOURCE_RESERVE_CU_6_BASE_IDX 0 2975#define mmSPI_RESOURCE_RESERVE_CU_7 0x11e3 2976#define mmSPI_RESOURCE_RESERVE_CU_7_BASE_IDX 0 2977#define mmSPI_RESOURCE_RESERVE_CU_8 0x11e4 2978#define mmSPI_RESOURCE_RESERVE_CU_8_BASE_IDX 0 2979#define mmSPI_RESOURCE_RESERVE_CU_9 0x11e5 2980#define mmSPI_RESOURCE_RESERVE_CU_9_BASE_IDX 0 2981#define mmSPI_RESOURCE_RESERVE_EN_CU_0 0x11e6 2982#define mmSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX 0 2983#define mmSPI_RESOURCE_RESERVE_EN_CU_1 0x11e7 2984#define mmSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX 0 2985#define mmSPI_RESOURCE_RESERVE_EN_CU_2 0x11e8 2986#define mmSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX 0 2987#define mmSPI_RESOURCE_RESERVE_EN_CU_3 0x11e9 2988#define mmSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX 0 2989#define mmSPI_RESOURCE_RESERVE_EN_CU_4 0x11ea 2990#define mmSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX 0 2991#define mmSPI_RESOURCE_RESERVE_EN_CU_5 0x11eb 2992#define mmSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX 0 2993#define mmSPI_RESOURCE_RESERVE_EN_CU_6 0x11ec 2994#define mmSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX 0 2995#define mmSPI_RESOURCE_RESERVE_EN_CU_7 0x11ed 2996#define mmSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX 0 2997#define mmSPI_RESOURCE_RESERVE_EN_CU_8 0x11ee 2998#define mmSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX 0 2999#define mmSPI_RESOURCE_RESERVE_EN_CU_9 0x11ef 3000#define mmSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX 0
3001#define mmSPI_RESOURCE_RESERVE_CU_10 0x11f0 3002#define mmSPI_RESOURCE_RESERVE_CU_10_BASE_IDX 0 3003#define mmSPI_RESOURCE_RESERVE_CU_11 0x11f1 3004#define mmSPI_RESOURCE_RESERVE_CU_11_BASE_IDX 0 3005#define mmSPI_RESOURCE_RESERVE_EN_CU_10 0x11f2 3006#define mmSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX 0 3007#define mmSPI_RESOURCE_RESERVE_EN_CU_11 0x11f3 3008#define mmSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX 0 3009#define mmSPI_RESOURCE_RESERVE_CU_12 0x11f4 3010#define mmSPI_RESOURCE_RESERVE_CU_12_BASE_IDX 0 3011#define mmSPI_RESOURCE_RESERVE_CU_13 0x11f5 3012#define mmSPI_RESOURCE_RESERVE_CU_13_BASE_IDX 0 3013#define mmSPI_RESOURCE_RESERVE_CU_14 0x11f6 3014#define mmSPI_RESOURCE_RESERVE_CU_14_BASE_IDX 0 3015#define mmSPI_RESOURCE_RESERVE_CU_15 0x11f7 3016#define mmSPI_RESOURCE_RESERVE_CU_15_BASE_IDX 0 3017#define mmSPI_RESOURCE_RESERVE_EN_CU_12 0x11f8 3018#define mmSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX 0 3019#define mmSPI_RESOURCE_RESERVE_EN_CU_13 0x11f9 3020#define mmSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX 0 3021#define mmSPI_RESOURCE_RESERVE_EN_CU_14 0x11fa 3022#define mmSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX 0 3023#define mmSPI_RESOURCE_RESERVE_EN_CU_15 0x11fb 3024#define mmSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX 0 3025#define mmSPI_COMPUTE_WF_CTX_SAVE 0x11fc 3026#define mmSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX 0 3027#define mmSPI_ARB_CNTL_0 0x11fd 3028#define mmSPI_ARB_CNTL_0_BASE_IDX 0 3029 3030 3031// addressBlock: gc_cpphqddec 3032// base address: 0xc800 3033#define mmCP_HQD_GFX_CONTROL 0x123e 3034#define mmCP_HQD_GFX_CONTROL_BASE_IDX 0 3035#define mmCP_HQD_GFX_STATUS 0x123f 3036#define mmCP_HQD_GFX_STATUS_BASE_IDX 0 3037#define mmCP_HPD_ROQ_OFFSETS 0x1240 3038#define mmCP_HPD_ROQ_OFFSETS_BASE_IDX 0 3039#define mmCP_HPD_STATUS0 0x1241 3040#define mmCP_HPD_STATUS0_BASE_IDX 0 3041#define mmCP_HPD_UTCL1_CNTL 0x1242 3042#define mmCP_HPD_UTCL1_CNTL_BASE_IDX 0 3043#define mmCP_HPD_UTCL1_ERROR 0x1243 3044#define mmCP_HPD_UTCL1_ERROR_BASE_IDX 0 3045#define mmCP_HPD_UTCL1_ERROR_ADDR 0x1244 3046#define mmCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX 0 3047#define mmCP_MQD_BASE_ADDR 0x1245 3048#define mmCP_MQD_BASE_ADDR_BASE_IDX 0 3049#define mmCP_MQD_BASE_ADDR_HI 0x1246 3050#define mmCP_MQD_BASE_ADDR_HI_BASE_IDX 0 3051#define mmCP_HQD_ACTIVE 0x1247 3052#define mmCP_HQD_ACTIVE_BASE_IDX 0 3053#define mmCP_HQD_VMID 0x1248 3054#define mmCP_HQD_VMID_BASE_IDX 0 3055#define mmCP_HQD_PERSISTENT_STATE 0x1249 3056#define mmCP_HQD_PERSISTENT_STATE_BASE_IDX 0 3057#define mmCP_HQD_PIPE_PRIORITY 0x124a 3058#define mmCP_HQD_PIPE_PRIORITY_BASE_IDX 0 3059#define mmCP_HQD_QUEUE_PRIORITY 0x124b 3060#define mmCP_HQD_QUEUE_PRIORITY_BASE_IDX 0 3061#define mmCP_HQD_QUANTUM 0x124c 3062#define mmCP_HQD_QUANTUM_BASE_IDX 0 3063#define mmCP_HQD_PQ_BASE 0x124d 3064#define mmCP_HQD_PQ_BASE_BASE_IDX 0 3065#define mmCP_HQD_PQ_BASE_HI 0x124e 3066#define mmCP_HQD_PQ_BASE_HI_BASE_IDX 0 3067#define mmCP_HQD_PQ_RPTR 0x124f 3068#define mmCP_HQD_PQ_RPTR_BASE_IDX 0 3069#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x1250 3070#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX 0 3071#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1251 3072#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX 0 3073#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x1252 3074#define mmCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX 0 3075#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x1253 3076#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX 0 3077#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x1254 3078#define mmCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX 0 3079#define mmCP_HQD_PQ_CONTROL 0x1256 3080#define mmCP_HQD_PQ_CONTROL_BASE_IDX 0 3081#define mmCP_HQD_IB_BASE_ADDR 0x1257 3082#define mmCP_HQD_IB_BASE_ADDR_BASE_IDX 0 3083#define mmCP_HQD_IB_BASE_ADDR_HI 0x1258 3084#define mmCP_HQD_IB_BASE_ADDR_HI_BASE_IDX 0 3085#define mmCP_HQD_IB_RPTR 0x1259 3086#define mmCP_HQD_IB_RPTR_BASE_IDX 0 3087#define mmCP_HQD_IB_CONTROL 0x125a 3088#define mmCP_HQD_IB_CONTROL_BASE_IDX 0 3089#define mmCP_HQD_IQ_TIMER 0x125b 3090#define mmCP_HQD_IQ_TIMER_BASE_IDX 0 3091#define mmCP_HQD_IQ_RPTR 0x125c 3092#define mmCP_HQD_IQ_RPTR_BASE_IDX 0 3093#define mmCP_HQD_DEQUEUE_REQUEST 0x125d 3094#define mmCP_HQD_DEQUEUE_REQUEST_BASE_IDX 0 3095#define mmCP_HQD_DMA_OFFLOAD 0x125e 3096#define mmCP_HQD_DMA_OFFLOAD_BASE_IDX 0 3097#define mmCP_HQD_OFFLOAD 0x125e 3098#define mmCP_HQD_OFFLOAD_BASE_IDX 0 3099#define mmCP_HQD_SEMA_CMD 0x125f 3100#define mmCP_HQD_SEMA_CMD_BASE_IDX 0 3101#define mmCP_HQD_MSG_TYPE 0x1260 3102#define mmCP_HQD_MSG_TYPE_BASE_IDX 0 3103#define mmCP_HQD_ATOMIC0_PREOP_LO 0x1261 3104#define mmCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX 0 3105#define mmCP_HQD_ATOMIC0_PREOP_HI 0x1262 3106#define mmCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX 0 3107#define mmCP_HQD_ATOMIC1_PREOP_LO 0x1263 3108#define mmCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX 0 3109#define mmCP_HQD_ATOMIC1_PREOP_HI 0x1264 3110#define mmCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX 0 3111#define mmCP_HQD_HQ_SCHEDULER0 0x1265 3112#define mmCP_HQD_HQ_SCHEDULER0_BASE_IDX 0 3113#define mmCP_HQD_HQ_STATUS0 0x1265 3114#define mmCP_HQD_HQ_STATUS0_BASE_IDX 0 3115#define mmCP_HQD_HQ_CONTROL0 0x1266 3116#define mmCP_HQD_HQ_CONTROL0_BASE_IDX 0 3117#define mmCP_HQD_HQ_SCHEDULER1 0x1266 3118#define mmCP_HQD_HQ_SCHEDULER1_BASE_IDX 0 3119#define mmCP_MQD_CONTROL 0x1267 3120#define mmCP_MQD_CONTROL_BASE_IDX 0 3121#define mmCP_HQD_HQ_STATUS1 0x1268 3122#define mmCP_HQD_HQ_STATUS1_BASE_IDX 0 3123#define mmCP_HQD_HQ_CONTROL1 0x1269 3124#define mmCP_HQD_HQ_CONTROL1_BASE_IDX 0 3125#define mmCP_HQD_EOP_BASE_ADDR 0x126a 3126#define mmCP_HQD_EOP_BASE_ADDR_BASE_IDX 0 3127#define mmCP_HQD_EOP_BASE_ADDR_HI 0x126b 3128#define mmCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX 0 3129#define mmCP_HQD_EOP_CONTROL 0x126c 3130#define mmCP_HQD_EOP_CONTROL_BASE_IDX 0 3131#define mmCP_HQD_EOP_RPTR 0x126d 3132#define mmCP_HQD_EOP_RPTR_BASE_IDX 0 3133#define mmCP_HQD_EOP_WPTR 0x126e 3134#define mmCP_HQD_EOP_WPTR_BASE_IDX 0 3135#define mmCP_HQD_EOP_EVENTS 0x126f 3136#define mmCP_HQD_EOP_EVENTS_BASE_IDX 0 3137#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO 0x1270 3138#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0 3139#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI 0x1271 3140#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0 3141#define mmCP_HQD_CTX_SAVE_CONTROL 0x1272 3142#define mmCP_HQD_CTX_SAVE_CONTROL_BASE_IDX 0 3143#define mmCP_HQD_CNTL_STACK_OFFSET 0x1273 3144#define mmCP_HQD_CNTL_STACK_OFFSET_BASE_IDX 0 3145#define mmCP_HQD_CNTL_STACK_SIZE 0x1274 3146#define mmCP_HQD_CNTL_STACK_SIZE_BASE_IDX 0 3147#define mmCP_HQD_WG_STATE_OFFSET 0x1275 3148#define mmCP_HQD_WG_STATE_OFFSET_BASE_IDX 0 3149#define mmCP_HQD_CTX_SAVE_SIZE 0x1276 3150#define mmCP_HQD_CTX_SAVE_SIZE_BASE_IDX 0 3151#define mmCP_HQD_GDS_RESOURCE_STATE 0x1277 3152#define mmCP_HQD_GDS_RESOURCE_STATE_BASE_IDX 0 3153#define mmCP_HQD_ERROR 0x1278 3154#define mmCP_HQD_ERROR_BASE_IDX 0 3155#define mmCP_HQD_EOP_WPTR_MEM 0x1279 3156#define mmCP_HQD_EOP_WPTR_MEM_BASE_IDX 0 3157#define mmCP_HQD_AQL_CONTROL 0x127a 3158#define mmCP_HQD_AQL_CONTROL_BASE_IDX 0 3159#define mmCP_HQD_PQ_WPTR_LO 0x127b 3160#define mmCP_HQD_PQ_WPTR_LO_BASE_IDX 0 3161#define mmCP_HQD_PQ_WPTR_HI 0x127c 3162#define mmCP_HQD_PQ_WPTR_HI_BASE_IDX 0 3163 3164 3165// addressBlock: gc_didtdec 3166// base address: 0xca00 3167#define mmDIDT_IND_INDEX 0x1280 3168#define mmDIDT_IND_INDEX_BASE_IDX 0 3169#define mmDIDT_IND_DATA 0x1281 3170#define mmDIDT_IND_DATA_BASE_IDX 0 3171 3172 3173// addressBlock: gc_gccacdec 3174// base address: 0xca10 3175#define mmGC_CAC_CTRL_1 0x1284 3176#define mmGC_CAC_CTRL_1_BASE_IDX 0 3177#define mmGC_CAC_CTRL_2 0x1285 3178#define mmGC_CAC_CTRL_2_BASE_IDX 0 3179#define mmGC_CAC_CGTT_CLK_CTRL 0x1286 3180#define mmGC_CAC_CGTT_CLK_CTRL_BASE_IDX 0 3181#define mmGC_CAC_AGGR_LOWER 0x1287 3182#define mmGC_CAC_AGGR_LOWER_BASE_IDX 0 3183#define mmGC_CAC_AGGR_UPPER 0x1288 3184#define mmGC_CAC_AGGR_UPPER_BASE_IDX 0 3185#define mmGC_CAC_PG_AGGR_LOWER 0x128b 3186#define mmGC_CAC_PG_AGGR_LOWER_BASE_IDX 0 3187#define mmGC_CAC_PG_AGGR_UPPER 0x128c 3188#define mmGC_CAC_PG_AGGR_UPPER_BASE_IDX 0 3189#define mmGC_CAC_SOFT_CTRL 0x128d 3190#define mmGC_CAC_SOFT_CTRL_BASE_IDX 0 3191#define mmGC_DIDT_CTRL0 0x128e 3192#define mmGC_DIDT_CTRL0_BASE_IDX 0 3193#define mmGC_DIDT_CTRL1 0x128f 3194#define mmGC_DIDT_CTRL1_BASE_IDX 0 3195#define mmGC_DIDT_CTRL2 0x1290 3196#define mmGC_DIDT_CTRL2_BASE_IDX 0 3197#define mmGC_DIDT_WEIGHT 0x1291 3198#define mmGC_DIDT_WEIGHT_BASE_IDX 0 3199#define mmGC_EDC_CTRL 0x1293 3200#define mmGC_EDC_CTRL_BASE_IDX 0 3201#define mmGC_EDC_THRESHOLD 0x1294 3202#define mmGC_EDC_THRESHOLD_BASE_IDX 0 3203#define mmGC_EDC_STATUS 0x1295 3204#define mmGC_EDC_STATUS_BASE_IDX 0 3205#define mmGC_EDC_OVERFLOW 0x1296 3206#define mmGC_EDC_OVERFLOW_BASE_IDX 0 3207#define mmGC_EDC_ROLLING_POWER_DELTA 0x1297 3208#define mmGC_EDC_ROLLING_POWER_DELTA_BASE_IDX 0 3209#define mmGC_DIDT_DROOP_CTRL 0x1298 3210#define mmGC_DIDT_DROOP_CTRL_BASE_IDX 0 3211#define mmGC_EDC_DROOP_CTRL 0x1299 3212#define mmGC_EDC_DROOP_CTRL_BASE_IDX 0 3213#define mmGC_CAC_IND_INDEX 0x129a 3214#define mmGC_CAC_IND_INDEX_BASE_IDX 0 3215#define mmGC_CAC_IND_DATA 0x129b 3216#define mmGC_CAC_IND_DATA_BASE_IDX 0 3217#define mmSE_CAC_CGTT_CLK_CTRL 0x129c 3218#define mmSE_CAC_CGTT_CLK_CTRL_BASE_IDX 0 3219#define mmSE_CAC_IND_INDEX 0x129d 3220#define mmSE_CAC_IND_INDEX_BASE_IDX 0 3221#define mmSE_CAC_IND_DATA 0x129e 3222#define mmSE_CAC_IND_DATA_BASE_IDX 0 3223 3224 3225// addressBlock: gc_tcpdec 3226// base address: 0xca80 3227#define mmTCP_WATCH0_ADDR_H 0x12a0 3228#define mmTCP_WATCH0_ADDR_H_BASE_IDX 0 3229#define mmTCP_WATCH0_ADDR_L 0x12a1 3230#define mmTCP_WATCH0_ADDR_L_BASE_IDX 0 3231#define mmTCP_WATCH0_CNTL 0x12a2 3232#define mmTCP_WATCH0_CNTL_BASE_IDX 0 3233#define mmTCP_WATCH1_ADDR_H 0x12a3 3234#define mmTCP_WATCH1_ADDR_H_BASE_IDX 0 3235#define mmTCP_WATCH1_ADDR_L 0x12a4 3236#define mmTCP_WATCH1_ADDR_L_BASE_IDX 0 3237#define mmTCP_WATCH1_CNTL 0x12a5 3238#define mmTCP_WATCH1_CNTL_BASE_IDX 0 3239#define mmTCP_WATCH2_ADDR_H 0x12a6 3240#define mmTCP_WATCH2_ADDR_H_BASE_IDX 0 3241#define mmTCP_WATCH2_ADDR_L 0x12a7 3242#define mmTCP_WATCH2_ADDR_L_BASE_IDX 0 3243#define mmTCP_WATCH2_CNTL 0x12a8 3244#define mmTCP_WATCH2_CNTL_BASE_IDX 0 3245#define mmTCP_WATCH3_ADDR_H 0x12a9 3246#define mmTCP_WATCH3_ADDR_H_BASE_IDX 0 3247#define mmTCP_WATCH3_ADDR_L 0x12aa 3248#define mmTCP_WATCH3_ADDR_L_BASE_IDX 0 3249#define mmTCP_WATCH3_CNTL 0x12ab 3250#define mmTCP_WATCH3_CNTL_BASE_IDX 0 3251#define mmTCP_GATCL1_CNTL 0x12b0 3252#define mmTCP_GATCL1_CNTL_BASE_IDX 0 3253#define mmTCP_ATC_EDC_GATCL1_CNT 0x12b1 3254#define mmTCP_ATC_EDC_GATCL1_CNT_BASE_IDX 0 3255#define mmTCP_GATCL1_DSM_CNTL 0x12b2 3256#define mmTCP_GATCL1_DSM_CNTL_BASE_IDX 0 3257#define mmTCP_CNTL2 0x12b4 3258#define mmTCP_CNTL2_BASE_IDX 0 3259#define mmTCP_UTCL1_CNTL1 0x12b5 3260#define mmTCP_UTCL1_CNTL1_BASE_IDX 0 3261#define mmTCP_UTCL1_CNTL2 0x12b6 3262#define mmTCP_UTCL1_CNTL2_BASE_IDX 0 3263#define mmTCP_UTCL1_STATUS 0x12b7 3264#define mmTCP_UTCL1_STATUS_BASE_IDX 0 3265#define mmTCP_PERFCOUNTER_FILTER 0x12b9 3266#define mmTCP_PERFCOUNTER_FILTER_BASE_IDX 0 3267#define mmTCP_PERFCOUNTER_FILTER_EN 0x12ba 3268#define mmTCP_PERFCOUNTER_FILTER_EN_BASE_IDX 0 3269 3270 3271// addressBlock: gc_gdspdec 3272// base address: 0xcc00 3273#define mmGDS_VMID0_BASE 0x1300 3274#define mmGDS_VMID0_BASE_BASE_IDX 0 3275#define mmGDS_VMID0_SIZE 0x1301 3276#define mmGDS_VMID0_SIZE_BASE_IDX 0 3277#define mmGDS_VMID1_BASE 0x1302 3278#define mmGDS_VMID1_BASE_BASE_IDX 0 3279#define mmGDS_VMID1_SIZE 0x1303 3280#define mmGDS_VMID1_SIZE_BASE_IDX 0 3281#define mmGDS_VMID2_BASE 0x1304 3282#define mmGDS_VMID2_BASE_BASE_IDX 0 3283#define mmGDS_VMID2_SIZE 0x1305 3284#define mmGDS_VMID2_SIZE_BASE_IDX 0 3285#define mmGDS_VMID3_BASE 0x1306 3286#define mmGDS_VMID3_BASE_BASE_IDX 0 3287#define mmGDS_VMID3_SIZE 0x1307 3288#define mmGDS_VMID3_SIZE_BASE_IDX 0 3289#define mmGDS_VMID4_BASE 0x1308 3290#define mmGDS_VMID4_BASE_BASE_IDX 0 3291#define mmGDS_VMID4_SIZE 0x1309 3292#define mmGDS_VMID4_SIZE_BASE_IDX 0 3293#define mmGDS_VMID5_BASE 0x130a 3294#define mmGDS_VMID5_BASE_BASE_IDX 0 3295#define mmGDS_VMID5_SIZE 0x130b 3296#define mmGDS_VMID5_SIZE_BASE_IDX 0 3297#define mmGDS_VMID6_BASE 0x130c 3298#define mmGDS_VMID6_BASE_BASE_IDX 0 3299#define mmGDS_VMID6_SIZE 0x130d 3300#define mmGDS_VMID6_SIZE_BASE_IDX 0 3301#define mmGDS_VMID7_BASE 0x130e 3302#define mmGDS_VMID7_BASE_BASE_IDX 0 3303#define mmGDS_VMID7_SIZE 0x130f 3304#define mmGDS_VMID7_SIZE_BASE_IDX 0 3305#define mmGDS_VMID8_BASE 0x1310 3306#define mmGDS_VMID8_BASE_BASE_IDX 0 3307#define mmGDS_VMID8_SIZE 0x1311 3308#define mmGDS_VMID8_SIZE_BASE_IDX 0 3309#define mmGDS_VMID9_BASE 0x1312 3310#define mmGDS_VMID9_BASE_BASE_IDX 0 3311#define mmGDS_VMID9_SIZE 0x1313 3312#define mmGDS_VMID9_SIZE_BASE_IDX 0 3313#define mmGDS_VMID10_BASE 0x1314 3314#define mmGDS_VMID10_BASE_BASE_IDX 0 3315#define mmGDS_VMID10_SIZE 0x1315 3316#define mmGDS_VMID10_SIZE_BASE_IDX 0 3317#define mmGDS_VMID11_BASE 0x1316 3318#define mmGDS_VMID11_BASE_BASE_IDX 0 3319#define mmGDS_VMID11_SIZE 0x1317 3320#define mmGDS_VMID11_SIZE_BASE_IDX 0 3321#define mmGDS_VMID12_BASE 0x1318 3322#define mmGDS_VMID12_BASE_BASE_IDX 0 3323#define mmGDS_VMID12_SIZE 0x1319 3324#define mmGDS_VMID12_SIZE_BASE_IDX 0 3325#define mmGDS_VMID13_BASE 0x131a 3326#define mmGDS_VMID13_BASE_BASE_IDX 0 3327#define mmGDS_VMID13_SIZE 0x131b 3328#define mmGDS_VMID13_SIZE_BASE_IDX 0 3329#define mmGDS_VMID14_BASE 0x131c 3330#define mmGDS_VMID14_BASE_BASE_IDX 0 3331#define mmGDS_VMID14_SIZE 0x131d 3332#define mmGDS_VMID14_SIZE_BASE_IDX 0 3333#define mmGDS_VMID15_BASE 0x131e 3334#define mmGDS_VMID15_BASE_BASE_IDX 0 3335#define mmGDS_VMID15_SIZE 0x131f 3336#define mmGDS_VMID15_SIZE_BASE_IDX 0 3337#define mmGDS_GWS_VMID0 0x1320 3338#define mmGDS_GWS_VMID0_BASE_IDX 0 3339#define mmGDS_GWS_VMID1 0x1321 3340#define mmGDS_GWS_VMID1_BASE_IDX 0 3341#define mmGDS_GWS_VMID2 0x1322 3342#define mmGDS_GWS_VMID2_BASE_IDX 0 3343#define mmGDS_GWS_VMID3 0x1323 3344#define mmGDS_GWS_VMID3_BASE_IDX 0 3345#define mmGDS_GWS_VMID4 0x1324 3346#define mmGDS_GWS_VMID4_BASE_IDX 0 3347#define mmGDS_GWS_VMID5 0x1325 3348#define mmGDS_GWS_VMID5_BASE_IDX 0 3349#define mmGDS_GWS_VMID6 0x1326 3350#define mmGDS_GWS_VMID6_BASE_IDX 0 3351#define mmGDS_GWS_VMID7 0x1327 3352#define mmGDS_GWS_VMID7_BASE_IDX 0 3353#define mmGDS_GWS_VMID8 0x1328 3354#define mmGDS_GWS_VMID8_BASE_IDX 0 3355#define mmGDS_GWS_VMID9 0x1329 3356#define mmGDS_GWS_VMID9_BASE_IDX 0 3357#define mmGDS_GWS_VMID10 0x132a 3358#define mmGDS_GWS_VMID10_BASE_IDX 0 3359#define mmGDS_GWS_VMID11 0x132b 3360#define mmGDS_GWS_VMID11_BASE_IDX 0 3361#define mmGDS_GWS_VMID12 0x132c 3362#define mmGDS_GWS_VMID12_BASE_IDX 0 3363#define mmGDS_GWS_VMID13 0x132d 3364#define mmGDS_GWS_VMID13_BASE_IDX 0 3365#define mmGDS_GWS_VMID14 0x132e 3366#define mmGDS_GWS_VMID14_BASE_IDX 0 3367#define mmGDS_GWS_VMID15 0x132f 3368#define mmGDS_GWS_VMID15_BASE_IDX 0 3369#define mmGDS_OA_VMID0 0x1330 3370#define mmGDS_OA_VMID0_BASE_IDX 0 3371#define mmGDS_OA_VMID1 0x1331 3372#define mmGDS_OA_VMID1_BASE_IDX 0 3373#define mmGDS_OA_VMID2 0x1332 3374#define mmGDS_OA_VMID2_BASE_IDX 0 3375#define mmGDS_OA_VMID3 0x1333 3376#define mmGDS_OA_VMID3_BASE_IDX 0 3377#define mmGDS_OA_VMID4 0x1334 3378#define mmGDS_OA_VMID4_BASE_IDX 0 3379#define mmGDS_OA_VMID5 0x1335 3380#define mmGDS_OA_VMID5_BASE_IDX 0 3381#define mmGDS_OA_VMID6 0x1336 3382#define mmGDS_OA_VMID6_BASE_IDX 0 3383#define mmGDS_OA_VMID7 0x1337 3384#define mmGDS_OA_VMID7_BASE_IDX 0 3385#define mmGDS_OA_VMID8 0x1338 3386#define mmGDS_OA_VMID8_BASE_IDX 0 3387#define mmGDS_OA_VMID9 0x1339 3388#define mmGDS_OA_VMID9_BASE_IDX 0 3389#define mmGDS_OA_VMID10 0x133a 3390#define mmGDS_OA_VMID10_BASE_IDX 0 3391#define mmGDS_OA_VMID11 0x133b 3392#define mmGDS_OA_VMID11_BASE_IDX 0 3393#define mmGDS_OA_VMID12 0x133c 3394#define mmGDS_OA_VMID12_BASE_IDX 0 3395#define mmGDS_OA_VMID13 0x133d 3396#define mmGDS_OA_VMID13_BASE_IDX 0 3397#define mmGDS_OA_VMID14 0x133e 3398#define mmGDS_OA_VMID14_BASE_IDX 0 3399#define mmGDS_OA_VMID15 0x133f 3400#define mmGDS_OA_VMID15_BASE_IDX 0 3401#define mmGDS_GWS_RESET0 0x1344 3402#define mmGDS_GWS_RESET0_BASE_IDX 0 3403#define mmGDS_GWS_RESET1 0x1345 3404#define mmGDS_GWS_RESET1_BASE_IDX 0 3405#define mmGDS_GWS_RESOURCE_RESET 0x1346 3406#define mmGDS_GWS_RESOURCE_RESET_BASE_IDX 0 3407#define mmGDS_COMPUTE_MAX_WAVE_ID 0x1348 3408#define mmGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX 0 3409#define mmGDS_OA_RESET_MASK 0x1349 3410#define mmGDS_OA_RESET_MASK_BASE_IDX 0 3411#define mmGDS_OA_RESET 0x134a 3412#define mmGDS_OA_RESET_BASE_IDX 0 3413#define mmGDS_ENHANCE 0x134b 3414#define mmGDS_ENHANCE_BASE_IDX 0 3415#define mmGDS_OA_CGPG_RESTORE 0x134c 3416#define mmGDS_OA_CGPG_RESTORE_BASE_IDX 0 3417#define mmGDS_CS_CTXSW_STATUS 0x134d 3418#define mmGDS_CS_CTXSW_STATUS_BASE_IDX 0 3419#define mmGDS_CS_CTXSW_CNT0 0x134e 3420#define mmGDS_CS_CTXSW_CNT0_BASE_IDX 0 3421#define mmGDS_CS_CTXSW_CNT1 0x134f 3422#define mmGDS_CS_CTXSW_CNT1_BASE_IDX 0 3423#define mmGDS_CS_CTXSW_CNT2 0x1350 3424#define mmGDS_CS_CTXSW_CNT2_BASE_IDX 0 3425#define mmGDS_CS_CTXSW_CNT3 0x1351 3426#define mmGDS_CS_CTXSW_CNT3_BASE_IDX 0 3427#define mmGDS_GFX_CTXSW_STATUS 0x1352 3428#define mmGDS_GFX_CTXSW_STATUS_BASE_IDX 0 3429#define mmGDS_VS_CTXSW_CNT0 0x1353 3430#define mmGDS_VS_CTXSW_CNT0_BASE_IDX 0 3431#define mmGDS_VS_CTXSW_CNT1 0x1354 3432#define mmGDS_VS_CTXSW_CNT1_BASE_IDX 0 3433#define mmGDS_VS_CTXSW_CNT2 0x1355 3434#define mmGDS_VS_CTXSW_CNT2_BASE_IDX 0 3435#define mmGDS_VS_CTXSW_CNT3 0x1356 3436#define mmGDS_VS_CTXSW_CNT3_BASE_IDX 0 3437#define mmGDS_PS0_CTXSW_CNT0 0x1357 3438#define mmGDS_PS0_CTXSW_CNT0_BASE_IDX 0 3439#define mmGDS_PS0_CTXSW_CNT1 0x1358 3440#define mmGDS_PS0_CTXSW_CNT1_BASE_IDX 0 3441#define mmGDS_PS0_CTXSW_CNT2 0x1359 3442#define mmGDS_PS0_CTXSW_CNT2_BASE_IDX 0 3443#define mmGDS_PS0_CTXSW_CNT3 0x135a 3444#define mmGDS_PS0_CTXSW_CNT3_BASE_IDX 0 3445#define mmGDS_PS1_CTXSW_CNT0 0x135b 3446#define mmGDS_PS1_CTXSW_CNT0_BASE_IDX 0 3447#define mmGDS_PS1_CTXSW_CNT1 0x135c 3448#define mmGDS_PS1_CTXSW_CNT1_BASE_IDX 0 3449#define mmGDS_PS1_CTXSW_CNT2 0x135d 3450#define mmGDS_PS1_CTXSW_CNT2_BASE_IDX 0 3451#define mmGDS_PS1_CTXSW_CNT3 0x135e 3452#define mmGDS_PS1_CTXSW_CNT3_BASE_IDX 0 3453#define mmGDS_PS2_CTXSW_CNT0 0x135f 3454#define mmGDS_PS2_CTXSW_CNT0_BASE_IDX 0 3455#define mmGDS_PS2_CTXSW_CNT1 0x1360 3456#define mmGDS_PS2_CTXSW_CNT1_BASE_IDX 0 3457#define mmGDS_PS2_CTXSW_CNT2 0x1361 3458#define mmGDS_PS2_CTXSW_CNT2_BASE_IDX 0 3459#define mmGDS_PS2_CTXSW_CNT3 0x1362 3460#define mmGDS_PS2_CTXSW_CNT3_BASE_IDX 0 3461#define mmGDS_PS3_CTXSW_CNT0 0x1363 3462#define mmGDS_PS3_CTXSW_CNT0_BASE_IDX 0 3463#define mmGDS_PS3_CTXSW_CNT1 0x1364 3464#define mmGDS_PS3_CTXSW_CNT1_BASE_IDX 0 3465#define mmGDS_PS3_CTXSW_CNT2 0x1365 3466#define mmGDS_PS3_CTXSW_CNT2_BASE_IDX 0 3467#define mmGDS_PS3_CTXSW_CNT3 0x1366 3468#define mmGDS_PS3_CTXSW_CNT3_BASE_IDX 0 3469#define mmGDS_PS4_CTXSW_CNT0 0x1367 3470#define mmGDS_PS4_CTXSW_CNT0_BASE_IDX 0 3471#define mmGDS_PS4_CTXSW_CNT1 0x1368 3472#define mmGDS_PS4_CTXSW_CNT1_BASE_IDX 0 3473#define mmGDS_PS4_CTXSW_CNT2 0x1369 3474#define mmGDS_PS4_CTXSW_CNT2_BASE_IDX 0 3475#define mmGDS_PS4_CTXSW_CNT3 0x136a 3476#define mmGDS_PS4_CTXSW_CNT3_BASE_IDX 0 3477#define mmGDS_PS5_CTXSW_CNT0 0x136b 3478#define mmGDS_PS5_CTXSW_CNT0_BASE_IDX 0 3479#define mmGDS_PS5_CTXSW_CNT1 0x136c 3480#define mmGDS_PS5_CTXSW_CNT1_BASE_IDX 0 3481#define mmGDS_PS5_CTXSW_CNT2 0x136d 3482#define mmGDS_PS5_CTXSW_CNT2_BASE_IDX 0 3483#define mmGDS_PS5_CTXSW_CNT3 0x136e 3484#define mmGDS_PS5_CTXSW_CNT3_BASE_IDX 0 3485#define mmGDS_PS6_CTXSW_CNT0 0x136f 3486#define mmGDS_PS6_CTXSW_CNT0_BASE_IDX 0 3487#define mmGDS_PS6_CTXSW_CNT1 0x1370 3488#define mmGDS_PS6_CTXSW_CNT1_BASE_IDX 0 3489#define mmGDS_PS6_CTXSW_CNT2 0x1371 3490#define mmGDS_PS6_CTXSW_CNT2_BASE_IDX 0 3491#define mmGDS_PS6_CTXSW_CNT3 0x1372 3492#define mmGDS_PS6_CTXSW_CNT3_BASE_IDX 0 3493#define mmGDS_PS7_CTXSW_CNT0 0x1373 3494#define mmGDS_PS7_CTXSW_CNT0_BASE_IDX 0 3495#define mmGDS_PS7_CTXSW_CNT1 0x1374 3496#define mmGDS_PS7_CTXSW_CNT1_BASE_IDX 0 3497#define mmGDS_PS7_CTXSW_CNT2 0x1375 3498#define mmGDS_PS7_CTXSW_CNT2_BASE_IDX 0 3499#define mmGDS_PS7_CTXSW_CNT3 0x1376 3500#define mmGDS_PS7_CTXSW_CNT3_BASE_IDX 0 3501#define mmGDS_GS_CTXSW_CNT0 0x1377 3502#define mmGDS_GS_CTXSW_CNT0_BASE_IDX 0 3503#define mmGDS_GS_CTXSW_CNT1 0x1378 3504#define mmGDS_GS_CTXSW_CNT1_BASE_IDX 0 3505#define mmGDS_GS_CTXSW_CNT2 0x1379 3506#define mmGDS_GS_CTXSW_CNT2_BASE_IDX 0 3507#define mmGDS_GS_CTXSW_CNT3 0x137a 3508#define mmGDS_GS_CTXSW_CNT3_BASE_IDX 0 3509 3510 3511// addressBlock: gc_rasdec 3512// base address: 0xce00 3513#define mmRAS_SIGNATURE_CONTROL 0x1380 3514#define mmRAS_SIGNATURE_CONTROL_BASE_IDX 0 3515#define mmRAS_SIGNATURE_MASK 0x1381 3516#define mmRAS_SIGNATURE_MASK_BASE_IDX 0 3517#define mmRAS_SX_SIGNATURE0 0x1382 3518#define mmRAS_SX_SIGNATURE0_BASE_IDX 0 3519#define mmRAS_SX_SIGNATURE1 0x1383 3520#define mmRAS_SX_SIGNATURE1_BASE_IDX 0 3521#define mmRAS_SX_SIGNATURE2 0x1384 3522#define mmRAS_SX_SIGNATURE2_BASE_IDX 0 3523#define mmRAS_SX_SIGNATURE3 0x1385 3524#define mmRAS_SX_SIGNATURE3_BASE_IDX 0 3525#define mmRAS_DB_SIGNATURE0 0x138b 3526#define mmRAS_DB_SIGNATURE0_BASE_IDX 0 3527#define mmRAS_PA_SIGNATURE0 0x138c 3528#define mmRAS_PA_SIGNATURE0_BASE_IDX 0 3529#define mmRAS_VGT_SIGNATURE0 0x138d 3530#define mmRAS_VGT_SIGNATURE0_BASE_IDX 0 3531#define mmRAS_SQ_SIGNATURE0 0x138e 3532#define mmRAS_SQ_SIGNATURE0_BASE_IDX 0 3533#define mmRAS_SC_SIGNATURE0 0x138f 3534#define mmRAS_SC_SIGNATURE0_BASE_IDX 0 3535#define mmRAS_SC_SIGNATURE1 0x1390 3536#define mmRAS_SC_SIGNATURE1_BASE_IDX 0 3537#define mmRAS_SC_SIGNATURE2 0x1391 3538#define mmRAS_SC_SIGNATURE2_BASE_IDX 0 3539#define mmRAS_SC_SIGNATURE3 0x1392 3540#define mmRAS_SC_SIGNATURE3_BASE_IDX 0 3541#define mmRAS_SC_SIGNATURE4 0x1393 3542#define mmRAS_SC_SIGNATURE4_BASE_IDX 0 3543#define mmRAS_SC_SIGNATURE5 0x1394 3544#define mmRAS_SC_SIGNATURE5_BASE_IDX 0 3545#define mmRAS_SC_SIGNATURE6 0x1395 3546#define mmRAS_SC_SIGNATURE6_BASE_IDX 0 3547#define mmRAS_SC_SIGNATURE7 0x1396 3548#define mmRAS_SC_SIGNATURE7_BASE_IDX 0 3549#define mmRAS_IA_SIGNATURE0 0x1397 3550#define mmRAS_IA_SIGNATURE0_BASE_IDX 0 3551#define mmRAS_IA_SIGNATURE1 0x1398 3552#define mmRAS_IA_SIGNATURE1_BASE_IDX 0 3553#define mmRAS_SPI_SIGNATURE0 0x1399 3554#define mmRAS_SPI_SIGNATURE0_BASE_IDX 0 3555#define mmRAS_SPI_SIGNATURE1 0x139a 3556#define mmRAS_SPI_SIGNATURE1_BASE_IDX 0 3557#define mmRAS_TA_SIGNATURE0 0x139b 3558#define mmRAS_TA_SIGNATURE0_BASE_IDX 0 3559#define mmRAS_TD_SIGNATURE0 0x139c 3560#define mmRAS_TD_SIGNATURE0_BASE_IDX 0 3561#define mmRAS_CB_SIGNATURE0 0x139d 3562#define mmRAS_CB_SIGNATURE0_BASE_IDX 0 3563#define mmRAS_BCI_SIGNATURE0 0x139e 3564#define mmRAS_BCI_SIGNATURE0_BASE_IDX 0 3565#define mmRAS_BCI_SIGNATURE1 0x139f 3566#define mmRAS_BCI_SIGNATURE1_BASE_IDX 0 3567#define mmRAS_TA_SIGNATURE1 0x13a0 3568#define mmRAS_TA_SIGNATURE1_BASE_IDX 0 3569 3570 3571// addressBlock: gc_gfxdec0 3572// base address: 0x28000 3573#define mmDB_RENDER_CONTROL 0x0000 3574#define mmDB_RENDER_CONTROL_BASE_IDX 1 3575#define mmDB_COUNT_CONTROL 0x0001 3576#define mmDB_COUNT_CONTROL_BASE_IDX 1 3577#define mmDB_DEPTH_VIEW 0x0002 3578#define mmDB_DEPTH_VIEW_BASE_IDX 1 3579#define mmDB_RENDER_OVERRIDE 0x0003 3580#define mmDB_RENDER_OVERRIDE_BASE_IDX 1 3581#define mmDB_RENDER_OVERRIDE2 0x0004 3582#define mmDB_RENDER_OVERRIDE2_BASE_IDX 1 3583#define mmDB_HTILE_DATA_BASE 0x0005 3584#define mmDB_HTILE_DATA_BASE_BASE_IDX 1 3585#define mmDB_HTILE_DATA_BASE_HI 0x0006 3586#define mmDB_HTILE_DATA_BASE_HI_BASE_IDX 1 3587#define mmDB_DEPTH_SIZE 0x0007 3588#define mmDB_DEPTH_SIZE_BASE_IDX 1 3589#define mmDB_DEPTH_BOUNDS_MIN 0x0008 3590#define mmDB_DEPTH_BOUNDS_MIN_BASE_IDX 1 3591#define mmDB_DEPTH_BOUNDS_MAX 0x0009 3592#define mmDB_DEPTH_BOUNDS_MAX_BASE_IDX 1 3593#define mmDB_STENCIL_CLEAR 0x000a 3594#define mmDB_STENCIL_CLEAR_BASE_IDX 1 3595#define mmDB_DEPTH_CLEAR 0x000b 3596#define mmDB_DEPTH_CLEAR_BASE_IDX 1 3597#define mmPA_SC_SCREEN_SCISSOR_TL 0x000c 3598#define mmPA_SC_SCREEN_SCISSOR_TL_BASE_IDX 1 3599#define mmPA_SC_SCREEN_SCISSOR_BR 0x000d 3600#define mmPA_SC_SCREEN_SCISSOR_BR_BASE_IDX 1 3601#define mmDB_Z_INFO 0x000e 3602#define mmDB_Z_INFO_BASE_IDX 1 3603#define mmDB_STENCIL_INFO 0x000f 3604#define mmDB_STENCIL_INFO_BASE_IDX 1 3605#define mmDB_Z_READ_BASE 0x0010 3606#define mmDB_Z_READ_BASE_BASE_IDX 1 3607#define mmDB_Z_READ_BASE_HI 0x0011 3608#define mmDB_Z_READ_BASE_HI_BASE_IDX 1 3609#define mmDB_STENCIL_READ_BASE 0x0012 3610#define mmDB_STENCIL_READ_BASE_BASE_IDX 1 3611#define mmDB_STENCIL_READ_BASE_HI 0x0013 3612#define mmDB_STENCIL_READ_BASE_HI_BASE_IDX 1 3613#define mmDB_Z_WRITE_BASE 0x0014 3614#define mmDB_Z_WRITE_BASE_BASE_IDX 1 3615#define mmDB_Z_WRITE_BASE_HI 0x0015 3616#define mmDB_Z_WRITE_BASE_HI_BASE_IDX 1 3617#define mmDB_STENCIL_WRITE_BASE 0x0016 3618#define mmDB_STENCIL_WRITE_BASE_BASE_IDX 1 3619#define mmDB_STENCIL_WRITE_BASE_HI 0x0017 3620#define mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1 3621#define mmDB_DFSM_CONTROL 0x0018 3622#define mmDB_DFSM_CONTROL_BASE_IDX 1 3623#define mmDB_Z_INFO2 0x001a 3624#define mmDB_Z_INFO2_BASE_IDX 1 3625#define mmDB_STENCIL_INFO2 0x001b 3626#define mmDB_STENCIL_INFO2_BASE_IDX 1 3627#define mmTA_BC_BASE_ADDR 0x0020 3628#define mmTA_BC_BASE_ADDR_BASE_IDX 1 3629#define mmTA_BC_BASE_ADDR_HI 0x0021 3630#define mmTA_BC_BASE_ADDR_HI_BASE_IDX 1 3631#define mmCOHER_DEST_BASE_HI_0 0x007a 3632#define mmCOHER_DEST_BASE_HI_0_BASE_IDX 1 3633#define mmCOHER_DEST_BASE_HI_1 0x007b 3634#define mmCOHER_DEST_BASE_HI_1_BASE_IDX 1 3635#define mmCOHER_DEST_BASE_HI_2 0x007c 3636#define mmCOHER_DEST_BASE_HI_2_BASE_IDX 1 3637#define mmCOHER_DEST_BASE_HI_3 0x007d 3638#define mmCOHER_DEST_BASE_HI_3_BASE_IDX 1 3639#define mmCOHER_DEST_BASE_2 0x007e 3640#define mmCOHER_DEST_BASE_2_BASE_IDX 1 3641#define mmCOHER_DEST_BASE_3 0x007f 3642#define mmCOHER_DEST_BASE_3_BASE_IDX 1 3643#define mmPA_SC_WINDOW_OFFSET 0x0080 3644#define mmPA_SC_WINDOW_OFFSET_BASE_IDX 1 3645#define mmPA_SC_WINDOW_SCISSOR_TL 0x0081 3646#define mmPA_SC_WINDOW_SCISSOR_TL_BASE_IDX 1 3647#define mmPA_SC_WINDOW_SCISSOR_BR 0x0082 3648#define mmPA_SC_WINDOW_SCISSOR_BR_BASE_IDX 1 3649#define mmPA_SC_CLIPRECT_RULE 0x0083 3650#define mmPA_SC_CLIPRECT_RULE_BASE_IDX 1 3651#define mmPA_SC_CLIPRECT_0_TL 0x0084 3652#define mmPA_SC_CLIPRECT_0_TL_BASE_IDX 1 3653#define mmPA_SC_CLIPRECT_0_BR 0x0085 3654#define mmPA_SC_CLIPRECT_0_BR_BASE_IDX 1 3655#define mmPA_SC_CLIPRECT_1_TL 0x0086 3656#define mmPA_SC_CLIPRECT_1_TL_BASE_IDX 1 3657#define mmPA_SC_CLIPRECT_1_BR 0x0087 3658#define mmPA_SC_CLIPRECT_1_BR_BASE_IDX 1 3659#define mmPA_SC_CLIPRECT_2_TL 0x0088 3660#define mmPA_SC_CLIPRECT_2_TL_BASE_IDX 1 3661#define mmPA_SC_CLIPRECT_2_BR 0x0089 3662#define mmPA_SC_CLIPRECT_2_BR_BASE_IDX 1 3663#define mmPA_SC_CLIPRECT_3_TL 0x008a 3664#define mmPA_SC_CLIPRECT_3_TL_BASE_IDX 1 3665#define mmPA_SC_CLIPRECT_3_BR 0x008b 3666#define mmPA_SC_CLIPRECT_3_BR_BASE_IDX 1 3667#define mmPA_SC_EDGERULE 0x008c 3668#define mmPA_SC_EDGERULE_BASE_IDX 1 3669#define mmPA_SU_HARDWARE_SCREEN_OFFSET 0x008d 3670#define mmPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX 1 3671#define mmCB_TARGET_MASK 0x008e 3672#define mmCB_TARGET_MASK_BASE_IDX 1 3673#define mmCB_SHADER_MASK 0x008f 3674#define mmCB_SHADER_MASK_BASE_IDX 1 3675#define mmPA_SC_GENERIC_SCISSOR_TL 0x0090 3676#define mmPA_SC_GENERIC_SCISSOR_TL_BASE_IDX 1 3677#define mmPA_SC_GENERIC_SCISSOR_BR 0x0091 3678#define mmPA_SC_GENERIC_SCISSOR_BR_BASE_IDX 1 3679#define mmCOHER_DEST_BASE_0 0x0092 3680#define mmCOHER_DEST_BASE_0_BASE_IDX 1 3681#define mmCOHER_DEST_BASE_1 0x0093 3682#define mmCOHER_DEST_BASE_1_BASE_IDX 1 3683#define mmPA_SC_VPORT_SCISSOR_0_TL 0x0094 3684#define mmPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX 1 3685#define mmPA_SC_VPORT_SCISSOR_0_BR 0x0095 3686#define mmPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX 1 3687#define mmPA_SC_VPORT_SCISSOR_1_TL 0x0096 3688#define mmPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX 1 3689#define mmPA_SC_VPORT_SCISSOR_1_BR 0x0097 3690#define mmPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX 1 3691#define mmPA_SC_VPORT_SCISSOR_2_TL 0x0098 3692#define mmPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX 1 3693#define mmPA_SC_VPORT_SCISSOR_2_BR 0x0099 3694#define mmPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX 1 3695#define mmPA_SC_VPORT_SCISSOR_3_TL 0x009a 3696#define mmPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX 1 3697#define mmPA_SC_VPORT_SCISSOR_3_BR 0x009b 3698#define mmPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX 1 3699#define mmPA_SC_VPORT_SCISSOR_4_TL 0x009c 3700#define mmPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX 1 3701#define mmPA_SC_VPORT_SCISSOR_4_BR 0x009d 3702#define mmPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX 1 3703#define mmPA_SC_VPORT_SCISSOR_5_TL 0x009e 3704#define mmPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX 1 3705#define mmPA_SC_VPORT_SCISSOR_5_BR 0x009f 3706#define mmPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX 1 3707#define mmPA_SC_VPORT_SCISSOR_6_TL 0x00a0 3708#define mmPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX 1 3709#define mmPA_SC_VPORT_SCISSOR_6_BR 0x00a1 3710#define mmPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX 1 3711#define mmPA_SC_VPORT_SCISSOR_7_TL 0x00a2 3712#define mmPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX 1 3713#define mmPA_SC_VPORT_SCISSOR_7_BR 0x00a3 3714#define mmPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX 1 3715#define mmPA_SC_VPORT_SCISSOR_8_TL 0x00a4 3716#define mmPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX 1 3717#define mmPA_SC_VPORT_SCISSOR_8_BR 0x00a5 3718#define mmPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX 1 3719#define mmPA_SC_VPORT_SCISSOR_9_TL 0x00a6 3720#define mmPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX 1 3721#define mmPA_SC_VPORT_SCISSOR_9_BR 0x00a7 3722#define mmPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX 1 3723#define mmPA_SC_VPORT_SCISSOR_10_TL 0x00a8 3724#define mmPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX 1 3725#define mmPA_SC_VPORT_SCISSOR_10_BR 0x00a9 3726#define mmPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX 1 3727#define mmPA_SC_VPORT_SCISSOR_11_TL 0x00aa 3728#define mmPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX 1 3729#define mmPA_SC_VPORT_SCISSOR_11_BR 0x00ab 3730#define mmPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX 1 3731#define mmPA_SC_VPORT_SCISSOR_12_TL 0x00ac 3732#define mmPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX 1 3733#define mmPA_SC_VPORT_SCISSOR_12_BR 0x00ad 3734#define mmPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX 1 3735#define mmPA_SC_VPORT_SCISSOR_13_TL 0x00ae 3736#define mmPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX 1 3737#define mmPA_SC_VPORT_SCISSOR_13_BR 0x00af 3738#define mmPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX 1 3739#define mmPA_SC_VPORT_SCISSOR_14_TL 0x00b0 3740#define mmPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX 1 3741#define mmPA_SC_VPORT_SCISSOR_14_BR 0x00b1 3742#define mmPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX 1 3743#define mmPA_SC_VPORT_SCISSOR_15_TL 0x00b2 3744#define mmPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX 1 3745#define mmPA_SC_VPORT_SCISSOR_15_BR 0x00b3 3746#define mmPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX 1 3747#define mmPA_SC_VPORT_ZMIN_0 0x00b4 3748#define mmPA_SC_VPORT_ZMIN_0_BASE_IDX 1 3749#define mmPA_SC_VPORT_ZMAX_0 0x00b5 3750#define mmPA_SC_VPORT_ZMAX_0_BASE_IDX 1 3751#define mmPA_SC_VPORT_ZMIN_1 0x00b6 3752#define mmPA_SC_VPORT_ZMIN_1_BASE_IDX 1 3753#define mmPA_SC_VPORT_ZMAX_1 0x00b7 3754#define mmPA_SC_VPORT_ZMAX_1_BASE_IDX 1 3755#define mmPA_SC_VPORT_ZMIN_2 0x00b8 3756#define mmPA_SC_VPORT_ZMIN_2_BASE_IDX 1 3757#define mmPA_SC_VPORT_ZMAX_2 0x00b9 3758#define mmPA_SC_VPORT_ZMAX_2_BASE_IDX 1 3759#define mmPA_SC_VPORT_ZMIN_3 0x00ba 3760#define mmPA_SC_VPORT_ZMIN_3_BASE_IDX 1 3761#define mmPA_SC_VPORT_ZMAX_3 0x00bb 3762#define mmPA_SC_VPORT_ZMAX_3_BASE_IDX 1 3763#define mmPA_SC_VPORT_ZMIN_4 0x00bc 3764#define mmPA_SC_VPORT_ZMIN_4_BASE_IDX 1 3765#define mmPA_SC_VPORT_ZMAX_4 0x00bd 3766#define mmPA_SC_VPORT_ZMAX_4_BASE_IDX 1 3767#define mmPA_SC_VPORT_ZMIN_5 0x00be 3768#define mmPA_SC_VPORT_ZMIN_5_BASE_IDX 1 3769#define mmPA_SC_VPORT_ZMAX_5 0x00bf 3770#define mmPA_SC_VPORT_ZMAX_5_BASE_IDX 1 3771#define mmPA_SC_VPORT_ZMIN_6 0x00c0 3772#define mmPA_SC_VPORT_ZMIN_6_BASE_IDX 1 3773#define mmPA_SC_VPORT_ZMAX_6 0x00c1 3774#define mmPA_SC_VPORT_ZMAX_6_BASE_IDX 1 3775#define mmPA_SC_VPORT_ZMIN_7 0x00c2 3776#define mmPA_SC_VPORT_ZMIN_7_BASE_IDX 1 3777#define mmPA_SC_VPORT_ZMAX_7 0x00c3 3778#define mmPA_SC_VPORT_ZMAX_7_BASE_IDX 1 3779#define mmPA_SC_VPORT_ZMIN_8 0x00c4 3780#define mmPA_SC_VPORT_ZMIN_8_BASE_IDX 1 3781#define mmPA_SC_VPORT_ZMAX_8 0x00c5 3782#define mmPA_SC_VPORT_ZMAX_8_BASE_IDX 1 3783#define mmPA_SC_VPORT_ZMIN_9 0x00c6 3784#define mmPA_SC_VPORT_ZMIN_9_BASE_IDX 1 3785#define mmPA_SC_VPORT_ZMAX_9 0x00c7 3786#define mmPA_SC_VPORT_ZMAX_9_BASE_IDX 1 3787#define mmPA_SC_VPORT_ZMIN_10 0x00c8 3788#define mmPA_SC_VPORT_ZMIN_10_BASE_IDX 1 3789#define mmPA_SC_VPORT_ZMAX_10 0x00c9 3790#define mmPA_SC_VPORT_ZMAX_10_BASE_IDX 1 3791#define mmPA_SC_VPORT_ZMIN_11 0x00ca 3792#define mmPA_SC_VPORT_ZMIN_11_BASE_IDX 1 3793#define mmPA_SC_VPORT_ZMAX_11 0x00cb 3794#define mmPA_SC_VPORT_ZMAX_11_BASE_IDX 1 3795#define mmPA_SC_VPORT_ZMIN_12 0x00cc 3796#define mmPA_SC_VPORT_ZMIN_12_BASE_IDX 1 3797#define mmPA_SC_VPORT_ZMAX_12 0x00cd 3798#define mmPA_SC_VPORT_ZMAX_12_BASE_IDX 1 3799#define mmPA_SC_VPORT_ZMIN_13 0x00ce 3800#define mmPA_SC_VPORT_ZMIN_13_BASE_IDX 1 3801#define mmPA_SC_VPORT_ZMAX_13 0x00cf 3802#define mmPA_SC_VPORT_ZMAX_13_BASE_IDX 1 3803#define mmPA_SC_VPORT_ZMIN_14 0x00d0 3804#define mmPA_SC_VPORT_ZMIN_14_BASE_IDX 1 3805#define mmPA_SC_VPORT_ZMAX_14 0x00d1 3806#define mmPA_SC_VPORT_ZMAX_14_BASE_IDX 1 3807#define mmPA_SC_VPORT_ZMIN_15 0x00d2 3808#define mmPA_SC_VPORT_ZMIN_15_BASE_IDX 1 3809#define mmPA_SC_VPORT_ZMAX_15 0x00d3 3810#define mmPA_SC_VPORT_ZMAX_15_BASE_IDX 1 3811#define mmPA_SC_RASTER_CONFIG 0x00d4 3812#define mmPA_SC_RASTER_CONFIG_BASE_IDX 1 3813#define mmPA_SC_RASTER_CONFIG_1 0x00d5 3814#define mmPA_SC_RASTER_CONFIG_1_BASE_IDX 1 3815#define mmPA_SC_SCREEN_EXTENT_CONTROL 0x00d6 3816#define mmPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX 1 3817#define mmPA_SC_TILE_STEERING_OVERRIDE 0x00d7 3818#define mmPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX 1 3819#define mmCP_PERFMON_CNTX_CNTL 0x00d8 3820#define mmCP_PERFMON_CNTX_CNTL_BASE_IDX 1 3821#define mmCP_PIPEID 0x00d9 3822#define mmCP_PIPEID_BASE_IDX 1 3823#define mmCP_RINGID 0x00d9 3824#define mmCP_RINGID_BASE_IDX 1 3825#define mmCP_VMID 0x00da 3826#define mmCP_VMID_BASE_IDX 1 3827#define mmPA_SC_RIGHT_VERT_GRID 0x00e8 3828#define mmPA_SC_RIGHT_VERT_GRID_BASE_IDX 1 3829#define mmPA_SC_LEFT_VERT_GRID 0x00e9 3830#define mmPA_SC_LEFT_VERT_GRID_BASE_IDX 1 3831#define mmPA_SC_HORIZ_GRID 0x00ea 3832#define mmPA_SC_HORIZ_GRID_BASE_IDX 1 3833#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x0103 3834#define mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1 3835#define mmCB_BLEND_RED 0x0105 3836#define mmCB_BLEND_RED_BASE_IDX 1 3837#define mmCB_BLEND_GREEN 0x0106 3838#define mmCB_BLEND_GREEN_BASE_IDX 1 3839#define mmCB_BLEND_BLUE 0x0107 3840#define mmCB_BLEND_BLUE_BASE_IDX 1 3841#define mmCB_BLEND_ALPHA 0x0108 3842#define mmCB_BLEND_ALPHA_BASE_IDX 1 3843#define mmCB_DCC_CONTROL 0x0109 3844#define mmCB_DCC_CONTROL_BASE_IDX 1 3845#define mmDB_STENCIL_CONTROL 0x010b 3846#define mmDB_STENCIL_CONTROL_BASE_IDX 1 3847#define mmDB_STENCILREFMASK 0x010c 3848#define mmDB_STENCILREFMASK_BASE_IDX 1 3849#define mmDB_STENCILREFMASK_BF 0x010d 3850#define mmDB_STENCILREFMASK_BF_BASE_IDX 1 3851#define mmPA_CL_VPORT_XSCALE 0x010f 3852#define mmPA_CL_VPORT_XSCALE_BASE_IDX 1 3853#define mmPA_CL_VPORT_XOFFSET 0x0110 3854#define mmPA_CL_VPORT_XOFFSET_BASE_IDX 1 3855#define mmPA_CL_VPORT_YSCALE 0x0111 3856#define mmPA_CL_VPORT_YSCALE_BASE_IDX 1 3857#define mmPA_CL_VPORT_YOFFSET 0x0112 3858#define mmPA_CL_VPORT_YOFFSET_BASE_IDX 1 3859#define mmPA_CL_VPORT_ZSCALE 0x0113 3860#define mmPA_CL_VPORT_ZSCALE_BASE_IDX 1 3861#define mmPA_CL_VPORT_ZOFFSET 0x0114 3862#define mmPA_CL_VPORT_ZOFFSET_BASE_IDX 1 3863#define mmPA_CL_VPORT_XSCALE_1 0x0115 3864#define mmPA_CL_VPORT_XSCALE_1_BASE_IDX 1 3865#define mmPA_CL_VPORT_XOFFSET_1 0x0116 3866#define mmPA_CL_VPORT_XOFFSET_1_BASE_IDX 1 3867#define mmPA_CL_VPORT_YSCALE_1 0x0117 3868#define mmPA_CL_VPORT_YSCALE_1_BASE_IDX 1 3869#define mmPA_CL_VPORT_YOFFSET_1 0x0118 3870#define mmPA_CL_VPORT_YOFFSET_1_BASE_IDX 1 3871#define mmPA_CL_VPORT_ZSCALE_1 0x0119 3872#define mmPA_CL_VPORT_ZSCALE_1_BASE_IDX 1 3873#define mmPA_CL_VPORT_ZOFFSET_1 0x011a 3874#define mmPA_CL_VPORT_ZOFFSET_1_BASE_IDX 1 3875#define mmPA_CL_VPORT_XSCALE_2 0x011b 3876#define mmPA_CL_VPORT_XSCALE_2_BASE_IDX 1 3877#define mmPA_CL_VPORT_XOFFSET_2 0x011c 3878#define mmPA_CL_VPORT_XOFFSET_2_BASE_IDX 1 3879#define mmPA_CL_VPORT_YSCALE_2 0x011d 3880#define mmPA_CL_VPORT_YSCALE_2_BASE_IDX 1 3881#define mmPA_CL_VPORT_YOFFSET_2 0x011e 3882#define mmPA_CL_VPORT_YOFFSET_2_BASE_IDX 1 3883#define mmPA_CL_VPORT_ZSCALE_2 0x011f 3884#define mmPA_CL_VPORT_ZSCALE_2_BASE_IDX 1 3885#define mmPA_CL_VPORT_ZOFFSET_2 0x0120 3886#define mmPA_CL_VPORT_ZOFFSET_2_BASE_IDX 1 3887#define mmPA_CL_VPORT_XSCALE_3 0x0121 3888#define mmPA_CL_VPORT_XSCALE_3_BASE_IDX 1 3889#define mmPA_CL_VPORT_XOFFSET_3 0x0122 3890#define mmPA_CL_VPORT_XOFFSET_3_BASE_IDX 1 3891#define mmPA_CL_VPORT_YSCALE_3 0x0123 3892#define mmPA_CL_VPORT_YSCALE_3_BASE_IDX 1 3893#define mmPA_CL_VPORT_YOFFSET_3 0x0124 3894#define mmPA_CL_VPORT_YOFFSET_3_BASE_IDX 1 3895#define mmPA_CL_VPORT_ZSCALE_3 0x0125 3896#define mmPA_CL_VPORT_ZSCALE_3_BASE_IDX 1 3897#define mmPA_CL_VPORT_ZOFFSET_3 0x0126 3898#define mmPA_CL_VPORT_ZOFFSET_3_BASE_IDX 1 3899#define mmPA_CL_VPORT_XSCALE_4 0x0127 3900#define mmPA_CL_VPORT_XSCALE_4_BASE_IDX 1 3901#define mmPA_CL_VPORT_XOFFSET_4 0x0128 3902#define mmPA_CL_VPORT_XOFFSET_4_BASE_IDX 1 3903#define mmPA_CL_VPORT_YSCALE_4 0x0129 3904#define mmPA_CL_VPORT_YSCALE_4_BASE_IDX 1 3905#define mmPA_CL_VPORT_YOFFSET_4 0x012a 3906#define mmPA_CL_VPORT_YOFFSET_4_BASE_IDX 1 3907#define mmPA_CL_VPORT_ZSCALE_4 0x012b 3908#define mmPA_CL_VPORT_ZSCALE_4_BASE_IDX 1 3909#define mmPA_CL_VPORT_ZOFFSET_4 0x012c 3910#define mmPA_CL_VPORT_ZOFFSET_4_BASE_IDX 1 3911#define mmPA_CL_VPORT_XSCALE_5 0x012d 3912#define mmPA_CL_VPORT_XSCALE_5_BASE_IDX 1 3913#define mmPA_CL_VPORT_XOFFSET_5 0x012e 3914#define mmPA_CL_VPORT_XOFFSET_5_BASE_IDX 1 3915#define mmPA_CL_VPORT_YSCALE_5 0x012f 3916#define mmPA_CL_VPORT_YSCALE_5_BASE_IDX 1 3917#define mmPA_CL_VPORT_YOFFSET_5 0x0130 3918#define mmPA_CL_VPORT_YOFFSET_5_BASE_IDX 1 3919#define mmPA_CL_VPORT_ZSCALE_5 0x0131 3920#define mmPA_CL_VPORT_ZSCALE_5_BASE_IDX 1 3921#define mmPA_CL_VPORT_ZOFFSET_5 0x0132 3922#define mmPA_CL_VPORT_ZOFFSET_5_BASE_IDX 1 3923#define mmPA_CL_VPORT_XSCALE_6 0x0133 3924#define mmPA_CL_VPORT_XSCALE_6_BASE_IDX 1 3925#define mmPA_CL_VPORT_XOFFSET_6 0x0134 3926#define mmPA_CL_VPORT_XOFFSET_6_BASE_IDX 1 3927#define mmPA_CL_VPORT_YSCALE_6 0x0135 3928#define mmPA_CL_VPORT_YSCALE_6_BASE_IDX 1 3929#define mmPA_CL_VPORT_YOFFSET_6 0x0136 3930#define mmPA_CL_VPORT_YOFFSET_6_BASE_IDX 1 3931#define mmPA_CL_VPORT_ZSCALE_6 0x0137 3932#define mmPA_CL_VPORT_ZSCALE_6_BASE_IDX 1 3933#define mmPA_CL_VPORT_ZOFFSET_6 0x0138 3934#define mmPA_CL_VPORT_ZOFFSET_6_BASE_IDX 1 3935#define mmPA_CL_VPORT_XSCALE_7 0x0139 3936#define mmPA_CL_VPORT_XSCALE_7_BASE_IDX 1 3937#define mmPA_CL_VPORT_XOFFSET_7 0x013a 3938#define mmPA_CL_VPORT_XOFFSET_7_BASE_IDX 1 3939#define mmPA_CL_VPORT_YSCALE_7 0x013b 3940#define mmPA_CL_VPORT_YSCALE_7_BASE_IDX 1 3941#define mmPA_CL_VPORT_YOFFSET_7 0x013c 3942#define mmPA_CL_VPORT_YOFFSET_7_BASE_IDX 1 3943#define mmPA_CL_VPORT_ZSCALE_7 0x013d 3944#define mmPA_CL_VPORT_ZSCALE_7_BASE_IDX 1 3945#define mmPA_CL_VPORT_ZOFFSET_7 0x013e 3946#define mmPA_CL_VPORT_ZOFFSET_7_BASE_IDX 1 3947#define mmPA_CL_VPORT_XSCALE_8 0x013f 3948#define mmPA_CL_VPORT_XSCALE_8_BASE_IDX 1 3949#define mmPA_CL_VPORT_XOFFSET_8 0x0140 3950#define mmPA_CL_VPORT_XOFFSET_8_BASE_IDX 1 3951#define mmPA_CL_VPORT_YSCALE_8 0x0141 3952#define mmPA_CL_VPORT_YSCALE_8_BASE_IDX 1 3953#define mmPA_CL_VPORT_YOFFSET_8 0x0142 3954#define mmPA_CL_VPORT_YOFFSET_8_BASE_IDX 1 3955#define mmPA_CL_VPORT_ZSCALE_8 0x0143 3956#define mmPA_CL_VPORT_ZSCALE_8_BASE_IDX 1 3957#define mmPA_CL_VPORT_ZOFFSET_8 0x0144 3958#define mmPA_CL_VPORT_ZOFFSET_8_BASE_IDX 1 3959#define mmPA_CL_VPORT_XSCALE_9 0x0145 3960#define mmPA_CL_VPORT_XSCALE_9_BASE_IDX 1 3961#define mmPA_CL_VPORT_XOFFSET_9 0x0146 3962#define mmPA_CL_VPORT_XOFFSET_9_BASE_IDX 1 3963#define mmPA_CL_VPORT_YSCALE_9 0x0147 3964#define mmPA_CL_VPORT_YSCALE_9_BASE_IDX 1 3965#define mmPA_CL_VPORT_YOFFSET_9 0x0148 3966#define mmPA_CL_VPORT_YOFFSET_9_BASE_IDX 1 3967#define mmPA_CL_VPORT_ZSCALE_9 0x0149 3968#define mmPA_CL_VPORT_ZSCALE_9_BASE_IDX 1 3969#define mmPA_CL_VPORT_ZOFFSET_9 0x014a 3970#define mmPA_CL_VPORT_ZOFFSET_9_BASE_IDX 1 3971#define mmPA_CL_VPORT_XSCALE_10 0x014b 3972#define mmPA_CL_VPORT_XSCALE_10_BASE_IDX 1 3973#define mmPA_CL_VPORT_XOFFSET_10 0x014c 3974#define mmPA_CL_VPORT_XOFFSET_10_BASE_IDX 1 3975#define mmPA_CL_VPORT_YSCALE_10 0x014d 3976#define mmPA_CL_VPORT_YSCALE_10_BASE_IDX 1 3977#define mmPA_CL_VPORT_YOFFSET_10 0x014e 3978#define mmPA_CL_VPORT_YOFFSET_10_BASE_IDX 1 3979#define mmPA_CL_VPORT_ZSCALE_10 0x014f 3980#define mmPA_CL_VPORT_ZSCALE_10_BASE_IDX 1 3981#define mmPA_CL_VPORT_ZOFFSET_10 0x0150 3982#define mmPA_CL_VPORT_ZOFFSET_10_BASE_IDX 1 3983#define mmPA_CL_VPORT_XSCALE_11 0x0151 3984#define mmPA_CL_VPORT_XSCALE_11_BASE_IDX 1 3985#define mmPA_CL_VPORT_XOFFSET_11 0x0152 3986#define mmPA_CL_VPORT_XOFFSET_11_BASE_IDX 1 3987#define mmPA_CL_VPORT_YSCALE_11 0x0153 3988#define mmPA_CL_VPORT_YSCALE_11_BASE_IDX 1 3989#define mmPA_CL_VPORT_YOFFSET_11 0x0154 3990#define mmPA_CL_VPORT_YOFFSET_11_BASE_IDX 1 3991#define mmPA_CL_VPORT_ZSCALE_11 0x0155 3992#define mmPA_CL_VPORT_ZSCALE_11_BASE_IDX 1 3993#define mmPA_CL_VPORT_ZOFFSET_11 0x0156 3994#define mmPA_CL_VPORT_ZOFFSET_11_BASE_IDX 1 3995#define mmPA_CL_VPORT_XSCALE_12 0x0157 3996#define mmPA_CL_VPORT_XSCALE_12_BASE_IDX 1 3997#define mmPA_CL_VPORT_XOFFSET_12 0x0158 3998#define mmPA_CL_VPORT_XOFFSET_12_BASE_IDX 1 3999#define mmPA_CL_VPORT_YSCALE_12 0x0159 4000#define mmPA_CL_VPORT_YSCALE_12_BASE_IDX 1
4001#define mmPA_CL_VPORT_YOFFSET_12 0x015a 4002#define mmPA_CL_VPORT_YOFFSET_12_BASE_IDX 1 4003#define mmPA_CL_VPORT_ZSCALE_12 0x015b 4004#define mmPA_CL_VPORT_ZSCALE_12_BASE_IDX 1 4005#define mmPA_CL_VPORT_ZOFFSET_12 0x015c 4006#define mmPA_CL_VPORT_ZOFFSET_12_BASE_IDX 1 4007#define mmPA_CL_VPORT_XSCALE_13 0x015d 4008#define mmPA_CL_VPORT_XSCALE_13_BASE_IDX 1 4009#define mmPA_CL_VPORT_XOFFSET_13 0x015e 4010#define mmPA_CL_VPORT_XOFFSET_13_BASE_IDX 1 4011#define mmPA_CL_VPORT_YSCALE_13 0x015f 4012#define mmPA_CL_VPORT_YSCALE_13_BASE_IDX 1 4013#define mmPA_CL_VPORT_YOFFSET_13 0x0160 4014#define mmPA_CL_VPORT_YOFFSET_13_BASE_IDX 1 4015#define mmPA_CL_VPORT_ZSCALE_13 0x0161 4016#define mmPA_CL_VPORT_ZSCALE_13_BASE_IDX 1 4017#define mmPA_CL_VPORT_ZOFFSET_13 0x0162 4018#define mmPA_CL_VPORT_ZOFFSET_13_BASE_IDX 1 4019#define mmPA_CL_VPORT_XSCALE_14 0x0163 4020#define mmPA_CL_VPORT_XSCALE_14_BASE_IDX 1 4021#define mmPA_CL_VPORT_XOFFSET_14 0x0164 4022#define mmPA_CL_VPORT_XOFFSET_14_BASE_IDX 1 4023#define mmPA_CL_VPORT_YSCALE_14 0x0165 4024#define mmPA_CL_VPORT_YSCALE_14_BASE_IDX 1 4025#define mmPA_CL_VPORT_YOFFSET_14 0x0166 4026#define mmPA_CL_VPORT_YOFFSET_14_BASE_IDX 1 4027#define mmPA_CL_VPORT_ZSCALE_14 0x0167 4028#define mmPA_CL_VPORT_ZSCALE_14_BASE_IDX 1 4029#define mmPA_CL_VPORT_ZOFFSET_14 0x0168 4030#define mmPA_CL_VPORT_ZOFFSET_14_BASE_IDX 1 4031#define mmPA_CL_VPORT_XSCALE_15 0x0169 4032#define mmPA_CL_VPORT_XSCALE_15_BASE_IDX 1 4033#define mmPA_CL_VPORT_XOFFSET_15 0x016a 4034#define mmPA_CL_VPORT_XOFFSET_15_BASE_IDX 1 4035#define mmPA_CL_VPORT_YSCALE_15 0x016b 4036#define mmPA_CL_VPORT_YSCALE_15_BASE_IDX 1 4037#define mmPA_CL_VPORT_YOFFSET_15 0x016c 4038#define mmPA_CL_VPORT_YOFFSET_15_BASE_IDX 1 4039#define mmPA_CL_VPORT_ZSCALE_15 0x016d 4040#define mmPA_CL_VPORT_ZSCALE_15_BASE_IDX 1 4041#define mmPA_CL_VPORT_ZOFFSET_15 0x016e 4042#define mmPA_CL_VPORT_ZOFFSET_15_BASE_IDX 1 4043#define mmPA_CL_UCP_0_X 0x016f 4044#define mmPA_CL_UCP_0_X_BASE_IDX 1 4045#define mmPA_CL_UCP_0_Y 0x0170 4046#define mmPA_CL_UCP_0_Y_BASE_IDX 1 4047#define mmPA_CL_UCP_0_Z 0x0171 4048#define mmPA_CL_UCP_0_Z_BASE_IDX 1 4049#define mmPA_CL_UCP_0_W 0x0172 4050#define mmPA_CL_UCP_0_W_BASE_IDX 1 4051#define mmPA_CL_UCP_1_X 0x0173 4052#define mmPA_CL_UCP_1_X_BASE_IDX 1 4053#define mmPA_CL_UCP_1_Y 0x0174 4054#define mmPA_CL_UCP_1_Y_BASE_IDX 1 4055#define mmPA_CL_UCP_1_Z 0x0175 4056#define mmPA_CL_UCP_1_Z_BASE_IDX 1 4057#define mmPA_CL_UCP_1_W 0x0176 4058#define mmPA_CL_UCP_1_W_BASE_IDX 1 4059#define mmPA_CL_UCP_2_X 0x0177 4060#define mmPA_CL_UCP_2_X_BASE_IDX 1 4061#define mmPA_CL_UCP_2_Y 0x0178 4062#define mmPA_CL_UCP_2_Y_BASE_IDX 1 4063#define mmPA_CL_UCP_2_Z 0x0179 4064#define mmPA_CL_UCP_2_Z_BASE_IDX 1 4065#define mmPA_CL_UCP_2_W 0x017a 4066#define mmPA_CL_UCP_2_W_BASE_IDX 1 4067#define mmPA_CL_UCP_3_X 0x017b 4068#define mmPA_CL_UCP_3_X_BASE_IDX 1 4069#define mmPA_CL_UCP_3_Y 0x017c 4070#define mmPA_CL_UCP_3_Y_BASE_IDX 1 4071#define mmPA_CL_UCP_3_Z 0x017d 4072#define mmPA_CL_UCP_3_Z_BASE_IDX 1 4073#define mmPA_CL_UCP_3_W 0x017e 4074#define mmPA_CL_UCP_3_W_BASE_IDX 1 4075#define mmPA_CL_UCP_4_X 0x017f 4076#define mmPA_CL_UCP_4_X_BASE_IDX 1 4077#define mmPA_CL_UCP_4_Y 0x0180 4078#define mmPA_CL_UCP_4_Y_BASE_IDX 1 4079#define mmPA_CL_UCP_4_Z 0x0181 4080#define mmPA_CL_UCP_4_Z_BASE_IDX 1 4081#define mmPA_CL_UCP_4_W 0x0182 4082#define mmPA_CL_UCP_4_W_BASE_IDX 1 4083#define mmPA_CL_UCP_5_X 0x0183 4084#define mmPA_CL_UCP_5_X_BASE_IDX 1 4085#define mmPA_CL_UCP_5_Y 0x0184 4086#define mmPA_CL_UCP_5_Y_BASE_IDX 1 4087#define mmPA_CL_UCP_5_Z 0x0185 4088#define mmPA_CL_UCP_5_Z_BASE_IDX 1 4089#define mmPA_CL_UCP_5_W 0x0186 4090#define mmPA_CL_UCP_5_W_BASE_IDX 1 4091#define mmSPI_PS_INPUT_CNTL_0 0x0191 4092#define mmSPI_PS_INPUT_CNTL_0_BASE_IDX 1 4093#define mmSPI_PS_INPUT_CNTL_1 0x0192 4094#define mmSPI_PS_INPUT_CNTL_1_BASE_IDX 1 4095#define mmSPI_PS_INPUT_CNTL_2 0x0193 4096#define mmSPI_PS_INPUT_CNTL_2_BASE_IDX 1 4097#define mmSPI_PS_INPUT_CNTL_3 0x0194 4098#define mmSPI_PS_INPUT_CNTL_3_BASE_IDX 1 4099#define mmSPI_PS_INPUT_CNTL_4 0x0195 4100#define mmSPI_PS_INPUT_CNTL_4_BASE_IDX 1 4101#define mmSPI_PS_INPUT_CNTL_5 0x0196 4102#define mmSPI_PS_INPUT_CNTL_5_BASE_IDX 1 4103#define mmSPI_PS_INPUT_CNTL_6 0x0197 4104#define mmSPI_PS_INPUT_CNTL_6_BASE_IDX 1 4105#define mmSPI_PS_INPUT_CNTL_7 0x0198 4106#define mmSPI_PS_INPUT_CNTL_7_BASE_IDX 1 4107#define mmSPI_PS_INPUT_CNTL_8 0x0199 4108#define mmSPI_PS_INPUT_CNTL_8_BASE_IDX 1 4109#define mmSPI_PS_INPUT_CNTL_9 0x019a 4110#define mmSPI_PS_INPUT_CNTL_9_BASE_IDX 1 4111#define mmSPI_PS_INPUT_CNTL_10 0x019b 4112#define mmSPI_PS_INPUT_CNTL_10_BASE_IDX 1 4113#define mmSPI_PS_INPUT_CNTL_11 0x019c 4114#define mmSPI_PS_INPUT_CNTL_11_BASE_IDX 1 4115#define mmSPI_PS_INPUT_CNTL_12 0x019d 4116#define mmSPI_PS_INPUT_CNTL_12_BASE_IDX 1 4117#define mmSPI_PS_INPUT_CNTL_13 0x019e 4118#define mmSPI_PS_INPUT_CNTL_13_BASE_IDX 1 4119#define mmSPI_PS_INPUT_CNTL_14 0x019f 4120#define mmSPI_PS_INPUT_CNTL_14_BASE_IDX 1 4121#define mmSPI_PS_INPUT_CNTL_15 0x01a0 4122#define mmSPI_PS_INPUT_CNTL_15_BASE_IDX 1 4123#define mmSPI_PS_INPUT_CNTL_16 0x01a1 4124#define mmSPI_PS_INPUT_CNTL_16_BASE_IDX 1 4125#define mmSPI_PS_INPUT_CNTL_17 0x01a2 4126#define mmSPI_PS_INPUT_CNTL_17_BASE_IDX 1 4127#define mmSPI_PS_INPUT_CNTL_18 0x01a3 4128#define mmSPI_PS_INPUT_CNTL_18_BASE_IDX 1 4129#define mmSPI_PS_INPUT_CNTL_19 0x01a4 4130#define mmSPI_PS_INPUT_CNTL_19_BASE_IDX 1 4131#define mmSPI_PS_INPUT_CNTL_20 0x01a5 4132#define mmSPI_PS_INPUT_CNTL_20_BASE_IDX 1 4133#define mmSPI_PS_INPUT_CNTL_21 0x01a6 4134#define mmSPI_PS_INPUT_CNTL_21_BASE_IDX 1 4135#define mmSPI_PS_INPUT_CNTL_22 0x01a7 4136#define mmSPI_PS_INPUT_CNTL_22_BASE_IDX 1 4137#define mmSPI_PS_INPUT_CNTL_23 0x01a8 4138#define mmSPI_PS_INPUT_CNTL_23_BASE_IDX 1 4139#define mmSPI_PS_INPUT_CNTL_24 0x01a9 4140#define mmSPI_PS_INPUT_CNTL_24_BASE_IDX 1 4141#define mmSPI_PS_INPUT_CNTL_25 0x01aa 4142#define mmSPI_PS_INPUT_CNTL_25_BASE_IDX 1 4143#define mmSPI_PS_INPUT_CNTL_26 0x01ab 4144#define mmSPI_PS_INPUT_CNTL_26_BASE_IDX 1 4145#define mmSPI_PS_INPUT_CNTL_27 0x01ac 4146#define mmSPI_PS_INPUT_CNTL_27_BASE_IDX 1 4147#define mmSPI_PS_INPUT_CNTL_28 0x01ad 4148#define mmSPI_PS_INPUT_CNTL_28_BASE_IDX 1 4149#define mmSPI_PS_INPUT_CNTL_29 0x01ae 4150#define mmSPI_PS_INPUT_CNTL_29_BASE_IDX 1 4151#define mmSPI_PS_INPUT_CNTL_30 0x01af 4152#define mmSPI_PS_INPUT_CNTL_30_BASE_IDX 1 4153#define mmSPI_PS_INPUT_CNTL_31 0x01b0 4154#define mmSPI_PS_INPUT_CNTL_31_BASE_IDX 1 4155#define mmSPI_VS_OUT_CONFIG 0x01b1 4156#define mmSPI_VS_OUT_CONFIG_BASE_IDX 1 4157#define mmSPI_PS_INPUT_ENA 0x01b3 4158#define mmSPI_PS_INPUT_ENA_BASE_IDX 1 4159#define mmSPI_PS_INPUT_ADDR 0x01b4 4160#define mmSPI_PS_INPUT_ADDR_BASE_IDX 1 4161#define mmSPI_INTERP_CONTROL_0 0x01b5 4162#define mmSPI_INTERP_CONTROL_0_BASE_IDX 1 4163#define mmSPI_PS_IN_CONTROL 0x01b6 4164#define mmSPI_PS_IN_CONTROL_BASE_IDX 1 4165#define mmSPI_BARYC_CNTL 0x01b8 4166#define mmSPI_BARYC_CNTL_BASE_IDX 1 4167#define mmSPI_TMPRING_SIZE 0x01ba 4168#define mmSPI_TMPRING_SIZE_BASE_IDX 1 4169#define mmSPI_SHADER_POS_FORMAT 0x01c3 4170#define mmSPI_SHADER_POS_FORMAT_BASE_IDX 1 4171#define mmSPI_SHADER_Z_FORMAT 0x01c4 4172#define mmSPI_SHADER_Z_FORMAT_BASE_IDX 1 4173#define mmSPI_SHADER_COL_FORMAT 0x01c5 4174#define mmSPI_SHADER_COL_FORMAT_BASE_IDX 1 4175#define mmSX_PS_DOWNCONVERT 0x01d5 4176#define mmSX_PS_DOWNCONVERT_BASE_IDX 1 4177#define mmSX_BLEND_OPT_EPSILON 0x01d6 4178#define mmSX_BLEND_OPT_EPSILON_BASE_IDX 1 4179#define mmSX_BLEND_OPT_CONTROL 0x01d7 4180#define mmSX_BLEND_OPT_CONTROL_BASE_IDX 1 4181#define mmSX_MRT0_BLEND_OPT 0x01d8 4182#define mmSX_MRT0_BLEND_OPT_BASE_IDX 1 4183#define mmSX_MRT1_BLEND_OPT 0x01d9 4184#define mmSX_MRT1_BLEND_OPT_BASE_IDX 1 4185#define mmSX_MRT2_BLEND_OPT 0x01da 4186#define mmSX_MRT2_BLEND_OPT_BASE_IDX 1 4187#define mmSX_MRT3_BLEND_OPT 0x01db 4188#define mmSX_MRT3_BLEND_OPT_BASE_IDX 1 4189#define mmSX_MRT4_BLEND_OPT 0x01dc 4190#define mmSX_MRT4_BLEND_OPT_BASE_IDX 1 4191#define mmSX_MRT5_BLEND_OPT 0x01dd 4192#define mmSX_MRT5_BLEND_OPT_BASE_IDX 1 4193#define mmSX_MRT6_BLEND_OPT 0x01de 4194#define mmSX_MRT6_BLEND_OPT_BASE_IDX 1 4195#define mmSX_MRT7_BLEND_OPT 0x01df 4196#define mmSX_MRT7_BLEND_OPT_BASE_IDX 1 4197#define mmCB_BLEND0_CONTROL 0x01e0 4198#define mmCB_BLEND0_CONTROL_BASE_IDX 1 4199#define mmCB_BLEND1_CONTROL 0x01e1 4200#define mmCB_BLEND1_CONTROL_BASE_IDX 1 4201#define mmCB_BLEND2_CONTROL 0x01e2 4202#define mmCB_BLEND2_CONTROL_BASE_IDX 1 4203#define mmCB_BLEND3_CONTROL 0x01e3 4204#define mmCB_BLEND3_CONTROL_BASE_IDX 1 4205#define mmCB_BLEND4_CONTROL 0x01e4 4206#define mmCB_BLEND4_CONTROL_BASE_IDX 1 4207#define mmCB_BLEND5_CONTROL 0x01e5 4208#define mmCB_BLEND5_CONTROL_BASE_IDX 1 4209#define mmCB_BLEND6_CONTROL 0x01e6 4210#define mmCB_BLEND6_CONTROL_BASE_IDX 1 4211#define mmCB_BLEND7_CONTROL 0x01e7 4212#define mmCB_BLEND7_CONTROL_BASE_IDX 1 4213#define mmCB_MRT0_EPITCH 0x01e8 4214#define mmCB_MRT0_EPITCH_BASE_IDX 1 4215#define mmCB_MRT1_EPITCH 0x01e9 4216#define mmCB_MRT1_EPITCH_BASE_IDX 1 4217#define mmCB_MRT2_EPITCH 0x01ea 4218#define mmCB_MRT2_EPITCH_BASE_IDX 1 4219#define mmCB_MRT3_EPITCH 0x01eb 4220#define mmCB_MRT3_EPITCH_BASE_IDX 1 4221#define mmCB_MRT4_EPITCH 0x01ec 4222#define mmCB_MRT4_EPITCH_BASE_IDX 1 4223#define mmCB_MRT5_EPITCH 0x01ed 4224#define mmCB_MRT5_EPITCH_BASE_IDX 1 4225#define mmCB_MRT6_EPITCH 0x01ee 4226#define mmCB_MRT6_EPITCH_BASE_IDX 1 4227#define mmCB_MRT7_EPITCH 0x01ef 4228#define mmCB_MRT7_EPITCH_BASE_IDX 1 4229#define mmCS_COPY_STATE 0x01f3 4230#define mmCS_COPY_STATE_BASE_IDX 1 4231#define mmGFX_COPY_STATE 0x01f4 4232#define mmGFX_COPY_STATE_BASE_IDX 1 4233#define mmPA_CL_POINT_X_RAD 0x01f5 4234#define mmPA_CL_POINT_X_RAD_BASE_IDX 1 4235#define mmPA_CL_POINT_Y_RAD 0x01f6 4236#define mmPA_CL_POINT_Y_RAD_BASE_IDX 1 4237#define mmPA_CL_POINT_SIZE 0x01f7 4238#define mmPA_CL_POINT_SIZE_BASE_IDX 1 4239#define mmPA_CL_POINT_CULL_RAD 0x01f8 4240#define mmPA_CL_POINT_CULL_RAD_BASE_IDX 1 4241#define mmVGT_DMA_BASE_HI 0x01f9 4242#define mmVGT_DMA_BASE_HI_BASE_IDX 1 4243#define mmVGT_DMA_BASE 0x01fa 4244#define mmVGT_DMA_BASE_BASE_IDX 1 4245#define mmVGT_DRAW_INITIATOR 0x01fc 4246#define mmVGT_DRAW_INITIATOR_BASE_IDX 1 4247#define mmVGT_IMMED_DATA 0x01fd 4248#define mmVGT_IMMED_DATA_BASE_IDX 1 4249#define mmVGT_EVENT_ADDRESS_REG 0x01fe 4250#define mmVGT_EVENT_ADDRESS_REG_BASE_IDX 1 4251#define mmDB_DEPTH_CONTROL 0x0200 4252#define mmDB_DEPTH_CONTROL_BASE_IDX 1 4253#define mmDB_EQAA 0x0201 4254#define mmDB_EQAA_BASE_IDX 1 4255#define mmCB_COLOR_CONTROL 0x0202 4256#define mmCB_COLOR_CONTROL_BASE_IDX 1 4257#define mmDB_SHADER_CONTROL 0x0203 4258#define mmDB_SHADER_CONTROL_BASE_IDX 1 4259#define mmPA_CL_CLIP_CNTL 0x0204 4260#define mmPA_CL_CLIP_CNTL_BASE_IDX 1 4261#define mmPA_SU_SC_MODE_CNTL 0x0205 4262#define mmPA_SU_SC_MODE_CNTL_BASE_IDX 1 4263#define mmPA_CL_VTE_CNTL 0x0206 4264#define mmPA_CL_VTE_CNTL_BASE_IDX 1 4265#define mmPA_CL_VS_OUT_CNTL 0x0207 4266#define mmPA_CL_VS_OUT_CNTL_BASE_IDX 1 4267#define mmPA_CL_NANINF_CNTL 0x0208 4268#define mmPA_CL_NANINF_CNTL_BASE_IDX 1 4269#define mmPA_SU_LINE_STIPPLE_CNTL 0x0209 4270#define mmPA_SU_LINE_STIPPLE_CNTL_BASE_IDX 1 4271#define mmPA_SU_LINE_STIPPLE_SCALE 0x020a 4272#define mmPA_SU_LINE_STIPPLE_SCALE_BASE_IDX 1 4273#define mmPA_SU_PRIM_FILTER_CNTL 0x020b 4274#define mmPA_SU_PRIM_FILTER_CNTL_BASE_IDX 1 4275#define mmPA_SU_SMALL_PRIM_FILTER_CNTL 0x020c 4276#define mmPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX 1 4277#define mmPA_CL_OBJPRIM_ID_CNTL 0x020d 4278#define mmPA_CL_OBJPRIM_ID_CNTL_BASE_IDX 1 4279#define mmPA_CL_NGG_CNTL 0x020e 4280#define mmPA_CL_NGG_CNTL_BASE_IDX 1 4281#define mmPA_SU_OVER_RASTERIZATION_CNTL 0x020f 4282#define mmPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX 1 4283#define mmPA_SU_POINT_SIZE 0x0280 4284#define mmPA_SU_POINT_SIZE_BASE_IDX 1 4285#define mmPA_SU_POINT_MINMAX 0x0281 4286#define mmPA_SU_POINT_MINMAX_BASE_IDX 1 4287#define mmPA_SU_LINE_CNTL 0x0282 4288#define mmPA_SU_LINE_CNTL_BASE_IDX 1 4289#define mmPA_SC_LINE_STIPPLE 0x0283 4290#define mmPA_SC_LINE_STIPPLE_BASE_IDX 1 4291#define mmVGT_OUTPUT_PATH_CNTL 0x0284 4292#define mmVGT_OUTPUT_PATH_CNTL_BASE_IDX 1 4293#define mmVGT_HOS_CNTL 0x0285 4294#define mmVGT_HOS_CNTL_BASE_IDX 1 4295#define mmVGT_HOS_MAX_TESS_LEVEL 0x0286 4296#define mmVGT_HOS_MAX_TESS_LEVEL_BASE_IDX 1 4297#define mmVGT_HOS_MIN_TESS_LEVEL 0x0287 4298#define mmVGT_HOS_MIN_TESS_LEVEL_BASE_IDX 1 4299#define mmVGT_HOS_REUSE_DEPTH 0x0288 4300#define mmVGT_HOS_REUSE_DEPTH_BASE_IDX 1 4301#define mmVGT_GROUP_PRIM_TYPE 0x0289 4302#define mmVGT_GROUP_PRIM_TYPE_BASE_IDX 1 4303#define mmVGT_GROUP_FIRST_DECR 0x028a 4304#define mmVGT_GROUP_FIRST_DECR_BASE_IDX 1 4305#define mmVGT_GROUP_DECR 0x028b 4306#define mmVGT_GROUP_DECR_BASE_IDX 1 4307#define mmVGT_GROUP_VECT_0_CNTL 0x028c 4308#define mmVGT_GROUP_VECT_0_CNTL_BASE_IDX 1 4309#define mmVGT_GROUP_VECT_1_CNTL 0x028d 4310#define mmVGT_GROUP_VECT_1_CNTL_BASE_IDX 1 4311#define mmVGT_GROUP_VECT_0_FMT_CNTL 0x028e 4312#define mmVGT_GROUP_VECT_0_FMT_CNTL_BASE_IDX 1 4313#define mmVGT_GROUP_VECT_1_FMT_CNTL 0x028f 4314#define mmVGT_GROUP_VECT_1_FMT_CNTL_BASE_IDX 1 4315#define mmVGT_GS_MODE 0x0290 4316#define mmVGT_GS_MODE_BASE_IDX 1 4317#define mmVGT_GS_ONCHIP_CNTL 0x0291 4318#define mmVGT_GS_ONCHIP_CNTL_BASE_IDX 1 4319#define mmPA_SC_MODE_CNTL_0 0x0292 4320#define mmPA_SC_MODE_CNTL_0_BASE_IDX 1 4321#define mmPA_SC_MODE_CNTL_1 0x0293 4322#define mmPA_SC_MODE_CNTL_1_BASE_IDX 1 4323#define mmVGT_ENHANCE 0x0294 4324#define mmVGT_ENHANCE_BASE_IDX 1 4325#define mmVGT_GS_PER_ES 0x0295 4326#define mmVGT_GS_PER_ES_BASE_IDX 1 4327#define mmVGT_ES_PER_GS 0x0296 4328#define mmVGT_ES_PER_GS_BASE_IDX 1 4329#define mmVGT_GS_PER_VS 0x0297 4330#define mmVGT_GS_PER_VS_BASE_IDX 1 4331#define mmVGT_GSVS_RING_OFFSET_1 0x0298 4332#define mmVGT_GSVS_RING_OFFSET_1_BASE_IDX 1 4333#define mmVGT_GSVS_RING_OFFSET_2 0x0299 4334#define mmVGT_GSVS_RING_OFFSET_2_BASE_IDX 1 4335#define mmVGT_GSVS_RING_OFFSET_3 0x029a 4336#define mmVGT_GSVS_RING_OFFSET_3_BASE_IDX 1 4337#define mmVGT_GS_OUT_PRIM_TYPE 0x029b 4338#define mmVGT_GS_OUT_PRIM_TYPE_BASE_IDX 1 4339#define mmIA_ENHANCE 0x029c 4340#define mmIA_ENHANCE_BASE_IDX 1 4341#define mmVGT_DMA_SIZE 0x029d 4342#define mmVGT_DMA_SIZE_BASE_IDX 1 4343#define mmVGT_DMA_MAX_SIZE 0x029e 4344#define mmVGT_DMA_MAX_SIZE_BASE_IDX 1 4345#define mmVGT_DMA_INDEX_TYPE 0x029f 4346#define mmVGT_DMA_INDEX_TYPE_BASE_IDX 1 4347#define mmWD_ENHANCE 0x02a0 4348#define mmWD_ENHANCE_BASE_IDX 1 4349#define mmVGT_PRIMITIVEID_EN 0x02a1 4350#define mmVGT_PRIMITIVEID_EN_BASE_IDX 1 4351#define mmVGT_DMA_NUM_INSTANCES 0x02a2 4352#define mmVGT_DMA_NUM_INSTANCES_BASE_IDX 1 4353#define mmVGT_PRIMITIVEID_RESET 0x02a3 4354#define mmVGT_PRIMITIVEID_RESET_BASE_IDX 1 4355#define mmVGT_EVENT_INITIATOR 0x02a4 4356#define mmVGT_EVENT_INITIATOR_BASE_IDX 1 4357#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP 0x02a5 4358#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_BASE_IDX 1 4359#define mmVGT_DRAW_PAYLOAD_CNTL 0x02a6 4360#define mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1 4361#define mmVGT_INSTANCE_STEP_RATE_0 0x02a8 4362#define mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX 1 4363#define mmVGT_INSTANCE_STEP_RATE_1 0x02a9 4364#define mmVGT_INSTANCE_STEP_RATE_1_BASE_IDX 1 4365#define mmVGT_ESGS_RING_ITEMSIZE 0x02ab 4366#define mmVGT_ESGS_RING_ITEMSIZE_BASE_IDX 1 4367#define mmVGT_GSVS_RING_ITEMSIZE 0x02ac 4368#define mmVGT_GSVS_RING_ITEMSIZE_BASE_IDX 1 4369#define mmVGT_REUSE_OFF 0x02ad 4370#define mmVGT_REUSE_OFF_BASE_IDX 1 4371#define mmVGT_VTX_CNT_EN 0x02ae 4372#define mmVGT_VTX_CNT_EN_BASE_IDX 1 4373#define mmDB_HTILE_SURFACE 0x02af 4374#define mmDB_HTILE_SURFACE_BASE_IDX 1 4375#define mmDB_SRESULTS_COMPARE_STATE0 0x02b0 4376#define mmDB_SRESULTS_COMPARE_STATE0_BASE_IDX 1 4377#define mmDB_SRESULTS_COMPARE_STATE1 0x02b1 4378#define mmDB_SRESULTS_COMPARE_STATE1_BASE_IDX 1 4379#define mmDB_PRELOAD_CONTROL 0x02b2 4380#define mmDB_PRELOAD_CONTROL_BASE_IDX 1 4381#define mmVGT_STRMOUT_BUFFER_SIZE_0 0x02b4 4382#define mmVGT_STRMOUT_BUFFER_SIZE_0_BASE_IDX 1 4383#define mmVGT_STRMOUT_VTX_STRIDE_0 0x02b5 4384#define mmVGT_STRMOUT_VTX_STRIDE_0_BASE_IDX 1 4385#define mmVGT_STRMOUT_BUFFER_OFFSET_0 0x02b7 4386#define mmVGT_STRMOUT_BUFFER_OFFSET_0_BASE_IDX 1 4387#define mmVGT_STRMOUT_BUFFER_SIZE_1 0x02b8 4388#define mmVGT_STRMOUT_BUFFER_SIZE_1_BASE_IDX 1 4389#define mmVGT_STRMOUT_VTX_STRIDE_1 0x02b9 4390#define mmVGT_STRMOUT_VTX_STRIDE_1_BASE_IDX 1 4391#define mmVGT_STRMOUT_BUFFER_OFFSET_1 0x02bb 4392#define mmVGT_STRMOUT_BUFFER_OFFSET_1_BASE_IDX 1 4393#define mmVGT_STRMOUT_BUFFER_SIZE_2 0x02bc 4394#define mmVGT_STRMOUT_BUFFER_SIZE_2_BASE_IDX 1 4395#define mmVGT_STRMOUT_VTX_STRIDE_2 0x02bd 4396#define mmVGT_STRMOUT_VTX_STRIDE_2_BASE_IDX 1 4397#define mmVGT_STRMOUT_BUFFER_OFFSET_2 0x02bf 4398#define mmVGT_STRMOUT_BUFFER_OFFSET_2_BASE_IDX 1 4399#define mmVGT_STRMOUT_BUFFER_SIZE_3 0x02c0 4400#define mmVGT_STRMOUT_BUFFER_SIZE_3_BASE_IDX 1 4401#define mmVGT_STRMOUT_VTX_STRIDE_3 0x02c1 4402#define mmVGT_STRMOUT_VTX_STRIDE_3_BASE_IDX 1 4403#define mmVGT_STRMOUT_BUFFER_OFFSET_3 0x02c3 4404#define mmVGT_STRMOUT_BUFFER_OFFSET_3_BASE_IDX 1 4405#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x02ca 4406#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX 1 4407#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x02cb 4408#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX 1 4409#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x02cc 4410#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX 1 4411#define mmVGT_GS_MAX_VERT_OUT 0x02ce 4412#define mmVGT_GS_MAX_VERT_OUT_BASE_IDX 1 4413#define mmVGT_TESS_DISTRIBUTION 0x02d4 4414#define mmVGT_TESS_DISTRIBUTION_BASE_IDX 1 4415#define mmVGT_SHADER_STAGES_EN 0x02d5 4416#define mmVGT_SHADER_STAGES_EN_BASE_IDX 1 4417#define mmVGT_LS_HS_CONFIG 0x02d6 4418#define mmVGT_LS_HS_CONFIG_BASE_IDX 1 4419#define mmVGT_GS_VERT_ITEMSIZE 0x02d7 4420#define mmVGT_GS_VERT_ITEMSIZE_BASE_IDX 1 4421#define mmVGT_GS_VERT_ITEMSIZE_1 0x02d8 4422#define mmVGT_GS_VERT_ITEMSIZE_1_BASE_IDX 1 4423#define mmVGT_GS_VERT_ITEMSIZE_2 0x02d9 4424#define mmVGT_GS_VERT_ITEMSIZE_2_BASE_IDX 1 4425#define mmVGT_GS_VERT_ITEMSIZE_3 0x02da 4426#define mmVGT_GS_VERT_ITEMSIZE_3_BASE_IDX 1 4427#define mmVGT_TF_PARAM 0x02db 4428#define mmVGT_TF_PARAM_BASE_IDX 1 4429#define mmDB_ALPHA_TO_MASK 0x02dc 4430#define mmDB_ALPHA_TO_MASK_BASE_IDX 1 4431#define mmVGT_DISPATCH_DRAW_INDEX 0x02dd 4432#define mmVGT_DISPATCH_DRAW_INDEX_BASE_IDX 1 4433#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0x02de 4434#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX 1 4435#define mmPA_SU_POLY_OFFSET_CLAMP 0x02df 4436#define mmPA_SU_POLY_OFFSET_CLAMP_BASE_IDX 1 4437#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0x02e0 4438#define mmPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX 1 4439#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0x02e1 4440#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX 1 4441#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0x02e2 4442#define mmPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX 1 4443#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0x02e3 4444#define mmPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX 1 4445#define mmVGT_GS_INSTANCE_CNT 0x02e4 4446#define mmVGT_GS_INSTANCE_CNT_BASE_IDX 1 4447#define mmVGT_STRMOUT_CONFIG 0x02e5 4448#define mmVGT_STRMOUT_CONFIG_BASE_IDX 1 4449#define mmVGT_STRMOUT_BUFFER_CONFIG 0x02e6 4450#define mmVGT_STRMOUT_BUFFER_CONFIG_BASE_IDX 1 4451#define mmVGT_DMA_EVENT_INITIATOR 0x02e7 4452#define mmVGT_DMA_EVENT_INITIATOR_BASE_IDX 1 4453#define mmPA_SC_CENTROID_PRIORITY_0 0x02f5 4454#define mmPA_SC_CENTROID_PRIORITY_0_BASE_IDX 1 4455#define mmPA_SC_CENTROID_PRIORITY_1 0x02f6 4456#define mmPA_SC_CENTROID_PRIORITY_1_BASE_IDX 1 4457#define mmPA_SC_LINE_CNTL 0x02f7 4458#define mmPA_SC_LINE_CNTL_BASE_IDX 1 4459#define mmPA_SC_AA_CONFIG 0x02f8 4460#define mmPA_SC_AA_CONFIG_BASE_IDX 1 4461#define mmPA_SU_VTX_CNTL 0x02f9 4462#define mmPA_SU_VTX_CNTL_BASE_IDX 1 4463#define mmPA_CL_GB_VERT_CLIP_ADJ 0x02fa 4464#define mmPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX 1 4465#define mmPA_CL_GB_VERT_DISC_ADJ 0x02fb 4466#define mmPA_CL_GB_VERT_DISC_ADJ_BASE_IDX 1 4467#define mmPA_CL_GB_HORZ_CLIP_ADJ 0x02fc 4468#define mmPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX 1 4469#define mmPA_CL_GB_HORZ_DISC_ADJ 0x02fd 4470#define mmPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX 1 4471#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x02fe 4472#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX 1 4473#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x02ff 4474#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX 1 4475#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x0300 4476#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX 1 4477#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x0301 4478#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX 1 4479#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x0302 4480#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX 1 4481#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x0303 4482#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX 1 4483#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x0304 4484#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX 1 4485#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x0305 4486#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX 1 4487#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x0306 4488#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX 1 4489#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x0307 4490#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX 1 4491#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x0308 4492#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX 1 4493#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x0309 4494#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX 1 4495#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x030a 4496#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX 1 4497#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x030b 4498#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX 1 4499#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x030c 4500#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX 1 4501#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x030d 4502#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX 1 4503#define mmPA_SC_AA_MASK_X0Y0_X1Y0 0x030e 4504#define mmPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX 1 4505#define mmPA_SC_AA_MASK_X0Y1_X1Y1 0x030f 4506#define mmPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX 1 4507#define mmPA_SC_SHADER_CONTROL 0x0310 4508#define mmPA_SC_SHADER_CONTROL_BASE_IDX 1 4509#define mmPA_SC_BINNER_CNTL_0 0x0311 4510#define mmPA_SC_BINNER_CNTL_0_BASE_IDX 1 4511#define mmPA_SC_BINNER_CNTL_1 0x0312 4512#define mmPA_SC_BINNER_CNTL_1_BASE_IDX 1 4513#define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL 0x0313 4514#define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX 1 4515#define mmPA_SC_NGG_MODE_CNTL 0x0314 4516#define mmPA_SC_NGG_MODE_CNTL_BASE_IDX 1 4517#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0x0316 4518#define mmVGT_VERTEX_REUSE_BLOCK_CNTL_BASE_IDX 1 4519#define mmVGT_OUT_DEALLOC_CNTL 0x0317 4520#define mmVGT_OUT_DEALLOC_CNTL_BASE_IDX 1 4521#define mmCB_COLOR0_BASE 0x0318 4522#define mmCB_COLOR0_BASE_BASE_IDX 1 4523#define mmCB_COLOR0_BASE_EXT 0x0319 4524#define mmCB_COLOR0_BASE_EXT_BASE_IDX 1 4525#define mmCB_COLOR0_ATTRIB2 0x031a 4526#define mmCB_COLOR0_ATTRIB2_BASE_IDX 1 4527#define mmCB_COLOR0_VIEW 0x031b 4528#define mmCB_COLOR0_VIEW_BASE_IDX 1 4529#define mmCB_COLOR0_INFO 0x031c 4530#define mmCB_COLOR0_INFO_BASE_IDX 1 4531#define mmCB_COLOR0_ATTRIB 0x031d 4532#define mmCB_COLOR0_ATTRIB_BASE_IDX 1 4533#define mmCB_COLOR0_DCC_CONTROL 0x031e 4534#define mmCB_COLOR0_DCC_CONTROL_BASE_IDX 1 4535#define mmCB_COLOR0_CMASK 0x031f 4536#define mmCB_COLOR0_CMASK_BASE_IDX 1 4537#define mmCB_COLOR0_CMASK_BASE_EXT 0x0320 4538#define mmCB_COLOR0_CMASK_BASE_EXT_BASE_IDX 1 4539#define mmCB_COLOR0_FMASK 0x0321 4540#define mmCB_COLOR0_FMASK_BASE_IDX 1 4541#define mmCB_COLOR0_FMASK_BASE_EXT 0x0322 4542#define mmCB_COLOR0_FMASK_BASE_EXT_BASE_IDX 1 4543#define mmCB_COLOR0_CLEAR_WORD0 0x0323 4544#define mmCB_COLOR0_CLEAR_WORD0_BASE_IDX 1 4545#define mmCB_COLOR0_CLEAR_WORD1 0x0324 4546#define mmCB_COLOR0_CLEAR_WORD1_BASE_IDX 1 4547#define mmCB_COLOR0_DCC_BASE 0x0325 4548#define mmCB_COLOR0_DCC_BASE_BASE_IDX 1 4549#define mmCB_COLOR0_DCC_BASE_EXT 0x0326 4550#define mmCB_COLOR0_DCC_BASE_EXT_BASE_IDX 1 4551#define mmCB_COLOR1_BASE 0x0327 4552#define mmCB_COLOR1_BASE_BASE_IDX 1 4553#define mmCB_COLOR1_BASE_EXT 0x0328 4554#define mmCB_COLOR1_BASE_EXT_BASE_IDX 1 4555#define mmCB_COLOR1_ATTRIB2 0x0329 4556#define mmCB_COLOR1_ATTRIB2_BASE_IDX 1 4557#define mmCB_COLOR1_VIEW 0x032a 4558#define mmCB_COLOR1_VIEW_BASE_IDX 1 4559#define mmCB_COLOR1_INFO 0x032b 4560#define mmCB_COLOR1_INFO_BASE_IDX 1 4561#define mmCB_COLOR1_ATTRIB 0x032c 4562#define mmCB_COLOR1_ATTRIB_BASE_IDX 1 4563#define mmCB_COLOR1_DCC_CONTROL 0x032d 4564#define mmCB_COLOR1_DCC_CONTROL_BASE_IDX 1 4565#define mmCB_COLOR1_CMASK 0x032e 4566#define mmCB_COLOR1_CMASK_BASE_IDX 1 4567#define mmCB_COLOR1_CMASK_BASE_EXT 0x032f 4568#define mmCB_COLOR1_CMASK_BASE_EXT_BASE_IDX 1 4569#define mmCB_COLOR1_FMASK 0x0330 4570#define mmCB_COLOR1_FMASK_BASE_IDX 1 4571#define mmCB_COLOR1_FMASK_BASE_EXT 0x0331 4572#define mmCB_COLOR1_FMASK_BASE_EXT_BASE_IDX 1 4573#define mmCB_COLOR1_CLEAR_WORD0 0x0332 4574#define mmCB_COLOR1_CLEAR_WORD0_BASE_IDX 1 4575#define mmCB_COLOR1_CLEAR_WORD1 0x0333 4576#define mmCB_COLOR1_CLEAR_WORD1_BASE_IDX 1 4577#define mmCB_COLOR1_DCC_BASE 0x0334 4578#define mmCB_COLOR1_DCC_BASE_BASE_IDX 1 4579#define mmCB_COLOR1_DCC_BASE_EXT 0x0335 4580#define mmCB_COLOR1_DCC_BASE_EXT_BASE_IDX 1 4581#define mmCB_COLOR2_BASE 0x0336 4582#define mmCB_COLOR2_BASE_BASE_IDX 1 4583#define mmCB_COLOR2_BASE_EXT 0x0337 4584#define mmCB_COLOR2_BASE_EXT_BASE_IDX 1 4585#define mmCB_COLOR2_ATTRIB2 0x0338 4586#define mmCB_COLOR2_ATTRIB2_BASE_IDX 1 4587#define mmCB_COLOR2_VIEW 0x0339 4588#define mmCB_COLOR2_VIEW_BASE_IDX 1 4589#define mmCB_COLOR2_INFO 0x033a 4590#define mmCB_COLOR2_INFO_BASE_IDX 1 4591#define mmCB_COLOR2_ATTRIB 0x033b 4592#define mmCB_COLOR2_ATTRIB_BASE_IDX 1 4593#define mmCB_COLOR2_DCC_CONTROL 0x033c 4594#define mmCB_COLOR2_DCC_CONTROL_BASE_IDX 1 4595#define mmCB_COLOR2_CMASK 0x033d 4596#define mmCB_COLOR2_CMASK_BASE_IDX 1 4597#define mmCB_COLOR2_CMASK_BASE_EXT 0x033e 4598#define mmCB_COLOR2_CMASK_BASE_EXT_BASE_IDX 1 4599#define mmCB_COLOR2_FMASK 0x033f 4600#define mmCB_COLOR2_FMASK_BASE_IDX 1 4601#define mmCB_COLOR2_FMASK_BASE_EXT 0x0340 4602#define mmCB_COLOR2_FMASK_BASE_EXT_BASE_IDX 1 4603#define mmCB_COLOR2_CLEAR_WORD0 0x0341 4604#define mmCB_COLOR2_CLEAR_WORD0_BASE_IDX 1 4605#define mmCB_COLOR2_CLEAR_WORD1 0x0342 4606#define mmCB_COLOR2_CLEAR_WORD1_BASE_IDX 1 4607#define mmCB_COLOR2_DCC_BASE 0x0343 4608#define mmCB_COLOR2_DCC_BASE_BASE_IDX 1 4609#define mmCB_COLOR2_DCC_BASE_EXT 0x0344 4610#define mmCB_COLOR2_DCC_BASE_EXT_BASE_IDX 1 4611#define mmCB_COLOR3_BASE 0x0345 4612#define mmCB_COLOR3_BASE_BASE_IDX 1 4613#define mmCB_COLOR3_BASE_EXT 0x0346 4614#define mmCB_COLOR3_BASE_EXT_BASE_IDX 1 4615#define mmCB_COLOR3_ATTRIB2 0x0347 4616#define mmCB_COLOR3_ATTRIB2_BASE_IDX 1 4617#define mmCB_COLOR3_VIEW 0x0348 4618#define mmCB_COLOR3_VIEW_BASE_IDX 1 4619#define mmCB_COLOR3_INFO 0x0349 4620#define mmCB_COLOR3_INFO_BASE_IDX 1 4621#define mmCB_COLOR3_ATTRIB 0x034a 4622#define mmCB_COLOR3_ATTRIB_BASE_IDX 1 4623#define mmCB_COLOR3_DCC_CONTROL 0x034b 4624#define mmCB_COLOR3_DCC_CONTROL_BASE_IDX 1 4625#define mmCB_COLOR3_CMASK 0x034c 4626#define mmCB_COLOR3_CMASK_BASE_IDX 1 4627#define mmCB_COLOR3_CMASK_BASE_EXT 0x034d 4628#define mmCB_COLOR3_CMASK_BASE_EXT_BASE_IDX 1 4629#define mmCB_COLOR3_FMASK 0x034e 4630#define mmCB_COLOR3_FMASK_BASE_IDX 1 4631#define mmCB_COLOR3_FMASK_BASE_EXT 0x034f 4632#define mmCB_COLOR3_FMASK_BASE_EXT_BASE_IDX 1 4633#define mmCB_COLOR3_CLEAR_WORD0 0x0350 4634#define mmCB_COLOR3_CLEAR_WORD0_BASE_IDX 1 4635#define mmCB_COLOR3_CLEAR_WORD1 0x0351 4636#define mmCB_COLOR3_CLEAR_WORD1_BASE_IDX 1 4637#define mmCB_COLOR3_DCC_BASE 0x0352 4638#define mmCB_COLOR3_DCC_BASE_BASE_IDX 1 4639#define mmCB_COLOR3_DCC_BASE_EXT 0x0353 4640#define mmCB_COLOR3_DCC_BASE_EXT_BASE_IDX 1 4641#define mmCB_COLOR4_BASE 0x0354 4642#define mmCB_COLOR4_BASE_BASE_IDX 1 4643#define mmCB_COLOR4_BASE_EXT 0x0355 4644#define mmCB_COLOR4_BASE_EXT_BASE_IDX 1 4645#define mmCB_COLOR4_ATTRIB2 0x0356 4646#define mmCB_COLOR4_ATTRIB2_BASE_IDX 1 4647#define mmCB_COLOR4_VIEW 0x0357 4648#define mmCB_COLOR4_VIEW_BASE_IDX 1 4649#define mmCB_COLOR4_INFO 0x0358 4650#define mmCB_COLOR4_INFO_BASE_IDX 1 4651#define mmCB_COLOR4_ATTRIB 0x0359 4652#define mmCB_COLOR4_ATTRIB_BASE_IDX 1 4653#define mmCB_COLOR4_DCC_CONTROL 0x035a 4654#define mmCB_COLOR4_DCC_CONTROL_BASE_IDX 1 4655#define mmCB_COLOR4_CMASK 0x035b 4656#define mmCB_COLOR4_CMASK_BASE_IDX 1 4657#define mmCB_COLOR4_CMASK_BASE_EXT 0x035c 4658#define mmCB_COLOR4_CMASK_BASE_EXT_BASE_IDX 1 4659#define mmCB_COLOR4_FMASK 0x035d 4660#define mmCB_COLOR4_FMASK_BASE_IDX 1 4661#define mmCB_COLOR4_FMASK_BASE_EXT 0x035e 4662#define mmCB_COLOR4_FMASK_BASE_EXT_BASE_IDX 1 4663#define mmCB_COLOR4_CLEAR_WORD0 0x035f 4664#define mmCB_COLOR4_CLEAR_WORD0_BASE_IDX 1 4665#define mmCB_COLOR4_CLEAR_WORD1 0x0360 4666#define mmCB_COLOR4_CLEAR_WORD1_BASE_IDX 1 4667#define mmCB_COLOR4_DCC_BASE 0x0361 4668#define mmCB_COLOR4_DCC_BASE_BASE_IDX 1 4669#define mmCB_COLOR4_DCC_BASE_EXT 0x0362 4670#define mmCB_COLOR4_DCC_BASE_EXT_BASE_IDX 1 4671#define mmCB_COLOR5_BASE 0x0363 4672#define mmCB_COLOR5_BASE_BASE_IDX 1 4673#define mmCB_COLOR5_BASE_EXT 0x0364 4674#define mmCB_COLOR5_BASE_EXT_BASE_IDX 1 4675#define mmCB_COLOR5_ATTRIB2 0x0365 4676#define mmCB_COLOR5_ATTRIB2_BASE_IDX 1 4677#define mmCB_COLOR5_VIEW 0x0366 4678#define mmCB_COLOR5_VIEW_BASE_IDX 1 4679#define mmCB_COLOR5_INFO 0x0367 4680#define mmCB_COLOR5_INFO_BASE_IDX 1 4681#define mmCB_COLOR5_ATTRIB 0x0368 4682#define mmCB_COLOR5_ATTRIB_BASE_IDX 1 4683#define mmCB_COLOR5_DCC_CONTROL 0x0369 4684#define mmCB_COLOR5_DCC_CONTROL_BASE_IDX 1 4685#define mmCB_COLOR5_CMASK 0x036a 4686#define mmCB_COLOR5_CMASK_BASE_IDX 1 4687#define mmCB_COLOR5_CMASK_BASE_EXT 0x036b 4688#define mmCB_COLOR5_CMASK_BASE_EXT_BASE_IDX 1 4689#define mmCB_COLOR5_FMASK 0x036c 4690#define mmCB_COLOR5_FMASK_BASE_IDX 1 4691#define mmCB_COLOR5_FMASK_BASE_EXT 0x036d 4692#define mmCB_COLOR5_FMASK_BASE_EXT_BASE_IDX 1 4693#define mmCB_COLOR5_CLEAR_WORD0 0x036e 4694#define mmCB_COLOR5_CLEAR_WORD0_BASE_IDX 1 4695#define mmCB_COLOR5_CLEAR_WORD1 0x036f 4696#define mmCB_COLOR5_CLEAR_WORD1_BASE_IDX 1 4697#define mmCB_COLOR5_DCC_BASE 0x0370 4698#define mmCB_COLOR5_DCC_BASE_BASE_IDX 1 4699#define mmCB_COLOR5_DCC_BASE_EXT 0x0371 4700#define mmCB_COLOR5_DCC_BASE_EXT_BASE_IDX 1 4701#define mmCB_COLOR6_BASE 0x0372 4702#define mmCB_COLOR6_BASE_BASE_IDX 1 4703#define mmCB_COLOR6_BASE_EXT 0x0373 4704#define mmCB_COLOR6_BASE_EXT_BASE_IDX 1 4705#define mmCB_COLOR6_ATTRIB2 0x0374 4706#define mmCB_COLOR6_ATTRIB2_BASE_IDX 1 4707#define mmCB_COLOR6_VIEW 0x0375 4708#define mmCB_COLOR6_VIEW_BASE_IDX 1 4709#define mmCB_COLOR6_INFO 0x0376 4710#define mmCB_COLOR6_INFO_BASE_IDX 1 4711#define mmCB_COLOR6_ATTRIB 0x0377 4712#define mmCB_COLOR6_ATTRIB_BASE_IDX 1 4713#define mmCB_COLOR6_DCC_CONTROL 0x0378 4714#define mmCB_COLOR6_DCC_CONTROL_BASE_IDX 1 4715#define mmCB_COLOR6_CMASK 0x0379 4716#define mmCB_COLOR6_CMASK_BASE_IDX 1 4717#define mmCB_COLOR6_CMASK_BASE_EXT 0x037a 4718#define mmCB_COLOR6_CMASK_BASE_EXT_BASE_IDX 1 4719#define mmCB_COLOR6_FMASK 0x037b 4720#define mmCB_COLOR6_FMASK_BASE_IDX 1 4721#define mmCB_COLOR6_FMASK_BASE_EXT 0x037c 4722#define mmCB_COLOR6_FMASK_BASE_EXT_BASE_IDX 1 4723#define mmCB_COLOR6_CLEAR_WORD0 0x037d 4724#define mmCB_COLOR6_CLEAR_WORD0_BASE_IDX 1 4725#define mmCB_COLOR6_CLEAR_WORD1 0x037e 4726#define mmCB_COLOR6_CLEAR_WORD1_BASE_IDX 1 4727#define mmCB_COLOR6_DCC_BASE 0x037f 4728#define mmCB_COLOR6_DCC_BASE_BASE_IDX 1 4729#define mmCB_COLOR6_DCC_BASE_EXT 0x0380 4730#define mmCB_COLOR6_DCC_BASE_EXT_BASE_IDX 1 4731#define mmCB_COLOR7_BASE 0x0381 4732#define mmCB_COLOR7_BASE_BASE_IDX 1 4733#define mmCB_COLOR7_BASE_EXT 0x0382 4734#define mmCB_COLOR7_BASE_EXT_BASE_IDX 1 4735#define mmCB_COLOR7_ATTRIB2 0x0383 4736#define mmCB_COLOR7_ATTRIB2_BASE_IDX 1 4737#define mmCB_COLOR7_VIEW 0x0384 4738#define mmCB_COLOR7_VIEW_BASE_IDX 1 4739#define mmCB_COLOR7_INFO 0x0385 4740#define mmCB_COLOR7_INFO_BASE_IDX 1 4741#define mmCB_COLOR7_ATTRIB 0x0386 4742#define mmCB_COLOR7_ATTRIB_BASE_IDX 1 4743#define mmCB_COLOR7_DCC_CONTROL 0x0387 4744#define mmCB_COLOR7_DCC_CONTROL_BASE_IDX 1 4745#define mmCB_COLOR7_CMASK 0x0388 4746#define mmCB_COLOR7_CMASK_BASE_IDX 1 4747#define mmCB_COLOR7_CMASK_BASE_EXT 0x0389 4748#define mmCB_COLOR7_CMASK_BASE_EXT_BASE_IDX 1 4749#define mmCB_COLOR7_FMASK 0x038a 4750#define mmCB_COLOR7_FMASK_BASE_IDX 1 4751#define mmCB_COLOR7_FMASK_BASE_EXT 0x038b 4752#define mmCB_COLOR7_FMASK_BASE_EXT_BASE_IDX 1 4753#define mmCB_COLOR7_CLEAR_WORD0 0x038c 4754#define mmCB_COLOR7_CLEAR_WORD0_BASE_IDX 1 4755#define mmCB_COLOR7_CLEAR_WORD1 0x038d 4756#define mmCB_COLOR7_CLEAR_WORD1_BASE_IDX 1 4757#define mmCB_COLOR7_DCC_BASE 0x038e 4758#define mmCB_COLOR7_DCC_BASE_BASE_IDX 1 4759#define mmCB_COLOR7_DCC_BASE_EXT 0x038f 4760#define mmCB_COLOR7_DCC_BASE_EXT_BASE_IDX 1 4761 4762 4763// addressBlock: gc_gfxudec 4764// base address: 0x30000 4765#define mmCP_EOP_DONE_ADDR_LO 0x2000 4766#define mmCP_EOP_DONE_ADDR_LO_BASE_IDX 1 4767#define mmCP_EOP_DONE_ADDR_HI 0x2001 4768#define mmCP_EOP_DONE_ADDR_HI_BASE_IDX 1 4769#define mmCP_EOP_DONE_DATA_LO 0x2002 4770#define mmCP_EOP_DONE_DATA_LO_BASE_IDX 1 4771#define mmCP_EOP_DONE_DATA_HI 0x2003 4772#define mmCP_EOP_DONE_DATA_HI_BASE_IDX 1 4773#define mmCP_EOP_LAST_FENCE_LO 0x2004 4774#define mmCP_EOP_LAST_FENCE_LO_BASE_IDX 1 4775#define mmCP_EOP_LAST_FENCE_HI 0x2005 4776#define mmCP_EOP_LAST_FENCE_HI_BASE_IDX 1 4777#define mmCP_STREAM_OUT_ADDR_LO 0x2006 4778#define mmCP_STREAM_OUT_ADDR_LO_BASE_IDX 1 4779#define mmCP_STREAM_OUT_ADDR_HI 0x2007 4780#define mmCP_STREAM_OUT_ADDR_HI_BASE_IDX 1 4781#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0x2008 4782#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO_BASE_IDX 1 4783#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0x2009 4784#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI_BASE_IDX 1 4785#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0x200a 4786#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO_BASE_IDX 1 4787#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0x200b 4788#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI_BASE_IDX 1 4789#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0x200c 4790#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO_BASE_IDX 1 4791#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0x200d 4792#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI_BASE_IDX 1 4793#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0x200e 4794#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO_BASE_IDX 1 4795#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0x200f 4796#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI_BASE_IDX 1 4797#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0x2010 4798#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO_BASE_IDX 1 4799#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0x2011 4800#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI_BASE_IDX 1 4801#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0x2012 4802#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO_BASE_IDX 1 4803#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0x2013 4804#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI_BASE_IDX 1 4805#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0x2014 4806#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX 1 4807#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0x2015 4808#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI_BASE_IDX 1 4809#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0x2016 4810#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO_BASE_IDX 1 4811#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0x2017 4812#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX 1 4813#define mmCP_PIPE_STATS_ADDR_LO 0x2018 4814#define mmCP_PIPE_STATS_ADDR_LO_BASE_IDX 1 4815#define mmCP_PIPE_STATS_ADDR_HI 0x2019 4816#define mmCP_PIPE_STATS_ADDR_HI_BASE_IDX 1 4817#define mmCP_VGT_IAVERT_COUNT_LO 0x201a 4818#define mmCP_VGT_IAVERT_COUNT_LO_BASE_IDX 1 4819#define mmCP_VGT_IAVERT_COUNT_HI 0x201b 4820#define mmCP_VGT_IAVERT_COUNT_HI_BASE_IDX 1 4821#define mmCP_VGT_IAPRIM_COUNT_LO 0x201c 4822#define mmCP_VGT_IAPRIM_COUNT_LO_BASE_IDX 1 4823#define mmCP_VGT_IAPRIM_COUNT_HI 0x201d 4824#define mmCP_VGT_IAPRIM_COUNT_HI_BASE_IDX 1 4825#define mmCP_VGT_GSPRIM_COUNT_LO 0x201e 4826#define mmCP_VGT_GSPRIM_COUNT_LO_BASE_IDX 1 4827#define mmCP_VGT_GSPRIM_COUNT_HI 0x201f 4828#define mmCP_VGT_GSPRIM_COUNT_HI_BASE_IDX 1 4829#define mmCP_VGT_VSINVOC_COUNT_LO 0x2020 4830#define mmCP_VGT_VSINVOC_COUNT_LO_BASE_IDX 1 4831#define mmCP_VGT_VSINVOC_COUNT_HI 0x2021 4832#define mmCP_VGT_VSINVOC_COUNT_HI_BASE_IDX 1 4833#define mmCP_VGT_GSINVOC_COUNT_LO 0x2022 4834#define mmCP_VGT_GSINVOC_COUNT_LO_BASE_IDX 1 4835#define mmCP_VGT_GSINVOC_COUNT_HI 0x2023 4836#define mmCP_VGT_GSINVOC_COUNT_HI_BASE_IDX 1 4837#define mmCP_VGT_HSINVOC_COUNT_LO 0x2024 4838#define mmCP_VGT_HSINVOC_COUNT_LO_BASE_IDX 1 4839#define mmCP_VGT_HSINVOC_COUNT_HI 0x2025 4840#define mmCP_VGT_HSINVOC_COUNT_HI_BASE_IDX 1 4841#define mmCP_VGT_DSINVOC_COUNT_LO 0x2026 4842#define mmCP_VGT_DSINVOC_COUNT_LO_BASE_IDX 1 4843#define mmCP_VGT_DSINVOC_COUNT_HI 0x2027 4844#define mmCP_VGT_DSINVOC_COUNT_HI_BASE_IDX 1 4845#define mmCP_PA_CINVOC_COUNT_LO 0x2028 4846#define mmCP_PA_CINVOC_COUNT_LO_BASE_IDX 1 4847#define mmCP_PA_CINVOC_COUNT_HI 0x2029 4848#define mmCP_PA_CINVOC_COUNT_HI_BASE_IDX 1 4849#define mmCP_PA_CPRIM_COUNT_LO 0x202a 4850#define mmCP_PA_CPRIM_COUNT_LO_BASE_IDX 1 4851#define mmCP_PA_CPRIM_COUNT_HI 0x202b 4852#define mmCP_PA_CPRIM_COUNT_HI_BASE_IDX 1 4853#define mmCP_SC_PSINVOC_COUNT0_LO 0x202c 4854#define mmCP_SC_PSINVOC_COUNT0_LO_BASE_IDX 1 4855#define mmCP_SC_PSINVOC_COUNT0_HI 0x202d 4856#define mmCP_SC_PSINVOC_COUNT0_HI_BASE_IDX 1 4857#define mmCP_SC_PSINVOC_COUNT1_LO 0x202e 4858#define mmCP_SC_PSINVOC_COUNT1_LO_BASE_IDX 1 4859#define mmCP_SC_PSINVOC_COUNT1_HI 0x202f 4860#define mmCP_SC_PSINVOC_COUNT1_HI_BASE_IDX 1 4861#define mmCP_VGT_CSINVOC_COUNT_LO 0x2030 4862#define mmCP_VGT_CSINVOC_COUNT_LO_BASE_IDX 1 4863#define mmCP_VGT_CSINVOC_COUNT_HI 0x2031 4864#define mmCP_VGT_CSINVOC_COUNT_HI_BASE_IDX 1 4865#define mmCP_PIPE_STATS_CONTROL 0x203d 4866#define mmCP_PIPE_STATS_CONTROL_BASE_IDX 1 4867#define mmCP_STREAM_OUT_CONTROL 0x203e 4868#define mmCP_STREAM_OUT_CONTROL_BASE_IDX 1 4869#define mmCP_STRMOUT_CNTL 0x203f 4870#define mmCP_STRMOUT_CNTL_BASE_IDX 1 4871#define mmSCRATCH_REG0 0x2040 4872#define mmSCRATCH_REG0_BASE_IDX 1 4873#define mmSCRATCH_REG1 0x2041 4874#define mmSCRATCH_REG1_BASE_IDX 1 4875#define mmSCRATCH_REG2 0x2042 4876#define mmSCRATCH_REG2_BASE_IDX 1 4877#define mmSCRATCH_REG3 0x2043 4878#define mmSCRATCH_REG3_BASE_IDX 1 4879#define mmSCRATCH_REG4 0x2044 4880#define mmSCRATCH_REG4_BASE_IDX 1 4881#define mmSCRATCH_REG5 0x2045 4882#define mmSCRATCH_REG5_BASE_IDX 1 4883#define mmSCRATCH_REG6 0x2046 4884#define mmSCRATCH_REG6_BASE_IDX 1 4885#define mmSCRATCH_REG7 0x2047 4886#define mmSCRATCH_REG7_BASE_IDX 1 4887#define mmCP_APPEND_DATA_HI 0x204c 4888#define mmCP_APPEND_DATA_HI_BASE_IDX 1 4889#define mmCP_APPEND_LAST_CS_FENCE_HI 0x204d 4890#define mmCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX 1 4891#define mmCP_APPEND_LAST_PS_FENCE_HI 0x204e 4892#define mmCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX 1 4893#define mmSCRATCH_UMSK 0x2050 4894#define mmSCRATCH_UMSK_BASE_IDX 1 4895#define mmSCRATCH_ADDR 0x2051 4896#define mmSCRATCH_ADDR_BASE_IDX 1 4897#define mmCP_PFP_ATOMIC_PREOP_LO 0x2052 4898#define mmCP_PFP_ATOMIC_PREOP_LO_BASE_IDX 1 4899#define mmCP_PFP_ATOMIC_PREOP_HI 0x2053 4900#define mmCP_PFP_ATOMIC_PREOP_HI_BASE_IDX 1 4901#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO 0x2054 4902#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 4903#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI 0x2055 4904#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 4905#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO 0x2056 4906#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 4907#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI 0x2057 4908#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 4909#define mmCP_APPEND_ADDR_LO 0x2058 4910#define mmCP_APPEND_ADDR_LO_BASE_IDX 1 4911#define mmCP_APPEND_ADDR_HI 0x2059 4912#define mmCP_APPEND_ADDR_HI_BASE_IDX 1 4913#define mmCP_APPEND_DATA_LO 0x205a 4914#define mmCP_APPEND_DATA_LO_BASE_IDX 1 4915#define mmCP_APPEND_LAST_CS_FENCE_LO 0x205b 4916#define mmCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX 1 4917#define mmCP_APPEND_LAST_PS_FENCE_LO 0x205c 4918#define mmCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX 1 4919#define mmCP_ATOMIC_PREOP_LO 0x205d 4920#define mmCP_ATOMIC_PREOP_LO_BASE_IDX 1 4921#define mmCP_ME_ATOMIC_PREOP_LO 0x205d 4922#define mmCP_ME_ATOMIC_PREOP_LO_BASE_IDX 1 4923#define mmCP_ATOMIC_PREOP_HI 0x205e 4924#define mmCP_ATOMIC_PREOP_HI_BASE_IDX 1 4925#define mmCP_ME_ATOMIC_PREOP_HI 0x205e 4926#define mmCP_ME_ATOMIC_PREOP_HI_BASE_IDX 1 4927#define mmCP_GDS_ATOMIC0_PREOP_LO 0x205f 4928#define mmCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 4929#define mmCP_ME_GDS_ATOMIC0_PREOP_LO 0x205f 4930#define mmCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 4931#define mmCP_GDS_ATOMIC0_PREOP_HI 0x2060 4932#define mmCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 4933#define mmCP_ME_GDS_ATOMIC0_PREOP_HI 0x2060 4934#define mmCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 4935#define mmCP_GDS_ATOMIC1_PREOP_LO 0x2061 4936#define mmCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 4937#define mmCP_ME_GDS_ATOMIC1_PREOP_LO 0x2061 4938#define mmCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 4939#define mmCP_GDS_ATOMIC1_PREOP_HI 0x2062 4940#define mmCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 4941#define mmCP_ME_GDS_ATOMIC1_PREOP_HI 0x2062 4942#define mmCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 4943#define mmCP_ME_MC_WADDR_LO 0x2069 4944#define mmCP_ME_MC_WADDR_LO_BASE_IDX 1 4945#define mmCP_ME_MC_WADDR_HI 0x206a 4946#define mmCP_ME_MC_WADDR_HI_BASE_IDX 1 4947#define mmCP_ME_MC_WDATA_LO 0x206b 4948#define mmCP_ME_MC_WDATA_LO_BASE_IDX 1 4949#define mmCP_ME_MC_WDATA_HI 0x206c 4950#define mmCP_ME_MC_WDATA_HI_BASE_IDX 1 4951#define mmCP_ME_MC_RADDR_LO 0x206d 4952#define mmCP_ME_MC_RADDR_LO_BASE_IDX 1 4953#define mmCP_ME_MC_RADDR_HI 0x206e 4954#define mmCP_ME_MC_RADDR_HI_BASE_IDX 1 4955#define mmCP_SEM_WAIT_TIMER 0x206f 4956#define mmCP_SEM_WAIT_TIMER_BASE_IDX 1 4957#define mmCP_SIG_SEM_ADDR_LO 0x2070 4958#define mmCP_SIG_SEM_ADDR_LO_BASE_IDX 1 4959#define mmCP_SIG_SEM_ADDR_HI 0x2071 4960#define mmCP_SIG_SEM_ADDR_HI_BASE_IDX 1 4961#define mmCP_WAIT_REG_MEM_TIMEOUT 0x2074 4962#define mmCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX 1 4963#define mmCP_WAIT_SEM_ADDR_LO 0x2075 4964#define mmCP_WAIT_SEM_ADDR_LO_BASE_IDX 1 4965#define mmCP_WAIT_SEM_ADDR_HI 0x2076 4966#define mmCP_WAIT_SEM_ADDR_HI_BASE_IDX 1 4967#define mmCP_DMA_PFP_CONTROL 0x2077 4968#define mmCP_DMA_PFP_CONTROL_BASE_IDX 1 4969#define mmCP_DMA_ME_CONTROL 0x2078 4970#define mmCP_DMA_ME_CONTROL_BASE_IDX 1 4971#define mmCP_COHER_BASE_HI 0x2079 4972#define mmCP_COHER_BASE_HI_BASE_IDX 1 4973#define mmCP_COHER_START_DELAY 0x207b 4974#define mmCP_COHER_START_DELAY_BASE_IDX 1 4975#define mmCP_COHER_CNTL 0x207c 4976#define mmCP_COHER_CNTL_BASE_IDX 1 4977#define mmCP_COHER_SIZE 0x207d 4978#define mmCP_COHER_SIZE_BASE_IDX 1 4979#define mmCP_COHER_BASE 0x207e 4980#define mmCP_COHER_BASE_BASE_IDX 1 4981#define mmCP_COHER_STATUS 0x207f 4982#define mmCP_COHER_STATUS_BASE_IDX 1 4983#define mmCP_DMA_ME_SRC_ADDR 0x2080 4984#define mmCP_DMA_ME_SRC_ADDR_BASE_IDX 1 4985#define mmCP_DMA_ME_SRC_ADDR_HI 0x2081 4986#define mmCP_DMA_ME_SRC_ADDR_HI_BASE_IDX 1 4987#define mmCP_DMA_ME_DST_ADDR 0x2082 4988#define mmCP_DMA_ME_DST_ADDR_BASE_IDX 1 4989#define mmCP_DMA_ME_DST_ADDR_HI 0x2083 4990#define mmCP_DMA_ME_DST_ADDR_HI_BASE_IDX 1 4991#define mmCP_DMA_ME_COMMAND 0x2084 4992#define mmCP_DMA_ME_COMMAND_BASE_IDX 1 4993#define mmCP_DMA_PFP_SRC_ADDR 0x2085 4994#define mmCP_DMA_PFP_SRC_ADDR_BASE_IDX 1 4995#define mmCP_DMA_PFP_SRC_ADDR_HI 0x2086 4996#define mmCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX 1 4997#define mmCP_DMA_PFP_DST_ADDR 0x2087 4998#define mmCP_DMA_PFP_DST_ADDR_BASE_IDX 1 4999#define mmCP_DMA_PFP_DST_ADDR_HI 0x2088 5000#define mmCP_DMA_PFP_DST_ADDR_HI_BASE_IDX 1
5001#define mmCP_DMA_PFP_COMMAND 0x2089 5002#define mmCP_DMA_PFP_COMMAND_BASE_IDX 1 5003#define mmCP_DMA_CNTL 0x208a 5004#define mmCP_DMA_CNTL_BASE_IDX 1 5005#define mmCP_DMA_READ_TAGS 0x208b 5006#define mmCP_DMA_READ_TAGS_BASE_IDX 1 5007#define mmCP_COHER_SIZE_HI 0x208c 5008#define mmCP_COHER_SIZE_HI_BASE_IDX 1 5009#define mmCP_PFP_IB_CONTROL 0x208d 5010#define mmCP_PFP_IB_CONTROL_BASE_IDX 1 5011#define mmCP_PFP_LOAD_CONTROL 0x208e 5012#define mmCP_PFP_LOAD_CONTROL_BASE_IDX 1 5013#define mmCP_SCRATCH_INDEX 0x208f 5014#define mmCP_SCRATCH_INDEX_BASE_IDX 1 5015#define mmCP_SCRATCH_DATA 0x2090 5016#define mmCP_SCRATCH_DATA_BASE_IDX 1 5017#define mmCP_RB_OFFSET 0x2091 5018#define mmCP_RB_OFFSET_BASE_IDX 1 5019#define mmCP_IB1_OFFSET 0x2092 5020#define mmCP_IB1_OFFSET_BASE_IDX 1 5021#define mmCP_IB2_OFFSET 0x2093 5022#define mmCP_IB2_OFFSET_BASE_IDX 1 5023#define mmCP_IB1_PREAMBLE_BEGIN 0x2094 5024#define mmCP_IB1_PREAMBLE_BEGIN_BASE_IDX 1 5025#define mmCP_IB1_PREAMBLE_END 0x2095 5026#define mmCP_IB1_PREAMBLE_END_BASE_IDX 1 5027#define mmCP_IB2_PREAMBLE_BEGIN 0x2096 5028#define mmCP_IB2_PREAMBLE_BEGIN_BASE_IDX 1 5029#define mmCP_IB2_PREAMBLE_END 0x2097 5030#define mmCP_IB2_PREAMBLE_END_BASE_IDX 1 5031#define mmCP_CE_IB1_OFFSET 0x2098 5032#define mmCP_CE_IB1_OFFSET_BASE_IDX 1 5033#define mmCP_CE_IB2_OFFSET 0x2099 5034#define mmCP_CE_IB2_OFFSET_BASE_IDX 1 5035#define mmCP_CE_COUNTER 0x209a 5036#define mmCP_CE_COUNTER_BASE_IDX 1 5037#define mmCP_CE_RB_OFFSET 0x209b 5038#define mmCP_CE_RB_OFFSET_BASE_IDX 1 5039#define mmCP_CE_INIT_CMD_BUFSZ 0x20bd 5040#define mmCP_CE_INIT_CMD_BUFSZ_BASE_IDX 1 5041#define mmCP_CE_IB1_CMD_BUFSZ 0x20be 5042#define mmCP_CE_IB1_CMD_BUFSZ_BASE_IDX 1 5043#define mmCP_CE_IB2_CMD_BUFSZ 0x20bf 5044#define mmCP_CE_IB2_CMD_BUFSZ_BASE_IDX 1 5045#define mmCP_IB1_CMD_BUFSZ 0x20c0 5046#define mmCP_IB1_CMD_BUFSZ_BASE_IDX 1 5047#define mmCP_IB2_CMD_BUFSZ 0x20c1 5048#define mmCP_IB2_CMD_BUFSZ_BASE_IDX 1 5049#define mmCP_ST_CMD_BUFSZ 0x20c2 5050#define mmCP_ST_CMD_BUFSZ_BASE_IDX 1 5051#define mmCP_CE_INIT_BASE_LO 0x20c3 5052#define mmCP_CE_INIT_BASE_LO_BASE_IDX 1 5053#define mmCP_CE_INIT_BASE_HI 0x20c4 5054#define mmCP_CE_INIT_BASE_HI_BASE_IDX 1 5055#define mmCP_CE_INIT_BUFSZ 0x20c5 5056#define mmCP_CE_INIT_BUFSZ_BASE_IDX 1 5057#define mmCP_CE_IB1_BASE_LO 0x20c6 5058#define mmCP_CE_IB1_BASE_LO_BASE_IDX 1 5059#define mmCP_CE_IB1_BASE_HI 0x20c7 5060#define mmCP_CE_IB1_BASE_HI_BASE_IDX 1 5061#define mmCP_CE_IB1_BUFSZ 0x20c8 5062#define mmCP_CE_IB1_BUFSZ_BASE_IDX 1 5063#define mmCP_CE_IB2_BASE_LO 0x20c9 5064#define mmCP_CE_IB2_BASE_LO_BASE_IDX 1 5065#define mmCP_CE_IB2_BASE_HI 0x20ca 5066#define mmCP_CE_IB2_BASE_HI_BASE_IDX 1 5067#define mmCP_CE_IB2_BUFSZ 0x20cb 5068#define mmCP_CE_IB2_BUFSZ_BASE_IDX 1 5069#define mmCP_IB1_BASE_LO 0x20cc 5070#define mmCP_IB1_BASE_LO_BASE_IDX 1 5071#define mmCP_IB1_BASE_HI 0x20cd 5072#define mmCP_IB1_BASE_HI_BASE_IDX 1 5073#define mmCP_IB1_BUFSZ 0x20ce 5074#define mmCP_IB1_BUFSZ_BASE_IDX 1 5075#define mmCP_IB2_BASE_LO 0x20cf 5076#define mmCP_IB2_BASE_LO_BASE_IDX 1 5077#define mmCP_IB2_BASE_HI 0x20d0 5078#define mmCP_IB2_BASE_HI_BASE_IDX 1 5079#define mmCP_IB2_BUFSZ 0x20d1 5080#define mmCP_IB2_BUFSZ_BASE_IDX 1 5081#define mmCP_ST_BASE_LO 0x20d2 5082#define mmCP_ST_BASE_LO_BASE_IDX 1 5083#define mmCP_ST_BASE_HI 0x20d3 5084#define mmCP_ST_BASE_HI_BASE_IDX 1 5085#define mmCP_ST_BUFSZ 0x20d4 5086#define mmCP_ST_BUFSZ_BASE_IDX 1 5087#define mmCP_EOP_DONE_EVENT_CNTL 0x20d5 5088#define mmCP_EOP_DONE_EVENT_CNTL_BASE_IDX 1 5089#define mmCP_EOP_DONE_DATA_CNTL 0x20d6 5090#define mmCP_EOP_DONE_DATA_CNTL_BASE_IDX 1 5091#define mmCP_EOP_DONE_CNTX_ID 0x20d7 5092#define mmCP_EOP_DONE_CNTX_ID_BASE_IDX 1 5093#define mmCP_PFP_COMPLETION_STATUS 0x20ec 5094#define mmCP_PFP_COMPLETION_STATUS_BASE_IDX 1 5095#define mmCP_CE_COMPLETION_STATUS 0x20ed 5096#define mmCP_CE_COMPLETION_STATUS_BASE_IDX 1 5097#define mmCP_PRED_NOT_VISIBLE 0x20ee 5098#define mmCP_PRED_NOT_VISIBLE_BASE_IDX 1 5099#define mmCP_PFP_METADATA_BASE_ADDR 0x20f0 5100#define mmCP_PFP_METADATA_BASE_ADDR_BASE_IDX 1 5101#define mmCP_PFP_METADATA_BASE_ADDR_HI 0x20f1 5102#define mmCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX 1 5103#define mmCP_CE_METADATA_BASE_ADDR 0x20f2 5104#define mmCP_CE_METADATA_BASE_ADDR_BASE_IDX 1 5105#define mmCP_CE_METADATA_BASE_ADDR_HI 0x20f3 5106#define mmCP_CE_METADATA_BASE_ADDR_HI_BASE_IDX 1 5107#define mmCP_DRAW_INDX_INDR_ADDR 0x20f4 5108#define mmCP_DRAW_INDX_INDR_ADDR_BASE_IDX 1 5109#define mmCP_DRAW_INDX_INDR_ADDR_HI 0x20f5 5110#define mmCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX 1 5111#define mmCP_DISPATCH_INDR_ADDR 0x20f6 5112#define mmCP_DISPATCH_INDR_ADDR_BASE_IDX 1 5113#define mmCP_DISPATCH_INDR_ADDR_HI 0x20f7 5114#define mmCP_DISPATCH_INDR_ADDR_HI_BASE_IDX 1 5115#define mmCP_INDEX_BASE_ADDR 0x20f8 5116#define mmCP_INDEX_BASE_ADDR_BASE_IDX 1 5117#define mmCP_INDEX_BASE_ADDR_HI 0x20f9 5118#define mmCP_INDEX_BASE_ADDR_HI_BASE_IDX 1 5119#define mmCP_INDEX_TYPE 0x20fa 5120#define mmCP_INDEX_TYPE_BASE_IDX 1 5121#define mmCP_GDS_BKUP_ADDR 0x20fb 5122#define mmCP_GDS_BKUP_ADDR_BASE_IDX 1 5123#define mmCP_GDS_BKUP_ADDR_HI 0x20fc 5124#define mmCP_GDS_BKUP_ADDR_HI_BASE_IDX 1 5125#define mmCP_SAMPLE_STATUS 0x20fd 5126#define mmCP_SAMPLE_STATUS_BASE_IDX 1 5127#define mmCP_ME_COHER_CNTL 0x20fe 5128#define mmCP_ME_COHER_CNTL_BASE_IDX 1 5129#define mmCP_ME_COHER_SIZE 0x20ff 5130#define mmCP_ME_COHER_SIZE_BASE_IDX 1 5131#define mmCP_ME_COHER_SIZE_HI 0x2100 5132#define mmCP_ME_COHER_SIZE_HI_BASE_IDX 1 5133#define mmCP_ME_COHER_BASE 0x2101 5134#define mmCP_ME_COHER_BASE_BASE_IDX 1 5135#define mmCP_ME_COHER_BASE_HI 0x2102 5136#define mmCP_ME_COHER_BASE_HI_BASE_IDX 1 5137#define mmCP_ME_COHER_STATUS 0x2103 5138#define mmCP_ME_COHER_STATUS_BASE_IDX 1 5139#define mmRLC_GPM_PERF_COUNT_0 0x2140 5140#define mmRLC_GPM_PERF_COUNT_0_BASE_IDX 1 5141#define mmRLC_GPM_PERF_COUNT_1 0x2141 5142#define mmRLC_GPM_PERF_COUNT_1_BASE_IDX 1 5143#define mmGRBM_GFX_INDEX 0x2200 5144#define mmGRBM_GFX_INDEX_BASE_IDX 1 5145#define mmVGT_GSVS_RING_SIZE 0x2241 5146#define mmVGT_GSVS_RING_SIZE_BASE_IDX 1 5147#define mmVGT_PRIMITIVE_TYPE 0x2242 5148#define mmVGT_PRIMITIVE_TYPE_BASE_IDX 1 5149#define mmVGT_INDEX_TYPE 0x2243 5150#define mmVGT_INDEX_TYPE_BASE_IDX 1 5151#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x2244 5152#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0_BASE_IDX 1 5153#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x2245 5154#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1_BASE_IDX 1 5155#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x2246 5156#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2_BASE_IDX 1 5157#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x2247 5158#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3_BASE_IDX 1 5159#define mmVGT_MAX_VTX_INDX 0x2248 5160#define mmVGT_MAX_VTX_INDX_BASE_IDX 1 5161#define mmVGT_MIN_VTX_INDX 0x2249 5162#define mmVGT_MIN_VTX_INDX_BASE_IDX 1 5163#define mmVGT_INDX_OFFSET 0x224a 5164#define mmVGT_INDX_OFFSET_BASE_IDX 1 5165#define mmVGT_MULTI_PRIM_IB_RESET_EN 0x224b 5166#define mmVGT_MULTI_PRIM_IB_RESET_EN_BASE_IDX 1 5167#define mmVGT_NUM_INDICES 0x224c 5168#define mmVGT_NUM_INDICES_BASE_IDX 1 5169#define mmVGT_NUM_INSTANCES 0x224d 5170#define mmVGT_NUM_INSTANCES_BASE_IDX 1 5171#define mmVGT_TF_RING_SIZE 0x224e 5172#define mmVGT_TF_RING_SIZE_BASE_IDX 1 5173#define mmVGT_HS_OFFCHIP_PARAM 0x224f 5174#define mmVGT_HS_OFFCHIP_PARAM_BASE_IDX 1 5175#define mmVGT_TF_MEMORY_BASE 0x2250 5176#define mmVGT_TF_MEMORY_BASE_BASE_IDX 1 5177#define mmVGT_TF_MEMORY_BASE_HI 0x2251 5178#define mmVGT_TF_MEMORY_BASE_HI_BASE_IDX 1 5179#define mmWD_POS_BUF_BASE 0x2252 5180#define mmWD_POS_BUF_BASE_BASE_IDX 1 5181#define mmWD_POS_BUF_BASE_HI 0x2253 5182#define mmWD_POS_BUF_BASE_HI_BASE_IDX 1 5183#define mmWD_CNTL_SB_BUF_BASE 0x2254 5184#define mmWD_CNTL_SB_BUF_BASE_BASE_IDX 1 5185#define mmWD_CNTL_SB_BUF_BASE_HI 0x2255 5186#define mmWD_CNTL_SB_BUF_BASE_HI_BASE_IDX 1 5187#define mmWD_INDEX_BUF_BASE 0x2256 5188#define mmWD_INDEX_BUF_BASE_BASE_IDX 1 5189#define mmWD_INDEX_BUF_BASE_HI 0x2257 5190#define mmWD_INDEX_BUF_BASE_HI_BASE_IDX 1 5191#define mmIA_MULTI_VGT_PARAM 0x2258 5192#define mmIA_MULTI_VGT_PARAM_BASE_IDX 1 5193#define mmVGT_INSTANCE_BASE_ID 0x225a 5194#define mmVGT_INSTANCE_BASE_ID_BASE_IDX 1 5195#define mmPA_SU_LINE_STIPPLE_VALUE 0x2280 5196#define mmPA_SU_LINE_STIPPLE_VALUE_BASE_IDX 1 5197#define mmPA_SC_LINE_STIPPLE_STATE 0x2281 5198#define mmPA_SC_LINE_STIPPLE_STATE_BASE_IDX 1 5199#define mmPA_SC_SCREEN_EXTENT_MIN_0 0x2284 5200#define mmPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX 1 5201#define mmPA_SC_SCREEN_EXTENT_MAX_0 0x2285 5202#define mmPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX 1 5203#define mmPA_SC_SCREEN_EXTENT_MIN_1 0x2286 5204#define mmPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX 1 5205#define mmPA_SC_SCREEN_EXTENT_MAX_1 0x228b 5206#define mmPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX 1 5207#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN 0x22a0 5208#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 5209#define mmPA_SC_P3D_TRAP_SCREEN_H 0x22a1 5210#define mmPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX 1 5211#define mmPA_SC_P3D_TRAP_SCREEN_V 0x22a2 5212#define mmPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX 1 5213#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0x22a3 5214#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 5215#define mmPA_SC_P3D_TRAP_SCREEN_COUNT 0x22a4 5216#define mmPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX 1 5217#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN 0x22a8 5218#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 5219#define mmPA_SC_HP3D_TRAP_SCREEN_H 0x22a9 5220#define mmPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX 1 5221#define mmPA_SC_HP3D_TRAP_SCREEN_V 0x22aa 5222#define mmPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX 1 5223#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0x22ab 5224#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 5225#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT 0x22ac 5226#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX 1 5227#define mmPA_SC_TRAP_SCREEN_HV_EN 0x22b0 5228#define mmPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX 1 5229#define mmPA_SC_TRAP_SCREEN_H 0x22b1 5230#define mmPA_SC_TRAP_SCREEN_H_BASE_IDX 1 5231#define mmPA_SC_TRAP_SCREEN_V 0x22b2 5232#define mmPA_SC_TRAP_SCREEN_V_BASE_IDX 1 5233#define mmPA_SC_TRAP_SCREEN_OCCURRENCE 0x22b3 5234#define mmPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 5235#define mmPA_SC_TRAP_SCREEN_COUNT 0x22b4 5236#define mmPA_SC_TRAP_SCREEN_COUNT_BASE_IDX 1 5237#define mmSQ_THREAD_TRACE_BASE 0x2330 5238#define mmSQ_THREAD_TRACE_BASE_BASE_IDX 1 5239#define mmSQ_THREAD_TRACE_SIZE 0x2331 5240#define mmSQ_THREAD_TRACE_SIZE_BASE_IDX 1 5241#define mmSQ_THREAD_TRACE_MASK 0x2332 5242#define mmSQ_THREAD_TRACE_MASK_BASE_IDX 1 5243#define mmSQ_THREAD_TRACE_TOKEN_MASK 0x2333 5244#define mmSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX 1 5245#define mmSQ_THREAD_TRACE_PERF_MASK 0x2334 5246#define mmSQ_THREAD_TRACE_PERF_MASK_BASE_IDX 1 5247#define mmSQ_THREAD_TRACE_CTRL 0x2335 5248#define mmSQ_THREAD_TRACE_CTRL_BASE_IDX 1 5249#define mmSQ_THREAD_TRACE_MODE 0x2336 5250#define mmSQ_THREAD_TRACE_MODE_BASE_IDX 1 5251#define mmSQ_THREAD_TRACE_BASE2 0x2337 5252#define mmSQ_THREAD_TRACE_BASE2_BASE_IDX 1 5253#define mmSQ_THREAD_TRACE_TOKEN_MASK2 0x2338 5254#define mmSQ_THREAD_TRACE_TOKEN_MASK2_BASE_IDX 1 5255#define mmSQ_THREAD_TRACE_WPTR 0x2339 5256#define mmSQ_THREAD_TRACE_WPTR_BASE_IDX 1 5257#define mmSQ_THREAD_TRACE_STATUS 0x233a 5258#define mmSQ_THREAD_TRACE_STATUS_BASE_IDX 1 5259#define mmSQ_THREAD_TRACE_HIWATER 0x233b 5260#define mmSQ_THREAD_TRACE_HIWATER_BASE_IDX 1 5261#define mmSQ_THREAD_TRACE_CNTR 0x233c 5262#define mmSQ_THREAD_TRACE_CNTR_BASE_IDX 1 5263#define mmSQ_THREAD_TRACE_USERDATA_0 0x2340 5264#define mmSQ_THREAD_TRACE_USERDATA_0_BASE_IDX 1 5265#define mmSQ_THREAD_TRACE_USERDATA_1 0x2341 5266#define mmSQ_THREAD_TRACE_USERDATA_1_BASE_IDX 1 5267#define mmSQ_THREAD_TRACE_USERDATA_2 0x2342 5268#define mmSQ_THREAD_TRACE_USERDATA_2_BASE_IDX 1 5269#define mmSQ_THREAD_TRACE_USERDATA_3 0x2343 5270#define mmSQ_THREAD_TRACE_USERDATA_3_BASE_IDX 1 5271#define mmSQC_CACHES 0x2348 5272#define mmSQC_CACHES_BASE_IDX 1 5273#define mmSQC_WRITEBACK 0x2349 5274#define mmSQC_WRITEBACK_BASE_IDX 1 5275#define mmTA_CS_BC_BASE_ADDR 0x2380 5276#define mmTA_CS_BC_BASE_ADDR_BASE_IDX 1 5277#define mmTA_CS_BC_BASE_ADDR_HI 0x2381 5278#define mmTA_CS_BC_BASE_ADDR_HI_BASE_IDX 1 5279#define mmDB_OCCLUSION_COUNT0_LOW 0x23c0 5280#define mmDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1 5281#define mmDB_OCCLUSION_COUNT0_HI 0x23c1 5282#define mmDB_OCCLUSION_COUNT0_HI_BASE_IDX 1 5283#define mmDB_OCCLUSION_COUNT1_LOW 0x23c2 5284#define mmDB_OCCLUSION_COUNT1_LOW_BASE_IDX 1 5285#define mmDB_OCCLUSION_COUNT1_HI 0x23c3 5286#define mmDB_OCCLUSION_COUNT1_HI_BASE_IDX 1 5287#define mmDB_OCCLUSION_COUNT2_LOW 0x23c4 5288#define mmDB_OCCLUSION_COUNT2_LOW_BASE_IDX 1 5289#define mmDB_OCCLUSION_COUNT2_HI 0x23c5 5290#define mmDB_OCCLUSION_COUNT2_HI_BASE_IDX 1 5291#define mmDB_OCCLUSION_COUNT3_LOW 0x23c6 5292#define mmDB_OCCLUSION_COUNT3_LOW_BASE_IDX 1 5293#define mmDB_OCCLUSION_COUNT3_HI 0x23c7 5294#define mmDB_OCCLUSION_COUNT3_HI_BASE_IDX 1 5295#define mmDB_ZPASS_COUNT_LOW 0x23fe 5296#define mmDB_ZPASS_COUNT_LOW_BASE_IDX 1 5297#define mmDB_ZPASS_COUNT_HI 0x23ff 5298#define mmDB_ZPASS_COUNT_HI_BASE_IDX 1 5299#define mmGDS_RD_ADDR 0x2400 5300#define mmGDS_RD_ADDR_BASE_IDX 1 5301#define mmGDS_RD_DATA 0x2401 5302#define mmGDS_RD_DATA_BASE_IDX 1 5303#define mmGDS_RD_BURST_ADDR 0x2402 5304#define mmGDS_RD_BURST_ADDR_BASE_IDX 1 5305#define mmGDS_RD_BURST_COUNT 0x2403 5306#define mmGDS_RD_BURST_COUNT_BASE_IDX 1 5307#define mmGDS_RD_BURST_DATA 0x2404 5308#define mmGDS_RD_BURST_DATA_BASE_IDX 1 5309#define mmGDS_WR_ADDR 0x2405 5310#define mmGDS_WR_ADDR_BASE_IDX 1 5311#define mmGDS_WR_DATA 0x2406 5312#define mmGDS_WR_DATA_BASE_IDX 1 5313#define mmGDS_WR_BURST_ADDR 0x2407 5314#define mmGDS_WR_BURST_ADDR_BASE_IDX 1 5315#define mmGDS_WR_BURST_DATA 0x2408 5316#define mmGDS_WR_BURST_DATA_BASE_IDX 1 5317#define mmGDS_WRITE_COMPLETE 0x2409 5318#define mmGDS_WRITE_COMPLETE_BASE_IDX 1 5319#define mmGDS_ATOM_CNTL 0x240a 5320#define mmGDS_ATOM_CNTL_BASE_IDX 1 5321#define mmGDS_ATOM_COMPLETE 0x240b 5322#define mmGDS_ATOM_COMPLETE_BASE_IDX 1 5323#define mmGDS_ATOM_BASE 0x240c 5324#define mmGDS_ATOM_BASE_BASE_IDX 1 5325#define mmGDS_ATOM_SIZE 0x240d 5326#define mmGDS_ATOM_SIZE_BASE_IDX 1 5327#define mmGDS_ATOM_OFFSET0 0x240e 5328#define mmGDS_ATOM_OFFSET0_BASE_IDX 1 5329#define mmGDS_ATOM_OFFSET1 0x240f 5330#define mmGDS_ATOM_OFFSET1_BASE_IDX 1 5331#define mmGDS_ATOM_DST 0x2410 5332#define mmGDS_ATOM_DST_BASE_IDX 1 5333#define mmGDS_ATOM_OP 0x2411 5334#define mmGDS_ATOM_OP_BASE_IDX 1 5335#define mmGDS_ATOM_SRC0 0x2412 5336#define mmGDS_ATOM_SRC0_BASE_IDX 1 5337#define mmGDS_ATOM_SRC0_U 0x2413 5338#define mmGDS_ATOM_SRC0_U_BASE_IDX 1 5339#define mmGDS_ATOM_SRC1 0x2414 5340#define mmGDS_ATOM_SRC1_BASE_IDX 1 5341#define mmGDS_ATOM_SRC1_U 0x2415 5342#define mmGDS_ATOM_SRC1_U_BASE_IDX 1 5343#define mmGDS_ATOM_READ0 0x2416 5344#define mmGDS_ATOM_READ0_BASE_IDX 1 5345#define mmGDS_ATOM_READ0_U 0x2417 5346#define mmGDS_ATOM_READ0_U_BASE_IDX 1 5347#define mmGDS_ATOM_READ1 0x2418 5348#define mmGDS_ATOM_READ1_BASE_IDX 1 5349#define mmGDS_ATOM_READ1_U 0x2419 5350#define mmGDS_ATOM_READ1_U_BASE_IDX 1 5351#define mmGDS_GWS_RESOURCE_CNTL 0x241a 5352#define mmGDS_GWS_RESOURCE_CNTL_BASE_IDX 1 5353#define mmGDS_GWS_RESOURCE 0x241b 5354#define mmGDS_GWS_RESOURCE_BASE_IDX 1 5355#define mmGDS_GWS_RESOURCE_CNT 0x241c 5356#define mmGDS_GWS_RESOURCE_CNT_BASE_IDX 1 5357#define mmGDS_OA_CNTL 0x241d 5358#define mmGDS_OA_CNTL_BASE_IDX 1 5359#define mmGDS_OA_COUNTER 0x241e 5360#define mmGDS_OA_COUNTER_BASE_IDX 1 5361#define mmGDS_OA_ADDRESS 0x241f 5362#define mmGDS_OA_ADDRESS_BASE_IDX 1 5363#define mmGDS_OA_INCDEC 0x2420 5364#define mmGDS_OA_INCDEC_BASE_IDX 1 5365#define mmGDS_OA_RING_SIZE 0x2421 5366#define mmGDS_OA_RING_SIZE_BASE_IDX 1 5367#define mmSPI_CONFIG_CNTL 0x2440 5368#define mmSPI_CONFIG_CNTL_BASE_IDX 1 5369#define mmSPI_CONFIG_CNTL_1 0x2441 5370#define mmSPI_CONFIG_CNTL_1_BASE_IDX 1 5371#define mmSPI_CONFIG_CNTL_2 0x2442 5372#define mmSPI_CONFIG_CNTL_2_BASE_IDX 1 5373 5374 5375// addressBlock: gc_perfddec 5376// base address: 0x34000 5377#define mmCPG_PERFCOUNTER1_LO 0x3000 5378#define mmCPG_PERFCOUNTER1_LO_BASE_IDX 1 5379#define mmCPG_PERFCOUNTER1_HI 0x3001 5380#define mmCPG_PERFCOUNTER1_HI_BASE_IDX 1 5381#define mmCPG_PERFCOUNTER0_LO 0x3002 5382#define mmCPG_PERFCOUNTER0_LO_BASE_IDX 1 5383#define mmCPG_PERFCOUNTER0_HI 0x3003 5384#define mmCPG_PERFCOUNTER0_HI_BASE_IDX 1 5385#define mmCPC_PERFCOUNTER1_LO 0x3004 5386#define mmCPC_PERFCOUNTER1_LO_BASE_IDX 1 5387#define mmCPC_PERFCOUNTER1_HI 0x3005 5388#define mmCPC_PERFCOUNTER1_HI_BASE_IDX 1 5389#define mmCPC_PERFCOUNTER0_LO 0x3006 5390#define mmCPC_PERFCOUNTER0_LO_BASE_IDX 1 5391#define mmCPC_PERFCOUNTER0_HI 0x3007 5392#define mmCPC_PERFCOUNTER0_HI_BASE_IDX 1 5393#define mmCPF_PERFCOUNTER1_LO 0x3008 5394#define mmCPF_PERFCOUNTER1_LO_BASE_IDX 1 5395#define mmCPF_PERFCOUNTER1_HI 0x3009 5396#define mmCPF_PERFCOUNTER1_HI_BASE_IDX 1 5397#define mmCPF_PERFCOUNTER0_LO 0x300a 5398#define mmCPF_PERFCOUNTER0_LO_BASE_IDX 1 5399#define mmCPF_PERFCOUNTER0_HI 0x300b 5400#define mmCPF_PERFCOUNTER0_HI_BASE_IDX 1 5401#define mmCPF_LATENCY_STATS_DATA 0x300c 5402#define mmCPF_LATENCY_STATS_DATA_BASE_IDX 1 5403#define mmCPG_LATENCY_STATS_DATA 0x300d 5404#define mmCPG_LATENCY_STATS_DATA_BASE_IDX 1 5405#define mmCPC_LATENCY_STATS_DATA 0x300e 5406#define mmCPC_LATENCY_STATS_DATA_BASE_IDX 1 5407#define mmGRBM_PERFCOUNTER0_LO 0x3040 5408#define mmGRBM_PERFCOUNTER0_LO_BASE_IDX 1 5409#define mmGRBM_PERFCOUNTER0_HI 0x3041 5410#define mmGRBM_PERFCOUNTER0_HI_BASE_IDX 1 5411#define mmGRBM_PERFCOUNTER1_LO 0x3043 5412#define mmGRBM_PERFCOUNTER1_LO_BASE_IDX 1 5413#define mmGRBM_PERFCOUNTER1_HI 0x3044 5414#define mmGRBM_PERFCOUNTER1_HI_BASE_IDX 1 5415#define mmGRBM_SE0_PERFCOUNTER_LO 0x3045 5416#define mmGRBM_SE0_PERFCOUNTER_LO_BASE_IDX 1 5417#define mmGRBM_SE0_PERFCOUNTER_HI 0x3046 5418#define mmGRBM_SE0_PERFCOUNTER_HI_BASE_IDX 1 5419#define mmGRBM_SE1_PERFCOUNTER_LO 0x3047 5420#define mmGRBM_SE1_PERFCOUNTER_LO_BASE_IDX 1 5421#define mmGRBM_SE1_PERFCOUNTER_HI 0x3048 5422#define mmGRBM_SE1_PERFCOUNTER_HI_BASE_IDX 1 5423#define mmGRBM_SE2_PERFCOUNTER_LO 0x3049 5424#define mmGRBM_SE2_PERFCOUNTER_LO_BASE_IDX 1 5425#define mmGRBM_SE2_PERFCOUNTER_HI 0x304a 5426#define mmGRBM_SE2_PERFCOUNTER_HI_BASE_IDX 1 5427#define mmGRBM_SE3_PERFCOUNTER_LO 0x304b 5428#define mmGRBM_SE3_PERFCOUNTER_LO_BASE_IDX 1 5429#define mmGRBM_SE3_PERFCOUNTER_HI 0x304c 5430#define mmGRBM_SE3_PERFCOUNTER_HI_BASE_IDX 1 5431#define mmWD_PERFCOUNTER0_LO 0x3080 5432#define mmWD_PERFCOUNTER0_LO_BASE_IDX 1 5433#define mmWD_PERFCOUNTER0_HI 0x3081 5434#define mmWD_PERFCOUNTER0_HI_BASE_IDX 1 5435#define mmWD_PERFCOUNTER1_LO 0x3082 5436#define mmWD_PERFCOUNTER1_LO_BASE_IDX 1 5437#define mmWD_PERFCOUNTER1_HI 0x3083 5438#define mmWD_PERFCOUNTER1_HI_BASE_IDX 1 5439#define mmWD_PERFCOUNTER2_LO 0x3084 5440#define mmWD_PERFCOUNTER2_LO_BASE_IDX 1 5441#define mmWD_PERFCOUNTER2_HI 0x3085 5442#define mmWD_PERFCOUNTER2_HI_BASE_IDX 1 5443#define mmWD_PERFCOUNTER3_LO 0x3086 5444#define mmWD_PERFCOUNTER3_LO_BASE_IDX 1 5445#define mmWD_PERFCOUNTER3_HI 0x3087 5446#define mmWD_PERFCOUNTER3_HI_BASE_IDX 1 5447#define mmIA_PERFCOUNTER0_LO 0x3088 5448#define mmIA_PERFCOUNTER0_LO_BASE_IDX 1 5449#define mmIA_PERFCOUNTER0_HI 0x3089 5450#define mmIA_PERFCOUNTER0_HI_BASE_IDX 1 5451#define mmIA_PERFCOUNTER1_LO 0x308a 5452#define mmIA_PERFCOUNTER1_LO_BASE_IDX 1 5453#define mmIA_PERFCOUNTER1_HI 0x308b 5454#define mmIA_PERFCOUNTER1_HI_BASE_IDX 1 5455#define mmIA_PERFCOUNTER2_LO 0x308c 5456#define mmIA_PERFCOUNTER2_LO_BASE_IDX 1 5457#define mmIA_PERFCOUNTER2_HI 0x308d 5458#define mmIA_PERFCOUNTER2_HI_BASE_IDX 1 5459#define mmIA_PERFCOUNTER3_LO 0x308e 5460#define mmIA_PERFCOUNTER3_LO_BASE_IDX 1 5461#define mmIA_PERFCOUNTER3_HI 0x308f 5462#define mmIA_PERFCOUNTER3_HI_BASE_IDX 1 5463#define mmVGT_PERFCOUNTER0_LO 0x3090 5464#define mmVGT_PERFCOUNTER0_LO_BASE_IDX 1 5465#define mmVGT_PERFCOUNTER0_HI 0x3091 5466#define mmVGT_PERFCOUNTER0_HI_BASE_IDX 1 5467#define mmVGT_PERFCOUNTER1_LO 0x3092 5468#define mmVGT_PERFCOUNTER1_LO_BASE_IDX 1 5469#define mmVGT_PERFCOUNTER1_HI 0x3093 5470#define mmVGT_PERFCOUNTER1_HI_BASE_IDX 1 5471#define mmVGT_PERFCOUNTER2_LO 0x3094 5472#define mmVGT_PERFCOUNTER2_LO_BASE_IDX 1 5473#define mmVGT_PERFCOUNTER2_HI 0x3095 5474#define mmVGT_PERFCOUNTER2_HI_BASE_IDX 1 5475#define mmVGT_PERFCOUNTER3_LO 0x3096 5476#define mmVGT_PERFCOUNTER3_LO_BASE_IDX 1 5477#define mmVGT_PERFCOUNTER3_HI 0x3097 5478#define mmVGT_PERFCOUNTER3_HI_BASE_IDX 1 5479#define mmPA_SU_PERFCOUNTER0_LO 0x3100 5480#define mmPA_SU_PERFCOUNTER0_LO_BASE_IDX 1 5481#define mmPA_SU_PERFCOUNTER0_HI 0x3101 5482#define mmPA_SU_PERFCOUNTER0_HI_BASE_IDX 1 5483#define mmPA_SU_PERFCOUNTER1_LO 0x3102 5484#define mmPA_SU_PERFCOUNTER1_LO_BASE_IDX 1 5485#define mmPA_SU_PERFCOUNTER1_HI 0x3103 5486#define mmPA_SU_PERFCOUNTER1_HI_BASE_IDX 1 5487#define mmPA_SU_PERFCOUNTER2_LO 0x3104 5488#define mmPA_SU_PERFCOUNTER2_LO_BASE_IDX 1 5489#define mmPA_SU_PERFCOUNTER2_HI 0x3105 5490#define mmPA_SU_PERFCOUNTER2_HI_BASE_IDX 1 5491#define mmPA_SU_PERFCOUNTER3_LO 0x3106 5492#define mmPA_SU_PERFCOUNTER3_LO_BASE_IDX 1 5493#define mmPA_SU_PERFCOUNTER3_HI 0x3107 5494#define mmPA_SU_PERFCOUNTER3_HI_BASE_IDX 1 5495#define mmPA_SC_PERFCOUNTER0_LO 0x3140 5496#define mmPA_SC_PERFCOUNTER0_LO_BASE_IDX 1 5497#define mmPA_SC_PERFCOUNTER0_HI 0x3141 5498#define mmPA_SC_PERFCOUNTER0_HI_BASE_IDX 1 5499#define mmPA_SC_PERFCOUNTER1_LO 0x3142 5500#define mmPA_SC_PERFCOUNTER1_LO_BASE_IDX 1 5501#define mmPA_SC_PERFCOUNTER1_HI 0x3143 5502#define mmPA_SC_PERFCOUNTER1_HI_BASE_IDX 1 5503#define mmPA_SC_PERFCOUNTER2_LO 0x3144 5504#define mmPA_SC_PERFCOUNTER2_LO_BASE_IDX 1 5505#define mmPA_SC_PERFCOUNTER2_HI 0x3145 5506#define mmPA_SC_PERFCOUNTER2_HI_BASE_IDX 1 5507#define mmPA_SC_PERFCOUNTER3_LO 0x3146 5508#define mmPA_SC_PERFCOUNTER3_LO_BASE_IDX 1 5509#define mmPA_SC_PERFCOUNTER3_HI 0x3147 5510#define mmPA_SC_PERFCOUNTER3_HI_BASE_IDX 1 5511#define mmPA_SC_PERFCOUNTER4_LO 0x3148 5512#define mmPA_SC_PERFCOUNTER4_LO_BASE_IDX 1 5513#define mmPA_SC_PERFCOUNTER4_HI 0x3149 5514#define mmPA_SC_PERFCOUNTER4_HI_BASE_IDX 1 5515#define mmPA_SC_PERFCOUNTER5_LO 0x314a 5516#define mmPA_SC_PERFCOUNTER5_LO_BASE_IDX 1 5517#define mmPA_SC_PERFCOUNTER5_HI 0x314b 5518#define mmPA_SC_PERFCOUNTER5_HI_BASE_IDX 1 5519#define mmPA_SC_PERFCOUNTER6_LO 0x314c 5520#define mmPA_SC_PERFCOUNTER6_LO_BASE_IDX 1 5521#define mmPA_SC_PERFCOUNTER6_HI 0x314d 5522#define mmPA_SC_PERFCOUNTER6_HI_BASE_IDX 1 5523#define mmPA_SC_PERFCOUNTER7_LO 0x314e 5524#define mmPA_SC_PERFCOUNTER7_LO_BASE_IDX 1 5525#define mmPA_SC_PERFCOUNTER7_HI 0x314f 5526#define mmPA_SC_PERFCOUNTER7_HI_BASE_IDX 1 5527#define mmSPI_PERFCOUNTER0_HI 0x3180 5528#define mmSPI_PERFCOUNTER0_HI_BASE_IDX 1 5529#define mmSPI_PERFCOUNTER0_LO 0x3181 5530#define mmSPI_PERFCOUNTER0_LO_BASE_IDX 1 5531#define mmSPI_PERFCOUNTER1_HI 0x3182 5532#define mmSPI_PERFCOUNTER1_HI_BASE_IDX 1 5533#define mmSPI_PERFCOUNTER1_LO 0x3183 5534#define mmSPI_PERFCOUNTER1_LO_BASE_IDX 1 5535#define mmSPI_PERFCOUNTER2_HI 0x3184 5536#define mmSPI_PERFCOUNTER2_HI_BASE_IDX 1 5537#define mmSPI_PERFCOUNTER2_LO 0x3185 5538#define mmSPI_PERFCOUNTER2_LO_BASE_IDX 1 5539#define mmSPI_PERFCOUNTER3_HI 0x3186 5540#define mmSPI_PERFCOUNTER3_HI_BASE_IDX 1 5541#define mmSPI_PERFCOUNTER3_LO 0x3187 5542#define mmSPI_PERFCOUNTER3_LO_BASE_IDX 1 5543#define mmSPI_PERFCOUNTER4_HI 0x3188 5544#define mmSPI_PERFCOUNTER4_HI_BASE_IDX 1 5545#define mmSPI_PERFCOUNTER4_LO 0x3189 5546#define mmSPI_PERFCOUNTER4_LO_BASE_IDX 1 5547#define mmSPI_PERFCOUNTER5_HI 0x318a 5548#define mmSPI_PERFCOUNTER5_HI_BASE_IDX 1 5549#define mmSPI_PERFCOUNTER5_LO 0x318b 5550#define mmSPI_PERFCOUNTER5_LO_BASE_IDX 1 5551#define mmSQ_PERFCOUNTER0_LO 0x31c0 5552#define mmSQ_PERFCOUNTER0_LO_BASE_IDX 1 5553#define mmSQ_PERFCOUNTER0_HI 0x31c1 5554#define mmSQ_PERFCOUNTER0_HI_BASE_IDX 1 5555#define mmSQ_PERFCOUNTER1_LO 0x31c2 5556#define mmSQ_PERFCOUNTER1_LO_BASE_IDX 1 5557#define mmSQ_PERFCOUNTER1_HI 0x31c3 5558#define mmSQ_PERFCOUNTER1_HI_BASE_IDX 1 5559#define mmSQ_PERFCOUNTER2_LO 0x31c4 5560#define mmSQ_PERFCOUNTER2_LO_BASE_IDX 1 5561#define mmSQ_PERFCOUNTER2_HI 0x31c5 5562#define mmSQ_PERFCOUNTER2_HI_BASE_IDX 1 5563#define mmSQ_PERFCOUNTER3_LO 0x31c6 5564#define mmSQ_PERFCOUNTER3_LO_BASE_IDX 1 5565#define mmSQ_PERFCOUNTER3_HI 0x31c7 5566#define mmSQ_PERFCOUNTER3_HI_BASE_IDX 1 5567#define mmSQ_PERFCOUNTER4_LO 0x31c8 5568#define mmSQ_PERFCOUNTER4_LO_BASE_IDX 1 5569#define mmSQ_PERFCOUNTER4_HI 0x31c9 5570#define mmSQ_PERFCOUNTER4_HI_BASE_IDX 1 5571#define mmSQ_PERFCOUNTER5_LO 0x31ca 5572#define mmSQ_PERFCOUNTER5_LO_BASE_IDX 1 5573#define mmSQ_PERFCOUNTER5_HI 0x31cb 5574#define mmSQ_PERFCOUNTER5_HI_BASE_IDX 1 5575#define mmSQ_PERFCOUNTER6_LO 0x31cc 5576#define mmSQ_PERFCOUNTER6_LO_BASE_IDX 1 5577#define mmSQ_PERFCOUNTER6_HI 0x31cd 5578#define mmSQ_PERFCOUNTER6_HI_BASE_IDX 1 5579#define mmSQ_PERFCOUNTER7_LO 0x31ce 5580#define mmSQ_PERFCOUNTER7_LO_BASE_IDX 1 5581#define mmSQ_PERFCOUNTER7_HI 0x31cf 5582#define mmSQ_PERFCOUNTER7_HI_BASE_IDX 1 5583#define mmSQ_PERFCOUNTER8_LO 0x31d0 5584#define mmSQ_PERFCOUNTER8_LO_BASE_IDX 1 5585#define mmSQ_PERFCOUNTER8_HI 0x31d1 5586#define mmSQ_PERFCOUNTER8_HI_BASE_IDX 1 5587#define mmSQ_PERFCOUNTER9_LO 0x31d2 5588#define mmSQ_PERFCOUNTER9_LO_BASE_IDX 1 5589#define mmSQ_PERFCOUNTER9_HI 0x31d3 5590#define mmSQ_PERFCOUNTER9_HI_BASE_IDX 1 5591#define mmSQ_PERFCOUNTER10_LO 0x31d4 5592#define mmSQ_PERFCOUNTER10_LO_BASE_IDX 1 5593#define mmSQ_PERFCOUNTER10_HI 0x31d5 5594#define mmSQ_PERFCOUNTER10_HI_BASE_IDX 1 5595#define mmSQ_PERFCOUNTER11_LO 0x31d6 5596#define mmSQ_PERFCOUNTER11_LO_BASE_IDX 1 5597#define mmSQ_PERFCOUNTER11_HI 0x31d7 5598#define mmSQ_PERFCOUNTER11_HI_BASE_IDX 1 5599#define mmSQ_PERFCOUNTER12_LO 0x31d8 5600#define mmSQ_PERFCOUNTER12_LO_BASE_IDX 1 5601#define mmSQ_PERFCOUNTER12_HI 0x31d9 5602#define mmSQ_PERFCOUNTER12_HI_BASE_IDX 1 5603#define mmSQ_PERFCOUNTER13_LO 0x31da 5604#define mmSQ_PERFCOUNTER13_LO_BASE_IDX 1 5605#define mmSQ_PERFCOUNTER13_HI 0x31db 5606#define mmSQ_PERFCOUNTER13_HI_BASE_IDX 1 5607#define mmSQ_PERFCOUNTER14_LO 0x31dc 5608#define mmSQ_PERFCOUNTER14_LO_BASE_IDX 1 5609#define mmSQ_PERFCOUNTER14_HI 0x31dd 5610#define mmSQ_PERFCOUNTER14_HI_BASE_IDX 1 5611#define mmSQ_PERFCOUNTER15_LO 0x31de 5612#define mmSQ_PERFCOUNTER15_LO_BASE_IDX 1 5613#define mmSQ_PERFCOUNTER15_HI 0x31df 5614#define mmSQ_PERFCOUNTER15_HI_BASE_IDX 1 5615#define mmSX_PERFCOUNTER0_LO 0x3240 5616#define mmSX_PERFCOUNTER0_LO_BASE_IDX 1 5617#define mmSX_PERFCOUNTER0_HI 0x3241 5618#define mmSX_PERFCOUNTER0_HI_BASE_IDX 1 5619#define mmSX_PERFCOUNTER1_LO 0x3242 5620#define mmSX_PERFCOUNTER1_LO_BASE_IDX 1 5621#define mmSX_PERFCOUNTER1_HI 0x3243 5622#define mmSX_PERFCOUNTER1_HI_BASE_IDX 1 5623#define mmSX_PERFCOUNTER2_LO 0x3244 5624#define mmSX_PERFCOUNTER2_LO_BASE_IDX 1 5625#define mmSX_PERFCOUNTER2_HI 0x3245 5626#define mmSX_PERFCOUNTER2_HI_BASE_IDX 1 5627#define mmSX_PERFCOUNTER3_LO 0x3246 5628#define mmSX_PERFCOUNTER3_LO_BASE_IDX 1 5629#define mmSX_PERFCOUNTER3_HI 0x3247 5630#define mmSX_PERFCOUNTER3_HI_BASE_IDX 1 5631#define mmGDS_PERFCOUNTER0_LO 0x3280 5632#define mmGDS_PERFCOUNTER0_LO_BASE_IDX 1 5633#define mmGDS_PERFCOUNTER0_HI 0x3281 5634#define mmGDS_PERFCOUNTER0_HI_BASE_IDX 1 5635#define mmGDS_PERFCOUNTER1_LO 0x3282 5636#define mmGDS_PERFCOUNTER1_LO_BASE_IDX 1 5637#define mmGDS_PERFCOUNTER1_HI 0x3283 5638#define mmGDS_PERFCOUNTER1_HI_BASE_IDX 1 5639#define mmGDS_PERFCOUNTER2_LO 0x3284 5640#define mmGDS_PERFCOUNTER2_LO_BASE_IDX 1 5641#define mmGDS_PERFCOUNTER2_HI 0x3285 5642#define mmGDS_PERFCOUNTER2_HI_BASE_IDX 1 5643#define mmGDS_PERFCOUNTER3_LO 0x3286 5644#define mmGDS_PERFCOUNTER3_LO_BASE_IDX 1 5645#define mmGDS_PERFCOUNTER3_HI 0x3287 5646#define mmGDS_PERFCOUNTER3_HI_BASE_IDX 1 5647#define mmTA_PERFCOUNTER0_LO 0x32c0 5648#define mmTA_PERFCOUNTER0_LO_BASE_IDX 1 5649#define mmTA_PERFCOUNTER0_HI 0x32c1 5650#define mmTA_PERFCOUNTER0_HI_BASE_IDX 1 5651#define mmTA_PERFCOUNTER1_LO 0x32c2 5652#define mmTA_PERFCOUNTER1_LO_BASE_IDX 1 5653#define mmTA_PERFCOUNTER1_HI 0x32c3 5654#define mmTA_PERFCOUNTER1_HI_BASE_IDX 1 5655#define mmTD_PERFCOUNTER0_LO 0x3300 5656#define mmTD_PERFCOUNTER0_LO_BASE_IDX 1 5657#define mmTD_PERFCOUNTER0_HI 0x3301 5658#define mmTD_PERFCOUNTER0_HI_BASE_IDX 1 5659#define mmTD_PERFCOUNTER1_LO 0x3302 5660#define mmTD_PERFCOUNTER1_LO_BASE_IDX 1 5661#define mmTD_PERFCOUNTER1_HI 0x3303 5662#define mmTD_PERFCOUNTER1_HI_BASE_IDX 1 5663#define mmTCP_PERFCOUNTER0_LO 0x3340 5664#define mmTCP_PERFCOUNTER0_LO_BASE_IDX 1 5665#define mmTCP_PERFCOUNTER0_HI 0x3341 5666#define mmTCP_PERFCOUNTER0_HI_BASE_IDX 1 5667#define mmTCP_PERFCOUNTER1_LO 0x3342 5668#define mmTCP_PERFCOUNTER1_LO_BASE_IDX 1 5669#define mmTCP_PERFCOUNTER1_HI 0x3343 5670#define mmTCP_PERFCOUNTER1_HI_BASE_IDX 1 5671#define mmTCP_PERFCOUNTER2_LO 0x3344 5672#define mmTCP_PERFCOUNTER2_LO_BASE_IDX 1 5673#define mmTCP_PERFCOUNTER2_HI 0x3345 5674#define mmTCP_PERFCOUNTER2_HI_BASE_IDX 1 5675#define mmTCP_PERFCOUNTER3_LO 0x3346 5676#define mmTCP_PERFCOUNTER3_LO_BASE_IDX 1 5677#define mmTCP_PERFCOUNTER3_HI 0x3347 5678#define mmTCP_PERFCOUNTER3_HI_BASE_IDX 1 5679#define mmTCC_PERFCOUNTER0_LO 0x3380 5680#define mmTCC_PERFCOUNTER0_LO_BASE_IDX 1 5681#define mmTCC_PERFCOUNTER0_HI 0x3381 5682#define mmTCC_PERFCOUNTER0_HI_BASE_IDX 1 5683#define mmTCC_PERFCOUNTER1_LO 0x3382 5684#define mmTCC_PERFCOUNTER1_LO_BASE_IDX 1 5685#define mmTCC_PERFCOUNTER1_HI 0x3383 5686#define mmTCC_PERFCOUNTER1_HI_BASE_IDX 1 5687#define mmTCC_PERFCOUNTER2_LO 0x3384 5688#define mmTCC_PERFCOUNTER2_LO_BASE_IDX 1 5689#define mmTCC_PERFCOUNTER2_HI 0x3385 5690#define mmTCC_PERFCOUNTER2_HI_BASE_IDX 1 5691#define mmTCC_PERFCOUNTER3_LO 0x3386 5692#define mmTCC_PERFCOUNTER3_LO_BASE_IDX 1 5693#define mmTCC_PERFCOUNTER3_HI 0x3387 5694#define mmTCC_PERFCOUNTER3_HI_BASE_IDX 1 5695#define mmTCA_PERFCOUNTER0_LO 0x3390 5696#define mmTCA_PERFCOUNTER0_LO_BASE_IDX 1 5697#define mmTCA_PERFCOUNTER0_HI 0x3391 5698#define mmTCA_PERFCOUNTER0_HI_BASE_IDX 1 5699#define mmTCA_PERFCOUNTER1_LO 0x3392 5700#define mmTCA_PERFCOUNTER1_LO_BASE_IDX 1 5701#define mmTCA_PERFCOUNTER1_HI 0x3393 5702#define mmTCA_PERFCOUNTER1_HI_BASE_IDX 1 5703#define mmTCA_PERFCOUNTER2_LO 0x3394 5704#define mmTCA_PERFCOUNTER2_LO_BASE_IDX 1 5705#define mmTCA_PERFCOUNTER2_HI 0x3395 5706#define mmTCA_PERFCOUNTER2_HI_BASE_IDX 1 5707#define mmTCA_PERFCOUNTER3_LO 0x3396 5708#define mmTCA_PERFCOUNTER3_LO_BASE_IDX 1 5709#define mmTCA_PERFCOUNTER3_HI 0x3397 5710#define mmTCA_PERFCOUNTER3_HI_BASE_IDX 1 5711#define mmCB_PERFCOUNTER0_LO 0x3406 5712#define mmCB_PERFCOUNTER0_LO_BASE_IDX 1 5713#define mmCB_PERFCOUNTER0_HI 0x3407 5714#define mmCB_PERFCOUNTER0_HI_BASE_IDX 1 5715#define mmCB_PERFCOUNTER1_LO 0x3408 5716#define mmCB_PERFCOUNTER1_LO_BASE_IDX 1 5717#define mmCB_PERFCOUNTER1_HI 0x3409 5718#define mmCB_PERFCOUNTER1_HI_BASE_IDX 1 5719#define mmCB_PERFCOUNTER2_LO 0x340a 5720#define mmCB_PERFCOUNTER2_LO_BASE_IDX 1 5721#define mmCB_PERFCOUNTER2_HI 0x340b 5722#define mmCB_PERFCOUNTER2_HI_BASE_IDX 1 5723#define mmCB_PERFCOUNTER3_LO 0x340c 5724#define mmCB_PERFCOUNTER3_LO_BASE_IDX 1 5725#define mmCB_PERFCOUNTER3_HI 0x340d 5726#define mmCB_PERFCOUNTER3_HI_BASE_IDX 1 5727#define mmDB_PERFCOUNTER0_LO 0x3440 5728#define mmDB_PERFCOUNTER0_LO_BASE_IDX 1 5729#define mmDB_PERFCOUNTER0_HI 0x3441 5730#define mmDB_PERFCOUNTER0_HI_BASE_IDX 1 5731#define mmDB_PERFCOUNTER1_LO 0x3442 5732#define mmDB_PERFCOUNTER1_LO_BASE_IDX 1 5733#define mmDB_PERFCOUNTER1_HI 0x3443 5734#define mmDB_PERFCOUNTER1_HI_BASE_IDX 1 5735#define mmDB_PERFCOUNTER2_LO 0x3444 5736#define mmDB_PERFCOUNTER2_LO_BASE_IDX 1 5737#define mmDB_PERFCOUNTER2_HI 0x3445 5738#define mmDB_PERFCOUNTER2_HI_BASE_IDX 1 5739#define mmDB_PERFCOUNTER3_LO 0x3446 5740#define mmDB_PERFCOUNTER3_LO_BASE_IDX 1 5741#define mmDB_PERFCOUNTER3_HI 0x3447 5742#define mmDB_PERFCOUNTER3_HI_BASE_IDX 1 5743#define mmRLC_PERFCOUNTER0_LO 0x3480 5744#define mmRLC_PERFCOUNTER0_LO_BASE_IDX 1 5745#define mmRLC_PERFCOUNTER0_HI 0x3481 5746#define mmRLC_PERFCOUNTER0_HI_BASE_IDX 1 5747#define mmRLC_PERFCOUNTER1_LO 0x3482 5748#define mmRLC_PERFCOUNTER1_LO_BASE_IDX 1 5749#define mmRLC_PERFCOUNTER1_HI 0x3483 5750#define mmRLC_PERFCOUNTER1_HI_BASE_IDX 1 5751#define mmRMI_PERFCOUNTER0_LO 0x34c0 5752#define mmRMI_PERFCOUNTER0_LO_BASE_IDX 1 5753#define mmRMI_PERFCOUNTER0_HI 0x34c1 5754#define mmRMI_PERFCOUNTER0_HI_BASE_IDX 1 5755#define mmRMI_PERFCOUNTER1_LO 0x34c2 5756#define mmRMI_PERFCOUNTER1_LO_BASE_IDX 1 5757#define mmRMI_PERFCOUNTER1_HI 0x34c3 5758#define mmRMI_PERFCOUNTER1_HI_BASE_IDX 1 5759#define mmRMI_PERFCOUNTER2_LO 0x34c4 5760#define mmRMI_PERFCOUNTER2_LO_BASE_IDX 1 5761#define mmRMI_PERFCOUNTER2_HI 0x34c5 5762#define mmRMI_PERFCOUNTER2_HI_BASE_IDX 1 5763#define mmRMI_PERFCOUNTER3_LO 0x34c6 5764#define mmRMI_PERFCOUNTER3_LO_BASE_IDX 1 5765#define mmRMI_PERFCOUNTER3_HI 0x34c7 5766#define mmRMI_PERFCOUNTER3_HI_BASE_IDX 1 5767 5768 5769// addressBlock: gc_utcl2_atcl2pfcntrdec 5770// base address: 0x35400 5771#define mmATC_L2_PERFCOUNTER_LO 0x3500 5772#define mmATC_L2_PERFCOUNTER_LO_BASE_IDX 1 5773#define mmATC_L2_PERFCOUNTER_HI 0x3501 5774#define mmATC_L2_PERFCOUNTER_HI_BASE_IDX 1 5775 5776 5777// addressBlock: gc_utcl2_vml2prdec 5778// base address: 0x35420 5779#define mmMC_VM_L2_PERFCOUNTER_LO 0x3508 5780#define mmMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 5781#define mmMC_VM_L2_PERFCOUNTER_HI 0x3509 5782#define mmMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 5783 5784 5785// addressBlock: gc_perfsdec 5786// base address: 0x36000 5787#define mmCPG_PERFCOUNTER1_SELECT 0x3800 5788#define mmCPG_PERFCOUNTER1_SELECT_BASE_IDX 1 5789#define mmCPG_PERFCOUNTER0_SELECT1 0x3801 5790#define mmCPG_PERFCOUNTER0_SELECT1_BASE_IDX 1 5791#define mmCPG_PERFCOUNTER0_SELECT 0x3802 5792#define mmCPG_PERFCOUNTER0_SELECT_BASE_IDX 1 5793#define mmCPC_PERFCOUNTER1_SELECT 0x3803 5794#define mmCPC_PERFCOUNTER1_SELECT_BASE_IDX 1 5795#define mmCPC_PERFCOUNTER0_SELECT1 0x3804 5796#define mmCPC_PERFCOUNTER0_SELECT1_BASE_IDX 1 5797#define mmCPF_PERFCOUNTER1_SELECT 0x3805 5798#define mmCPF_PERFCOUNTER1_SELECT_BASE_IDX 1 5799#define mmCPF_PERFCOUNTER0_SELECT1 0x3806 5800#define mmCPF_PERFCOUNTER0_SELECT1_BASE_IDX 1 5801#define mmCPF_PERFCOUNTER0_SELECT 0x3807 5802#define mmCPF_PERFCOUNTER0_SELECT_BASE_IDX 1 5803#define mmCP_PERFMON_CNTL 0x3808 5804#define mmCP_PERFMON_CNTL_BASE_IDX 1 5805#define mmCPC_PERFCOUNTER0_SELECT 0x3809 5806#define mmCPC_PERFCOUNTER0_SELECT_BASE_IDX 1 5807#define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT 0x380a 5808#define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 5809#define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT 0x380b 5810#define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 5811#define mmCPF_LATENCY_STATS_SELECT 0x380c 5812#define mmCPF_LATENCY_STATS_SELECT_BASE_IDX 1 5813#define mmCPG_LATENCY_STATS_SELECT 0x380d 5814#define mmCPG_LATENCY_STATS_SELECT_BASE_IDX 1 5815#define mmCPC_LATENCY_STATS_SELECT 0x380e 5816#define mmCPC_LATENCY_STATS_SELECT_BASE_IDX 1 5817#define mmCP_DRAW_OBJECT 0x3810 5818#define mmCP_DRAW_OBJECT_BASE_IDX 1 5819#define mmCP_DRAW_OBJECT_COUNTER 0x3811 5820#define mmCP_DRAW_OBJECT_COUNTER_BASE_IDX 1 5821#define mmCP_DRAW_WINDOW_MASK_HI 0x3812 5822#define mmCP_DRAW_WINDOW_MASK_HI_BASE_IDX 1 5823#define mmCP_DRAW_WINDOW_HI 0x3813 5824#define mmCP_DRAW_WINDOW_HI_BASE_IDX 1 5825#define mmCP_DRAW_WINDOW_LO 0x3814 5826#define mmCP_DRAW_WINDOW_LO_BASE_IDX 1 5827#define mmCP_DRAW_WINDOW_CNTL 0x3815 5828#define mmCP_DRAW_WINDOW_CNTL_BASE_IDX 1 5829#define mmGRBM_PERFCOUNTER0_SELECT 0x3840 5830#define mmGRBM_PERFCOUNTER0_SELECT_BASE_IDX 1 5831#define mmGRBM_PERFCOUNTER1_SELECT 0x3841 5832#define mmGRBM_PERFCOUNTER1_SELECT_BASE_IDX 1 5833#define mmGRBM_SE0_PERFCOUNTER_SELECT 0x3842 5834#define mmGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX 1 5835#define mmGRBM_SE1_PERFCOUNTER_SELECT 0x3843 5836#define mmGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX 1 5837#define mmGRBM_SE2_PERFCOUNTER_SELECT 0x3844 5838#define mmGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX 1 5839#define mmGRBM_SE3_PERFCOUNTER_SELECT 0x3845 5840#define mmGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX 1 5841#define mmWD_PERFCOUNTER0_SELECT 0x3880 5842#define mmWD_PERFCOUNTER0_SELECT_BASE_IDX 1 5843#define mmWD_PERFCOUNTER1_SELECT 0x3881 5844#define mmWD_PERFCOUNTER1_SELECT_BASE_IDX 1 5845#define mmWD_PERFCOUNTER2_SELECT 0x3882 5846#define mmWD_PERFCOUNTER2_SELECT_BASE_IDX 1 5847#define mmWD_PERFCOUNTER3_SELECT 0x3883 5848#define mmWD_PERFCOUNTER3_SELECT_BASE_IDX 1 5849#define mmIA_PERFCOUNTER0_SELECT 0x3884 5850#define mmIA_PERFCOUNTER0_SELECT_BASE_IDX 1 5851#define mmIA_PERFCOUNTER1_SELECT 0x3885 5852#define mmIA_PERFCOUNTER1_SELECT_BASE_IDX 1 5853#define mmIA_PERFCOUNTER2_SELECT 0x3886 5854#define mmIA_PERFCOUNTER2_SELECT_BASE_IDX 1 5855#define mmIA_PERFCOUNTER3_SELECT 0x3887 5856#define mmIA_PERFCOUNTER3_SELECT_BASE_IDX 1 5857#define mmIA_PERFCOUNTER0_SELECT1 0x3888 5858#define mmIA_PERFCOUNTER0_SELECT1_BASE_IDX 1 5859#define mmVGT_PERFCOUNTER0_SELECT 0x388c 5860#define mmVGT_PERFCOUNTER0_SELECT_BASE_IDX 1 5861#define mmVGT_PERFCOUNTER1_SELECT 0x388d 5862#define mmVGT_PERFCOUNTER1_SELECT_BASE_IDX 1 5863#define mmVGT_PERFCOUNTER2_SELECT 0x388e 5864#define mmVGT_PERFCOUNTER2_SELECT_BASE_IDX 1 5865#define mmVGT_PERFCOUNTER3_SELECT 0x388f 5866#define mmVGT_PERFCOUNTER3_SELECT_BASE_IDX 1 5867#define mmVGT_PERFCOUNTER0_SELECT1 0x3890 5868#define mmVGT_PERFCOUNTER0_SELECT1_BASE_IDX 1 5869#define mmVGT_PERFCOUNTER1_SELECT1 0x3891 5870#define mmVGT_PERFCOUNTER1_SELECT1_BASE_IDX 1 5871#define mmVGT_PERFCOUNTER_SEID_MASK 0x3894 5872#define mmVGT_PERFCOUNTER_SEID_MASK_BASE_IDX 1 5873#define mmPA_SU_PERFCOUNTER0_SELECT 0x3900 5874#define mmPA_SU_PERFCOUNTER0_SELECT_BASE_IDX 1 5875#define mmPA_SU_PERFCOUNTER0_SELECT1 0x3901 5876#define mmPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX 1 5877#define mmPA_SU_PERFCOUNTER1_SELECT 0x3902 5878#define mmPA_SU_PERFCOUNTER1_SELECT_BASE_IDX 1 5879#define mmPA_SU_PERFCOUNTER1_SELECT1 0x3903 5880#define mmPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX 1 5881#define mmPA_SU_PERFCOUNTER2_SELECT 0x3904 5882#define mmPA_SU_PERFCOUNTER2_SELECT_BASE_IDX 1 5883#define mmPA_SU_PERFCOUNTER3_SELECT 0x3905 5884#define mmPA_SU_PERFCOUNTER3_SELECT_BASE_IDX 1 5885#define mmPA_SC_PERFCOUNTER0_SELECT 0x3940 5886#define mmPA_SC_PERFCOUNTER0_SELECT_BASE_IDX 1 5887#define mmPA_SC_PERFCOUNTER0_SELECT1 0x3941 5888#define mmPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX 1 5889#define mmPA_SC_PERFCOUNTER1_SELECT 0x3942 5890#define mmPA_SC_PERFCOUNTER1_SELECT_BASE_IDX 1 5891#define mmPA_SC_PERFCOUNTER2_SELECT 0x3943 5892#define mmPA_SC_PERFCOUNTER2_SELECT_BASE_IDX 1 5893#define mmPA_SC_PERFCOUNTER3_SELECT 0x3944 5894#define mmPA_SC_PERFCOUNTER3_SELECT_BASE_IDX 1 5895#define mmPA_SC_PERFCOUNTER4_SELECT 0x3945 5896#define mmPA_SC_PERFCOUNTER4_SELECT_BASE_IDX 1 5897#define mmPA_SC_PERFCOUNTER5_SELECT 0x3946 5898#define mmPA_SC_PERFCOUNTER5_SELECT_BASE_IDX 1 5899#define mmPA_SC_PERFCOUNTER6_SELECT 0x3947 5900#define mmPA_SC_PERFCOUNTER6_SELECT_BASE_IDX 1 5901#define mmPA_SC_PERFCOUNTER7_SELECT 0x3948 5902#define mmPA_SC_PERFCOUNTER7_SELECT_BASE_IDX 1 5903#define mmSPI_PERFCOUNTER0_SELECT 0x3980 5904#define mmSPI_PERFCOUNTER0_SELECT_BASE_IDX 1 5905#define mmSPI_PERFCOUNTER1_SELECT 0x3981 5906#define mmSPI_PERFCOUNTER1_SELECT_BASE_IDX 1 5907#define mmSPI_PERFCOUNTER2_SELECT 0x3982 5908#define mmSPI_PERFCOUNTER2_SELECT_BASE_IDX 1 5909#define mmSPI_PERFCOUNTER3_SELECT 0x3983 5910#define mmSPI_PERFCOUNTER3_SELECT_BASE_IDX 1 5911#define mmSPI_PERFCOUNTER0_SELECT1 0x3984 5912#define mmSPI_PERFCOUNTER0_SELECT1_BASE_IDX 1 5913#define mmSPI_PERFCOUNTER1_SELECT1 0x3985 5914#define mmSPI_PERFCOUNTER1_SELECT1_BASE_IDX 1 5915#define mmSPI_PERFCOUNTER2_SELECT1 0x3986 5916#define mmSPI_PERFCOUNTER2_SELECT1_BASE_IDX 1 5917#define mmSPI_PERFCOUNTER3_SELECT1 0x3987 5918#define mmSPI_PERFCOUNTER3_SELECT1_BASE_IDX 1 5919#define mmSPI_PERFCOUNTER4_SELECT 0x3988 5920#define mmSPI_PERFCOUNTER4_SELECT_BASE_IDX 1 5921#define mmSPI_PERFCOUNTER5_SELECT 0x3989 5922#define mmSPI_PERFCOUNTER5_SELECT_BASE_IDX 1 5923#define mmSPI_PERFCOUNTER_BINS 0x398a 5924#define mmSPI_PERFCOUNTER_BINS_BASE_IDX 1 5925#define mmSQ_PERFCOUNTER0_SELECT 0x39c0 5926#define mmSQ_PERFCOUNTER0_SELECT_BASE_IDX 1 5927#define mmSQ_PERFCOUNTER1_SELECT 0x39c1 5928#define mmSQ_PERFCOUNTER1_SELECT_BASE_IDX 1 5929#define mmSQ_PERFCOUNTER2_SELECT 0x39c2 5930#define mmSQ_PERFCOUNTER2_SELECT_BASE_IDX 1 5931#define mmSQ_PERFCOUNTER3_SELECT 0x39c3 5932#define mmSQ_PERFCOUNTER3_SELECT_BASE_IDX 1 5933#define mmSQ_PERFCOUNTER4_SELECT 0x39c4 5934#define mmSQ_PERFCOUNTER4_SELECT_BASE_IDX 1 5935#define mmSQ_PERFCOUNTER5_SELECT 0x39c5 5936#define mmSQ_PERFCOUNTER5_SELECT_BASE_IDX 1 5937#define mmSQ_PERFCOUNTER6_SELECT 0x39c6 5938#define mmSQ_PERFCOUNTER6_SELECT_BASE_IDX 1 5939#define mmSQ_PERFCOUNTER7_SELECT 0x39c7 5940#define mmSQ_PERFCOUNTER7_SELECT_BASE_IDX 1 5941#define mmSQ_PERFCOUNTER8_SELECT 0x39c8 5942#define mmSQ_PERFCOUNTER8_SELECT_BASE_IDX 1 5943#define mmSQ_PERFCOUNTER9_SELECT 0x39c9 5944#define mmSQ_PERFCOUNTER9_SELECT_BASE_IDX 1 5945#define mmSQ_PERFCOUNTER10_SELECT 0x39ca 5946#define mmSQ_PERFCOUNTER10_SELECT_BASE_IDX 1 5947#define mmSQ_PERFCOUNTER11_SELECT 0x39cb 5948#define mmSQ_PERFCOUNTER11_SELECT_BASE_IDX 1 5949#define mmSQ_PERFCOUNTER12_SELECT 0x39cc 5950#define mmSQ_PERFCOUNTER12_SELECT_BASE_IDX 1 5951#define mmSQ_PERFCOUNTER13_SELECT 0x39cd 5952#define mmSQ_PERFCOUNTER13_SELECT_BASE_IDX 1 5953#define mmSQ_PERFCOUNTER14_SELECT 0x39ce 5954#define mmSQ_PERFCOUNTER14_SELECT_BASE_IDX 1 5955#define mmSQ_PERFCOUNTER15_SELECT 0x39cf 5956#define mmSQ_PERFCOUNTER15_SELECT_BASE_IDX 1 5957#define mmSQ_PERFCOUNTER_CTRL 0x39e0 5958#define mmSQ_PERFCOUNTER_CTRL_BASE_IDX 1 5959#define mmSQ_PERFCOUNTER_MASK 0x39e1 5960#define mmSQ_PERFCOUNTER_MASK_BASE_IDX 1 5961#define mmSQ_PERFCOUNTER_CTRL2 0x39e2 5962#define mmSQ_PERFCOUNTER_CTRL2_BASE_IDX 1 5963#define mmSX_PERFCOUNTER0_SELECT 0x3a40 5964#define mmSX_PERFCOUNTER0_SELECT_BASE_IDX 1 5965#define mmSX_PERFCOUNTER1_SELECT 0x3a41 5966#define mmSX_PERFCOUNTER1_SELECT_BASE_IDX 1 5967#define mmSX_PERFCOUNTER2_SELECT 0x3a42 5968#define mmSX_PERFCOUNTER2_SELECT_BASE_IDX 1 5969#define mmSX_PERFCOUNTER3_SELECT 0x3a43 5970#define mmSX_PERFCOUNTER3_SELECT_BASE_IDX 1 5971#define mmSX_PERFCOUNTER0_SELECT1 0x3a44 5972#define mmSX_PERFCOUNTER0_SELECT1_BASE_IDX 1 5973#define mmSX_PERFCOUNTER1_SELECT1 0x3a45 5974#define mmSX_PERFCOUNTER1_SELECT1_BASE_IDX 1 5975#define mmGDS_PERFCOUNTER0_SELECT 0x3a80 5976#define mmGDS_PERFCOUNTER0_SELECT_BASE_IDX 1 5977#define mmGDS_PERFCOUNTER1_SELECT 0x3a81 5978#define mmGDS_PERFCOUNTER1_SELECT_BASE_IDX 1 5979#define mmGDS_PERFCOUNTER2_SELECT 0x3a82 5980#define mmGDS_PERFCOUNTER2_SELECT_BASE_IDX 1 5981#define mmGDS_PERFCOUNTER3_SELECT 0x3a83 5982#define mmGDS_PERFCOUNTER3_SELECT_BASE_IDX 1 5983#define mmGDS_PERFCOUNTER0_SELECT1 0x3a84 5984#define mmGDS_PERFCOUNTER0_SELECT1_BASE_IDX 1 5985#define mmTA_PERFCOUNTER0_SELECT 0x3ac0 5986#define mmTA_PERFCOUNTER0_SELECT_BASE_IDX 1 5987#define mmTA_PERFCOUNTER0_SELECT1 0x3ac1 5988#define mmTA_PERFCOUNTER0_SELECT1_BASE_IDX 1 5989#define mmTA_PERFCOUNTER1_SELECT 0x3ac2 5990#define mmTA_PERFCOUNTER1_SELECT_BASE_IDX 1 5991#define mmTD_PERFCOUNTER0_SELECT 0x3b00 5992#define mmTD_PERFCOUNTER0_SELECT_BASE_IDX 1 5993#define mmTD_PERFCOUNTER0_SELECT1 0x3b01 5994#define mmTD_PERFCOUNTER0_SELECT1_BASE_IDX 1 5995#define mmTD_PERFCOUNTER1_SELECT 0x3b02 5996#define mmTD_PERFCOUNTER1_SELECT_BASE_IDX 1 5997#define mmTCP_PERFCOUNTER0_SELECT 0x3b40 5998#define mmTCP_PERFCOUNTER0_SELECT_BASE_IDX 1 5999#define mmTCP_PERFCOUNTER0_SELECT1 0x3b41 6000#define mmTCP_PERFCOUNTER0_SELECT1_BASE_IDX 1
6001#define mmTCP_PERFCOUNTER1_SELECT 0x3b42 6002#define mmTCP_PERFCOUNTER1_SELECT_BASE_IDX 1 6003#define mmTCP_PERFCOUNTER1_SELECT1 0x3b43 6004#define mmTCP_PERFCOUNTER1_SELECT1_BASE_IDX 1 6005#define mmTCP_PERFCOUNTER2_SELECT 0x3b44 6006#define mmTCP_PERFCOUNTER2_SELECT_BASE_IDX 1 6007#define mmTCP_PERFCOUNTER3_SELECT 0x3b45 6008#define mmTCP_PERFCOUNTER3_SELECT_BASE_IDX 1 6009#define mmTCC_PERFCOUNTER0_SELECT 0x3b80 6010#define mmTCC_PERFCOUNTER0_SELECT_BASE_IDX 1 6011#define mmTCC_PERFCOUNTER0_SELECT1 0x3b81 6012#define mmTCC_PERFCOUNTER0_SELECT1_BASE_IDX 1 6013#define mmTCC_PERFCOUNTER1_SELECT 0x3b82 6014#define mmTCC_PERFCOUNTER1_SELECT_BASE_IDX 1 6015#define mmTCC_PERFCOUNTER1_SELECT1 0x3b83 6016#define mmTCC_PERFCOUNTER1_SELECT1_BASE_IDX 1 6017#define mmTCC_PERFCOUNTER2_SELECT 0x3b84 6018#define mmTCC_PERFCOUNTER2_SELECT_BASE_IDX 1 6019#define mmTCC_PERFCOUNTER3_SELECT 0x3b85 6020#define mmTCC_PERFCOUNTER3_SELECT_BASE_IDX 1 6021#define mmTCA_PERFCOUNTER0_SELECT 0x3b90 6022#define mmTCA_PERFCOUNTER0_SELECT_BASE_IDX 1 6023#define mmTCA_PERFCOUNTER0_SELECT1 0x3b91 6024#define mmTCA_PERFCOUNTER0_SELECT1_BASE_IDX 1 6025#define mmTCA_PERFCOUNTER1_SELECT 0x3b92 6026#define mmTCA_PERFCOUNTER1_SELECT_BASE_IDX 1 6027#define mmTCA_PERFCOUNTER1_SELECT1 0x3b93 6028#define mmTCA_PERFCOUNTER1_SELECT1_BASE_IDX 1 6029#define mmTCA_PERFCOUNTER2_SELECT 0x3b94 6030#define mmTCA_PERFCOUNTER2_SELECT_BASE_IDX 1 6031#define mmTCA_PERFCOUNTER3_SELECT 0x3b95 6032#define mmTCA_PERFCOUNTER3_SELECT_BASE_IDX 1 6033#define mmCB_PERFCOUNTER_FILTER 0x3c00 6034#define mmCB_PERFCOUNTER_FILTER_BASE_IDX 1 6035#define mmCB_PERFCOUNTER0_SELECT 0x3c01 6036#define mmCB_PERFCOUNTER0_SELECT_BASE_IDX 1 6037#define mmCB_PERFCOUNTER0_SELECT1 0x3c02 6038#define mmCB_PERFCOUNTER0_SELECT1_BASE_IDX 1 6039#define mmCB_PERFCOUNTER1_SELECT 0x3c03 6040#define mmCB_PERFCOUNTER1_SELECT_BASE_IDX 1 6041#define mmCB_PERFCOUNTER2_SELECT 0x3c04 6042#define mmCB_PERFCOUNTER2_SELECT_BASE_IDX 1 6043#define mmCB_PERFCOUNTER3_SELECT 0x3c05 6044#define mmCB_PERFCOUNTER3_SELECT_BASE_IDX 1 6045#define mmDB_PERFCOUNTER0_SELECT 0x3c40 6046#define mmDB_PERFCOUNTER0_SELECT_BASE_IDX 1 6047#define mmDB_PERFCOUNTER0_SELECT1 0x3c41 6048#define mmDB_PERFCOUNTER0_SELECT1_BASE_IDX 1 6049#define mmDB_PERFCOUNTER1_SELECT 0x3c42 6050#define mmDB_PERFCOUNTER1_SELECT_BASE_IDX 1 6051#define mmDB_PERFCOUNTER1_SELECT1 0x3c43 6052#define mmDB_PERFCOUNTER1_SELECT1_BASE_IDX 1 6053#define mmDB_PERFCOUNTER2_SELECT 0x3c44 6054#define mmDB_PERFCOUNTER2_SELECT_BASE_IDX 1 6055#define mmDB_PERFCOUNTER3_SELECT 0x3c46 6056#define mmDB_PERFCOUNTER3_SELECT_BASE_IDX 1 6057#define mmRLC_SPM_PERFMON_CNTL 0x3c80 6058#define mmRLC_SPM_PERFMON_CNTL_BASE_IDX 1 6059#define mmRLC_SPM_PERFMON_RING_BASE_LO 0x3c81 6060#define mmRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX 1 6061#define mmRLC_SPM_PERFMON_RING_BASE_HI 0x3c82 6062#define mmRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX 1 6063#define mmRLC_SPM_PERFMON_RING_SIZE 0x3c83 6064#define mmRLC_SPM_PERFMON_RING_SIZE_BASE_IDX 1 6065#define mmRLC_SPM_PERFMON_SEGMENT_SIZE 0x3c84 6066#define mmRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX 1 6067#define mmRLC_SPM_SE_MUXSEL_ADDR 0x3c85 6068#define mmRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX 1 6069#define mmRLC_SPM_SE_MUXSEL_DATA 0x3c86 6070#define mmRLC_SPM_SE_MUXSEL_DATA_BASE_IDX 1 6071#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0x3c87 6072#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6073#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0x3c88 6074#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6075#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0x3c89 6076#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6077#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0x3c8a 6078#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6079#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0x3c8b 6080#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6081#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0x3c8c 6082#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6083#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0x3c8d 6084#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6085#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0x3c8e 6086#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6087#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0x3c90 6088#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6089#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0x3c91 6090#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6091#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0x3c92 6092#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6093#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0x3c93 6094#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6095#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0x3c94 6096#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6097#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0x3c95 6098#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6099#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0x3c96 6100#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6101#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0x3c97 6102#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6103#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0x3c98 6104#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6105#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0x3c9a 6106#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6107#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR 0x3c9b 6108#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX 1 6109#define mmRLC_SPM_GLOBAL_MUXSEL_DATA 0x3c9c 6110#define mmRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX 1 6111#define mmRLC_SPM_RING_RDPTR 0x3c9d 6112#define mmRLC_SPM_RING_RDPTR_BASE_IDX 1 6113#define mmRLC_SPM_SEGMENT_THRESHOLD 0x3c9e 6114#define mmRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX 1 6115#define mmRLC_SPM_RMI_PERFMON_SAMPLE_DELAY 0x3ca3 6116#define mmRLC_SPM_RMI_PERFMON_SAMPLE_DELAY_BASE_IDX 1 6117#define mmRLC_PERFMON_CLK_CNTL 0x3cbf 6118#define mmRLC_PERFMON_CLK_CNTL_BASE_IDX 1 6119#define mmRLC_PERFMON_CNTL 0x3cc0 6120#define mmRLC_PERFMON_CNTL_BASE_IDX 1 6121#define mmRLC_PERFCOUNTER0_SELECT 0x3cc1 6122#define mmRLC_PERFCOUNTER0_SELECT_BASE_IDX 1 6123#define mmRLC_PERFCOUNTER1_SELECT 0x3cc2 6124#define mmRLC_PERFCOUNTER1_SELECT_BASE_IDX 1 6125#define mmRLC_GPU_IOV_PERF_CNT_CNTL 0x3cc3 6126#define mmRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX 1 6127#define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR 0x3cc4 6128#define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX 1 6129#define mmRLC_GPU_IOV_PERF_CNT_WR_DATA 0x3cc5 6130#define mmRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX 1 6131#define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR 0x3cc6 6132#define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX 1 6133#define mmRLC_GPU_IOV_PERF_CNT_RD_DATA 0x3cc7 6134#define mmRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX 1 6135#define mmRMI_PERFCOUNTER0_SELECT 0x3d00 6136#define mmRMI_PERFCOUNTER0_SELECT_BASE_IDX 1 6137#define mmRMI_PERFCOUNTER0_SELECT1 0x3d01 6138#define mmRMI_PERFCOUNTER0_SELECT1_BASE_IDX 1 6139#define mmRMI_PERFCOUNTER1_SELECT 0x3d02 6140#define mmRMI_PERFCOUNTER1_SELECT_BASE_IDX 1 6141#define mmRMI_PERFCOUNTER2_SELECT 0x3d03 6142#define mmRMI_PERFCOUNTER2_SELECT_BASE_IDX 1 6143#define mmRMI_PERFCOUNTER2_SELECT1 0x3d04 6144#define mmRMI_PERFCOUNTER2_SELECT1_BASE_IDX 1 6145#define mmRMI_PERFCOUNTER3_SELECT 0x3d05 6146#define mmRMI_PERFCOUNTER3_SELECT_BASE_IDX 1 6147#define mmRMI_PERF_COUNTER_CNTL 0x3d06 6148#define mmRMI_PERF_COUNTER_CNTL_BASE_IDX 1 6149 6150 6151// addressBlock: gc_utcl2_atcl2pfcntldec 6152// base address: 0x37500 6153#define mmATC_L2_PERFCOUNTER0_CFG 0x3d40 6154#define mmATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1 6155#define mmATC_L2_PERFCOUNTER1_CFG 0x3d41 6156#define mmATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1 6157#define mmATC_L2_PERFCOUNTER_RSLT_CNTL 0x3d42 6158#define mmATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 6159 6160 6161// addressBlock: gc_utcl2_vml2pldec 6162// base address: 0x37530 6163#define mmMC_VM_L2_PERFCOUNTER0_CFG 0x3d4c 6164#define mmMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 6165#define mmMC_VM_L2_PERFCOUNTER1_CFG 0x3d4d 6166#define mmMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 6167#define mmMC_VM_L2_PERFCOUNTER2_CFG 0x3d4e 6168#define mmMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 6169#define mmMC_VM_L2_PERFCOUNTER3_CFG 0x3d4f 6170#define mmMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 6171#define mmMC_VM_L2_PERFCOUNTER4_CFG 0x3d50 6172#define mmMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 6173#define mmMC_VM_L2_PERFCOUNTER5_CFG 0x3d51 6174#define mmMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 6175#define mmMC_VM_L2_PERFCOUNTER6_CFG 0x3d52 6176#define mmMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 6177#define mmMC_VM_L2_PERFCOUNTER7_CFG 0x3d53 6178#define mmMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 6179#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x3d54 6180#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 6181 6182 6183// addressBlock: gc_rlcpdec 6184// base address: 0x3b000 6185#define mmRLC_CNTL 0x4c00 6186#define mmRLC_CNTL_BASE_IDX 1 6187#define mmRLC_STAT 0x4c04 6188#define mmRLC_STAT_BASE_IDX 1 6189#define mmRLC_SAFE_MODE 0x4c05 6190#define mmRLC_SAFE_MODE_BASE_IDX 1 6191#define mmRLC_MEM_SLP_CNTL 0x4c06 6192#define mmRLC_MEM_SLP_CNTL_BASE_IDX 1 6193#define mmSMU_RLC_RESPONSE 0x4c07 6194#define mmSMU_RLC_RESPONSE_BASE_IDX 1 6195#define mmRLC_RLCV_SAFE_MODE 0x4c08 6196#define mmRLC_RLCV_SAFE_MODE_BASE_IDX 1 6197#define mmRLC_SMU_SAFE_MODE 0x4c09 6198#define mmRLC_SMU_SAFE_MODE_BASE_IDX 1 6199#define mmRLC_RLCV_COMMAND 0x4c0a 6200#define mmRLC_RLCV_COMMAND_BASE_IDX 1 6201#define mmRLC_REFCLOCK_TIMESTAMP_LSB 0x4c0c 6202#define mmRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX 1 6203#define mmRLC_REFCLOCK_TIMESTAMP_MSB 0x4c0d 6204#define mmRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX 1 6205#define mmRLC_GPM_TIMER_INT_0 0x4c0e 6206#define mmRLC_GPM_TIMER_INT_0_BASE_IDX 1 6207#define mmRLC_GPM_TIMER_INT_1 0x4c0f 6208#define mmRLC_GPM_TIMER_INT_1_BASE_IDX 1 6209#define mmRLC_GPM_TIMER_INT_2 0x4c10 6210#define mmRLC_GPM_TIMER_INT_2_BASE_IDX 1 6211#define mmRLC_GPM_TIMER_CTRL 0x4c11 6212#define mmRLC_GPM_TIMER_CTRL_BASE_IDX 1 6213#define mmRLC_LB_CNTR_MAX 0x4c12 6214#define mmRLC_LB_CNTR_MAX_BASE_IDX 1 6215#define mmRLC_GPM_TIMER_STAT 0x4c13 6216#define mmRLC_GPM_TIMER_STAT_BASE_IDX 1 6217#define mmRLC_GPM_TIMER_INT_3 0x4c15 6218#define mmRLC_GPM_TIMER_INT_3_BASE_IDX 1 6219#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_1 0x4c16 6220#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_1_BASE_IDX 1 6221#define mmRLC_SERDES_NONCU_MASTER_BUSY_1 0x4c17 6222#define mmRLC_SERDES_NONCU_MASTER_BUSY_1_BASE_IDX 1 6223#define mmRLC_INT_STAT 0x4c18 6224#define mmRLC_INT_STAT_BASE_IDX 1 6225#define mmRLC_LB_CNTL 0x4c19 6226#define mmRLC_LB_CNTL_BASE_IDX 1 6227#define mmRLC_MGCG_CTRL 0x4c1a 6228#define mmRLC_MGCG_CTRL_BASE_IDX 1 6229#define mmRLC_LB_CNTR_INIT 0x4c1b 6230#define mmRLC_LB_CNTR_INIT_BASE_IDX 1 6231#define mmRLC_LOAD_BALANCE_CNTR 0x4c1c 6232#define mmRLC_LOAD_BALANCE_CNTR_BASE_IDX 1 6233#define mmRLC_JUMP_TABLE_RESTORE 0x4c1e 6234#define mmRLC_JUMP_TABLE_RESTORE_BASE_IDX 1 6235#define mmRLC_PG_DELAY_2 0x4c1f 6236#define mmRLC_PG_DELAY_2_BASE_IDX 1 6237#define mmRLC_GPU_CLOCK_COUNT_LSB 0x4c24 6238#define mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1 6239#define mmRLC_GPU_CLOCK_COUNT_MSB 0x4c25 6240#define mmRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX 1 6241#define mmRLC_CAPTURE_GPU_CLOCK_COUNT 0x4c26 6242#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX 1 6243#define mmRLC_UCODE_CNTL 0x4c27 6244#define mmRLC_UCODE_CNTL_BASE_IDX 1 6245#define mmRLC_GPM_THREAD_RESET 0x4c28 6246#define mmRLC_GPM_THREAD_RESET_BASE_IDX 1 6247#define mmRLC_GPM_CP_DMA_COMPLETE_T0 0x4c29 6248#define mmRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX 1 6249#define mmRLC_GPM_CP_DMA_COMPLETE_T1 0x4c2a 6250#define mmRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX 1 6251#define mmRLC_FIREWALL_VIOLATION 0x4c2b 6252#define mmRLC_FIREWALL_VIOLATION_BASE_IDX 1 6253#define mmRLC_GPM_STAT 0x4c40 6254#define mmRLC_GPM_STAT_BASE_IDX 1 6255#define mmRLC_GPU_CLOCK_32_RES_SEL 0x4c41 6256#define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX 1 6257#define mmRLC_GPU_CLOCK_32 0x4c42 6258#define mmRLC_GPU_CLOCK_32_BASE_IDX 1 6259#define mmRLC_PG_CNTL 0x4c43 6260#define mmRLC_PG_CNTL_BASE_IDX 1 6261#define mmRLC_GPM_THREAD_PRIORITY 0x4c44 6262#define mmRLC_GPM_THREAD_PRIORITY_BASE_IDX 1 6263#define mmRLC_GPM_THREAD_ENABLE 0x4c45 6264#define mmRLC_GPM_THREAD_ENABLE_BASE_IDX 1 6265#define mmRLC_CGTT_MGCG_OVERRIDE 0x4c48 6266#define mmRLC_CGTT_MGCG_OVERRIDE_BASE_IDX 1 6267#define mmRLC_CGCG_CGLS_CTRL 0x4c49 6268#define mmRLC_CGCG_CGLS_CTRL_BASE_IDX 1 6269#define mmRLC_CGCG_RAMP_CTRL 0x4c4a 6270#define mmRLC_CGCG_RAMP_CTRL_BASE_IDX 1 6271#define mmRLC_DYN_PG_STATUS 0x4c4b 6272#define mmRLC_DYN_PG_STATUS_BASE_IDX 1 6273#define mmRLC_DYN_PG_REQUEST 0x4c4c 6274#define mmRLC_DYN_PG_REQUEST_BASE_IDX 1 6275#define mmRLC_PG_DELAY 0x4c4d 6276#define mmRLC_PG_DELAY_BASE_IDX 1 6277#define mmRLC_CU_STATUS 0x4c4e 6278#define mmRLC_CU_STATUS_BASE_IDX 1 6279#define mmRLC_LB_INIT_CU_MASK 0x4c4f 6280#define mmRLC_LB_INIT_CU_MASK_BASE_IDX 1 6281#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK 0x4c50 6282#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK_BASE_IDX 1 6283#define mmRLC_LB_PARAMS 0x4c51 6284#define mmRLC_LB_PARAMS_BASE_IDX 1 6285#define mmRLC_THREAD1_DELAY 0x4c52 6286#define mmRLC_THREAD1_DELAY_BASE_IDX 1 6287#define mmRLC_PG_ALWAYS_ON_CU_MASK 0x4c53 6288#define mmRLC_PG_ALWAYS_ON_CU_MASK_BASE_IDX 1 6289#define mmRLC_MAX_PG_CU 0x4c54 6290#define mmRLC_MAX_PG_CU_BASE_IDX 1 6291#define mmRLC_AUTO_PG_CTRL 0x4c55 6292#define mmRLC_AUTO_PG_CTRL_BASE_IDX 1 6293#define mmRLC_SMU_GRBM_REG_SAVE_CTRL 0x4c56 6294#define mmRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX 1 6295#define mmRLC_SERDES_RD_MASTER_INDEX 0x4c59 6296#define mmRLC_SERDES_RD_MASTER_INDEX_BASE_IDX 1 6297#define mmRLC_SERDES_RD_DATA_0 0x4c5a 6298#define mmRLC_SERDES_RD_DATA_0_BASE_IDX 1 6299#define mmRLC_SERDES_RD_DATA_1 0x4c5b 6300#define mmRLC_SERDES_RD_DATA_1_BASE_IDX 1 6301#define mmRLC_SERDES_RD_DATA_2 0x4c5c 6302#define mmRLC_SERDES_RD_DATA_2_BASE_IDX 1 6303#define mmRLC_SERDES_WR_CU_MASTER_MASK 0x4c5d 6304#define mmRLC_SERDES_WR_CU_MASTER_MASK_BASE_IDX 1 6305#define mmRLC_SERDES_WR_NONCU_MASTER_MASK 0x4c5e 6306#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_BASE_IDX 1 6307#define mmRLC_SERDES_WR_CTRL 0x4c5f 6308#define mmRLC_SERDES_WR_CTRL_BASE_IDX 1 6309#define mmRLC_SERDES_WR_DATA 0x4c60 6310#define mmRLC_SERDES_WR_DATA_BASE_IDX 1 6311#define mmRLC_SERDES_CU_MASTER_BUSY 0x4c61 6312#define mmRLC_SERDES_CU_MASTER_BUSY_BASE_IDX 1 6313#define mmRLC_SERDES_NONCU_MASTER_BUSY 0x4c62 6314#define mmRLC_SERDES_NONCU_MASTER_BUSY_BASE_IDX 1 6315#define mmRLC_GPM_GENERAL_0 0x4c63 6316#define mmRLC_GPM_GENERAL_0_BASE_IDX 1 6317#define mmRLC_GPM_GENERAL_1 0x4c64 6318#define mmRLC_GPM_GENERAL_1_BASE_IDX 1 6319#define mmRLC_GPM_GENERAL_2 0x4c65 6320#define mmRLC_GPM_GENERAL_2_BASE_IDX 1 6321#define mmRLC_GPM_GENERAL_3 0x4c66 6322#define mmRLC_GPM_GENERAL_3_BASE_IDX 1 6323#define mmRLC_GPM_GENERAL_4 0x4c67 6324#define mmRLC_GPM_GENERAL_4_BASE_IDX 1 6325#define mmRLC_GPM_GENERAL_5 0x4c68 6326#define mmRLC_GPM_GENERAL_5_BASE_IDX 1 6327#define mmRLC_GPM_GENERAL_6 0x4c69 6328#define mmRLC_GPM_GENERAL_6_BASE_IDX 1 6329#define mmRLC_GPM_GENERAL_7 0x4c6a 6330#define mmRLC_GPM_GENERAL_7_BASE_IDX 1 6331#define mmRLC_GPM_SCRATCH_ADDR 0x4c6c 6332#define mmRLC_GPM_SCRATCH_ADDR_BASE_IDX 1 6333#define mmRLC_GPM_SCRATCH_DATA 0x4c6d 6334#define mmRLC_GPM_SCRATCH_DATA_BASE_IDX 1 6335#define mmRLC_STATIC_PG_STATUS 0x4c6e 6336#define mmRLC_STATIC_PG_STATUS_BASE_IDX 1 6337#define mmRLC_SPM_MC_CNTL 0x4c71 6338#define mmRLC_SPM_MC_CNTL_BASE_IDX 1 6339#define mmRLC_SPM_INT_CNTL 0x4c72 6340#define mmRLC_SPM_INT_CNTL_BASE_IDX 1 6341#define mmRLC_SPM_INT_STATUS 0x4c73 6342#define mmRLC_SPM_INT_STATUS_BASE_IDX 1 6343#define mmRLC_SMU_MESSAGE 0x4c76 6344#define mmRLC_SMU_MESSAGE_BASE_IDX 1 6345#define mmRLC_GPM_LOG_SIZE 0x4c77 6346#define mmRLC_GPM_LOG_SIZE_BASE_IDX 1 6347#define mmRLC_PG_DELAY_3 0x4c78 6348#define mmRLC_PG_DELAY_3_BASE_IDX 1 6349#define mmRLC_GPR_REG1 0x4c79 6350#define mmRLC_GPR_REG1_BASE_IDX 1 6351#define mmRLC_GPR_REG2 0x4c7a 6352#define mmRLC_GPR_REG2_BASE_IDX 1 6353#define mmRLC_GPM_LOG_CONT 0x4c7b 6354#define mmRLC_GPM_LOG_CONT_BASE_IDX 1 6355#define mmRLC_GPM_INT_DISABLE_TH0 0x4c7c 6356#define mmRLC_GPM_INT_DISABLE_TH0_BASE_IDX 1 6357#define mmRLC_GPM_INT_DISABLE_TH1 0x4c7d 6358#define mmRLC_GPM_INT_DISABLE_TH1_BASE_IDX 1 6359#define mmRLC_GPM_INT_FORCE_TH0 0x4c7e 6360#define mmRLC_GPM_INT_FORCE_TH0_BASE_IDX 1 6361#define mmRLC_GPM_INT_FORCE_TH1 0x4c7f 6362#define mmRLC_GPM_INT_FORCE_TH1_BASE_IDX 1 6363#define mmRLC_SRM_CNTL 0x4c80 6364#define mmRLC_SRM_CNTL_BASE_IDX 1 6365#define mmRLC_SRM_ARAM_ADDR 0x4c83 6366#define mmRLC_SRM_ARAM_ADDR_BASE_IDX 1 6367#define mmRLC_SRM_ARAM_DATA 0x4c84 6368#define mmRLC_SRM_ARAM_DATA_BASE_IDX 1 6369#define mmRLC_SRM_DRAM_ADDR 0x4c85 6370#define mmRLC_SRM_DRAM_ADDR_BASE_IDX 1 6371#define mmRLC_SRM_DRAM_DATA 0x4c86 6372#define mmRLC_SRM_DRAM_DATA_BASE_IDX 1 6373#define mmRLC_SRM_GPM_COMMAND 0x4c87 6374#define mmRLC_SRM_GPM_COMMAND_BASE_IDX 1 6375#define mmRLC_SRM_GPM_COMMAND_STATUS 0x4c88 6376#define mmRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX 1 6377#define mmRLC_SRM_RLCV_COMMAND 0x4c89 6378#define mmRLC_SRM_RLCV_COMMAND_BASE_IDX 1 6379#define mmRLC_SRM_RLCV_COMMAND_STATUS 0x4c8a 6380#define mmRLC_SRM_RLCV_COMMAND_STATUS_BASE_IDX 1 6381#define mmRLC_SRM_INDEX_CNTL_ADDR_0 0x4c8b 6382#define mmRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX 1 6383#define mmRLC_SRM_INDEX_CNTL_ADDR_1 0x4c8c 6384#define mmRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX 1 6385#define mmRLC_SRM_INDEX_CNTL_ADDR_2 0x4c8d 6386#define mmRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX 1 6387#define mmRLC_SRM_INDEX_CNTL_ADDR_3 0x4c8e 6388#define mmRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX 1 6389#define mmRLC_SRM_INDEX_CNTL_ADDR_4 0x4c8f 6390#define mmRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX 1 6391#define mmRLC_SRM_INDEX_CNTL_ADDR_5 0x4c90 6392#define mmRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX 1 6393#define mmRLC_SRM_INDEX_CNTL_ADDR_6 0x4c91 6394#define mmRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX 1 6395#define mmRLC_SRM_INDEX_CNTL_ADDR_7 0x4c92 6396#define mmRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX 1 6397#define mmRLC_SRM_INDEX_CNTL_DATA_0 0x4c93 6398#define mmRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX 1 6399#define mmRLC_SRM_INDEX_CNTL_DATA_1 0x4c94 6400#define mmRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX 1 6401#define mmRLC_SRM_INDEX_CNTL_DATA_2 0x4c95 6402#define mmRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX 1 6403#define mmRLC_SRM_INDEX_CNTL_DATA_3 0x4c96 6404#define mmRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX 1 6405#define mmRLC_SRM_INDEX_CNTL_DATA_4 0x4c97 6406#define mmRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX 1 6407#define mmRLC_SRM_INDEX_CNTL_DATA_5 0x4c98 6408#define mmRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX 1 6409#define mmRLC_SRM_INDEX_CNTL_DATA_6 0x4c99 6410#define mmRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX 1 6411#define mmRLC_SRM_INDEX_CNTL_DATA_7 0x4c9a 6412#define mmRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX 1 6413#define mmRLC_SRM_STAT 0x4c9b 6414#define mmRLC_SRM_STAT_BASE_IDX 1 6415#define mmRLC_SRM_GPM_ABORT 0x4c9c 6416#define mmRLC_SRM_GPM_ABORT_BASE_IDX 1 6417#define mmRLC_CSIB_ADDR_LO 0x4ca2 6418#define mmRLC_CSIB_ADDR_LO_BASE_IDX 1 6419#define mmRLC_CSIB_ADDR_HI 0x4ca3 6420#define mmRLC_CSIB_ADDR_HI_BASE_IDX 1 6421#define mmRLC_CSIB_LENGTH 0x4ca4 6422#define mmRLC_CSIB_LENGTH_BASE_IDX 1 6423#define mmRLC_SMU_COMMAND 0x4ca9 6424#define mmRLC_SMU_COMMAND_BASE_IDX 1 6425#define mmRLC_CP_SCHEDULERS 0x4caa 6426#define mmRLC_CP_SCHEDULERS_BASE_IDX 1 6427#define mmRLC_SMU_ARGUMENT_1 0x4cab 6428#define mmRLC_SMU_ARGUMENT_1_BASE_IDX 1 6429#define mmRLC_SMU_ARGUMENT_2 0x4cac 6430#define mmRLC_SMU_ARGUMENT_2_BASE_IDX 1 6431#define mmRLC_GPM_GENERAL_8 0x4cad 6432#define mmRLC_GPM_GENERAL_8_BASE_IDX 1 6433#define mmRLC_GPM_GENERAL_9 0x4cae 6434#define mmRLC_GPM_GENERAL_9_BASE_IDX 1 6435#define mmRLC_GPM_GENERAL_10 0x4caf 6436#define mmRLC_GPM_GENERAL_10_BASE_IDX 1 6437#define mmRLC_GPM_GENERAL_11 0x4cb0 6438#define mmRLC_GPM_GENERAL_11_BASE_IDX 1 6439#define mmRLC_GPM_GENERAL_12 0x4cb1 6440#define mmRLC_GPM_GENERAL_12_BASE_IDX 1 6441#define mmRLC_GPM_UTCL1_CNTL_0 0x4cb2 6442#define mmRLC_GPM_UTCL1_CNTL_0_BASE_IDX 1 6443#define mmRLC_GPM_UTCL1_CNTL_1 0x4cb3 6444#define mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX 1 6445#define mmRLC_GPM_UTCL1_CNTL_2 0x4cb4 6446#define mmRLC_GPM_UTCL1_CNTL_2_BASE_IDX 1 6447#define mmRLC_SPM_UTCL1_CNTL 0x4cb5 6448#define mmRLC_SPM_UTCL1_CNTL_BASE_IDX 1 6449#define mmRLC_UTCL1_STATUS_2 0x4cb6 6450#define mmRLC_UTCL1_STATUS_2_BASE_IDX 1 6451#define mmRLC_LB_THR_CONFIG_2 0x4cb8 6452#define mmRLC_LB_THR_CONFIG_2_BASE_IDX 1 6453#define mmRLC_LB_THR_CONFIG_3 0x4cb9 6454#define mmRLC_LB_THR_CONFIG_3_BASE_IDX 1 6455#define mmRLC_LB_THR_CONFIG_4 0x4cba 6456#define mmRLC_LB_THR_CONFIG_4_BASE_IDX 1 6457#define mmRLC_SPM_UTCL1_ERROR_1 0x4cbc 6458#define mmRLC_SPM_UTCL1_ERROR_1_BASE_IDX 1 6459#define mmRLC_SPM_UTCL1_ERROR_2 0x4cbd 6460#define mmRLC_SPM_UTCL1_ERROR_2_BASE_IDX 1 6461#define mmRLC_GPM_UTCL1_TH0_ERROR_1 0x4cbe 6462#define mmRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX 1 6463#define mmRLC_LB_THR_CONFIG_1 0x4cbf 6464#define mmRLC_LB_THR_CONFIG_1_BASE_IDX 1 6465#define mmRLC_GPM_UTCL1_TH0_ERROR_2 0x4cc0 6466#define mmRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX 1 6467#define mmRLC_GPM_UTCL1_TH1_ERROR_1 0x4cc1 6468#define mmRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX 1 6469#define mmRLC_GPM_UTCL1_TH1_ERROR_2 0x4cc2 6470#define mmRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX 1 6471#define mmRLC_GPM_UTCL1_TH2_ERROR_1 0x4cc3 6472#define mmRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX 1 6473#define mmRLC_GPM_UTCL1_TH2_ERROR_2 0x4cc4 6474#define mmRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX 1 6475#define mmRLC_CGCG_CGLS_CTRL_3D 0x4cc5 6476#define mmRLC_CGCG_CGLS_CTRL_3D_BASE_IDX 1 6477#define mmRLC_CGCG_RAMP_CTRL_3D 0x4cc6 6478#define mmRLC_CGCG_RAMP_CTRL_3D_BASE_IDX 1 6479#define mmRLC_SEMAPHORE_0 0x4cc7 6480#define mmRLC_SEMAPHORE_0_BASE_IDX 1 6481#define mmRLC_SEMAPHORE_1 0x4cc8 6482#define mmRLC_SEMAPHORE_1_BASE_IDX 1 6483#define mmRLC_CP_EOF_INT 0x4cca 6484#define mmRLC_CP_EOF_INT_BASE_IDX 1 6485#define mmRLC_CP_EOF_INT_CNT 0x4ccb 6486#define mmRLC_CP_EOF_INT_CNT_BASE_IDX 1 6487#define mmRLC_SPARE_INT 0x4ccc 6488#define mmRLC_SPARE_INT_BASE_IDX 1 6489#define mmRLC_PREWALKER_UTCL1_CNTL 0x4ccd 6490#define mmRLC_PREWALKER_UTCL1_CNTL_BASE_IDX 1 6491#define mmRLC_PREWALKER_UTCL1_TRIG 0x4cce 6492#define mmRLC_PREWALKER_UTCL1_TRIG_BASE_IDX 1 6493#define mmRLC_PREWALKER_UTCL1_ADDR_LSB 0x4ccf 6494#define mmRLC_PREWALKER_UTCL1_ADDR_LSB_BASE_IDX 1 6495#define mmRLC_PREWALKER_UTCL1_ADDR_MSB 0x4cd0 6496#define mmRLC_PREWALKER_UTCL1_ADDR_MSB_BASE_IDX 1 6497#define mmRLC_PREWALKER_UTCL1_SIZE_LSB 0x4cd1 6498#define mmRLC_PREWALKER_UTCL1_SIZE_LSB_BASE_IDX 1 6499#define mmRLC_PREWALKER_UTCL1_SIZE_MSB 0x4cd2 6500#define mmRLC_PREWALKER_UTCL1_SIZE_MSB_BASE_IDX 1 6501#define mmRLC_DSM_TRIG 0x4cd3 6502#define mmRLC_DSM_TRIG_BASE_IDX 1 6503#define mmRLC_UTCL1_STATUS 0x4cd4 6504#define mmRLC_UTCL1_STATUS_BASE_IDX 1 6505#define mmRLC_R2I_CNTL_0 0x4cd5 6506#define mmRLC_R2I_CNTL_0_BASE_IDX 1 6507#define mmRLC_R2I_CNTL_1 0x4cd6 6508#define mmRLC_R2I_CNTL_1_BASE_IDX 1 6509#define mmRLC_R2I_CNTL_2 0x4cd7 6510#define mmRLC_R2I_CNTL_2_BASE_IDX 1 6511#define mmRLC_R2I_CNTL_3 0x4cd8 6512#define mmRLC_R2I_CNTL_3_BASE_IDX 1 6513#define mmRLC_UTCL2_CNTL 0x4cd9 6514#define mmRLC_UTCL2_CNTL_BASE_IDX 1 6515#define mmRLC_LBPW_CU_STAT 0x4cda 6516#define mmRLC_LBPW_CU_STAT_BASE_IDX 1 6517#define mmRLC_DS_CNTL 0x4cdb 6518#define mmRLC_DS_CNTL_BASE_IDX 1 6519#define mmRLC_RLCV_SPARE_INT 0x4f30 6520#define mmRLC_RLCV_SPARE_INT_BASE_IDX 1 6521 6522 6523// addressBlock: gc_pwrdec 6524// base address: 0x3c000 6525#define mmCGTS_SM_CTRL_REG 0x5000 6526#define mmCGTS_SM_CTRL_REG_BASE_IDX 1 6527#define mmCGTS_RD_CTRL_REG 0x5001 6528#define mmCGTS_RD_CTRL_REG_BASE_IDX 1 6529#define mmCGTS_RD_REG 0x5002 6530#define mmCGTS_RD_REG_BASE_IDX 1 6531#define mmCGTS_TCC_DISABLE 0x5003 6532#define mmCGTS_TCC_DISABLE_BASE_IDX 1 6533#define mmCGTS_USER_TCC_DISABLE 0x5004 6534#define mmCGTS_USER_TCC_DISABLE_BASE_IDX 1 6535#define mmCGTS_CU0_SP0_CTRL_REG 0x5008 6536#define mmCGTS_CU0_SP0_CTRL_REG_BASE_IDX 1 6537#define mmCGTS_CU0_LDS_SQ_CTRL_REG 0x5009 6538#define mmCGTS_CU0_LDS_SQ_CTRL_REG_BASE_IDX 1 6539#define mmCGTS_CU0_TA_SQC_CTRL_REG 0x500a 6540#define mmCGTS_CU0_TA_SQC_CTRL_REG_BASE_IDX 1 6541#define mmCGTS_CU0_SP1_CTRL_REG 0x500b 6542#define mmCGTS_CU0_SP1_CTRL_REG_BASE_IDX 1 6543#define mmCGTS_CU0_TD_TCP_CTRL_REG 0x500c 6544#define mmCGTS_CU0_TD_TCP_CTRL_REG_BASE_IDX 1 6545#define mmCGTS_CU1_SP0_CTRL_REG 0x500d 6546#define mmCGTS_CU1_SP0_CTRL_REG_BASE_IDX 1 6547#define mmCGTS_CU1_LDS_SQ_CTRL_REG 0x500e 6548#define mmCGTS_CU1_LDS_SQ_CTRL_REG_BASE_IDX 1 6549#define mmCGTS_CU1_TA_SQC_CTRL_REG 0x500f 6550#define mmCGTS_CU1_TA_SQC_CTRL_REG_BASE_IDX 1 6551#define mmCGTS_CU1_SP1_CTRL_REG 0x5010 6552#define mmCGTS_CU1_SP1_CTRL_REG_BASE_IDX 1 6553#define mmCGTS_CU1_TD_TCP_CTRL_REG 0x5011 6554#define mmCGTS_CU1_TD_TCP_CTRL_REG_BASE_IDX 1 6555#define mmCGTS_CU2_SP0_CTRL_REG 0x5012 6556#define mmCGTS_CU2_SP0_CTRL_REG_BASE_IDX 1 6557#define mmCGTS_CU2_LDS_SQ_CTRL_REG 0x5013 6558#define mmCGTS_CU2_LDS_SQ_CTRL_REG_BASE_IDX 1 6559#define mmCGTS_CU2_TA_SQC_CTRL_REG 0x5014 6560#define mmCGTS_CU2_TA_SQC_CTRL_REG_BASE_IDX 1 6561#define mmCGTS_CU2_SP1_CTRL_REG 0x5015 6562#define mmCGTS_CU2_SP1_CTRL_REG_BASE_IDX 1 6563#define mmCGTS_CU2_TD_TCP_CTRL_REG 0x5016 6564#define mmCGTS_CU2_TD_TCP_CTRL_REG_BASE_IDX 1 6565#define mmCGTS_CU3_SP0_CTRL_REG 0x5017 6566#define mmCGTS_CU3_SP0_CTRL_REG_BASE_IDX 1 6567#define mmCGTS_CU3_LDS_SQ_CTRL_REG 0x5018 6568#define mmCGTS_CU3_LDS_SQ_CTRL_REG_BASE_IDX 1 6569#define mmCGTS_CU3_TA_SQC_CTRL_REG 0x5019 6570#define mmCGTS_CU3_TA_SQC_CTRL_REG_BASE_IDX 1 6571#define mmCGTS_CU3_SP1_CTRL_REG 0x501a 6572#define mmCGTS_CU3_SP1_CTRL_REG_BASE_IDX 1 6573#define mmCGTS_CU3_TD_TCP_CTRL_REG 0x501b 6574#define mmCGTS_CU3_TD_TCP_CTRL_REG_BASE_IDX 1 6575#define mmCGTS_CU4_SP0_CTRL_REG 0x501c 6576#define mmCGTS_CU4_SP0_CTRL_REG_BASE_IDX 1 6577#define mmCGTS_CU4_LDS_SQ_CTRL_REG 0x501d 6578#define mmCGTS_CU4_LDS_SQ_CTRL_REG_BASE_IDX 1 6579#define mmCGTS_CU4_TA_SQC_CTRL_REG 0x501e 6580#define mmCGTS_CU4_TA_SQC_CTRL_REG_BASE_IDX 1 6581#define mmCGTS_CU4_SP1_CTRL_REG 0x501f 6582#define mmCGTS_CU4_SP1_CTRL_REG_BASE_IDX 1 6583#define mmCGTS_CU4_TD_TCP_CTRL_REG 0x5020 6584#define mmCGTS_CU4_TD_TCP_CTRL_REG_BASE_IDX 1 6585#define mmCGTS_CU5_SP0_CTRL_REG 0x5021 6586#define mmCGTS_CU5_SP0_CTRL_REG_BASE_IDX 1 6587#define mmCGTS_CU5_LDS_SQ_CTRL_REG 0x5022 6588#define mmCGTS_CU5_LDS_SQ_CTRL_REG_BASE_IDX 1 6589#define mmCGTS_CU5_TA_SQC_CTRL_REG 0x5023 6590#define mmCGTS_CU5_TA_SQC_CTRL_REG_BASE_IDX 1 6591#define mmCGTS_CU5_SP1_CTRL_REG 0x5024 6592#define mmCGTS_CU5_SP1_CTRL_REG_BASE_IDX 1 6593#define mmCGTS_CU5_TD_TCP_CTRL_REG 0x5025 6594#define mmCGTS_CU5_TD_TCP_CTRL_REG_BASE_IDX 1 6595#define mmCGTS_CU6_SP0_CTRL_REG 0x5026 6596#define mmCGTS_CU6_SP0_CTRL_REG_BASE_IDX 1 6597#define mmCGTS_CU6_LDS_SQ_CTRL_REG 0x5027 6598#define mmCGTS_CU6_LDS_SQ_CTRL_REG_BASE_IDX 1 6599#define mmCGTS_CU6_TA_SQC_CTRL_REG 0x5028 6600#define mmCGTS_CU6_TA_SQC_CTRL_REG_BASE_IDX 1 6601#define mmCGTS_CU6_SP1_CTRL_REG 0x5029 6602#define mmCGTS_CU6_SP1_CTRL_REG_BASE_IDX 1 6603#define mmCGTS_CU6_TD_TCP_CTRL_REG 0x502a 6604#define mmCGTS_CU6_TD_TCP_CTRL_REG_BASE_IDX 1 6605#define mmCGTS_CU7_SP0_CTRL_REG 0x502b 6606#define mmCGTS_CU7_SP0_CTRL_REG_BASE_IDX 1 6607#define mmCGTS_CU7_LDS_SQ_CTRL_REG 0x502c 6608#define mmCGTS_CU7_LDS_SQ_CTRL_REG_BASE_IDX 1 6609#define mmCGTS_CU7_TA_SQC_CTRL_REG 0x502d 6610#define mmCGTS_CU7_TA_SQC_CTRL_REG_BASE_IDX 1 6611#define mmCGTS_CU7_SP1_CTRL_REG 0x502e 6612#define mmCGTS_CU7_SP1_CTRL_REG_BASE_IDX 1 6613#define mmCGTS_CU7_TD_TCP_CTRL_REG 0x502f 6614#define mmCGTS_CU7_TD_TCP_CTRL_REG_BASE_IDX 1 6615#define mmCGTS_CU8_SP0_CTRL_REG 0x5030 6616#define mmCGTS_CU8_SP0_CTRL_REG_BASE_IDX 1 6617#define mmCGTS_CU8_LDS_SQ_CTRL_REG 0x5031 6618#define mmCGTS_CU8_LDS_SQ_CTRL_REG_BASE_IDX 1 6619#define mmCGTS_CU8_TA_SQC_CTRL_REG 0x5032 6620#define mmCGTS_CU8_TA_SQC_CTRL_REG_BASE_IDX 1 6621#define mmCGTS_CU8_SP1_CTRL_REG 0x5033 6622#define mmCGTS_CU8_SP1_CTRL_REG_BASE_IDX 1 6623#define mmCGTS_CU8_TD_TCP_CTRL_REG 0x5034 6624#define mmCGTS_CU8_TD_TCP_CTRL_REG_BASE_IDX 1 6625#define mmCGTS_CU9_SP0_CTRL_REG 0x5035 6626#define mmCGTS_CU9_SP0_CTRL_REG_BASE_IDX 1 6627#define mmCGTS_CU9_LDS_SQ_CTRL_REG 0x5036 6628#define mmCGTS_CU9_LDS_SQ_CTRL_REG_BASE_IDX 1 6629#define mmCGTS_CU9_TA_SQC_CTRL_REG 0x5037 6630#define mmCGTS_CU9_TA_SQC_CTRL_REG_BASE_IDX 1 6631#define mmCGTS_CU9_SP1_CTRL_REG 0x5038 6632#define mmCGTS_CU9_SP1_CTRL_REG_BASE_IDX 1 6633#define mmCGTS_CU9_TD_TCP_CTRL_REG 0x5039 6634#define mmCGTS_CU9_TD_TCP_CTRL_REG_BASE_IDX 1 6635#define mmCGTS_CU10_SP0_CTRL_REG 0x503a 6636#define mmCGTS_CU10_SP0_CTRL_REG_BASE_IDX 1 6637#define mmCGTS_CU10_LDS_SQ_CTRL_REG 0x503b 6638#define mmCGTS_CU10_LDS_SQ_CTRL_REG_BASE_IDX 1 6639#define mmCGTS_CU10_TA_SQC_CTRL_REG 0x503c 6640#define mmCGTS_CU10_TA_SQC_CTRL_REG_BASE_IDX 1 6641#define mmCGTS_CU10_SP1_CTRL_REG 0x503d 6642#define mmCGTS_CU10_SP1_CTRL_REG_BASE_IDX 1 6643#define mmCGTS_CU10_TD_TCP_CTRL_REG 0x503e 6644#define mmCGTS_CU10_TD_TCP_CTRL_REG_BASE_IDX 1 6645#define mmCGTS_CU11_SP0_CTRL_REG 0x503f 6646#define mmCGTS_CU11_SP0_CTRL_REG_BASE_IDX 1 6647#define mmCGTS_CU11_LDS_SQ_CTRL_REG 0x5040 6648#define mmCGTS_CU11_LDS_SQ_CTRL_REG_BASE_IDX 1 6649#define mmCGTS_CU11_TA_SQC_CTRL_REG 0x5041 6650#define mmCGTS_CU11_TA_SQC_CTRL_REG_BASE_IDX 1 6651#define mmCGTS_CU11_SP1_CTRL_REG 0x5042 6652#define mmCGTS_CU11_SP1_CTRL_REG_BASE_IDX 1 6653#define mmCGTS_CU11_TD_TCP_CTRL_REG 0x5043 6654#define mmCGTS_CU11_TD_TCP_CTRL_REG_BASE_IDX 1 6655#define mmCGTS_CU12_SP0_CTRL_REG 0x5044 6656#define mmCGTS_CU12_SP0_CTRL_REG_BASE_IDX 1 6657#define mmCGTS_CU12_LDS_SQ_CTRL_REG 0x5045 6658#define mmCGTS_CU12_LDS_SQ_CTRL_REG_BASE_IDX 1 6659#define mmCGTS_CU12_TA_SQC_CTRL_REG 0x5046 6660#define mmCGTS_CU12_TA_SQC_CTRL_REG_BASE_IDX 1 6661#define mmCGTS_CU12_SP1_CTRL_REG 0x5047 6662#define mmCGTS_CU12_SP1_CTRL_REG_BASE_IDX 1 6663#define mmCGTS_CU12_TD_TCP_CTRL_REG 0x5048 6664#define mmCGTS_CU12_TD_TCP_CTRL_REG_BASE_IDX 1 6665#define mmCGTS_CU13_SP0_CTRL_REG 0x5049 6666#define mmCGTS_CU13_SP0_CTRL_REG_BASE_IDX 1 6667#define mmCGTS_CU13_LDS_SQ_CTRL_REG 0x504a 6668#define mmCGTS_CU13_LDS_SQ_CTRL_REG_BASE_IDX 1 6669#define mmCGTS_CU13_TA_SQC_CTRL_REG 0x504b 6670#define mmCGTS_CU13_TA_SQC_CTRL_REG_BASE_IDX 1 6671#define mmCGTS_CU13_SP1_CTRL_REG 0x504c 6672#define mmCGTS_CU13_SP1_CTRL_REG_BASE_IDX 1 6673#define mmCGTS_CU13_TD_TCP_CTRL_REG 0x504d 6674#define mmCGTS_CU13_TD_TCP_CTRL_REG_BASE_IDX 1 6675#define mmCGTS_CU14_SP0_CTRL_REG 0x504e 6676#define mmCGTS_CU14_SP0_CTRL_REG_BASE_IDX 1 6677#define mmCGTS_CU14_LDS_SQ_CTRL_REG 0x504f 6678#define mmCGTS_CU14_LDS_SQ_CTRL_REG_BASE_IDX 1 6679#define mmCGTS_CU14_TA_SQC_CTRL_REG 0x5050 6680#define mmCGTS_CU14_TA_SQC_CTRL_REG_BASE_IDX 1 6681#define mmCGTS_CU14_SP1_CTRL_REG 0x5051 6682#define mmCGTS_CU14_SP1_CTRL_REG_BASE_IDX 1 6683#define mmCGTS_CU14_TD_TCP_CTRL_REG 0x5052 6684#define mmCGTS_CU14_TD_TCP_CTRL_REG_BASE_IDX 1 6685#define mmCGTS_CU15_SP0_CTRL_REG 0x5053 6686#define mmCGTS_CU15_SP0_CTRL_REG_BASE_IDX 1 6687#define mmCGTS_CU15_LDS_SQ_CTRL_REG 0x5054 6688#define mmCGTS_CU15_LDS_SQ_CTRL_REG_BASE_IDX 1 6689#define mmCGTS_CU15_TA_SQC_CTRL_REG 0x5055 6690#define mmCGTS_CU15_TA_SQC_CTRL_REG_BASE_IDX 1 6691#define mmCGTS_CU15_SP1_CTRL_REG 0x5056 6692#define mmCGTS_CU15_SP1_CTRL_REG_BASE_IDX 1 6693#define mmCGTS_CU15_TD_TCP_CTRL_REG 0x5057 6694#define mmCGTS_CU15_TD_TCP_CTRL_REG_BASE_IDX 1 6695#define mmCGTS_CU0_TCPI_CTRL_REG 0x5058 6696#define mmCGTS_CU0_TCPI_CTRL_REG_BASE_IDX 1 6697#define mmCGTS_CU1_TCPI_CTRL_REG 0x5059 6698#define mmCGTS_CU1_TCPI_CTRL_REG_BASE_IDX 1 6699#define mmCGTS_CU2_TCPI_CTRL_REG 0x505a 6700#define mmCGTS_CU2_TCPI_CTRL_REG_BASE_IDX 1 6701#define mmCGTS_CU3_TCPI_CTRL_REG 0x505b 6702#define mmCGTS_CU3_TCPI_CTRL_REG_BASE_IDX 1 6703#define mmCGTS_CU4_TCPI_CTRL_REG 0x505c 6704#define mmCGTS_CU4_TCPI_CTRL_REG_BASE_IDX 1 6705#define mmCGTS_CU5_TCPI_CTRL_REG 0x505d 6706#define mmCGTS_CU5_TCPI_CTRL_REG_BASE_IDX 1 6707#define mmCGTS_CU6_TCPI_CTRL_REG 0x505e 6708#define mmCGTS_CU6_TCPI_CTRL_REG_BASE_IDX 1 6709#define mmCGTS_CU7_TCPI_CTRL_REG 0x505f 6710#define mmCGTS_CU7_TCPI_CTRL_REG_BASE_IDX 1 6711#define mmCGTS_CU8_TCPI_CTRL_REG 0x5060 6712#define mmCGTS_CU8_TCPI_CTRL_REG_BASE_IDX 1 6713#define mmCGTS_CU9_TCPI_CTRL_REG 0x5061 6714#define mmCGTS_CU9_TCPI_CTRL_REG_BASE_IDX 1 6715#define mmCGTS_CU10_TCPI_CTRL_REG 0x5062 6716#define mmCGTS_CU10_TCPI_CTRL_REG_BASE_IDX 1 6717#define mmCGTS_CU11_TCPI_CTRL_REG 0x5063 6718#define mmCGTS_CU11_TCPI_CTRL_REG_BASE_IDX 1 6719#define mmCGTS_CU12_TCPI_CTRL_REG 0x5064 6720#define mmCGTS_CU12_TCPI_CTRL_REG_BASE_IDX 1 6721#define mmCGTS_CU13_TCPI_CTRL_REG 0x5065 6722#define mmCGTS_CU13_TCPI_CTRL_REG_BASE_IDX 1 6723#define mmCGTS_CU14_TCPI_CTRL_REG 0x5066 6724#define mmCGTS_CU14_TCPI_CTRL_REG_BASE_IDX 1 6725#define mmCGTS_CU15_TCPI_CTRL_REG 0x5067 6726#define mmCGTS_CU15_TCPI_CTRL_REG_BASE_IDX 1 6727#define mmCGTT_SPI_CLK_CTRL 0x5080 6728#define mmCGTT_SPI_CLK_CTRL_BASE_IDX 1 6729#define mmCGTT_PC_CLK_CTRL 0x5081 6730#define mmCGTT_PC_CLK_CTRL_BASE_IDX 1 6731#define mmCGTT_BCI_CLK_CTRL 0x5082 6732#define mmCGTT_BCI_CLK_CTRL_BASE_IDX 1 6733#define mmCGTT_VGT_CLK_CTRL 0x5084 6734#define mmCGTT_VGT_CLK_CTRL_BASE_IDX 1 6735#define mmCGTT_IA_CLK_CTRL 0x5085 6736#define mmCGTT_IA_CLK_CTRL_BASE_IDX 1 6737#define mmCGTT_WD_CLK_CTRL 0x5086 6738#define mmCGTT_WD_CLK_CTRL_BASE_IDX 1 6739#define mmCGTT_PA_CLK_CTRL 0x5088 6740#define mmCGTT_PA_CLK_CTRL_BASE_IDX 1 6741#define mmCGTT_SC_CLK_CTRL0 0x5089 6742#define mmCGTT_SC_CLK_CTRL0_BASE_IDX 1 6743#define mmCGTT_SC_CLK_CTRL1 0x508a 6744#define mmCGTT_SC_CLK_CTRL1_BASE_IDX 1 6745#define mmCGTT_SQ_CLK_CTRL 0x508c 6746#define mmCGTT_SQ_CLK_CTRL_BASE_IDX 1 6747#define mmCGTT_SQG_CLK_CTRL 0x508d 6748#define mmCGTT_SQG_CLK_CTRL_BASE_IDX 1 6749#define mmSQ_ALU_CLK_CTRL 0x508e 6750#define mmSQ_ALU_CLK_CTRL_BASE_IDX 1 6751#define mmSQ_TEX_CLK_CTRL 0x508f 6752#define mmSQ_TEX_CLK_CTRL_BASE_IDX 1 6753#define mmSQ_LDS_CLK_CTRL 0x5090 6754#define mmSQ_LDS_CLK_CTRL_BASE_IDX 1 6755#define mmSQ_POWER_THROTTLE 0x5091 6756#define mmSQ_POWER_THROTTLE_BASE_IDX 1 6757#define mmSQ_POWER_THROTTLE2 0x5092 6758#define mmSQ_POWER_THROTTLE2_BASE_IDX 1 6759#define mmCGTT_SX_CLK_CTRL0 0x5094 6760#define mmCGTT_SX_CLK_CTRL0_BASE_IDX 1 6761#define mmCGTT_SX_CLK_CTRL1 0x5095 6762#define mmCGTT_SX_CLK_CTRL1_BASE_IDX 1 6763#define mmCGTT_SX_CLK_CTRL2 0x5096 6764#define mmCGTT_SX_CLK_CTRL2_BASE_IDX 1 6765#define mmCGTT_SX_CLK_CTRL3 0x5097 6766#define mmCGTT_SX_CLK_CTRL3_BASE_IDX 1 6767#define mmCGTT_SX_CLK_CTRL4 0x5098 6768#define mmCGTT_SX_CLK_CTRL4_BASE_IDX 1 6769#define mmTD_CGTT_CTRL 0x509c 6770#define mmTD_CGTT_CTRL_BASE_IDX 1 6771#define mmTA_CGTT_CTRL 0x509d 6772#define mmTA_CGTT_CTRL_BASE_IDX 1 6773#define mmCGTT_TCPI_CLK_CTRL 0x509e 6774#define mmCGTT_TCPI_CLK_CTRL_BASE_IDX 1 6775#define mmCGTT_TCI_CLK_CTRL 0x509f 6776#define mmCGTT_TCI_CLK_CTRL_BASE_IDX 1 6777#define mmCGTT_GDS_CLK_CTRL 0x50a0 6778#define mmCGTT_GDS_CLK_CTRL_BASE_IDX 1 6779#define mmDB_CGTT_CLK_CTRL_0 0x50a4 6780#define mmDB_CGTT_CLK_CTRL_0_BASE_IDX 1 6781#define mmCB_CGTT_SCLK_CTRL 0x50a8 6782#define mmCB_CGTT_SCLK_CTRL_BASE_IDX 1 6783#define mmTCC_CGTT_SCLK_CTRL 0x50ac 6784#define mmTCC_CGTT_SCLK_CTRL_BASE_IDX 1 6785#define mmTCA_CGTT_SCLK_CTRL 0x50ad 6786#define mmTCA_CGTT_SCLK_CTRL_BASE_IDX 1 6787#define mmCGTT_CP_CLK_CTRL 0x50b0 6788#define mmCGTT_CP_CLK_CTRL_BASE_IDX 1 6789#define mmCGTT_CPF_CLK_CTRL 0x50b1 6790#define mmCGTT_CPF_CLK_CTRL_BASE_IDX 1 6791#define mmCGTT_CPC_CLK_CTRL 0x50b2 6792#define mmCGTT_CPC_CLK_CTRL_BASE_IDX 1 6793#define mmRLC_PWR_CTRL 0x50b4 6794#define mmRLC_PWR_CTRL_BASE_IDX 1 6795#define mmCGTT_RLC_CLK_CTRL 0x50b5 6796#define mmCGTT_RLC_CLK_CTRL_BASE_IDX 1 6797#define mmRLC_GFX_RM_CNTL 0x50b6 6798#define mmRLC_GFX_RM_CNTL_BASE_IDX 1 6799#define mmRMI_CGTT_SCLK_CTRL 0x50c0 6800#define mmRMI_CGTT_SCLK_CTRL_BASE_IDX 1 6801#define mmCGTT_TCPF_CLK_CTRL 0x50c1 6802#define mmCGTT_TCPF_CLK_CTRL_BASE_IDX 1 6803 6804 6805// addressBlock: gc_ea_pwrdec 6806// base address: 0x3c000 6807#define mmGCEA_CGTT_CLK_CTRL 0x50c4 6808#define mmGCEA_CGTT_CLK_CTRL_BASE_IDX 1 6809 6810 6811// addressBlock: gc_utcl2_vmsharedhvdec 6812// base address: 0x3ea00 6813#define mmMC_VM_FB_SIZE_OFFSET_VF0 0x5a80 6814#define mmMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1 6815#define mmMC_VM_FB_SIZE_OFFSET_VF1 0x5a81 6816#define mmMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1 6817#define mmMC_VM_FB_SIZE_OFFSET_VF2 0x5a82 6818#define mmMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1 6819#define mmMC_VM_FB_SIZE_OFFSET_VF3 0x5a83 6820#define mmMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1 6821#define mmMC_VM_FB_SIZE_OFFSET_VF4 0x5a84 6822#define mmMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1 6823#define mmMC_VM_FB_SIZE_OFFSET_VF5 0x5a85 6824#define mmMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1 6825#define mmMC_VM_FB_SIZE_OFFSET_VF6 0x5a86 6826#define mmMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1 6827#define mmMC_VM_FB_SIZE_OFFSET_VF7 0x5a87 6828#define mmMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1 6829#define mmMC_VM_FB_SIZE_OFFSET_VF8 0x5a88 6830#define mmMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1 6831#define mmMC_VM_FB_SIZE_OFFSET_VF9 0x5a89 6832#define mmMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1 6833#define mmMC_VM_FB_SIZE_OFFSET_VF10 0x5a8a 6834#define mmMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1 6835#define mmMC_VM_FB_SIZE_OFFSET_VF11 0x5a8b 6836#define mmMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1 6837#define mmMC_VM_FB_SIZE_OFFSET_VF12 0x5a8c 6838#define mmMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1 6839#define mmMC_VM_FB_SIZE_OFFSET_VF13 0x5a8d 6840#define mmMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1 6841#define mmMC_VM_FB_SIZE_OFFSET_VF14 0x5a8e 6842#define mmMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1 6843#define mmMC_VM_FB_SIZE_OFFSET_VF15 0x5a8f 6844#define mmMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1 6845#define mmVM_IOMMU_MMIO_CNTRL_1 0x5a90 6846#define mmVM_IOMMU_MMIO_CNTRL_1_BASE_IDX 1 6847#define mmMC_VM_MARC_BASE_LO_0 0x5a91 6848#define mmMC_VM_MARC_BASE_LO_0_BASE_IDX 1 6849#define mmMC_VM_MARC_BASE_LO_1 0x5a92 6850#define mmMC_VM_MARC_BASE_LO_1_BASE_IDX 1 6851#define mmMC_VM_MARC_BASE_LO_2 0x5a93 6852#define mmMC_VM_MARC_BASE_LO_2_BASE_IDX 1 6853#define mmMC_VM_MARC_BASE_LO_3 0x5a94 6854#define mmMC_VM_MARC_BASE_LO_3_BASE_IDX 1 6855#define mmMC_VM_MARC_BASE_HI_0 0x5a95 6856#define mmMC_VM_MARC_BASE_HI_0_BASE_IDX 1 6857#define mmMC_VM_MARC_BASE_HI_1 0x5a96 6858#define mmMC_VM_MARC_BASE_HI_1_BASE_IDX 1 6859#define mmMC_VM_MARC_BASE_HI_2 0x5a97 6860#define mmMC_VM_MARC_BASE_HI_2_BASE_IDX 1 6861#define mmMC_VM_MARC_BASE_HI_3 0x5a98 6862#define mmMC_VM_MARC_BASE_HI_3_BASE_IDX 1 6863#define mmMC_VM_MARC_RELOC_LO_0 0x5a99 6864#define mmMC_VM_MARC_RELOC_LO_0_BASE_IDX 1 6865#define mmMC_VM_MARC_RELOC_LO_1 0x5a9a 6866#define mmMC_VM_MARC_RELOC_LO_1_BASE_IDX 1 6867#define mmMC_VM_MARC_RELOC_LO_2 0x5a9b 6868#define mmMC_VM_MARC_RELOC_LO_2_BASE_IDX 1 6869#define mmMC_VM_MARC_RELOC_LO_3 0x5a9c 6870#define mmMC_VM_MARC_RELOC_LO_3_BASE_IDX 1 6871#define mmMC_VM_MARC_RELOC_HI_0 0x5a9d 6872#define mmMC_VM_MARC_RELOC_HI_0_BASE_IDX 1 6873#define mmMC_VM_MARC_RELOC_HI_1 0x5a9e 6874#define mmMC_VM_MARC_RELOC_HI_1_BASE_IDX 1 6875#define mmMC_VM_MARC_RELOC_HI_2 0x5a9f 6876#define mmMC_VM_MARC_RELOC_HI_2_BASE_IDX 1 6877#define mmMC_VM_MARC_RELOC_HI_3 0x5aa0 6878#define mmMC_VM_MARC_RELOC_HI_3_BASE_IDX 1 6879#define mmMC_VM_MARC_LEN_LO_0 0x5aa1 6880#define mmMC_VM_MARC_LEN_LO_0_BASE_IDX 1 6881#define mmMC_VM_MARC_LEN_LO_1 0x5aa2 6882#define mmMC_VM_MARC_LEN_LO_1_BASE_IDX 1 6883#define mmMC_VM_MARC_LEN_LO_2 0x5aa3 6884#define mmMC_VM_MARC_LEN_LO_2_BASE_IDX 1 6885#define mmMC_VM_MARC_LEN_LO_3 0x5aa4 6886#define mmMC_VM_MARC_LEN_LO_3_BASE_IDX 1 6887#define mmMC_VM_MARC_LEN_HI_0 0x5aa5 6888#define mmMC_VM_MARC_LEN_HI_0_BASE_IDX 1 6889#define mmMC_VM_MARC_LEN_HI_1 0x5aa6 6890#define mmMC_VM_MARC_LEN_HI_1_BASE_IDX 1 6891#define mmMC_VM_MARC_LEN_HI_2 0x5aa7 6892#define mmMC_VM_MARC_LEN_HI_2_BASE_IDX 1 6893#define mmMC_VM_MARC_LEN_HI_3 0x5aa8 6894#define mmMC_VM_MARC_LEN_HI_3_BASE_IDX 1 6895#define mmVM_IOMMU_CONTROL_REGISTER 0x5aa9 6896#define mmVM_IOMMU_CONTROL_REGISTER_BASE_IDX 1 6897#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x5aaa 6898#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1 6899#define mmVM_PCIE_ATS_CNTL 0x5aab 6900#define mmVM_PCIE_ATS_CNTL_BASE_IDX 1 6901#define mmVM_PCIE_ATS_CNTL_VF_0 0x5aac 6902#define mmVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 1 6903#define mmVM_PCIE_ATS_CNTL_VF_1 0x5aad 6904#define mmVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 1 6905#define mmVM_PCIE_ATS_CNTL_VF_2 0x5aae 6906#define mmVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 1 6907#define mmVM_PCIE_ATS_CNTL_VF_3 0x5aaf 6908#define mmVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 1 6909#define mmVM_PCIE_ATS_CNTL_VF_4 0x5ab0 6910#define mmVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 1 6911#define mmVM_PCIE_ATS_CNTL_VF_5 0x5ab1 6912#define mmVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 1 6913#define mmVM_PCIE_ATS_CNTL_VF_6 0x5ab2 6914#define mmVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 1 6915#define mmVM_PCIE_ATS_CNTL_VF_7 0x5ab3 6916#define mmVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 1 6917#define mmVM_PCIE_ATS_CNTL_VF_8 0x5ab4 6918#define mmVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 1 6919#define mmVM_PCIE_ATS_CNTL_VF_9 0x5ab5 6920#define mmVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 1 6921#define mmVM_PCIE_ATS_CNTL_VF_10 0x5ab6 6922#define mmVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 1 6923#define mmVM_PCIE_ATS_CNTL_VF_11 0x5ab7 6924#define mmVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 1 6925#define mmVM_PCIE_ATS_CNTL_VF_12 0x5ab8 6926#define mmVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 1 6927#define mmVM_PCIE_ATS_CNTL_VF_13 0x5ab9 6928#define mmVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 1 6929#define mmVM_PCIE_ATS_CNTL_VF_14 0x5aba 6930#define mmVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 1 6931#define mmVM_PCIE_ATS_CNTL_VF_15 0x5abb 6932#define mmVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 1 6933#define mmUTCL2_CGTT_CLK_CTRL 0x5abc 6934#define mmUTCL2_CGTT_CLK_CTRL_BASE_IDX 1 6935 6936 6937// addressBlock: gc_hypdec 6938// base address: 0x3e000 6939#define mmCP_HYP_PFP_UCODE_ADDR 0x5814 6940#define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 6941#define mmCP_PFP_UCODE_ADDR 0x5814 6942#define mmCP_PFP_UCODE_ADDR_BASE_IDX 1 6943#define mmCP_HYP_PFP_UCODE_DATA 0x5815 6944#define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 6945#define mmCP_PFP_UCODE_DATA 0x5815 6946#define mmCP_PFP_UCODE_DATA_BASE_IDX 1 6947#define mmCP_HYP_ME_UCODE_ADDR 0x5816 6948#define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 6949#define mmCP_ME_RAM_RADDR 0x5816 6950#define mmCP_ME_RAM_RADDR_BASE_IDX 1 6951#define mmCP_ME_RAM_WADDR 0x5816 6952#define mmCP_ME_RAM_WADDR_BASE_IDX 1 6953#define mmCP_HYP_ME_UCODE_DATA 0x5817 6954#define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 6955#define mmCP_ME_RAM_DATA 0x5817 6956#define mmCP_ME_RAM_DATA_BASE_IDX 1 6957#define mmCP_CE_UCODE_ADDR 0x5818 6958#define mmCP_CE_UCODE_ADDR_BASE_IDX 1 6959#define mmCP_HYP_CE_UCODE_ADDR 0x5818 6960#define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 6961#define mmCP_CE_UCODE_DATA 0x5819 6962#define mmCP_CE_UCODE_DATA_BASE_IDX 1 6963#define mmCP_HYP_CE_UCODE_DATA 0x5819 6964#define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 6965#define mmCP_HYP_MEC1_UCODE_ADDR 0x581a 6966#define mmCP_HYP_MEC1_UCODE_ADDR_BASE_IDX 1 6967#define mmCP_MEC_ME1_UCODE_ADDR 0x581a 6968#define mmCP_MEC_ME1_UCODE_ADDR_BASE_IDX 1 6969#define mmCP_HYP_MEC1_UCODE_DATA 0x581b 6970#define mmCP_HYP_MEC1_UCODE_DATA_BASE_IDX 1 6971#define mmCP_MEC_ME1_UCODE_DATA 0x581b 6972#define mmCP_MEC_ME1_UCODE_DATA_BASE_IDX 1 6973#define mmCP_HYP_MEC2_UCODE_ADDR 0x581c 6974#define mmCP_HYP_MEC2_UCODE_ADDR_BASE_IDX 1 6975#define mmCP_MEC_ME2_UCODE_ADDR 0x581c 6976#define mmCP_MEC_ME2_UCODE_ADDR_BASE_IDX 1 6977#define mmCP_HYP_MEC2_UCODE_DATA 0x581d 6978#define mmCP_HYP_MEC2_UCODE_DATA_BASE_IDX 1 6979#define mmCP_MEC_ME2_UCODE_DATA 0x581d 6980#define mmCP_MEC_ME2_UCODE_DATA_BASE_IDX 1 6981#define mmRLC_GPM_UCODE_ADDR 0x583c 6982#define mmRLC_GPM_UCODE_ADDR_BASE_IDX 1 6983#define mmRLC_GPM_UCODE_DATA 0x583d 6984#define mmRLC_GPM_UCODE_DATA_BASE_IDX 1 6985#define mmGRBM_GFX_INDEX_SR_SELECT 0x5a00 6986#define mmGRBM_GFX_INDEX_SR_SELECT_BASE_IDX 1 6987#define mmGRBM_GFX_INDEX_SR_DATA 0x5a01 6988#define mmGRBM_GFX_INDEX_SR_DATA_BASE_IDX 1 6989#define mmGRBM_GFX_CNTL_SR_SELECT 0x5a02 6990#define mmGRBM_GFX_CNTL_SR_SELECT_BASE_IDX 1 6991#define mmGRBM_GFX_CNTL_SR_DATA 0x5a03 6992#define mmGRBM_GFX_CNTL_SR_DATA_BASE_IDX 1 6993#define mmGRBM_CAM_INDEX 0x5a04 6994#define mmGRBM_CAM_INDEX_BASE_IDX 1 6995#define mmGRBM_HYP_CAM_INDEX 0x5a04 6996#define mmGRBM_HYP_CAM_INDEX_BASE_IDX 1 6997#define mmGRBM_CAM_DATA 0x5a05 6998#define mmGRBM_CAM_DATA_BASE_IDX 1 6999#define mmGRBM_HYP_CAM_DATA 0x5a05 7000#define mmGRBM_HYP_CAM_DATA_BASE_IDX 1
7001#define mmRLC_GPU_IOV_VF_ENABLE 0x5b00 7002#define mmRLC_GPU_IOV_VF_ENABLE_BASE_IDX 1 7003#define mmRLC_GFX_RM_CNTL_ADJ 0x5b01 7004#define mmRLC_GFX_RM_CNTL_ADJ_BASE_IDX 1 7005#define mmRLC_GPU_IOV_CFG_REG6 0x5b06 7006#define mmRLC_GPU_IOV_CFG_REG6_BASE_IDX 1 7007#define mmRLC_GPU_IOV_CFG_REG8 0x5b20 7008#define mmRLC_GPU_IOV_CFG_REG8_BASE_IDX 1 7009#define mmRLC_RLCV_TIMER_INT_0 0x5b25 7010#define mmRLC_RLCV_TIMER_INT_0_BASE_IDX 1 7011#define mmRLC_RLCV_TIMER_CTRL 0x5b26 7012#define mmRLC_RLCV_TIMER_CTRL_BASE_IDX 1 7013#define mmRLC_RLCV_TIMER_STAT 0x5b27 7014#define mmRLC_RLCV_TIMER_STAT_BASE_IDX 1 7015#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS 0x5b2a 7016#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX 1 7017#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET 0x5b2b 7018#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX 1 7019#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR 0x5b2c 7020#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX 1 7021#define mmRLC_GPU_IOV_VF_MASK 0x5b2d 7022#define mmRLC_GPU_IOV_VF_MASK_BASE_IDX 1 7023#define mmRLC_HYP_SEMAPHORE_2 0x5b2e 7024#define mmRLC_HYP_SEMAPHORE_2_BASE_IDX 1 7025#define mmRLC_HYP_SEMAPHORE_3 0x5b2f 7026#define mmRLC_HYP_SEMAPHORE_3_BASE_IDX 1 7027#define mmRLC_CLK_CNTL 0x5b31 7028#define mmRLC_CLK_CNTL_BASE_IDX 1 7029#define mmRLC_GPU_IOV_SCH_BLOCK 0x5b34 7030#define mmRLC_GPU_IOV_SCH_BLOCK_BASE_IDX 1 7031#define mmRLC_GPU_IOV_CFG_REG1 0x5b35 7032#define mmRLC_GPU_IOV_CFG_REG1_BASE_IDX 1 7033#define mmRLC_GPU_IOV_CFG_REG2 0x5b36 7034#define mmRLC_GPU_IOV_CFG_REG2_BASE_IDX 1 7035#define mmRLC_GPU_IOV_VM_BUSY_STATUS 0x5b37 7036#define mmRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX 1 7037#define mmRLC_GPU_IOV_SCH_0 0x5b38 7038#define mmRLC_GPU_IOV_SCH_0_BASE_IDX 1 7039#define mmRLC_GPU_IOV_ACTIVE_FCN_ID 0x5b39 7040#define mmRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX 1 7041#define mmRLC_GPU_IOV_SCH_3 0x5b3a 7042#define mmRLC_GPU_IOV_SCH_3_BASE_IDX 1 7043#define mmRLC_GPU_IOV_SCH_1 0x5b3b 7044#define mmRLC_GPU_IOV_SCH_1_BASE_IDX 1 7045#define mmRLC_GPU_IOV_SCH_2 0x5b3c 7046#define mmRLC_GPU_IOV_SCH_2_BASE_IDX 1 7047#define mmRLC_GPU_IOV_UCODE_ADDR 0x5b42 7048#define mmRLC_GPU_IOV_UCODE_ADDR_BASE_IDX 1 7049#define mmRLC_GPU_IOV_UCODE_DATA 0x5b43 7050#define mmRLC_GPU_IOV_UCODE_DATA_BASE_IDX 1 7051#define mmRLC_GPU_IOV_SCRATCH_ADDR 0x5b44 7052#define mmRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX 1 7053#define mmRLC_GPU_IOV_SCRATCH_DATA 0x5b45 7054#define mmRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX 1 7055#define mmRLC_GPU_IOV_F32_CNTL 0x5b46 7056#define mmRLC_GPU_IOV_F32_CNTL_BASE_IDX 1 7057#define mmRLC_GPU_IOV_F32_RESET 0x5b47 7058#define mmRLC_GPU_IOV_F32_RESET_BASE_IDX 1 7059#define mmRLC_GPU_IOV_SDMA0_STATUS 0x5b48 7060#define mmRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX 1 7061#define mmRLC_GPU_IOV_SDMA1_STATUS 0x5b49 7062#define mmRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX 1 7063#define mmRLC_GPU_IOV_SMU_RESPONSE 0x5b4a 7064#define mmRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX 1 7065#define mmRLC_GPU_IOV_VIRT_RESET_REQ 0x5b4c 7066#define mmRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX 1 7067#define mmRLC_GPU_IOV_RLC_RESPONSE 0x5b4d 7068#define mmRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX 1 7069#define mmRLC_GPU_IOV_INT_DISABLE 0x5b4e 7070#define mmRLC_GPU_IOV_INT_DISABLE_BASE_IDX 1 7071#define mmRLC_GPU_IOV_INT_FORCE 0x5b4f 7072#define mmRLC_GPU_IOV_INT_FORCE_BASE_IDX 1 7073#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS 0x5b50 7074#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX 1 7075#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS 0x5b51 7076#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX 1 7077 7078 7079// addressBlock: gccacind 7080// base address: 0x0 7081#define ixGC_CAC_CNTL 0x0000 7082#define ixGC_CAC_OVR_SEL 0x0001 7083#define ixGC_CAC_OVR_VAL 0x0002 7084#define ixGC_CAC_WEIGHT_BCI_0 0x0003 7085#define ixGC_CAC_WEIGHT_CB_0 0x0004 7086#define ixGC_CAC_WEIGHT_CB_1 0x0005 7087#define ixGC_CAC_WEIGHT_CP_0 0x0008 7088#define ixGC_CAC_WEIGHT_CP_1 0x0009 7089#define ixGC_CAC_WEIGHT_DB_0 0x000a 7090#define ixGC_CAC_WEIGHT_DB_1 0x000b 7091#define ixGC_CAC_WEIGHT_GDS_0 0x000e 7092#define ixGC_CAC_WEIGHT_GDS_1 0x000f 7093#define ixGC_CAC_WEIGHT_IA_0 0x0010 7094#define ixGC_CAC_WEIGHT_LDS_0 0x0011 7095#define ixGC_CAC_WEIGHT_LDS_1 0x0012 7096#define ixGC_CAC_WEIGHT_PA_0 0x0013 7097#define ixGC_CAC_WEIGHT_PC_0 0x0014 7098#define ixGC_CAC_WEIGHT_SC_0 0x0015 7099#define ixGC_CAC_WEIGHT_SPI_0 0x0016 7100#define ixGC_CAC_WEIGHT_SPI_1 0x0017 7101#define ixGC_CAC_WEIGHT_SPI_2 0x0018 7102#define ixGC_CAC_WEIGHT_SQ_0 0x001a 7103#define ixGC_CAC_WEIGHT_SQ_1 0x001b 7104#define ixGC_CAC_WEIGHT_SQ_2 0x001c 7105#define ixGC_CAC_WEIGHT_SQ_3 0x001d 7106#define ixGC_CAC_WEIGHT_SQ_4 0x001e 7107#define ixGC_CAC_WEIGHT_SX_0 0x001f 7108#define ixGC_CAC_WEIGHT_SXRB_0 0x0020 7109#define ixGC_CAC_WEIGHT_TA_0 0x0021 7110#define ixGC_CAC_WEIGHT_TCC_0 0x0022 7111#define ixGC_CAC_WEIGHT_TCC_1 0x0023 7112#define ixGC_CAC_WEIGHT_TCC_2 0x0024 7113#define ixGC_CAC_WEIGHT_TCP_0 0x0025 7114#define ixGC_CAC_WEIGHT_TCP_1 0x0026 7115#define ixGC_CAC_WEIGHT_TCP_2 0x0027 7116#define ixGC_CAC_WEIGHT_TD_0 0x0028 7117#define ixGC_CAC_WEIGHT_TD_1 0x0029 7118#define ixGC_CAC_WEIGHT_TD_2 0x002a 7119#define ixGC_CAC_WEIGHT_VGT_0 0x002b 7120#define ixGC_CAC_WEIGHT_VGT_1 0x002c 7121#define ixGC_CAC_WEIGHT_WD_0 0x002d 7122#define ixGC_CAC_WEIGHT_CU_0 0x0032 7123#define ixGC_CAC_WEIGHT_CU_1 0x0033 7124#define ixGC_CAC_WEIGHT_CU_2 0x0034 7125#define ixGC_CAC_WEIGHT_CU_3 0x0035 7126#define ixGC_CAC_WEIGHT_CU_4 0x0036 7127#define ixGC_CAC_WEIGHT_CU_5 0x0037 7128#define ixGC_CAC_ACC_BCI0 0x0042 7129#define ixGC_CAC_ACC_CB0 0x0043 7130#define ixGC_CAC_ACC_CB1 0x0044 7131#define ixGC_CAC_ACC_CB2 0x0045 7132#define ixGC_CAC_ACC_CB3 0x0046 7133#define ixGC_CAC_ACC_CP0 0x004b 7134#define ixGC_CAC_ACC_CP1 0x004c 7135#define ixGC_CAC_ACC_CP2 0x004d 7136#define ixGC_CAC_ACC_DB0 0x004e 7137#define ixGC_CAC_ACC_DB1 0x004f 7138#define ixGC_CAC_ACC_DB2 0x0050 7139#define ixGC_CAC_ACC_DB3 0x0051 7140#define ixGC_CAC_ACC_GDS0 0x0056 7141#define ixGC_CAC_ACC_GDS1 0x0057 7142#define ixGC_CAC_ACC_GDS2 0x0058 7143#define ixGC_CAC_ACC_GDS3 0x0059 7144#define ixGC_CAC_ACC_IA0 0x005a 7145#define ixGC_CAC_ACC_LDS0 0x005b 7146#define ixGC_CAC_ACC_LDS1 0x005c 7147#define ixGC_CAC_ACC_LDS2 0x005d 7148#define ixGC_CAC_ACC_LDS3 0x005e 7149#define ixGC_CAC_ACC_PA0 0x005f 7150#define ixGC_CAC_ACC_PA1 0x0060 7151#define ixGC_CAC_ACC_PC0 0x0061 7152#define ixGC_CAC_ACC_SC0 0x0062 7153#define ixGC_CAC_ACC_SPI0 0x0063 7154#define ixGC_CAC_ACC_SPI1 0x0064 7155#define ixGC_CAC_ACC_SPI2 0x0065 7156#define ixGC_CAC_ACC_SPI3 0x0066 7157#define ixGC_CAC_ACC_SPI4 0x0067 7158#define ixGC_CAC_ACC_SPI5 0x0068 7159#define ixGC_CAC_WEIGHT_PG_0 0x0069 7160#define ixGC_CAC_ACC_PG0 0x006a 7161#define ixGC_CAC_OVRD_PG 0x006b 7162#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_0 0x006f 7163#define ixGC_CAC_ACC_EA0 0x0070 7164#define ixGC_CAC_ACC_EA1 0x0071 7165#define ixGC_CAC_ACC_EA2 0x0072 7166#define ixGC_CAC_ACC_EA3 0x0073 7167#define ixGC_CAC_ACC_UTCL2_ATCL20 0x0074 7168#define ixGC_CAC_OVRD_EA 0x0075 7169#define ixGC_CAC_OVRD_UTCL2_ATCL2 0x0076 7170#define ixGC_CAC_WEIGHT_EA_0 0x0077 7171#define ixGC_CAC_WEIGHT_EA_1 0x0078 7172#define ixGC_CAC_WEIGHT_RMI_0 0x0079 7173#define ixGC_CAC_ACC_RMI0 0x007a 7174#define ixGC_CAC_OVRD_RMI 0x007b 7175#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_1 0x007c 7176#define ixGC_CAC_ACC_UTCL2_ATCL21 0x007d 7177#define ixGC_CAC_ACC_UTCL2_ATCL22 0x007e 7178#define ixGC_CAC_ACC_UTCL2_ATCL23 0x007f 7179#define ixGC_CAC_ACC_EA4 0x0080 7180#define ixGC_CAC_ACC_EA5 0x0081 7181#define ixGC_CAC_WEIGHT_EA_2 0x0082 7182#define ixGC_CAC_ACC_SQ0_LOWER 0x0089 7183#define ixGC_CAC_ACC_SQ0_UPPER 0x008a 7184#define ixGC_CAC_ACC_SQ1_LOWER 0x008b 7185#define ixGC_CAC_ACC_SQ1_UPPER 0x008c 7186#define ixGC_CAC_ACC_SQ2_LOWER 0x008d 7187#define ixGC_CAC_ACC_SQ2_UPPER 0x008e 7188#define ixGC_CAC_ACC_SQ3_LOWER 0x008f 7189#define ixGC_CAC_ACC_SQ3_UPPER 0x0090 7190#define ixGC_CAC_ACC_SQ4_LOWER 0x0091 7191#define ixGC_CAC_ACC_SQ4_UPPER 0x0092 7192#define ixGC_CAC_ACC_SQ5_LOWER 0x0093 7193#define ixGC_CAC_ACC_SQ5_UPPER 0x0094 7194#define ixGC_CAC_ACC_SQ6_LOWER 0x0095 7195#define ixGC_CAC_ACC_SQ6_UPPER 0x0096 7196#define ixGC_CAC_ACC_SQ7_LOWER 0x0097 7197#define ixGC_CAC_ACC_SQ7_UPPER 0x0098 7198#define ixGC_CAC_ACC_SQ8_LOWER 0x0099 7199#define ixGC_CAC_ACC_SQ8_UPPER 0x009a 7200#define ixGC_CAC_ACC_SX0 0x009b 7201#define ixGC_CAC_ACC_SXRB0 0x009c 7202#define ixGC_CAC_ACC_SXRB1 0x009d 7203#define ixGC_CAC_ACC_TA0 0x009e 7204#define ixGC_CAC_ACC_TCC0 0x009f 7205#define ixGC_CAC_ACC_TCC1 0x00a0 7206#define ixGC_CAC_ACC_TCC2 0x00a1 7207#define ixGC_CAC_ACC_TCC3 0x00a2 7208#define ixGC_CAC_ACC_TCC4 0x00a3 7209#define ixGC_CAC_ACC_TCP0 0x00a4 7210#define ixGC_CAC_ACC_TCP1 0x00a5 7211#define ixGC_CAC_ACC_TCP2 0x00a6 7212#define ixGC_CAC_ACC_TCP3 0x00a7 7213#define ixGC_CAC_ACC_TCP4 0x00a8 7214#define ixGC_CAC_ACC_TD0 0x00a9 7215#define ixGC_CAC_ACC_TD1 0x00aa 7216#define ixGC_CAC_ACC_TD2 0x00ab 7217#define ixGC_CAC_ACC_TD3 0x00ac 7218#define ixGC_CAC_ACC_TD4 0x00ad 7219#define ixGC_CAC_ACC_TD5 0x00ae 7220#define ixGC_CAC_ACC_VGT0 0x00af 7221#define ixGC_CAC_ACC_VGT1 0x00b0 7222#define ixGC_CAC_ACC_VGT2 0x00b1 7223#define ixGC_CAC_ACC_WD0 0x00b2 7224#define ixGC_CAC_ACC_CU0 0x00ba 7225#define ixGC_CAC_ACC_CU1 0x00bb 7226#define ixGC_CAC_ACC_CU2 0x00bc 7227#define ixGC_CAC_ACC_CU3 0x00bd 7228#define ixGC_CAC_ACC_CU4 0x00be 7229#define ixGC_CAC_ACC_CU5 0x00bf 7230#define ixGC_CAC_ACC_CU6 0x00c0 7231#define ixGC_CAC_ACC_CU7 0x00c1 7232#define ixGC_CAC_ACC_CU8 0x00c2 7233#define ixGC_CAC_ACC_CU9 0x00c3 7234#define ixGC_CAC_ACC_CU10 0x00c4 7235#define ixGC_CAC_OVRD_BCI 0x00da 7236#define ixGC_CAC_OVRD_CB 0x00db 7237#define ixGC_CAC_OVRD_CP 0x00dd 7238#define ixGC_CAC_OVRD_DB 0x00de 7239#define ixGC_CAC_OVRD_GDS 0x00e0 7240#define ixGC_CAC_OVRD_IA 0x00e1 7241#define ixGC_CAC_OVRD_LDS 0x00e2 7242#define ixGC_CAC_OVRD_PA 0x00e3 7243#define ixGC_CAC_OVRD_PC 0x00e4 7244#define ixGC_CAC_OVRD_SC 0x00e5 7245#define ixGC_CAC_OVRD_SPI 0x00e6 7246#define ixGC_CAC_OVRD_CU 0x00e7 7247#define ixGC_CAC_OVRD_SQ 0x00e8 7248#define ixGC_CAC_OVRD_SX 0x00e9 7249#define ixGC_CAC_OVRD_SXRB 0x00ea 7250#define ixGC_CAC_OVRD_TA 0x00eb 7251#define ixGC_CAC_OVRD_TCC 0x00ec 7252#define ixGC_CAC_OVRD_TCP 0x00ed 7253#define ixGC_CAC_OVRD_TD 0x00ee 7254#define ixGC_CAC_OVRD_VGT 0x00ef 7255#define ixGC_CAC_OVRD_WD 0x00f0 7256#define ixGC_CAC_ACC_BCI1 0x00ff 7257#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_2 0x0100 7258#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_0 0x0101 7259#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_1 0x0102 7260#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_2 0x0103 7261#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_3 0x0104 7262#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_4 0x0105 7263#define ixGC_CAC_WEIGHT_UTCL2_VML2_0 0x0106 7264#define ixGC_CAC_WEIGHT_UTCL2_VML2_1 0x0107 7265#define ixGC_CAC_WEIGHT_UTCL2_VML2_2 0x0108 7266#define ixGC_CAC_ACC_UTCL2_ATCL24 0x0109 7267#define ixGC_CAC_ACC_UTCL2_ROUTER0 0x010a 7268#define ixGC_CAC_ACC_UTCL2_ROUTER1 0x010b 7269#define ixGC_CAC_ACC_UTCL2_ROUTER2 0x010c 7270#define ixGC_CAC_ACC_UTCL2_ROUTER3 0x010d 7271#define ixGC_CAC_ACC_UTCL2_ROUTER4 0x010e 7272#define ixGC_CAC_ACC_UTCL2_ROUTER5 0x010f 7273#define ixGC_CAC_ACC_UTCL2_ROUTER6 0x0110 7274#define ixGC_CAC_ACC_UTCL2_ROUTER7 0x0111 7275#define ixGC_CAC_ACC_UTCL2_ROUTER8 0x0112 7276#define ixGC_CAC_ACC_UTCL2_ROUTER9 0x0113 7277#define ixGC_CAC_ACC_UTCL2_VML20 0x0114 7278#define ixGC_CAC_ACC_UTCL2_VML21 0x0115 7279#define ixGC_CAC_ACC_UTCL2_VML22 0x0116 7280#define ixGC_CAC_ACC_UTCL2_VML23 0x0117 7281#define ixGC_CAC_ACC_UTCL2_VML24 0x0118 7282#define ixGC_CAC_OVRD_UTCL2_ROUTER 0x0119 7283#define ixGC_CAC_OVRD_UTCL2_VML2 0x011a 7284#define ixGC_CAC_WEIGHT_UTCL2_WALKER_0 0x011b 7285#define ixGC_CAC_WEIGHT_UTCL2_WALKER_1 0x011c 7286#define ixGC_CAC_WEIGHT_UTCL2_WALKER_2 0x011d 7287#define ixGC_CAC_ACC_UTCL2_WALKER0 0x011e 7288#define ixGC_CAC_ACC_UTCL2_WALKER1 0x011f 7289#define ixGC_CAC_ACC_UTCL2_WALKER2 0x0120 7290#define ixGC_CAC_ACC_UTCL2_WALKER3 0x0121 7291#define ixGC_CAC_ACC_UTCL2_WALKER4 0x0122 7292#define ixGC_CAC_OVRD_UTCL2_WALKER 0x0123 7293 7294 7295// addressBlock: secacind 7296// base address: 0x0 7297#define ixSE_CAC_CNTL 0x0000 7298#define ixSE_CAC_OVR_SEL 0x0001 7299#define ixSE_CAC_OVR_VAL 0x0002 7300 7301 7302// addressBlock: sqind 7303// base address: 0x0 7304#define ixSQ_DEBUG_STS_LOCAL 0x0008 7305#define ixSQ_WAVE_MODE 0x0011 7306#define ixSQ_WAVE_STATUS 0x0012 7307#define ixSQ_WAVE_TRAPSTS 0x0013 7308#define ixSQ_WAVE_HW_ID 0x0014 7309#define ixSQ_WAVE_GPR_ALLOC 0x0015 7310#define ixSQ_WAVE_LDS_ALLOC 0x0016 7311#define ixSQ_WAVE_IB_STS 0x0017 7312#define ixSQ_WAVE_PC_LO 0x0018 7313#define ixSQ_WAVE_PC_HI 0x0019 7314#define ixSQ_WAVE_INST_DW0 0x001a 7315#define ixSQ_WAVE_INST_DW1 0x001b 7316#define ixSQ_WAVE_IB_DBG0 0x001c 7317#define ixSQ_WAVE_IB_DBG1 0x001d 7318#define ixSQ_WAVE_FLUSH_IB 0x001e 7319#define ixSQ_WAVE_TTMP0 0x026c 7320#define ixSQ_WAVE_TTMP1 0x026d 7321#define ixSQ_WAVE_TTMP2 0x026e 7322#define ixSQ_WAVE_TTMP3 0x026f 7323#define ixSQ_WAVE_TTMP4 0x0270 7324#define ixSQ_WAVE_TTMP5 0x0271 7325#define ixSQ_WAVE_TTMP6 0x0272 7326#define ixSQ_WAVE_TTMP7 0x0273 7327#define ixSQ_WAVE_TTMP8 0x0274 7328#define ixSQ_WAVE_TTMP9 0x0275 7329#define ixSQ_WAVE_TTMP10 0x0276 7330#define ixSQ_WAVE_TTMP11 0x0277 7331#define ixSQ_WAVE_TTMP12 0x0278 7332#define ixSQ_WAVE_TTMP13 0x0279 7333#define ixSQ_WAVE_TTMP14 0x027a 7334#define ixSQ_WAVE_TTMP15 0x027b 7335#define ixSQ_WAVE_M0 0x027c 7336#define ixSQ_WAVE_EXEC_LO 0x027e 7337#define ixSQ_WAVE_EXEC_HI 0x027f 7338#define ixSQ_INTERRUPT_WORD_AUTO_CTXID 0x20c0 7339#define ixSQ_INTERRUPT_WORD_AUTO_HI 0x20c0 7340#define ixSQ_INTERRUPT_WORD_AUTO_LO 0x20c0 7341#define ixSQ_INTERRUPT_WORD_CMN_CTXID 0x20c0 7342#define ixSQ_INTERRUPT_WORD_CMN_HI 0x20c0 7343#define ixSQ_INTERRUPT_WORD_WAVE_CTXID 0x20c0 7344#define ixSQ_INTERRUPT_WORD_WAVE_HI 0x20c0 7345#define ixSQ_INTERRUPT_WORD_WAVE_LO 0x20c0 7346 7347 7348// addressBlock: didtind 7349// base address: 0x0 7350#define ixDIDT_SQ_CTRL0 0x0000 7351#define ixDIDT_SQ_CTRL1 0x0001 7352#define ixDIDT_SQ_CTRL2 0x0002 7353#define ixDIDT_SQ_STALL_CTRL 0x0004 7354#define ixDIDT_SQ_TUNING_CTRL 0x0005 7355#define ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL 0x0006 7356#define ixDIDT_SQ_CTRL3 0x0007 7357#define ixDIDT_SQ_STALL_PATTERN_1_2 0x0008 7358#define ixDIDT_SQ_STALL_PATTERN_3_4 0x0009 7359#define ixDIDT_SQ_STALL_PATTERN_5_6 0x000a 7360#define ixDIDT_SQ_STALL_PATTERN_7 0x000b 7361#define ixDIDT_SQ_WEIGHT0_3 0x0010 7362#define ixDIDT_SQ_WEIGHT4_7 0x0011 7363#define ixDIDT_SQ_WEIGHT8_11 0x0012 7364#define ixDIDT_SQ_EDC_CTRL 0x0013 7365#define ixDIDT_SQ_EDC_THRESHOLD 0x0014 7366#define ixDIDT_SQ_EDC_STALL_PATTERN_1_2 0x0015 7367#define ixDIDT_SQ_EDC_STALL_PATTERN_3_4 0x0016 7368#define ixDIDT_SQ_EDC_STALL_PATTERN_5_6 0x0017 7369#define ixDIDT_SQ_EDC_STALL_PATTERN_7 0x0018 7370#define ixDIDT_SQ_EDC_STATUS 0x0019 7371#define ixDIDT_SQ_EDC_STALL_DELAY_1 0x001a 7372#define ixDIDT_SQ_EDC_STALL_DELAY_2 0x001b 7373#define ixDIDT_SQ_EDC_STALL_DELAY_3 0x001c 7374#define ixDIDT_SQ_EDC_OVERFLOW 0x001e 7375#define ixDIDT_SQ_EDC_ROLLING_POWER_DELTA 0x001f 7376#define ixDIDT_DB_CTRL0 0x0020 7377#define ixDIDT_DB_CTRL1 0x0021 7378#define ixDIDT_DB_CTRL2 0x0022 7379#define ixDIDT_DB_STALL_CTRL 0x0024 7380#define ixDIDT_DB_TUNING_CTRL 0x0025 7381#define ixDIDT_DB_STALL_AUTO_RELEASE_CTRL 0x0026 7382#define ixDIDT_DB_CTRL3 0x0027 7383#define ixDIDT_DB_STALL_PATTERN_1_2 0x0028 7384#define ixDIDT_DB_STALL_PATTERN_3_4 0x0029 7385#define ixDIDT_DB_STALL_PATTERN_5_6 0x002a 7386#define ixDIDT_DB_STALL_PATTERN_7 0x002b 7387#define ixDIDT_DB_WEIGHT0_3 0x0030 7388#define ixDIDT_DB_WEIGHT4_7 0x0031 7389#define ixDIDT_DB_WEIGHT8_11 0x0032 7390#define ixDIDT_DB_EDC_CTRL 0x0033 7391#define ixDIDT_DB_EDC_THRESHOLD 0x0034 7392#define ixDIDT_DB_EDC_STALL_PATTERN_1_2 0x0035 7393#define ixDIDT_DB_EDC_STALL_PATTERN_3_4 0x0036 7394#define ixDIDT_DB_EDC_STALL_PATTERN_5_6 0x0037 7395#define ixDIDT_DB_EDC_STALL_PATTERN_7 0x0038 7396#define ixDIDT_DB_EDC_STATUS 0x0039 7397#define ixDIDT_DB_EDC_STALL_DELAY_1 0x003a 7398#define ixDIDT_DB_EDC_OVERFLOW 0x003e 7399#define ixDIDT_DB_EDC_ROLLING_POWER_DELTA 0x003f 7400#define ixDIDT_TD_CTRL0 0x0040 7401#define ixDIDT_TD_CTRL1 0x0041 7402#define ixDIDT_TD_CTRL2 0x0042 7403#define ixDIDT_TD_STALL_CTRL 0x0044 7404#define ixDIDT_TD_TUNING_CTRL 0x0045 7405#define ixDIDT_TD_STALL_AUTO_RELEASE_CTRL 0x0046 7406#define ixDIDT_TD_CTRL3 0x0047 7407#define ixDIDT_TD_STALL_PATTERN_1_2 0x0048 7408#define ixDIDT_TD_STALL_PATTERN_3_4 0x0049 7409#define ixDIDT_TD_STALL_PATTERN_5_6 0x004a 7410#define ixDIDT_TD_STALL_PATTERN_7 0x004b 7411#define ixDIDT_TD_WEIGHT0_3 0x0050 7412#define ixDIDT_TD_WEIGHT4_7 0x0051 7413#define ixDIDT_TD_WEIGHT8_11 0x0052 7414#define ixDIDT_TD_EDC_CTRL 0x0053 7415#define ixDIDT_TD_EDC_THRESHOLD 0x0054 7416#define ixDIDT_TD_EDC_STALL_PATTERN_1_2 0x0055 7417#define ixDIDT_TD_EDC_STALL_PATTERN_3_4 0x0056 7418#define ixDIDT_TD_EDC_STALL_PATTERN_5_6 0x0057 7419#define ixDIDT_TD_EDC_STALL_PATTERN_7 0x0058 7420#define ixDIDT_TD_EDC_STATUS 0x0059 7421#define ixDIDT_TD_EDC_STALL_DELAY_1 0x005a 7422#define ixDIDT_TD_EDC_STALL_DELAY_2 0x005b 7423#define ixDIDT_TD_EDC_STALL_DELAY_3 0x005c 7424#define ixDIDT_TD_EDC_OVERFLOW 0x005e 7425#define ixDIDT_TD_EDC_ROLLING_POWER_DELTA 0x005f 7426#define ixDIDT_TCP_CTRL0 0x0060 7427#define ixDIDT_TCP_CTRL1 0x0061 7428#define ixDIDT_TCP_CTRL2 0x0062 7429#define ixDIDT_TCP_STALL_CTRL 0x0064 7430#define ixDIDT_TCP_TUNING_CTRL 0x0065 7431#define ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL 0x0066 7432#define ixDIDT_TCP_CTRL3 0x0067 7433#define ixDIDT_TCP_STALL_PATTERN_1_2 0x0068 7434#define ixDIDT_TCP_STALL_PATTERN_3_4 0x0069 7435#define ixDIDT_TCP_STALL_PATTERN_5_6 0x006a 7436#define ixDIDT_TCP_STALL_PATTERN_7 0x006b 7437#define ixDIDT_TCP_WEIGHT0_3 0x0070 7438#define ixDIDT_TCP_WEIGHT4_7 0x0071 7439#define ixDIDT_TCP_WEIGHT8_11 0x0072 7440#define ixDIDT_TCP_EDC_CTRL 0x0073 7441#define ixDIDT_TCP_EDC_THRESHOLD 0x0074 7442#define ixDIDT_TCP_EDC_STALL_PATTERN_1_2 0x0075 7443#define ixDIDT_TCP_EDC_STALL_PATTERN_3_4 0x0076 7444#define ixDIDT_TCP_EDC_STALL_PATTERN_5_6 0x0077 7445#define ixDIDT_TCP_EDC_STALL_PATTERN_7 0x0078 7446#define ixDIDT_TCP_EDC_STATUS 0x0079 7447#define ixDIDT_TCP_EDC_STALL_DELAY_1 0x007a 7448#define ixDIDT_TCP_EDC_STALL_DELAY_2 0x007b 7449#define ixDIDT_TCP_EDC_STALL_DELAY_3 0x007c 7450#define ixDIDT_TCP_EDC_OVERFLOW 0x007e 7451#define ixDIDT_TCP_EDC_ROLLING_POWER_DELTA 0x007f 7452#define ixDIDT_DBR_CTRL0 0x0080 7453#define ixDIDT_DBR_CTRL1 0x0081 7454#define ixDIDT_DBR_CTRL2 0x0082 7455#define ixDIDT_DBR_STALL_CTRL 0x0084 7456#define ixDIDT_DBR_TUNING_CTRL 0x0085 7457#define ixDIDT_DBR_STALL_AUTO_RELEASE_CTRL 0x0086 7458#define ixDIDT_DBR_CTRL3 0x0087 7459#define ixDIDT_DBR_STALL_PATTERN_1_2 0x0088 7460#define ixDIDT_DBR_STALL_PATTERN_3_4 0x0089 7461#define ixDIDT_DBR_STALL_PATTERN_5_6 0x008a 7462#define ixDIDT_DBR_STALL_PATTERN_7 0x008b 7463#define ixDIDT_DBR_WEIGHT0_3 0x0090 7464#define ixDIDT_DBR_WEIGHT4_7 0x0091 7465#define ixDIDT_DBR_WEIGHT8_11 0x0092 7466#define ixDIDT_DBR_EDC_CTRL 0x0093 7467#define ixDIDT_DBR_EDC_THRESHOLD 0x0094 7468#define ixDIDT_DBR_EDC_STALL_PATTERN_1_2 0x0095 7469#define ixDIDT_DBR_EDC_STALL_PATTERN_3_4 0x0096 7470#define ixDIDT_DBR_EDC_STALL_PATTERN_5_6 0x0097 7471#define ixDIDT_DBR_EDC_STALL_PATTERN_7 0x0098 7472#define ixDIDT_DBR_EDC_STATUS 0x0099 7473#define ixDIDT_DBR_EDC_STALL_DELAY_1 0x009a 7474#define ixDIDT_DBR_EDC_OVERFLOW 0x009e 7475#define ixDIDT_DBR_EDC_ROLLING_POWER_DELTA 0x009f 7476#define ixDIDT_SQ_STALL_EVENT_COUNTER 0x00a0 7477#define ixDIDT_DB_STALL_EVENT_COUNTER 0x00a1 7478#define ixDIDT_TD_STALL_EVENT_COUNTER 0x00a2 7479#define ixDIDT_TCP_STALL_EVENT_COUNTER 0x00a3 7480#define ixDIDT_DBR_STALL_EVENT_COUNTER 0x00a4 7481 7482 7483#endif 7484