LXR linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c

   1/*
   2 * Copyright 2012 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Ben Skeggs
  23 */
  24#include "nv40.h"
  25#include "regs.h"
  26
  27#include <subdev/fb.h>
  28#include <engine/fifo.h>
  29
  30static void
  31nv44_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile)
  32{
  33        struct nv40_gr *gr = nv40_gr(base);
  34        struct nvkm_device *device = gr->base.engine.subdev.device;
  35        struct nvkm_fifo *fifo = device->fifo;
  36        unsigned long flags;
  37
  38        nvkm_fifo_pause(fifo, &flags);
  39        nv04_gr_idle(&gr->base);
  40
  41        switch (device->chipset) {
  42        case 0x44:
  43        case 0x4a:
  44                nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
  45                nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
  46                nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);
  47                break;
  48        case 0x46:
  49        case 0x4c:
  50        case 0x63:
  51        case 0x67:
  52        case 0x68:
  53                nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch);
  54                nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit);
  55                nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr);
  56                nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch);
  57                nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit);
  58                nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr);
  59                break;
  60        case 0x4e:
  61                nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
  62                nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
  63                nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);
  64                nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch);
  65                nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit);
  66                nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr);
  67                break;
  68        default:
  69                WARN_ON(1);
  70                break;
  71        }
  72
  73        nvkm_fifo_start(fifo, &flags);
  74}
  75
  76static const struct nvkm_gr_func
  77nv44_gr = {
  78        .init = nv40_gr_init,
  79        .intr = nv40_gr_intr,
  80        .tile = nv44_gr_tile,
  81        .units = nv40_gr_units,
  82        .chan_new = nv40_gr_chan_new,
  83        .sclass = {
  84                { -1, -1, 0x0012, &nv40_gr_object }, /* beta1 */
  85                { -1, -1, 0x0019, &nv40_gr_object }, /* clip */
  86                { -1, -1, 0x0030, &nv40_gr_object }, /* null */
  87                { -1, -1, 0x0039, &nv40_gr_object }, /* m2mf */
  88                { -1, -1, 0x0043, &nv40_gr_object }, /* rop */
  89                { -1, -1, 0x0044, &nv40_gr_object }, /* patt */
  90                { -1, -1, 0x004a, &nv40_gr_object }, /* gdi */
  91                { -1, -1, 0x0062, &nv40_gr_object }, /* surf2d */
  92                { -1, -1, 0x0072, &nv40_gr_object }, /* beta4 */
  93                { -1, -1, 0x0089, &nv40_gr_object }, /* sifm */
  94                { -1, -1, 0x008a, &nv40_gr_object }, /* ifc */
  95                { -1, -1, 0x009f, &nv40_gr_object }, /* imageblit */
  96                { -1, -1, 0x3062, &nv40_gr_object }, /* surf2d (nv40) */
  97                { -1, -1, 0x3089, &nv40_gr_object }, /* sifm (nv40) */
  98                { -1, -1, 0x309e, &nv40_gr_object }, /* swzsurf (nv40) */
  99                { -1, -1, 0x4497, &nv40_gr_object }, /* curie */
 100                {}
 101        }
 102};
 103
 104int
 105nv44_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
 106{
 107        return nv40_gr_new_(&nv44_gr, device, type, inst, pgr);
 108}
 109