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35#ifndef __R128_DRV_H__
36#define __R128_DRV_H__
37
38#include <drm/ati_pcigart.h>
39#include <drm/drm_legacy.h>
40
41
42
43#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc."
44
45#define DRIVER_NAME "r128"
46#define DRIVER_DESC "ATI Rage 128"
47#define DRIVER_DATE "20030725"
48
49
50
51
52
53
54
55#define DRIVER_MAJOR 2
56#define DRIVER_MINOR 5
57#define DRIVER_PATCHLEVEL 0
58
59#define GET_RING_HEAD(dev_priv) R128_READ(R128_PM4_BUFFER_DL_RPTR)
60
61typedef struct drm_r128_freelist {
62 unsigned int age;
63 struct drm_buf *buf;
64 struct drm_r128_freelist *next;
65 struct drm_r128_freelist *prev;
66} drm_r128_freelist_t;
67
68typedef struct drm_r128_ring_buffer {
69 u32 *start;
70 u32 *end;
71 int size;
72 int size_l2qw;
73
74 u32 tail;
75 u32 tail_mask;
76 int space;
77
78 int high_mark;
79} drm_r128_ring_buffer_t;
80
81typedef struct drm_r128_private {
82 drm_r128_ring_buffer_t ring;
83 drm_r128_sarea_t *sarea_priv;
84
85 int cce_mode;
86 int cce_fifo_size;
87 int cce_running;
88
89 drm_r128_freelist_t *head;
90 drm_r128_freelist_t *tail;
91
92 int usec_timeout;
93 int is_pci;
94 unsigned long cce_buffers_offset;
95
96 atomic_t idle_count;
97
98 int page_flipping;
99 int current_page;
100 u32 crtc_offset;
101 u32 crtc_offset_cntl;
102
103 atomic_t vbl_received;
104
105 u32 color_fmt;
106 unsigned int front_offset;
107 unsigned int front_pitch;
108 unsigned int back_offset;
109 unsigned int back_pitch;
110
111 u32 depth_fmt;
112 unsigned int depth_offset;
113 unsigned int depth_pitch;
114 unsigned int span_offset;
115
116 u32 front_pitch_offset_c;
117 u32 back_pitch_offset_c;
118 u32 depth_pitch_offset_c;
119 u32 span_pitch_offset_c;
120
121 drm_local_map_t *sarea;
122 drm_local_map_t *mmio;
123 drm_local_map_t *cce_ring;
124 drm_local_map_t *ring_rptr;
125 drm_local_map_t *agp_textures;
126 struct drm_ati_pcigart_info gart_info;
127} drm_r128_private_t;
128
129typedef struct drm_r128_buf_priv {
130 u32 age;
131 int prim;
132 int discard;
133 int dispatched;
134 drm_r128_freelist_t *list_entry;
135} drm_r128_buf_priv_t;
136
137extern const struct drm_ioctl_desc r128_ioctls[];
138extern int r128_max_ioctl;
139
140
141extern int r128_cce_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
142extern int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
143extern int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
144extern int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
145extern int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
146extern int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
147extern int r128_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
148extern int r128_cce_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
149
150extern int r128_cce_stipple(struct drm_device *dev, void *data, struct drm_file *file_priv);
151extern int r128_cce_depth(struct drm_device *dev, void *data, struct drm_file *file_priv);
152extern int r128_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv);
153
154extern void r128_freelist_reset(struct drm_device *dev);
155
156extern int r128_wait_ring(drm_r128_private_t *dev_priv, int n);
157
158extern int r128_do_cce_idle(drm_r128_private_t *dev_priv);
159extern int r128_do_cleanup_cce(struct drm_device *dev);
160
161extern int r128_enable_vblank(struct drm_device *dev, unsigned int pipe);
162extern void r128_disable_vblank(struct drm_device *dev, unsigned int pipe);
163extern u32 r128_get_vblank_counter(struct drm_device *dev, unsigned int pipe);
164extern irqreturn_t r128_driver_irq_handler(int irq, void *arg);
165extern void r128_driver_irq_preinstall(struct drm_device *dev);
166extern int r128_driver_irq_postinstall(struct drm_device *dev);
167extern void r128_driver_irq_uninstall(struct drm_device *dev);
168extern void r128_driver_lastclose(struct drm_device *dev);
169extern int r128_driver_load(struct drm_device *dev, unsigned long flags);
170extern void r128_driver_preclose(struct drm_device *dev,
171 struct drm_file *file_priv);
172
173extern long r128_compat_ioctl(struct file *filp, unsigned int cmd,
174 unsigned long arg);
175
176
177
178
179
180#define R128_AUX_SC_CNTL 0x1660
181# define R128_AUX1_SC_EN (1 << 0)
182# define R128_AUX1_SC_MODE_OR (0 << 1)
183# define R128_AUX1_SC_MODE_NAND (1 << 1)
184# define R128_AUX2_SC_EN (1 << 2)
185# define R128_AUX2_SC_MODE_OR (0 << 3)
186# define R128_AUX2_SC_MODE_NAND (1 << 3)
187# define R128_AUX3_SC_EN (1 << 4)
188# define R128_AUX3_SC_MODE_OR (0 << 5)
189# define R128_AUX3_SC_MODE_NAND (1 << 5)
190#define R128_AUX1_SC_LEFT 0x1664
191#define R128_AUX1_SC_RIGHT 0x1668
192#define R128_AUX1_SC_TOP 0x166c
193#define R128_AUX1_SC_BOTTOM 0x1670
194#define R128_AUX2_SC_LEFT 0x1674
195#define R128_AUX2_SC_RIGHT 0x1678
196#define R128_AUX2_SC_TOP 0x167c
197#define R128_AUX2_SC_BOTTOM 0x1680
198#define R128_AUX3_SC_LEFT 0x1684
199#define R128_AUX3_SC_RIGHT 0x1688
200#define R128_AUX3_SC_TOP 0x168c
201#define R128_AUX3_SC_BOTTOM 0x1690
202
203#define R128_BRUSH_DATA0 0x1480
204#define R128_BUS_CNTL 0x0030
205# define R128_BUS_MASTER_DIS (1 << 6)
206
207#define R128_CLOCK_CNTL_INDEX 0x0008
208#define R128_CLOCK_CNTL_DATA 0x000c
209# define R128_PLL_WR_EN (1 << 7)
210#define R128_CONSTANT_COLOR_C 0x1d34
211#define R128_CRTC_OFFSET 0x0224
212#define R128_CRTC_OFFSET_CNTL 0x0228
213# define R128_CRTC_OFFSET_FLIP_CNTL (1 << 16)
214
215#define R128_DP_GUI_MASTER_CNTL 0x146c
216# define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
217# define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
218# define R128_GMC_BRUSH_SOLID_COLOR (13 << 4)
219# define R128_GMC_BRUSH_NONE (15 << 4)
220# define R128_GMC_DST_16BPP (4 << 8)
221# define R128_GMC_DST_24BPP (5 << 8)
222# define R128_GMC_DST_32BPP (6 << 8)
223# define R128_GMC_DST_DATATYPE_SHIFT 8
224# define R128_GMC_SRC_DATATYPE_COLOR (3 << 12)
225# define R128_DP_SRC_SOURCE_MEMORY (2 << 24)
226# define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24)
227# define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28)
228# define R128_GMC_AUX_CLIP_DIS (1 << 29)
229# define R128_GMC_WR_MSK_DIS (1 << 30)
230# define R128_ROP3_S 0x00cc0000
231# define R128_ROP3_P 0x00f00000
232#define R128_DP_WRITE_MASK 0x16cc
233#define R128_DST_PITCH_OFFSET_C 0x1c80
234# define R128_DST_TILE (1 << 31)
235
236#define R128_GEN_INT_CNTL 0x0040
237# define R128_CRTC_VBLANK_INT_EN (1 << 0)
238#define R128_GEN_INT_STATUS 0x0044
239# define R128_CRTC_VBLANK_INT (1 << 0)
240# define R128_CRTC_VBLANK_INT_AK (1 << 0)
241#define R128_GEN_RESET_CNTL 0x00f0
242# define R128_SOFT_RESET_GUI (1 << 0)
243
244#define R128_GUI_SCRATCH_REG0 0x15e0
245#define R128_GUI_SCRATCH_REG1 0x15e4
246#define R128_GUI_SCRATCH_REG2 0x15e8
247#define R128_GUI_SCRATCH_REG3 0x15ec
248#define R128_GUI_SCRATCH_REG4 0x15f0
249#define R128_GUI_SCRATCH_REG5 0x15f4
250
251#define R128_GUI_STAT 0x1740
252# define R128_GUI_FIFOCNT_MASK 0x0fff
253# define R128_GUI_ACTIVE (1 << 31)
254
255#define R128_MCLK_CNTL 0x000f
256# define R128_FORCE_GCP (1 << 16)
257# define R128_FORCE_PIPE3D_CP (1 << 17)
258# define R128_FORCE_RCP (1 << 18)
259
260#define R128_PC_GUI_CTLSTAT 0x1748
261#define R128_PC_NGUI_CTLSTAT 0x0184
262# define R128_PC_FLUSH_GUI (3 << 0)
263# define R128_PC_RI_GUI (1 << 2)
264# define R128_PC_FLUSH_ALL 0x00ff
265# define R128_PC_BUSY (1 << 31)
266
267#define R128_PCI_GART_PAGE 0x017c
268#define R128_PRIM_TEX_CNTL_C 0x1cb0
269
270#define R128_SCALE_3D_CNTL 0x1a00
271#define R128_SEC_TEX_CNTL_C 0x1d00
272#define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c
273#define R128_SETUP_CNTL 0x1bc4
274#define R128_STEN_REF_MASK_C 0x1d40
275
276#define R128_TEX_CNTL_C 0x1c9c
277# define R128_TEX_CACHE_FLUSH (1 << 23)
278
279#define R128_WAIT_UNTIL 0x1720
280# define R128_EVENT_CRTC_OFFSET (1 << 0)
281#define R128_WINDOW_XY_OFFSET 0x1bcc
282
283
284
285#define R128_PM4_BUFFER_OFFSET 0x0700
286#define R128_PM4_BUFFER_CNTL 0x0704
287# define R128_PM4_MASK (15 << 28)
288# define R128_PM4_NONPM4 (0 << 28)
289# define R128_PM4_192PIO (1 << 28)
290# define R128_PM4_192BM (2 << 28)
291# define R128_PM4_128PIO_64INDBM (3 << 28)
292# define R128_PM4_128BM_64INDBM (4 << 28)
293# define R128_PM4_64PIO_128INDBM (5 << 28)
294# define R128_PM4_64BM_128INDBM (6 << 28)
295# define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28)
296# define R128_PM4_64BM_64VCBM_64INDBM (8 << 28)
297# define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28)
298# define R128_PM4_BUFFER_CNTL_NOUPDATE (1 << 27)
299
300#define R128_PM4_BUFFER_WM_CNTL 0x0708
301# define R128_WMA_SHIFT 0
302# define R128_WMB_SHIFT 8
303# define R128_WMC_SHIFT 16
304# define R128_WB_WM_SHIFT 24
305
306#define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c
307#define R128_PM4_BUFFER_DL_RPTR 0x0710
308#define R128_PM4_BUFFER_DL_WPTR 0x0714
309# define R128_PM4_BUFFER_DL_DONE (1 << 31)
310
311#define R128_PM4_VC_FPU_SETUP 0x071c
312
313#define R128_PM4_IW_INDOFF 0x0738
314#define R128_PM4_IW_INDSIZE 0x073c
315
316#define R128_PM4_STAT 0x07b8
317# define R128_PM4_FIFOCNT_MASK 0x0fff
318# define R128_PM4_BUSY (1 << 16)
319# define R128_PM4_GUI_ACTIVE (1 << 31)
320
321#define R128_PM4_MICROCODE_ADDR 0x07d4
322#define R128_PM4_MICROCODE_RADDR 0x07d8
323#define R128_PM4_MICROCODE_DATAH 0x07dc
324#define R128_PM4_MICROCODE_DATAL 0x07e0
325
326#define R128_PM4_BUFFER_ADDR 0x07f0
327#define R128_PM4_MICRO_CNTL 0x07fc
328# define R128_PM4_MICRO_FREERUN (1 << 30)
329
330#define R128_PM4_FIFO_DATA_EVEN 0x1000
331#define R128_PM4_FIFO_DATA_ODD 0x1004
332
333
334
335#define R128_CCE_PACKET0 0x00000000
336#define R128_CCE_PACKET1 0x40000000
337#define R128_CCE_PACKET2 0x80000000
338#define R128_CCE_PACKET3 0xC0000000
339# define R128_CNTL_HOSTDATA_BLT 0x00009400
340# define R128_CNTL_PAINT_MULTI 0x00009A00
341# define R128_CNTL_BITBLT_MULTI 0x00009B00
342# define R128_3D_RNDR_GEN_INDX_PRIM 0x00002300
343
344#define R128_CCE_PACKET_MASK 0xC0000000
345#define R128_CCE_PACKET_COUNT_MASK 0x3fff0000
346#define R128_CCE_PACKET0_REG_MASK 0x000007ff
347#define R128_CCE_PACKET1_REG0_MASK 0x000007ff
348#define R128_CCE_PACKET1_REG1_MASK 0x003ff800
349
350#define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000
351#define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001
352#define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002
353#define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003
354#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004
355#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005
356#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006
357#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007
358#define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010
359#define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020
360#define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030
361#define R128_CCE_VC_CNTL_NUM_SHIFT 16
362
363#define R128_DATATYPE_VQ 0
364#define R128_DATATYPE_CI4 1
365#define R128_DATATYPE_CI8 2
366#define R128_DATATYPE_ARGB1555 3
367#define R128_DATATYPE_RGB565 4
368#define R128_DATATYPE_RGB888 5
369#define R128_DATATYPE_ARGB8888 6
370#define R128_DATATYPE_RGB332 7
371#define R128_DATATYPE_Y8 8
372#define R128_DATATYPE_RGB8 9
373#define R128_DATATYPE_CI16 10
374#define R128_DATATYPE_YVYU422 11
375#define R128_DATATYPE_VYUY422 12
376#define R128_DATATYPE_AYUV444 14
377#define R128_DATATYPE_ARGB4444 15
378
379
380#define R128_AGP_OFFSET 0x02000000
381
382#define R128_WATERMARK_L 16
383#define R128_WATERMARK_M 8
384#define R128_WATERMARK_N 8
385#define R128_WATERMARK_K 128
386
387#define R128_MAX_USEC_TIMEOUT 100000
388
389#define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0
390#define R128_LAST_DISPATCH_REG R128_GUI_SCRATCH_REG1
391#define R128_MAX_VB_AGE 0x7fffffff
392#define R128_MAX_VB_VERTS (0xffff)
393
394#define R128_RING_HIGH_MARK 128
395
396#define R128_PERFORMANCE_BOXES 0
397
398#define R128_PCIGART_TABLE_SIZE 32768
399
400#define R128_READ(reg) DRM_READ32(dev_priv->mmio, (reg))
401#define R128_WRITE(reg, val) DRM_WRITE32(dev_priv->mmio, (reg), (val))
402#define R128_READ8(reg) DRM_READ8(dev_priv->mmio, (reg))
403#define R128_WRITE8(reg, val) DRM_WRITE8(dev_priv->mmio, (reg), (val))
404
405#define R128_WRITE_PLL(addr, val) \
406do { \
407 R128_WRITE8(R128_CLOCK_CNTL_INDEX, \
408 ((addr) & 0x1f) | R128_PLL_WR_EN); \
409 R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \
410} while (0)
411
412#define CCE_PACKET0(reg, n) (R128_CCE_PACKET0 | \
413 ((n) << 16) | ((reg) >> 2))
414#define CCE_PACKET1(reg0, reg1) (R128_CCE_PACKET1 | \
415 (((reg1) >> 2) << 11) | ((reg0) >> 2))
416#define CCE_PACKET2() (R128_CCE_PACKET2)
417#define CCE_PACKET3(pkt, n) (R128_CCE_PACKET3 | \
418 (pkt) | ((n) << 16))
419
420static __inline__ void r128_update_ring_snapshot(drm_r128_private_t *dev_priv)
421{
422 drm_r128_ring_buffer_t *ring = &dev_priv->ring;
423 ring->space = (GET_RING_HEAD(dev_priv) - ring->tail) * sizeof(u32);
424 if (ring->space <= 0)
425 ring->space += ring->size;
426}
427
428
429
430
431
432#define DEV_INIT_TEST_WITH_RETURN(_dev_priv) \
433do { \
434 if (!_dev_priv) { \
435 DRM_ERROR("called with no initialization\n"); \
436 return -EINVAL; \
437 } \
438} while (0)
439
440#define RING_SPACE_TEST_WITH_RETURN(dev_priv) \
441do { \
442 drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; \
443 if (ring->space < ring->high_mark) { \
444 for (i = 0 ; i < dev_priv->usec_timeout ; i++) { \
445 r128_update_ring_snapshot(dev_priv); \
446 if (ring->space >= ring->high_mark) \
447 goto __ring_space_done; \
448 DRM_UDELAY(1); \
449 } \
450 DRM_ERROR("ring space check failed!\n"); \
451 return -EBUSY; \
452 } \
453 __ring_space_done: \
454 ; \
455} while (0)
456
457#define VB_AGE_TEST_WITH_RETURN(dev_priv) \
458do { \
459 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; \
460 if (sarea_priv->last_dispatch >= R128_MAX_VB_AGE) { \
461 int __ret = r128_do_cce_idle(dev_priv); \
462 if (__ret) \
463 return __ret; \
464 sarea_priv->last_dispatch = 0; \
465 r128_freelist_reset(dev); \
466 } \
467} while (0)
468
469#define R128_WAIT_UNTIL_PAGE_FLIPPED() do { \
470 OUT_RING(CCE_PACKET0(R128_WAIT_UNTIL, 0)); \
471 OUT_RING(R128_EVENT_CRTC_OFFSET); \
472} while (0)
473
474
475
476
477
478#define R128_VERBOSE 0
479
480#define RING_LOCALS \
481 int write, _nr; unsigned int tail_mask; volatile u32 *ring;
482
483#define BEGIN_RING(n) do { \
484 if (R128_VERBOSE) \
485 DRM_INFO("BEGIN_RING(%d)\n", (n)); \
486 if (dev_priv->ring.space <= (n) * sizeof(u32)) { \
487 COMMIT_RING(); \
488 r128_wait_ring(dev_priv, (n) * sizeof(u32)); \
489 } \
490 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
491 ring = dev_priv->ring.start; \
492 write = dev_priv->ring.tail; \
493 tail_mask = dev_priv->ring.tail_mask; \
494} while (0)
495
496
497
498
499
500
501#define R128_BROKEN_CCE 1
502
503#define ADVANCE_RING() do { \
504 if (R128_VERBOSE) \
505 DRM_INFO("ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
506 write, dev_priv->ring.tail); \
507 if (R128_BROKEN_CCE && write < 32) \
508 memcpy(dev_priv->ring.end, \
509 dev_priv->ring.start, \
510 write * sizeof(u32)); \
511 if (((dev_priv->ring.tail + _nr) & tail_mask) != write) \
512 DRM_ERROR( \
513 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
514 ((dev_priv->ring.tail + _nr) & tail_mask), \
515 write, __LINE__); \
516 else \
517 dev_priv->ring.tail = write; \
518} while (0)
519
520#define COMMIT_RING() do { \
521 if (R128_VERBOSE) \
522 DRM_INFO("COMMIT_RING() tail=0x%06x\n", \
523 dev_priv->ring.tail); \
524 mb(); \
525 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, dev_priv->ring.tail); \
526 R128_READ(R128_PM4_BUFFER_DL_WPTR); \
527} while (0)
528
529#define OUT_RING(x) do { \
530 if (R128_VERBOSE) \
531 DRM_INFO(" OUT_RING( 0x%08x ) at 0x%x\n", \
532 (unsigned int)(x), write); \
533 ring[write++] = cpu_to_le32(x); \
534 write &= tail_mask; \
535} while (0)
536
537#endif
538
