linux/drivers/gpu/drm/radeon/radeon_combios.c
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   1/*
   2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
   3 * Copyright 2007-8 Advanced Micro Devices, Inc.
   4 * Copyright 2008 Red Hat Inc.
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a
   7 * copy of this software and associated documentation files (the "Software"),
   8 * to deal in the Software without restriction, including without limitation
   9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10 * and/or sell copies of the Software, and to permit persons to whom the
  11 * Software is furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22 * OTHER DEALINGS IN THE SOFTWARE.
  23 *
  24 * Authors: Dave Airlie
  25 *          Alex Deucher
  26 */
  27
  28#include <linux/pci.h>
  29
  30#include <drm/drm_device.h>
  31#include <drm/radeon_drm.h>
  32
  33#include "radeon.h"
  34#include "radeon_legacy_encoders.h"
  35#include "atom.h"
  36
  37#ifdef CONFIG_PPC_PMAC
  38/* not sure which of these are needed */
  39#include <asm/machdep.h>
  40#include <asm/pmac_feature.h>
  41#include <asm/prom.h>
  42#endif /* CONFIG_PPC_PMAC */
  43
  44/* old legacy ATI BIOS routines */
  45
  46/* COMBIOS table offsets */
  47enum radeon_combios_table_offset {
  48        /* absolute offset tables */
  49        COMBIOS_ASIC_INIT_1_TABLE,
  50        COMBIOS_BIOS_SUPPORT_TABLE,
  51        COMBIOS_DAC_PROGRAMMING_TABLE,
  52        COMBIOS_MAX_COLOR_DEPTH_TABLE,
  53        COMBIOS_CRTC_INFO_TABLE,
  54        COMBIOS_PLL_INFO_TABLE,
  55        COMBIOS_TV_INFO_TABLE,
  56        COMBIOS_DFP_INFO_TABLE,
  57        COMBIOS_HW_CONFIG_INFO_TABLE,
  58        COMBIOS_MULTIMEDIA_INFO_TABLE,
  59        COMBIOS_TV_STD_PATCH_TABLE,
  60        COMBIOS_LCD_INFO_TABLE,
  61        COMBIOS_MOBILE_INFO_TABLE,
  62        COMBIOS_PLL_INIT_TABLE,
  63        COMBIOS_MEM_CONFIG_TABLE,
  64        COMBIOS_SAVE_MASK_TABLE,
  65        COMBIOS_HARDCODED_EDID_TABLE,
  66        COMBIOS_ASIC_INIT_2_TABLE,
  67        COMBIOS_CONNECTOR_INFO_TABLE,
  68        COMBIOS_DYN_CLK_1_TABLE,
  69        COMBIOS_RESERVED_MEM_TABLE,
  70        COMBIOS_EXT_TMDS_INFO_TABLE,
  71        COMBIOS_MEM_CLK_INFO_TABLE,
  72        COMBIOS_EXT_DAC_INFO_TABLE,
  73        COMBIOS_MISC_INFO_TABLE,
  74        COMBIOS_CRT_INFO_TABLE,
  75        COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
  76        COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
  77        COMBIOS_FAN_SPEED_INFO_TABLE,
  78        COMBIOS_OVERDRIVE_INFO_TABLE,
  79        COMBIOS_OEM_INFO_TABLE,
  80        COMBIOS_DYN_CLK_2_TABLE,
  81        COMBIOS_POWER_CONNECTOR_INFO_TABLE,
  82        COMBIOS_I2C_INFO_TABLE,
  83        /* relative offset tables */
  84        COMBIOS_ASIC_INIT_3_TABLE,      /* offset from misc info */
  85        COMBIOS_ASIC_INIT_4_TABLE,      /* offset from misc info */
  86        COMBIOS_DETECTED_MEM_TABLE,     /* offset from misc info */
  87        COMBIOS_ASIC_INIT_5_TABLE,      /* offset from misc info */
  88        COMBIOS_RAM_RESET_TABLE,        /* offset from mem config */
  89        COMBIOS_POWERPLAY_INFO_TABLE,   /* offset from mobile info */
  90        COMBIOS_GPIO_INFO_TABLE,        /* offset from mobile info */
  91        COMBIOS_LCD_DDC_INFO_TABLE,     /* offset from mobile info */
  92        COMBIOS_TMDS_POWER_TABLE,       /* offset from mobile info */
  93        COMBIOS_TMDS_POWER_ON_TABLE,    /* offset from tmds power */
  94        COMBIOS_TMDS_POWER_OFF_TABLE,   /* offset from tmds power */
  95};
  96
  97enum radeon_combios_ddc {
  98        DDC_NONE_DETECTED,
  99        DDC_MONID,
 100        DDC_DVI,
 101        DDC_VGA,
 102        DDC_CRT2,
 103        DDC_LCD,
 104        DDC_GPIO,
 105};
 106
 107enum radeon_combios_connector {
 108        CONNECTOR_NONE_LEGACY,
 109        CONNECTOR_PROPRIETARY_LEGACY,
 110        CONNECTOR_CRT_LEGACY,
 111        CONNECTOR_DVI_I_LEGACY,
 112        CONNECTOR_DVI_D_LEGACY,
 113        CONNECTOR_CTV_LEGACY,
 114        CONNECTOR_STV_LEGACY,
 115        CONNECTOR_UNSUPPORTED_LEGACY
 116};
 117
 118static const int legacy_connector_convert[] = {
 119        DRM_MODE_CONNECTOR_Unknown,
 120        DRM_MODE_CONNECTOR_DVID,
 121        DRM_MODE_CONNECTOR_VGA,
 122        DRM_MODE_CONNECTOR_DVII,
 123        DRM_MODE_CONNECTOR_DVID,
 124        DRM_MODE_CONNECTOR_Composite,
 125        DRM_MODE_CONNECTOR_SVIDEO,
 126        DRM_MODE_CONNECTOR_Unknown,
 127};
 128
 129static uint16_t combios_get_table_offset(struct drm_device *dev,
 130                                         enum radeon_combios_table_offset table)
 131{
 132        struct radeon_device *rdev = dev->dev_private;
 133        int rev, size;
 134        uint16_t offset = 0, check_offset;
 135
 136        if (!rdev->bios)
 137                return 0;
 138
 139        switch (table) {
 140                /* absolute offset tables */
 141        case COMBIOS_ASIC_INIT_1_TABLE:
 142                check_offset = 0xc;
 143                break;
 144        case COMBIOS_BIOS_SUPPORT_TABLE:
 145                check_offset = 0x14;
 146                break;
 147        case COMBIOS_DAC_PROGRAMMING_TABLE:
 148                check_offset = 0x2a;
 149                break;
 150        case COMBIOS_MAX_COLOR_DEPTH_TABLE:
 151                check_offset = 0x2c;
 152                break;
 153        case COMBIOS_CRTC_INFO_TABLE:
 154                check_offset = 0x2e;
 155                break;
 156        case COMBIOS_PLL_INFO_TABLE:
 157                check_offset = 0x30;
 158                break;
 159        case COMBIOS_TV_INFO_TABLE:
 160                check_offset = 0x32;
 161                break;
 162        case COMBIOS_DFP_INFO_TABLE:
 163                check_offset = 0x34;
 164                break;
 165        case COMBIOS_HW_CONFIG_INFO_TABLE:
 166                check_offset = 0x36;
 167                break;
 168        case COMBIOS_MULTIMEDIA_INFO_TABLE:
 169                check_offset = 0x38;
 170                break;
 171        case COMBIOS_TV_STD_PATCH_TABLE:
 172                check_offset = 0x3e;
 173                break;
 174        case COMBIOS_LCD_INFO_TABLE:
 175                check_offset = 0x40;
 176                break;
 177        case COMBIOS_MOBILE_INFO_TABLE:
 178                check_offset = 0x42;
 179                break;
 180        case COMBIOS_PLL_INIT_TABLE:
 181                check_offset = 0x46;
 182                break;
 183        case COMBIOS_MEM_CONFIG_TABLE:
 184                check_offset = 0x48;
 185                break;
 186        case COMBIOS_SAVE_MASK_TABLE:
 187                check_offset = 0x4a;
 188                break;
 189        case COMBIOS_HARDCODED_EDID_TABLE:
 190                check_offset = 0x4c;
 191                break;
 192        case COMBIOS_ASIC_INIT_2_TABLE:
 193                check_offset = 0x4e;
 194                break;
 195        case COMBIOS_CONNECTOR_INFO_TABLE:
 196                check_offset = 0x50;
 197                break;
 198        case COMBIOS_DYN_CLK_1_TABLE:
 199                check_offset = 0x52;
 200                break;
 201        case COMBIOS_RESERVED_MEM_TABLE:
 202                check_offset = 0x54;
 203                break;
 204        case COMBIOS_EXT_TMDS_INFO_TABLE:
 205                check_offset = 0x58;
 206                break;
 207        case COMBIOS_MEM_CLK_INFO_TABLE:
 208                check_offset = 0x5a;
 209                break;
 210        case COMBIOS_EXT_DAC_INFO_TABLE:
 211                check_offset = 0x5c;
 212                break;
 213        case COMBIOS_MISC_INFO_TABLE:
 214                check_offset = 0x5e;
 215                break;
 216        case COMBIOS_CRT_INFO_TABLE:
 217                check_offset = 0x60;
 218                break;
 219        case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
 220                check_offset = 0x62;
 221                break;
 222        case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
 223                check_offset = 0x64;
 224                break;
 225        case COMBIOS_FAN_SPEED_INFO_TABLE:
 226                check_offset = 0x66;
 227                break;
 228        case COMBIOS_OVERDRIVE_INFO_TABLE:
 229                check_offset = 0x68;
 230                break;
 231        case COMBIOS_OEM_INFO_TABLE:
 232                check_offset = 0x6a;
 233                break;
 234        case COMBIOS_DYN_CLK_2_TABLE:
 235                check_offset = 0x6c;
 236                break;
 237        case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
 238                check_offset = 0x6e;
 239                break;
 240        case COMBIOS_I2C_INFO_TABLE:
 241                check_offset = 0x70;
 242                break;
 243                /* relative offset tables */
 244        case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
 245                check_offset =
 246                    combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 247                if (check_offset) {
 248                        rev = RBIOS8(check_offset);
 249                        if (rev > 0) {
 250                                check_offset = RBIOS16(check_offset + 0x3);
 251                                if (check_offset)
 252                                        offset = check_offset;
 253                        }
 254                }
 255                break;
 256        case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
 257                check_offset =
 258                    combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 259                if (check_offset) {
 260                        rev = RBIOS8(check_offset);
 261                        if (rev > 0) {
 262                                check_offset = RBIOS16(check_offset + 0x5);
 263                                if (check_offset)
 264                                        offset = check_offset;
 265                        }
 266                }
 267                break;
 268        case COMBIOS_DETECTED_MEM_TABLE:        /* offset from misc info */
 269                check_offset =
 270                    combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 271                if (check_offset) {
 272                        rev = RBIOS8(check_offset);
 273                        if (rev > 0) {
 274                                check_offset = RBIOS16(check_offset + 0x7);
 275                                if (check_offset)
 276                                        offset = check_offset;
 277                        }
 278                }
 279                break;
 280        case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
 281                check_offset =
 282                    combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 283                if (check_offset) {
 284                        rev = RBIOS8(check_offset);
 285                        if (rev == 2) {
 286                                check_offset = RBIOS16(check_offset + 0x9);
 287                                if (check_offset)
 288                                        offset = check_offset;
 289                        }
 290                }
 291                break;
 292        case COMBIOS_RAM_RESET_TABLE:   /* offset from mem config */
 293                check_offset =
 294                    combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
 295                if (check_offset) {
 296                        while (RBIOS8(check_offset++));
 297                        check_offset += 2;
 298                        if (check_offset)
 299                                offset = check_offset;
 300                }
 301                break;
 302        case COMBIOS_POWERPLAY_INFO_TABLE:      /* offset from mobile info */
 303                check_offset =
 304                    combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 305                if (check_offset) {
 306                        check_offset = RBIOS16(check_offset + 0x11);
 307                        if (check_offset)
 308                                offset = check_offset;
 309                }
 310                break;
 311        case COMBIOS_GPIO_INFO_TABLE:   /* offset from mobile info */
 312                check_offset =
 313                    combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 314                if (check_offset) {
 315                        check_offset = RBIOS16(check_offset + 0x13);
 316                        if (check_offset)
 317                                offset = check_offset;
 318                }
 319                break;
 320        case COMBIOS_LCD_DDC_INFO_TABLE:        /* offset from mobile info */
 321                check_offset =
 322                    combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 323                if (check_offset) {
 324                        check_offset = RBIOS16(check_offset + 0x15);
 325                        if (check_offset)
 326                                offset = check_offset;
 327                }
 328                break;
 329        case COMBIOS_TMDS_POWER_TABLE:  /* offset from mobile info */
 330                check_offset =
 331                    combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 332                if (check_offset) {
 333                        check_offset = RBIOS16(check_offset + 0x17);
 334                        if (check_offset)
 335                                offset = check_offset;
 336                }
 337                break;
 338        case COMBIOS_TMDS_POWER_ON_TABLE:       /* offset from tmds power */
 339                check_offset =
 340                    combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 341                if (check_offset) {
 342                        check_offset = RBIOS16(check_offset + 0x2);
 343                        if (check_offset)
 344                                offset = check_offset;
 345                }
 346                break;
 347        case COMBIOS_TMDS_POWER_OFF_TABLE:      /* offset from tmds power */
 348                check_offset =
 349                    combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 350                if (check_offset) {
 351                        check_offset = RBIOS16(check_offset + 0x4);
 352                        if (check_offset)
 353                                offset = check_offset;
 354                }
 355                break;
 356        default:
 357                check_offset = 0;
 358                break;
 359        }
 360
 361        size = RBIOS8(rdev->bios_header_start + 0x6);
 362        /* check absolute offset tables */
 363        if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size)
 364                offset = RBIOS16(rdev->bios_header_start + check_offset);
 365
 366        return offset;
 367}
 368
 369bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
 370{
 371        int edid_info, size;
 372        struct edid *edid;
 373        unsigned char *raw;
 374        edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
 375        if (!edid_info)
 376                return false;
 377
 378        raw = rdev->bios + edid_info;
 379        size = EDID_LENGTH * (raw[0x7e] + 1);
 380        edid = kmalloc(size, GFP_KERNEL);
 381        if (edid == NULL)
 382                return false;
 383
 384        memcpy((unsigned char *)edid, raw, size);
 385
 386        if (!drm_edid_is_valid(edid)) {
 387                kfree(edid);
 388                return false;
 389        }
 390
 391        rdev->mode_info.bios_hardcoded_edid = edid;
 392        rdev->mode_info.bios_hardcoded_edid_size = size;
 393        return true;
 394}
 395
 396/* this is used for atom LCDs as well */
 397struct edid *
 398radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
 399{
 400        struct edid *edid;
 401
 402        if (rdev->mode_info.bios_hardcoded_edid) {
 403                edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
 404                if (edid) {
 405                        memcpy((unsigned char *)edid,
 406                               (unsigned char *)rdev->mode_info.bios_hardcoded_edid,
 407                               rdev->mode_info.bios_hardcoded_edid_size);
 408                        return edid;
 409                }
 410        }
 411        return NULL;
 412}
 413
 414static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
 415                                                       enum radeon_combios_ddc ddc,
 416                                                       u32 clk_mask,
 417                                                       u32 data_mask)
 418{
 419        struct radeon_i2c_bus_rec i2c;
 420        int ddc_line = 0;
 421
 422        /* ddc id            = mask reg
 423         * DDC_NONE_DETECTED = none
 424         * DDC_DVI           = RADEON_GPIO_DVI_DDC
 425         * DDC_VGA           = RADEON_GPIO_VGA_DDC
 426         * DDC_LCD           = RADEON_GPIOPAD_MASK
 427         * DDC_GPIO          = RADEON_MDGPIO_MASK
 428         * r1xx
 429         * DDC_MONID         = RADEON_GPIO_MONID
 430         * DDC_CRT2          = RADEON_GPIO_CRT2_DDC
 431         * r200
 432         * DDC_MONID         = RADEON_GPIO_MONID
 433         * DDC_CRT2          = RADEON_GPIO_DVI_DDC
 434         * r300/r350
 435         * DDC_MONID         = RADEON_GPIO_DVI_DDC
 436         * DDC_CRT2          = RADEON_GPIO_DVI_DDC
 437         * rv2xx/rv3xx
 438         * DDC_MONID         = RADEON_GPIO_MONID
 439         * DDC_CRT2          = RADEON_GPIO_MONID
 440         * rs3xx/rs4xx
 441         * DDC_MONID         = RADEON_GPIOPAD_MASK
 442         * DDC_CRT2          = RADEON_GPIO_MONID
 443         */
 444        switch (ddc) {
 445        case DDC_NONE_DETECTED:
 446        default:
 447                ddc_line = 0;
 448                break;
 449        case DDC_DVI:
 450                ddc_line = RADEON_GPIO_DVI_DDC;
 451                break;
 452        case DDC_VGA:
 453                ddc_line = RADEON_GPIO_VGA_DDC;
 454                break;
 455        case DDC_LCD:
 456                ddc_line = RADEON_GPIOPAD_MASK;
 457                break;
 458        case DDC_GPIO:
 459                ddc_line = RADEON_MDGPIO_MASK;
 460                break;
 461        case DDC_MONID:
 462                if (rdev->family == CHIP_RS300 ||
 463                    rdev->family == CHIP_RS400 ||
 464                    rdev->family == CHIP_RS480)
 465                        ddc_line = RADEON_GPIOPAD_MASK;
 466                else if (rdev->family == CHIP_R300 ||
 467                         rdev->family == CHIP_R350) {
 468                        ddc_line = RADEON_GPIO_DVI_DDC;
 469                        ddc = DDC_DVI;
 470                } else
 471                        ddc_line = RADEON_GPIO_MONID;
 472                break;
 473        case DDC_CRT2:
 474                if (rdev->family == CHIP_R200 ||
 475                    rdev->family == CHIP_R300 ||
 476                    rdev->family == CHIP_R350) {
 477                        ddc_line = RADEON_GPIO_DVI_DDC;
 478                        ddc = DDC_DVI;
 479                } else if (rdev->family == CHIP_RS300 ||
 480                           rdev->family == CHIP_RS400 ||
 481                           rdev->family == CHIP_RS480)
 482                        ddc_line = RADEON_GPIO_MONID;
 483                else if (rdev->family >= CHIP_RV350) {
 484                        ddc_line = RADEON_GPIO_MONID;
 485                        ddc = DDC_MONID;
 486                } else
 487                        ddc_line = RADEON_GPIO_CRT2_DDC;
 488                break;
 489        }
 490
 491        if (ddc_line == RADEON_GPIOPAD_MASK) {
 492                i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
 493                i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
 494                i2c.a_clk_reg = RADEON_GPIOPAD_A;
 495                i2c.a_data_reg = RADEON_GPIOPAD_A;
 496                i2c.en_clk_reg = RADEON_GPIOPAD_EN;
 497                i2c.en_data_reg = RADEON_GPIOPAD_EN;
 498                i2c.y_clk_reg = RADEON_GPIOPAD_Y;
 499                i2c.y_data_reg = RADEON_GPIOPAD_Y;
 500        } else if (ddc_line == RADEON_MDGPIO_MASK) {
 501                i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
 502                i2c.mask_data_reg = RADEON_MDGPIO_MASK;
 503                i2c.a_clk_reg = RADEON_MDGPIO_A;
 504                i2c.a_data_reg = RADEON_MDGPIO_A;
 505                i2c.en_clk_reg = RADEON_MDGPIO_EN;
 506                i2c.en_data_reg = RADEON_MDGPIO_EN;
 507                i2c.y_clk_reg = RADEON_MDGPIO_Y;
 508                i2c.y_data_reg = RADEON_MDGPIO_Y;
 509        } else {
 510                i2c.mask_clk_reg = ddc_line;
 511                i2c.mask_data_reg = ddc_line;
 512                i2c.a_clk_reg = ddc_line;
 513                i2c.a_data_reg = ddc_line;
 514                i2c.en_clk_reg = ddc_line;
 515                i2c.en_data_reg = ddc_line;
 516                i2c.y_clk_reg = ddc_line;
 517                i2c.y_data_reg = ddc_line;
 518        }
 519
 520        if (clk_mask && data_mask) {
 521                /* system specific masks */
 522                i2c.mask_clk_mask = clk_mask;
 523                i2c.mask_data_mask = data_mask;
 524                i2c.a_clk_mask = clk_mask;
 525                i2c.a_data_mask = data_mask;
 526                i2c.en_clk_mask = clk_mask;
 527                i2c.en_data_mask = data_mask;
 528                i2c.y_clk_mask = clk_mask;
 529                i2c.y_data_mask = data_mask;
 530        } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
 531                   (ddc_line == RADEON_MDGPIO_MASK)) {
 532                /* default gpiopad masks */
 533                i2c.mask_clk_mask = (0x20 << 8);
 534                i2c.mask_data_mask = 0x80;
 535                i2c.a_clk_mask = (0x20 << 8);
 536                i2c.a_data_mask = 0x80;
 537                i2c.en_clk_mask = (0x20 << 8);
 538                i2c.en_data_mask = 0x80;
 539                i2c.y_clk_mask = (0x20 << 8);
 540                i2c.y_data_mask = 0x80;
 541        } else {
 542                /* default masks for ddc pads */
 543                i2c.mask_clk_mask = RADEON_GPIO_MASK_1;
 544                i2c.mask_data_mask = RADEON_GPIO_MASK_0;
 545                i2c.a_clk_mask = RADEON_GPIO_A_1;
 546                i2c.a_data_mask = RADEON_GPIO_A_0;
 547                i2c.en_clk_mask = RADEON_GPIO_EN_1;
 548                i2c.en_data_mask = RADEON_GPIO_EN_0;
 549                i2c.y_clk_mask = RADEON_GPIO_Y_1;
 550                i2c.y_data_mask = RADEON_GPIO_Y_0;
 551        }
 552
 553        switch (rdev->family) {
 554        case CHIP_R100:
 555        case CHIP_RV100:
 556        case CHIP_RS100:
 557        case CHIP_RV200:
 558        case CHIP_RS200:
 559        case CHIP_RS300:
 560                switch (ddc_line) {
 561                case RADEON_GPIO_DVI_DDC:
 562                        i2c.hw_capable = true;
 563                        break;
 564                default:
 565                        i2c.hw_capable = false;
 566                        break;
 567                }
 568                break;
 569        case CHIP_R200:
 570                switch (ddc_line) {
 571                case RADEON_GPIO_DVI_DDC:
 572                case RADEON_GPIO_MONID:
 573                        i2c.hw_capable = true;
 574                        break;
 575                default:
 576                        i2c.hw_capable = false;
 577                        break;
 578                }
 579                break;
 580        case CHIP_RV250:
 581        case CHIP_RV280:
 582                switch (ddc_line) {
 583                case RADEON_GPIO_VGA_DDC:
 584                case RADEON_GPIO_DVI_DDC:
 585                case RADEON_GPIO_CRT2_DDC:
 586                        i2c.hw_capable = true;
 587                        break;
 588                default:
 589                        i2c.hw_capable = false;
 590                        break;
 591                }
 592                break;
 593        case CHIP_R300:
 594        case CHIP_R350:
 595                switch (ddc_line) {
 596                case RADEON_GPIO_VGA_DDC:
 597                case RADEON_GPIO_DVI_DDC:
 598                        i2c.hw_capable = true;
 599                        break;
 600                default:
 601                        i2c.hw_capable = false;
 602                        break;
 603                }
 604                break;
 605        case CHIP_RV350:
 606        case CHIP_RV380:
 607        case CHIP_RS400:
 608        case CHIP_RS480:
 609                switch (ddc_line) {
 610                case RADEON_GPIO_VGA_DDC:
 611                case RADEON_GPIO_DVI_DDC:
 612                        i2c.hw_capable = true;
 613                        break;
 614                case RADEON_GPIO_MONID:
 615                        /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
 616                         * reliably on some pre-r4xx hardware; not sure why.
 617                         */
 618                        i2c.hw_capable = false;
 619                        break;
 620                default:
 621                        i2c.hw_capable = false;
 622                        break;
 623                }
 624                break;
 625        default:
 626                i2c.hw_capable = false;
 627                break;
 628        }
 629        i2c.mm_i2c = false;
 630
 631        i2c.i2c_id = ddc;
 632        i2c.hpd = RADEON_HPD_NONE;
 633
 634        if (ddc_line)
 635                i2c.valid = true;
 636        else
 637                i2c.valid = false;
 638
 639        return i2c;
 640}
 641
 642static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev)
 643{
 644        struct drm_device *dev = rdev->ddev;
 645        struct radeon_i2c_bus_rec i2c;
 646        u16 offset;
 647        u8 id, blocks, clk, data;
 648        int i;
 649
 650        i2c.valid = false;
 651
 652        offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
 653        if (offset) {
 654                blocks = RBIOS8(offset + 2);
 655                for (i = 0; i < blocks; i++) {
 656                        id = RBIOS8(offset + 3 + (i * 5) + 0);
 657                        if (id == 136) {
 658                                clk = RBIOS8(offset + 3 + (i * 5) + 3);
 659                                data = RBIOS8(offset + 3 + (i * 5) + 4);
 660                                /* gpiopad */
 661                                i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
 662                                                            (1 << clk), (1 << data));
 663                                break;
 664                        }
 665                }
 666        }
 667        return i2c;
 668}
 669
 670void radeon_combios_i2c_init(struct radeon_device *rdev)
 671{
 672        struct drm_device *dev = rdev->ddev;
 673        struct radeon_i2c_bus_rec i2c;
 674
 675        /* actual hw pads
 676         * r1xx/rs2xx/rs3xx
 677         * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
 678         * r200
 679         * 0x60, 0x64, 0x68, mm
 680         * r300/r350
 681         * 0x60, 0x64, mm
 682         * rv2xx/rv3xx/rs4xx
 683         * 0x60, 0x64, 0x68, gpiopads, mm
 684         */
 685
 686        /* 0x60 */
 687        i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
 688        rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
 689        /* 0x64 */
 690        i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
 691        rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
 692
 693        /* mm i2c */
 694        i2c.valid = true;
 695        i2c.hw_capable = true;
 696        i2c.mm_i2c = true;
 697        i2c.i2c_id = 0xa0;
 698        rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
 699
 700        if (rdev->family == CHIP_R300 ||
 701            rdev->family == CHIP_R350) {
 702                /* only 2 sw i2c pads */
 703        } else if (rdev->family == CHIP_RS300 ||
 704                   rdev->family == CHIP_RS400 ||
 705                   rdev->family == CHIP_RS480) {
 706                /* 0x68 */
 707                i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
 708                rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 709
 710                /* gpiopad */
 711                i2c = radeon_combios_get_i2c_info_from_table(rdev);
 712                if (i2c.valid)
 713                        rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
 714        } else if ((rdev->family == CHIP_R200) ||
 715                   (rdev->family >= CHIP_R300)) {
 716                /* 0x68 */
 717                i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
 718                rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 719        } else {
 720                /* 0x68 */
 721                i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
 722                rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 723                /* 0x6c */
 724                i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
 725                rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
 726        }
 727}
 728
 729bool radeon_combios_get_clock_info(struct drm_device *dev)
 730{
 731        struct radeon_device *rdev = dev->dev_private;
 732        uint16_t pll_info;
 733        struct radeon_pll *p1pll = &rdev->clock.p1pll;
 734        struct radeon_pll *p2pll = &rdev->clock.p2pll;
 735        struct radeon_pll *spll = &rdev->clock.spll;
 736        struct radeon_pll *mpll = &rdev->clock.mpll;
 737        int8_t rev;
 738        uint16_t sclk, mclk;
 739
 740        pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
 741        if (pll_info) {
 742                rev = RBIOS8(pll_info);
 743
 744                /* pixel clocks */
 745                p1pll->reference_freq = RBIOS16(pll_info + 0xe);
 746                p1pll->reference_div = RBIOS16(pll_info + 0x10);
 747                p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
 748                p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
 749                p1pll->lcd_pll_out_min = p1pll->pll_out_min;
 750                p1pll->lcd_pll_out_max = p1pll->pll_out_max;
 751
 752                if (rev > 9) {
 753                        p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
 754                        p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
 755                } else {
 756                        p1pll->pll_in_min = 40;
 757                        p1pll->pll_in_max = 500;
 758                }
 759                *p2pll = *p1pll;
 760
 761                /* system clock */
 762                spll->reference_freq = RBIOS16(pll_info + 0x1a);
 763                spll->reference_div = RBIOS16(pll_info + 0x1c);
 764                spll->pll_out_min = RBIOS32(pll_info + 0x1e);
 765                spll->pll_out_max = RBIOS32(pll_info + 0x22);
 766
 767                if (rev > 10) {
 768                        spll->pll_in_min = RBIOS32(pll_info + 0x48);
 769                        spll->pll_in_max = RBIOS32(pll_info + 0x4c);
 770                } else {
 771                        /* ??? */
 772                        spll->pll_in_min = 40;
 773                        spll->pll_in_max = 500;
 774                }
 775
 776                /* memory clock */
 777                mpll->reference_freq = RBIOS16(pll_info + 0x26);
 778                mpll->reference_div = RBIOS16(pll_info + 0x28);
 779                mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
 780                mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
 781
 782                if (rev > 10) {
 783                        mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
 784                        mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
 785                } else {
 786                        /* ??? */
 787                        mpll->pll_in_min = 40;
 788                        mpll->pll_in_max = 500;
 789                }
 790
 791                /* default sclk/mclk */
 792                sclk = RBIOS16(pll_info + 0xa);
 793                mclk = RBIOS16(pll_info + 0x8);
 794                if (sclk == 0)
 795                        sclk = 200 * 100;
 796                if (mclk == 0)
 797                        mclk = 200 * 100;
 798
 799                rdev->clock.default_sclk = sclk;
 800                rdev->clock.default_mclk = mclk;
 801
 802                if (RBIOS32(pll_info + 0x16))
 803                        rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
 804                else
 805                        rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
 806
 807                return true;
 808        }
 809        return false;
 810}
 811
 812bool radeon_combios_sideport_present(struct radeon_device *rdev)
 813{
 814        struct drm_device *dev = rdev->ddev;
 815        u16 igp_info;
 816
 817        /* sideport is AMD only */
 818        if (rdev->family == CHIP_RS400)
 819                return false;
 820
 821        igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
 822
 823        if (igp_info) {
 824                if (RBIOS16(igp_info + 0x4))
 825                        return true;
 826        }
 827        return false;
 828}
 829
 830static const uint32_t default_primarydac_adj[CHIP_LAST] = {
 831        0x00000808,             /* r100  */
 832        0x00000808,             /* rv100 */
 833        0x00000808,             /* rs100 */
 834        0x00000808,             /* rv200 */
 835        0x00000808,             /* rs200 */
 836        0x00000808,             /* r200  */
 837        0x00000808,             /* rv250 */
 838        0x00000000,             /* rs300 */
 839        0x00000808,             /* rv280 */
 840        0x00000808,             /* r300  */
 841        0x00000808,             /* r350  */
 842        0x00000808,             /* rv350 */
 843        0x00000808,             /* rv380 */
 844        0x00000808,             /* r420  */
 845        0x00000808,             /* r423  */
 846        0x00000808,             /* rv410 */
 847        0x00000000,             /* rs400 */
 848        0x00000000,             /* rs480 */
 849};
 850
 851static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
 852                                                          struct radeon_encoder_primary_dac *p_dac)
 853{
 854        p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
 855        return;
 856}
 857
 858struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
 859                                                                       radeon_encoder
 860                                                                       *encoder)
 861{
 862        struct drm_device *dev = encoder->base.dev;
 863        struct radeon_device *rdev = dev->dev_private;
 864        uint16_t dac_info;
 865        uint8_t rev, bg, dac;
 866        struct radeon_encoder_primary_dac *p_dac = NULL;
 867        int found = 0;
 868
 869        p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
 870                        GFP_KERNEL);
 871
 872        if (!p_dac)
 873                return NULL;
 874
 875        /* check CRT table */
 876        dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 877        if (dac_info) {
 878                rev = RBIOS8(dac_info) & 0x3;
 879                if (rev < 2) {
 880                        bg = RBIOS8(dac_info + 0x2) & 0xf;
 881                        dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
 882                        p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 883                } else {
 884                        bg = RBIOS8(dac_info + 0x2) & 0xf;
 885                        dac = RBIOS8(dac_info + 0x3) & 0xf;
 886                        p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 887                }
 888                /* if the values are zeros, use the table */
 889                if ((dac == 0) || (bg == 0))
 890                        found = 0;
 891                else
 892                        found = 1;
 893        }
 894
 895        /* quirks */
 896        /* Radeon 7000 (RV100) */
 897        if (((rdev->pdev->device == 0x5159) &&
 898            (rdev->pdev->subsystem_vendor == 0x174B) &&
 899            (rdev->pdev->subsystem_device == 0x7c28)) ||
 900        /* Radeon 9100 (R200) */
 901           ((rdev->pdev->device == 0x514D) &&
 902            (rdev->pdev->subsystem_vendor == 0x174B) &&
 903            (rdev->pdev->subsystem_device == 0x7149))) {
 904                /* vbios value is bad, use the default */
 905                found = 0;
 906        }
 907
 908        if (!found) /* fallback to defaults */
 909                radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
 910
 911        return p_dac;
 912}
 913
 914enum radeon_tv_std
 915radeon_combios_get_tv_info(struct radeon_device *rdev)
 916{
 917        struct drm_device *dev = rdev->ddev;
 918        uint16_t tv_info;
 919        enum radeon_tv_std tv_std = TV_STD_NTSC;
 920
 921        tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 922        if (tv_info) {
 923                if (RBIOS8(tv_info + 6) == 'T') {
 924                        switch (RBIOS8(tv_info + 7) & 0xf) {
 925                        case 1:
 926                                tv_std = TV_STD_NTSC;
 927                                DRM_DEBUG_KMS("Default TV standard: NTSC\n");
 928                                break;
 929                        case 2:
 930                                tv_std = TV_STD_PAL;
 931                                DRM_DEBUG_KMS("Default TV standard: PAL\n");
 932                                break;
 933                        case 3:
 934                                tv_std = TV_STD_PAL_M;
 935                                DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
 936                                break;
 937                        case 4:
 938                                tv_std = TV_STD_PAL_60;
 939                                DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
 940                                break;
 941                        case 5:
 942                                tv_std = TV_STD_NTSC_J;
 943                                DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
 944                                break;
 945                        case 6:
 946                                tv_std = TV_STD_SCART_PAL;
 947                                DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
 948                                break;
 949                        default:
 950                                tv_std = TV_STD_NTSC;
 951                                DRM_DEBUG_KMS
 952                                    ("Unknown TV standard; defaulting to NTSC\n");
 953                                break;
 954                        }
 955
 956                        switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
 957                        case 0:
 958                                DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
 959                                break;
 960                        case 1:
 961                                DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
 962                                break;
 963                        case 2:
 964                                DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
 965                                break;
 966                        case 3:
 967                                DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
 968                                break;
 969                        default:
 970                                break;
 971                        }
 972                }
 973        }
 974        return tv_std;
 975}
 976
 977static const uint32_t default_tvdac_adj[CHIP_LAST] = {
 978        0x00000000,             /* r100  */
 979        0x00280000,             /* rv100 */
 980        0x00000000,             /* rs100 */
 981        0x00880000,             /* rv200 */
 982        0x00000000,             /* rs200 */
 983        0x00000000,             /* r200  */
 984        0x00770000,             /* rv250 */
 985        0x00290000,             /* rs300 */
 986        0x00560000,             /* rv280 */
 987        0x00780000,             /* r300  */
 988        0x00770000,             /* r350  */
 989        0x00780000,             /* rv350 */
 990        0x00780000,             /* rv380 */
 991        0x01080000,             /* r420  */
 992        0x01080000,             /* r423  */
 993        0x01080000,             /* rv410 */
 994        0x00780000,             /* rs400 */
 995        0x00780000,             /* rs480 */
 996};
 997
 998static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
 999                                                     struct radeon_encoder_tv_dac *tv_dac)
1000{
1001        tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1002        if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1003                tv_dac->ps2_tvdac_adj = 0x00880000;
1004        tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1005        tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1006        return;
1007}
1008
1009struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1010                                                             radeon_encoder
1011                                                             *encoder)
1012{
1013        struct drm_device *dev = encoder->base.dev;
1014        struct radeon_device *rdev = dev->dev_private;
1015        uint16_t dac_info;
1016        uint8_t rev, bg, dac;
1017        struct radeon_encoder_tv_dac *tv_dac = NULL;
1018        int found = 0;
1019
1020        tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1021        if (!tv_dac)
1022                return NULL;
1023
1024        /* first check TV table */
1025        dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1026        if (dac_info) {
1027                rev = RBIOS8(dac_info + 0x3);
1028                if (rev > 4) {
1029                        bg = RBIOS8(dac_info + 0xc) & 0xf;
1030                        dac = RBIOS8(dac_info + 0xd) & 0xf;
1031                        tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1032
1033                        bg = RBIOS8(dac_info + 0xe) & 0xf;
1034                        dac = RBIOS8(dac_info + 0xf) & 0xf;
1035                        tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1036
1037                        bg = RBIOS8(dac_info + 0x10) & 0xf;
1038                        dac = RBIOS8(dac_info + 0x11) & 0xf;
1039                        tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1040                        /* if the values are all zeros, use the table */
1041                        if (tv_dac->ps2_tvdac_adj)
1042                                found = 1;
1043                } else if (rev > 1) {
1044                        bg = RBIOS8(dac_info + 0xc) & 0xf;
1045                        dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1046                        tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1047
1048                        bg = RBIOS8(dac_info + 0xd) & 0xf;
1049                        dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1050                        tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1051
1052                        bg = RBIOS8(dac_info + 0xe) & 0xf;
1053                        dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1054                        tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1055                        /* if the values are all zeros, use the table */
1056                        if (tv_dac->ps2_tvdac_adj)
1057                                found = 1;
1058                }
1059                tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1060        }
1061        if (!found) {
1062                /* then check CRT table */
1063                dac_info =
1064                    combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1065                if (dac_info) {
1066                        rev = RBIOS8(dac_info) & 0x3;
1067                        if (rev < 2) {
1068                                bg = RBIOS8(dac_info + 0x3) & 0xf;
1069                                dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1070                                tv_dac->ps2_tvdac_adj =
1071                                    (bg << 16) | (dac << 20);
1072                                tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1073                                tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1074                                /* if the values are all zeros, use the table */
1075                                if (tv_dac->ps2_tvdac_adj)
1076                                        found = 1;
1077                        } else {
1078                                bg = RBIOS8(dac_info + 0x4) & 0xf;
1079                                dac = RBIOS8(dac_info + 0x5) & 0xf;
1080                                tv_dac->ps2_tvdac_adj =
1081                                    (bg << 16) | (dac << 20);
1082                                tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1083                                tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1084                                /* if the values are all zeros, use the table */
1085                                if (tv_dac->ps2_tvdac_adj)
1086                                        found = 1;
1087                        }
1088                } else {
1089                        DRM_INFO("No TV DAC info found in BIOS\n");
1090                }
1091        }
1092
1093        if (!found) /* fallback to defaults */
1094                radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1095
1096        return tv_dac;
1097}
1098
1099static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1100                                                                         radeon_device
1101                                                                         *rdev)
1102{
1103        struct radeon_encoder_lvds *lvds = NULL;
1104        uint32_t fp_vert_stretch, fp_horz_stretch;
1105        uint32_t ppll_div_sel, ppll_val;
1106        uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1107
1108        lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1109
1110        if (!lvds)
1111                return NULL;
1112
1113        fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1114        fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1115
1116        /* These should be fail-safe defaults, fingers crossed */
1117        lvds->panel_pwr_delay = 200;
1118        lvds->panel_vcc_delay = 2000;
1119
1120        lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1121        lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1122        lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1123
1124        if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1125                lvds->native_mode.vdisplay =
1126                    ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1127                     RADEON_VERT_PANEL_SHIFT) + 1;
1128        else
1129                lvds->native_mode.vdisplay =
1130                    (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1131
1132        if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1133                lvds->native_mode.hdisplay =
1134                    (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1135                      RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1136        else
1137                lvds->native_mode.hdisplay =
1138                    ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1139
1140        if ((lvds->native_mode.hdisplay < 640) ||
1141            (lvds->native_mode.vdisplay < 480)) {
1142                lvds->native_mode.hdisplay = 640;
1143                lvds->native_mode.vdisplay = 480;
1144        }
1145
1146        ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1147        ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1148        if ((ppll_val & 0x000707ff) == 0x1bb)
1149                lvds->use_bios_dividers = false;
1150        else {
1151                lvds->panel_ref_divider =
1152                    RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1153                lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1154                lvds->panel_fb_divider = ppll_val & 0x7ff;
1155
1156                if ((lvds->panel_ref_divider != 0) &&
1157                    (lvds->panel_fb_divider > 3))
1158                        lvds->use_bios_dividers = true;
1159        }
1160        lvds->panel_vcc_delay = 200;
1161
1162        DRM_INFO("Panel info derived from registers\n");
1163        DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1164                 lvds->native_mode.vdisplay);
1165
1166        return lvds;
1167}
1168
1169struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1170                                                         *encoder)
1171{
1172        struct drm_device *dev = encoder->base.dev;
1173        struct radeon_device *rdev = dev->dev_private;
1174        uint16_t lcd_info;
1175        uint32_t panel_setup;
1176        char stmp[30];
1177        int tmp, i;
1178        struct radeon_encoder_lvds *lvds = NULL;
1179
1180        lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1181
1182        if (lcd_info) {
1183                lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1184
1185                if (!lvds)
1186                        return NULL;
1187
1188                for (i = 0; i < 24; i++)
1189                        stmp[i] = RBIOS8(lcd_info + i + 1);
1190                stmp[24] = 0;
1191
1192                DRM_INFO("Panel ID String: %s\n", stmp);
1193
1194                lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1195                lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1196
1197                DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1198                         lvds->native_mode.vdisplay);
1199
1200                lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1201                lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1202
1203                lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1204                lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1205                lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1206
1207                lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1208                lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1209                lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1210                if ((lvds->panel_ref_divider != 0) &&
1211                    (lvds->panel_fb_divider > 3))
1212                        lvds->use_bios_dividers = true;
1213
1214                panel_setup = RBIOS32(lcd_info + 0x39);
1215                lvds->lvds_gen_cntl = 0xff00;
1216                if (panel_setup & 0x1)
1217                        lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1218
1219                if ((panel_setup >> 4) & 0x1)
1220                        lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1221
1222                switch ((panel_setup >> 8) & 0x7) {
1223                case 0:
1224                        lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1225                        break;
1226                case 1:
1227                        lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1228                        break;
1229                case 2:
1230                        lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1231                        break;
1232                default:
1233                        break;
1234                }
1235
1236                if ((panel_setup >> 16) & 0x1)
1237                        lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1238
1239                if ((panel_setup >> 17) & 0x1)
1240                        lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1241
1242                if ((panel_setup >> 18) & 0x1)
1243                        lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1244
1245                if ((panel_setup >> 23) & 0x1)
1246                        lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1247
1248                lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1249
1250                for (i = 0; i < 32; i++) {
1251                        tmp = RBIOS16(lcd_info + 64 + i * 2);
1252                        if (tmp == 0)
1253                                break;
1254
1255                        if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1256                            (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1257                                u32 hss = (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1258
1259                                if (hss > lvds->native_mode.hdisplay)
1260                                        hss = (10 - 1) * 8;
1261
1262                                lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1263                                        (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1264                                lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1265                                        hss;
1266                                lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1267                                        (RBIOS8(tmp + 23) * 8);
1268
1269                                lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1270                                        (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1271                                lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1272                                        ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1273                                lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1274                                        ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1275
1276                                lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1277                                lvds->native_mode.flags = 0;
1278                                /* set crtc values */
1279                                drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1280
1281                        }
1282                }
1283        } else {
1284                DRM_INFO("No panel info found in BIOS\n");
1285                lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1286        }
1287
1288        if (lvds)
1289                encoder->native_mode = lvds->native_mode;
1290        return lvds;
1291}
1292
1293static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1294        {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R100  */
1295        {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV100 */
1296        {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS100 */
1297        {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV200 */
1298        {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RS200 */
1299        {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R200  */
1300        {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}},  /* CHIP_RV250 */
1301        {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS300 */
1302        {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}},    /* CHIP_RV280 */
1303        {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R300  */
1304        {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R350  */
1305        {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV350 */
1306        {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV380 */
1307        {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R420  */
1308        {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R423  */
1309        {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_RV410 */
1310        { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS400 */
1311        { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS480 */
1312};
1313
1314bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1315                                            struct radeon_encoder_int_tmds *tmds)
1316{
1317        struct drm_device *dev = encoder->base.dev;
1318        struct radeon_device *rdev = dev->dev_private;
1319        int i;
1320
1321        for (i = 0; i < 4; i++) {
1322                tmds->tmds_pll[i].value =
1323                        default_tmds_pll[rdev->family][i].value;
1324                tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1325        }
1326
1327        return true;
1328}
1329
1330bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1331                                              struct radeon_encoder_int_tmds *tmds)
1332{
1333        struct drm_device *dev = encoder->base.dev;
1334        struct radeon_device *rdev = dev->dev_private;
1335        uint16_t tmds_info;
1336        int i, n;
1337        uint8_t ver;
1338
1339        tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1340
1341        if (tmds_info) {
1342                ver = RBIOS8(tmds_info);
1343                DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1344                if (ver == 3) {
1345                        n = RBIOS8(tmds_info + 5) + 1;
1346                        if (n > 4)
1347                                n = 4;
1348                        for (i = 0; i < n; i++) {
1349                                tmds->tmds_pll[i].value =
1350                                    RBIOS32(tmds_info + i * 10 + 0x08);
1351                                tmds->tmds_pll[i].freq =
1352                                    RBIOS16(tmds_info + i * 10 + 0x10);
1353                                DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1354                                          tmds->tmds_pll[i].freq,
1355                                          tmds->tmds_pll[i].value);
1356                        }
1357                } else if (ver == 4) {
1358                        int stride = 0;
1359                        n = RBIOS8(tmds_info + 5) + 1;
1360                        if (n > 4)
1361                                n = 4;
1362                        for (i = 0; i < n; i++) {
1363                                tmds->tmds_pll[i].value =
1364                                    RBIOS32(tmds_info + stride + 0x08);
1365                                tmds->tmds_pll[i].freq =
1366                                    RBIOS16(tmds_info + stride + 0x10);
1367                                if (i == 0)
1368                                        stride += 10;
1369                                else
1370                                        stride += 6;
1371                                DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1372                                          tmds->tmds_pll[i].freq,
1373                                          tmds->tmds_pll[i].value);
1374                        }
1375                }
1376        } else {
1377                DRM_INFO("No TMDS info found in BIOS\n");
1378                return false;
1379        }
1380        return true;
1381}
1382
1383bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1384                                                struct radeon_encoder_ext_tmds *tmds)
1385{
1386        struct drm_device *dev = encoder->base.dev;
1387        struct radeon_device *rdev = dev->dev_private;
1388        struct radeon_i2c_bus_rec i2c_bus;
1389
1390        /* default for macs */
1391        i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1392        tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1393
1394        /* XXX some macs have duallink chips */
1395        switch (rdev->mode_info.connector_table) {
1396        case CT_POWERBOOK_EXTERNAL:
1397        case CT_MINI_EXTERNAL:
1398        default:
1399                tmds->dvo_chip = DVO_SIL164;
1400                tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1401                break;
1402        }
1403
1404        return true;
1405}
1406
1407bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1408                                                  struct radeon_encoder_ext_tmds *tmds)
1409{
1410        struct drm_device *dev = encoder->base.dev;
1411        struct radeon_device *rdev = dev->dev_private;
1412        uint16_t offset;
1413        uint8_t ver;
1414        enum radeon_combios_ddc gpio;
1415        struct radeon_i2c_bus_rec i2c_bus;
1416
1417        tmds->i2c_bus = NULL;
1418        if (rdev->flags & RADEON_IS_IGP) {
1419                i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1420                tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1421                tmds->dvo_chip = DVO_SIL164;
1422                tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1423        } else {
1424                offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1425                if (offset) {
1426                        ver = RBIOS8(offset);
1427                        DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1428                        tmds->slave_addr = RBIOS8(offset + 4 + 2);
1429                        tmds->slave_addr >>= 1; /* 7 bit addressing */
1430                        gpio = RBIOS8(offset + 4 + 3);
1431                        if (gpio == DDC_LCD) {
1432                                /* MM i2c */
1433                                i2c_bus.valid = true;
1434                                i2c_bus.hw_capable = true;
1435                                i2c_bus.mm_i2c = true;
1436                                i2c_bus.i2c_id = 0xa0;
1437                        } else
1438                                i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1439                        tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1440                }
1441        }
1442
1443        if (!tmds->i2c_bus) {
1444                DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1445                return false;
1446        }
1447
1448        return true;
1449}
1450
1451bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1452{
1453        struct radeon_device *rdev = dev->dev_private;
1454        struct radeon_i2c_bus_rec ddc_i2c;
1455        struct radeon_hpd hpd;
1456
1457        rdev->mode_info.connector_table = radeon_connector_table;
1458        if (rdev->mode_info.connector_table == CT_NONE) {
1459#ifdef CONFIG_PPC_PMAC
1460                if (of_machine_is_compatible("PowerBook3,3")) {
1461                        /* powerbook with VGA */
1462                        rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1463                } else if (of_machine_is_compatible("PowerBook3,4") ||
1464                           of_machine_is_compatible("PowerBook3,5")) {
1465                        /* powerbook with internal tmds */
1466                        rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1467                } else if (of_machine_is_compatible("PowerBook5,1") ||
1468                           of_machine_is_compatible("PowerBook5,2") ||
1469                           of_machine_is_compatible("PowerBook5,3") ||
1470                           of_machine_is_compatible("PowerBook5,4") ||
1471                           of_machine_is_compatible("PowerBook5,5")) {
1472                        /* powerbook with external single link tmds (sil164) */
1473                        rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1474                } else if (of_machine_is_compatible("PowerBook5,6")) {
1475                        /* powerbook with external dual or single link tmds */
1476                        rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1477                } else if (of_machine_is_compatible("PowerBook5,7") ||
1478                           of_machine_is_compatible("PowerBook5,8") ||
1479                           of_machine_is_compatible("PowerBook5,9")) {
1480                        /* PowerBook6,2 ? */
1481                        /* powerbook with external dual link tmds (sil1178?) */
1482                        rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1483                } else if (of_machine_is_compatible("PowerBook4,1") ||
1484                           of_machine_is_compatible("PowerBook4,2") ||
1485                           of_machine_is_compatible("PowerBook4,3") ||
1486                           of_machine_is_compatible("PowerBook6,3") ||
1487                           of_machine_is_compatible("PowerBook6,5") ||
1488                           of_machine_is_compatible("PowerBook6,7")) {
1489                        /* ibook */
1490                        rdev->mode_info.connector_table = CT_IBOOK;
1491                } else if (of_machine_is_compatible("PowerMac3,5")) {
1492                        /* PowerMac G4 Silver radeon 7500 */
1493                        rdev->mode_info.connector_table = CT_MAC_G4_SILVER;
1494                } else if (of_machine_is_compatible("PowerMac4,4")) {
1495                        /* emac */
1496                        rdev->mode_info.connector_table = CT_EMAC;
1497                } else if (of_machine_is_compatible("PowerMac10,1")) {
1498                        /* mini with internal tmds */
1499                        rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1500                } else if (of_machine_is_compatible("PowerMac10,2")) {
1501                        /* mini with external tmds */
1502                        rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1503                } else if (of_machine_is_compatible("PowerMac12,1")) {
1504                        /* PowerMac8,1 ? */
1505                        /* imac g5 isight */
1506                        rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1507                } else if ((rdev->pdev->device == 0x4a48) &&
1508                           (rdev->pdev->subsystem_vendor == 0x1002) &&
1509                           (rdev->pdev->subsystem_device == 0x4a48)) {
1510                        /* Mac X800 */
1511                        rdev->mode_info.connector_table = CT_MAC_X800;
1512                } else if ((of_machine_is_compatible("PowerMac7,2") ||
1513                            of_machine_is_compatible("PowerMac7,3")) &&
1514                           (rdev->pdev->device == 0x4150) &&
1515                           (rdev->pdev->subsystem_vendor == 0x1002) &&
1516                           (rdev->pdev->subsystem_device == 0x4150)) {
1517                        /* Mac G5 tower 9600 */
1518                        rdev->mode_info.connector_table = CT_MAC_G5_9600;
1519                } else if ((rdev->pdev->device == 0x4c66) &&
1520                           (rdev->pdev->subsystem_vendor == 0x1002) &&
1521                           (rdev->pdev->subsystem_device == 0x4c66)) {
1522                        /* SAM440ep RV250 embedded board */
1523                        rdev->mode_info.connector_table = CT_SAM440EP;
1524                } else
1525#endif /* CONFIG_PPC_PMAC */
1526#ifdef CONFIG_PPC64
1527                if (ASIC_IS_RN50(rdev))
1528                        rdev->mode_info.connector_table = CT_RN50_POWER;
1529                else
1530#endif
1531                        rdev->mode_info.connector_table = CT_GENERIC;
1532        }
1533
1534        switch (rdev->mode_info.connector_table) {
1535        case CT_GENERIC:
1536                DRM_INFO("Connector Table: %d (generic)\n",
1537                         rdev->mode_info.connector_table);
1538                /* these are the most common settings */
1539                if (rdev->flags & RADEON_SINGLE_CRTC) {
1540                        /* VGA - primary dac */
1541                        ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1542                        hpd.hpd = RADEON_HPD_NONE;
1543                        radeon_add_legacy_encoder(dev,
1544                                                  radeon_get_encoder_enum(dev,
1545                                                                        ATOM_DEVICE_CRT1_SUPPORT,
1546                                                                        1),
1547                                                  ATOM_DEVICE_CRT1_SUPPORT);
1548                        radeon_add_legacy_connector(dev, 0,
1549                                                    ATOM_DEVICE_CRT1_SUPPORT,
1550                                                    DRM_MODE_CONNECTOR_VGA,
1551                                                    &ddc_i2c,
1552                                                    CONNECTOR_OBJECT_ID_VGA,
1553                                                    &hpd);
1554                } else if (rdev->flags & RADEON_IS_MOBILITY) {
1555                        /* LVDS */
1556                        ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1557                        hpd.hpd = RADEON_HPD_NONE;
1558                        radeon_add_legacy_encoder(dev,
1559                                                  radeon_get_encoder_enum(dev,
1560                                                                        ATOM_DEVICE_LCD1_SUPPORT,
1561                                                                        0),
1562                                                  ATOM_DEVICE_LCD1_SUPPORT);
1563                        radeon_add_legacy_connector(dev, 0,
1564                                                    ATOM_DEVICE_LCD1_SUPPORT,
1565                                                    DRM_MODE_CONNECTOR_LVDS,
1566                                                    &ddc_i2c,
1567                                                    CONNECTOR_OBJECT_ID_LVDS,
1568                                                    &hpd);
1569
1570                        /* VGA - primary dac */
1571                        ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1572                        hpd.hpd = RADEON_HPD_NONE;
1573                        radeon_add_legacy_encoder(dev,
1574                                                  radeon_get_encoder_enum(dev,
1575                                                                        ATOM_DEVICE_CRT1_SUPPORT,
1576                                                                        1),
1577                                                  ATOM_DEVICE_CRT1_SUPPORT);
1578                        radeon_add_legacy_connector(dev, 1,
1579                                                    ATOM_DEVICE_CRT1_SUPPORT,
1580                                                    DRM_MODE_CONNECTOR_VGA,
1581                                                    &ddc_i2c,
1582                                                    CONNECTOR_OBJECT_ID_VGA,
1583                                                    &hpd);
1584                } else {
1585                        /* DVI-I - tv dac, int tmds */
1586                        ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1587                        hpd.hpd = RADEON_HPD_1;
1588                        radeon_add_legacy_encoder(dev,
1589                                                  radeon_get_encoder_enum(dev,
1590                                                                        ATOM_DEVICE_DFP1_SUPPORT,
1591                                                                        0),
1592                                                  ATOM_DEVICE_DFP1_SUPPORT);
1593                        radeon_add_legacy_encoder(dev,
1594                                                  radeon_get_encoder_enum(dev,
1595                                                                        ATOM_DEVICE_CRT2_SUPPORT,
1596                                                                        2),
1597                                                  ATOM_DEVICE_CRT2_SUPPORT);
1598                        radeon_add_legacy_connector(dev, 0,
1599                                                    ATOM_DEVICE_DFP1_SUPPORT |
1600                                                    ATOM_DEVICE_CRT2_SUPPORT,
1601                                                    DRM_MODE_CONNECTOR_DVII,
1602                                                    &ddc_i2c,
1603                                                    CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1604                                                    &hpd);
1605
1606                        /* VGA - primary dac */
1607                        ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1608                        hpd.hpd = RADEON_HPD_NONE;
1609                        radeon_add_legacy_encoder(dev,
1610                                                  radeon_get_encoder_enum(dev,
1611                                                                        ATOM_DEVICE_CRT1_SUPPORT,
1612                                                                        1),
1613                                                  ATOM_DEVICE_CRT1_SUPPORT);
1614                        radeon_add_legacy_connector(dev, 1,
1615                                                    ATOM_DEVICE_CRT1_SUPPORT,
1616                                                    DRM_MODE_CONNECTOR_VGA,
1617                                                    &ddc_i2c,
1618                                                    CONNECTOR_OBJECT_ID_VGA,
1619                                                    &hpd);
1620                }
1621
1622                if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1623                        /* TV - tv dac */
1624                        ddc_i2c.valid = false;
1625                        hpd.hpd = RADEON_HPD_NONE;
1626                        radeon_add_legacy_encoder(dev,
1627                                                  radeon_get_encoder_enum(dev,
1628                                                                        ATOM_DEVICE_TV1_SUPPORT,
1629                                                                        2),
1630                                                  ATOM_DEVICE_TV1_SUPPORT);
1631                        radeon_add_legacy_connector(dev, 2,
1632                                                    ATOM_DEVICE_TV1_SUPPORT,
1633                                                    DRM_MODE_CONNECTOR_SVIDEO,
1634                                                    &ddc_i2c,
1635                                                    CONNECTOR_OBJECT_ID_SVIDEO,
1636                                                    &hpd);
1637                }
1638                break;
1639        case CT_IBOOK:
1640                DRM_INFO("Connector Table: %d (ibook)\n",
1641                         rdev->mode_info.connector_table);
1642                /* LVDS */
1643                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1644                hpd.hpd = RADEON_HPD_NONE;
1645                radeon_add_legacy_encoder(dev,
1646                                          radeon_get_encoder_enum(dev,
1647                                                                ATOM_DEVICE_LCD1_SUPPORT,
1648                                                                0),
1649                                          ATOM_DEVICE_LCD1_SUPPORT);
1650                radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1651                                            DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1652                                            CONNECTOR_OBJECT_ID_LVDS,
1653                                            &hpd);
1654                /* VGA - TV DAC */
1655                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1656                hpd.hpd = RADEON_HPD_NONE;
1657                radeon_add_legacy_encoder(dev,
1658                                          radeon_get_encoder_enum(dev,
1659                                                                ATOM_DEVICE_CRT2_SUPPORT,
1660                                                                2),
1661                                          ATOM_DEVICE_CRT2_SUPPORT);
1662                radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1663                                            DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1664                                            CONNECTOR_OBJECT_ID_VGA,
1665                                            &hpd);
1666                /* TV - TV DAC */
1667                ddc_i2c.valid = false;
1668                hpd.hpd = RADEON_HPD_NONE;
1669                radeon_add_legacy_encoder(dev,
1670                                          radeon_get_encoder_enum(dev,
1671                                                                ATOM_DEVICE_TV1_SUPPORT,
1672                                                                2),
1673                                          ATOM_DEVICE_TV1_SUPPORT);
1674                radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1675                                            DRM_MODE_CONNECTOR_SVIDEO,
1676                                            &ddc_i2c,
1677                                            CONNECTOR_OBJECT_ID_SVIDEO,
1678                                            &hpd);
1679                break;
1680        case CT_POWERBOOK_EXTERNAL:
1681                DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1682                         rdev->mode_info.connector_table);
1683                /* LVDS */
1684                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1685                hpd.hpd = RADEON_HPD_NONE;
1686                radeon_add_legacy_encoder(dev,
1687                                          radeon_get_encoder_enum(dev,
1688                                                                ATOM_DEVICE_LCD1_SUPPORT,
1689                                                                0),
1690                                          ATOM_DEVICE_LCD1_SUPPORT);
1691                radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1692                                            DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1693                                            CONNECTOR_OBJECT_ID_LVDS,
1694                                            &hpd);
1695                /* DVI-I - primary dac, ext tmds */
1696                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1697                hpd.hpd = RADEON_HPD_2; /* ??? */
1698                radeon_add_legacy_encoder(dev,
1699                                          radeon_get_encoder_enum(dev,
1700                                                                ATOM_DEVICE_DFP2_SUPPORT,
1701                                                                0),
1702                                          ATOM_DEVICE_DFP2_SUPPORT);
1703                radeon_add_legacy_encoder(dev,
1704                                          radeon_get_encoder_enum(dev,
1705                                                                ATOM_DEVICE_CRT1_SUPPORT,
1706                                                                1),
1707                                          ATOM_DEVICE_CRT1_SUPPORT);
1708                /* XXX some are SL */
1709                radeon_add_legacy_connector(dev, 1,
1710                                            ATOM_DEVICE_DFP2_SUPPORT |
1711                                            ATOM_DEVICE_CRT1_SUPPORT,
1712                                            DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1713                                            CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1714                                            &hpd);
1715                /* TV - TV DAC */
1716                ddc_i2c.valid = false;
1717                hpd.hpd = RADEON_HPD_NONE;
1718                radeon_add_legacy_encoder(dev,
1719                                          radeon_get_encoder_enum(dev,
1720                                                                ATOM_DEVICE_TV1_SUPPORT,
1721                                                                2),
1722                                          ATOM_DEVICE_TV1_SUPPORT);
1723                radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1724                                            DRM_MODE_CONNECTOR_SVIDEO,
1725                                            &ddc_i2c,
1726                                            CONNECTOR_OBJECT_ID_SVIDEO,
1727                                            &hpd);
1728                break;
1729        case CT_POWERBOOK_INTERNAL:
1730                DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1731                         rdev->mode_info.connector_table);
1732                /* LVDS */
1733                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1734                hpd.hpd = RADEON_HPD_NONE;
1735                radeon_add_legacy_encoder(dev,
1736                                          radeon_get_encoder_enum(dev,
1737                                                                ATOM_DEVICE_LCD1_SUPPORT,
1738                                                                0),
1739                                          ATOM_DEVICE_LCD1_SUPPORT);
1740                radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1741                                            DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1742                                            CONNECTOR_OBJECT_ID_LVDS,
1743                                            &hpd);
1744                /* DVI-I - primary dac, int tmds */
1745                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1746                hpd.hpd = RADEON_HPD_1; /* ??? */
1747                radeon_add_legacy_encoder(dev,
1748                                          radeon_get_encoder_enum(dev,
1749                                                                ATOM_DEVICE_DFP1_SUPPORT,
1750                                                                0),
1751                                          ATOM_DEVICE_DFP1_SUPPORT);
1752                radeon_add_legacy_encoder(dev,
1753                                          radeon_get_encoder_enum(dev,
1754                                                                ATOM_DEVICE_CRT1_SUPPORT,
1755                                                                1),
1756                                          ATOM_DEVICE_CRT1_SUPPORT);
1757                radeon_add_legacy_connector(dev, 1,
1758                                            ATOM_DEVICE_DFP1_SUPPORT |
1759                                            ATOM_DEVICE_CRT1_SUPPORT,
1760                                            DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1761                                            CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1762                                            &hpd);
1763                /* TV - TV DAC */
1764                ddc_i2c.valid = false;
1765                hpd.hpd = RADEON_HPD_NONE;
1766                radeon_add_legacy_encoder(dev,
1767                                          radeon_get_encoder_enum(dev,
1768                                                                ATOM_DEVICE_TV1_SUPPORT,
1769                                                                2),
1770                                          ATOM_DEVICE_TV1_SUPPORT);
1771                radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1772                                            DRM_MODE_CONNECTOR_SVIDEO,
1773                                            &ddc_i2c,
1774                                            CONNECTOR_OBJECT_ID_SVIDEO,
1775                                            &hpd);
1776                break;
1777        case CT_POWERBOOK_VGA:
1778                DRM_INFO("Connector Table: %d (powerbook vga)\n",
1779                         rdev->mode_info.connector_table);
1780                /* LVDS */
1781                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1782                hpd.hpd = RADEON_HPD_NONE;
1783                radeon_add_legacy_encoder(dev,
1784                                          radeon_get_encoder_enum(dev,
1785                                                                ATOM_DEVICE_LCD1_SUPPORT,
1786                                                                0),
1787                                          ATOM_DEVICE_LCD1_SUPPORT);
1788                radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1789                                            DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1790                                            CONNECTOR_OBJECT_ID_LVDS,
1791                                            &hpd);
1792                /* VGA - primary dac */
1793                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1794                hpd.hpd = RADEON_HPD_NONE;
1795                radeon_add_legacy_encoder(dev,
1796                                          radeon_get_encoder_enum(dev,
1797                                                                ATOM_DEVICE_CRT1_SUPPORT,
1798                                                                1),
1799                                          ATOM_DEVICE_CRT1_SUPPORT);
1800                radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1801                                            DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1802                                            CONNECTOR_OBJECT_ID_VGA,
1803                                            &hpd);
1804                /* TV - TV DAC */
1805                ddc_i2c.valid = false;
1806                hpd.hpd = RADEON_HPD_NONE;
1807                radeon_add_legacy_encoder(dev,
1808                                          radeon_get_encoder_enum(dev,
1809                                                                ATOM_DEVICE_TV1_SUPPORT,
1810                                                                2),
1811                                          ATOM_DEVICE_TV1_SUPPORT);
1812                radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1813                                            DRM_MODE_CONNECTOR_SVIDEO,
1814                                            &ddc_i2c,
1815                                            CONNECTOR_OBJECT_ID_SVIDEO,
1816                                            &hpd);
1817                break;
1818        case CT_MINI_EXTERNAL:
1819                DRM_INFO("Connector Table: %d (mini external tmds)\n",
1820                         rdev->mode_info.connector_table);
1821                /* DVI-I - tv dac, ext tmds */
1822                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1823                hpd.hpd = RADEON_HPD_2; /* ??? */
1824                radeon_add_legacy_encoder(dev,
1825                                          radeon_get_encoder_enum(dev,
1826                                                                ATOM_DEVICE_DFP2_SUPPORT,
1827                                                                0),
1828                                          ATOM_DEVICE_DFP2_SUPPORT);
1829                radeon_add_legacy_encoder(dev,
1830                                          radeon_get_encoder_enum(dev,
1831                                                                ATOM_DEVICE_CRT2_SUPPORT,
1832                                                                2),
1833                                          ATOM_DEVICE_CRT2_SUPPORT);
1834                /* XXX are any DL? */
1835                radeon_add_legacy_connector(dev, 0,
1836                                            ATOM_DEVICE_DFP2_SUPPORT |
1837                                            ATOM_DEVICE_CRT2_SUPPORT,
1838                                            DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1839                                            CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1840                                            &hpd);
1841                /* TV - TV DAC */
1842                ddc_i2c.valid = false;
1843                hpd.hpd = RADEON_HPD_NONE;
1844                radeon_add_legacy_encoder(dev,
1845                                          radeon_get_encoder_enum(dev,
1846                                                                ATOM_DEVICE_TV1_SUPPORT,
1847                                                                2),
1848                                          ATOM_DEVICE_TV1_SUPPORT);
1849                radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1850                                            DRM_MODE_CONNECTOR_SVIDEO,
1851                                            &ddc_i2c,
1852                                            CONNECTOR_OBJECT_ID_SVIDEO,
1853                                            &hpd);
1854                break;
1855        case CT_MINI_INTERNAL:
1856                DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1857                         rdev->mode_info.connector_table);
1858                /* DVI-I - tv dac, int tmds */
1859                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1860                hpd.hpd = RADEON_HPD_1; /* ??? */
1861                radeon_add_legacy_encoder(dev,
1862                                          radeon_get_encoder_enum(dev,
1863                                                                ATOM_DEVICE_DFP1_SUPPORT,
1864                                                                0),
1865                                          ATOM_DEVICE_DFP1_SUPPORT);
1866                radeon_add_legacy_encoder(dev,
1867                                          radeon_get_encoder_enum(dev,
1868                                                                ATOM_DEVICE_CRT2_SUPPORT,
1869                                                                2),
1870                                          ATOM_DEVICE_CRT2_SUPPORT);
1871                radeon_add_legacy_connector(dev, 0,
1872                                            ATOM_DEVICE_DFP1_SUPPORT |
1873                                            ATOM_DEVICE_CRT2_SUPPORT,
1874                                            DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1875                                            CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1876                                            &hpd);
1877                /* TV - TV DAC */
1878                ddc_i2c.valid = false;
1879                hpd.hpd = RADEON_HPD_NONE;
1880                radeon_add_legacy_encoder(dev,
1881                                          radeon_get_encoder_enum(dev,
1882                                                                ATOM_DEVICE_TV1_SUPPORT,
1883                                                                2),
1884                                          ATOM_DEVICE_TV1_SUPPORT);
1885                radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1886                                            DRM_MODE_CONNECTOR_SVIDEO,
1887                                            &ddc_i2c,
1888                                            CONNECTOR_OBJECT_ID_SVIDEO,
1889                                            &hpd);
1890                break;
1891        case CT_IMAC_G5_ISIGHT:
1892                DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1893                         rdev->mode_info.connector_table);
1894                /* DVI-D - int tmds */
1895                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1896                hpd.hpd = RADEON_HPD_1; /* ??? */
1897                radeon_add_legacy_encoder(dev,
1898                                          radeon_get_encoder_enum(dev,
1899                                                                ATOM_DEVICE_DFP1_SUPPORT,
1900                                                                0),
1901                                          ATOM_DEVICE_DFP1_SUPPORT);
1902                radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1903                                            DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1904                                            CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1905                                            &hpd);
1906                /* VGA - tv dac */
1907                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1908                hpd.hpd = RADEON_HPD_NONE;
1909                radeon_add_legacy_encoder(dev,
1910                                          radeon_get_encoder_enum(dev,
1911                                                                ATOM_DEVICE_CRT2_SUPPORT,
1912                                                                2),
1913                                          ATOM_DEVICE_CRT2_SUPPORT);
1914                radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1915                                            DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1916                                            CONNECTOR_OBJECT_ID_VGA,
1917                                            &hpd);
1918                /* TV - TV DAC */
1919                ddc_i2c.valid = false;
1920                hpd.hpd = RADEON_HPD_NONE;
1921                radeon_add_legacy_encoder(dev,
1922                                          radeon_get_encoder_enum(dev,
1923                                                                ATOM_DEVICE_TV1_SUPPORT,
1924                                                                2),
1925                                          ATOM_DEVICE_TV1_SUPPORT);
1926                radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1927                                            DRM_MODE_CONNECTOR_SVIDEO,
1928                                            &ddc_i2c,
1929                                            CONNECTOR_OBJECT_ID_SVIDEO,
1930                                            &hpd);
1931                break;
1932        case CT_EMAC:
1933                DRM_INFO("Connector Table: %d (emac)\n",
1934                         rdev->mode_info.connector_table);
1935                /* VGA - primary dac */
1936                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1937                hpd.hpd = RADEON_HPD_NONE;
1938                radeon_add_legacy_encoder(dev,
1939                                          radeon_get_encoder_enum(dev,
1940                                                                ATOM_DEVICE_CRT1_SUPPORT,
1941                                                                1),
1942                                          ATOM_DEVICE_CRT1_SUPPORT);
1943                radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1944                                            DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1945                                            CONNECTOR_OBJECT_ID_VGA,
1946                                            &hpd);
1947                /* VGA - tv dac */
1948                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1949                hpd.hpd = RADEON_HPD_NONE;
1950                radeon_add_legacy_encoder(dev,
1951                                          radeon_get_encoder_enum(dev,
1952                                                                ATOM_DEVICE_CRT2_SUPPORT,
1953                                                                2),
1954                                          ATOM_DEVICE_CRT2_SUPPORT);
1955                radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1956                                            DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1957                                            CONNECTOR_OBJECT_ID_VGA,
1958                                            &hpd);
1959                /* TV - TV DAC */
1960                ddc_i2c.valid = false;
1961                hpd.hpd = RADEON_HPD_NONE;
1962                radeon_add_legacy_encoder(dev,
1963                                          radeon_get_encoder_enum(dev,
1964                                                                ATOM_DEVICE_TV1_SUPPORT,
1965                                                                2),
1966                                          ATOM_DEVICE_TV1_SUPPORT);
1967                radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1968                                            DRM_MODE_CONNECTOR_SVIDEO,
1969                                            &ddc_i2c,
1970                                            CONNECTOR_OBJECT_ID_SVIDEO,
1971                                            &hpd);
1972                break;
1973        case CT_RN50_POWER:
1974                DRM_INFO("Connector Table: %d (rn50-power)\n",
1975                         rdev->mode_info.connector_table);
1976                /* VGA - primary dac */
1977                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1978                hpd.hpd = RADEON_HPD_NONE;
1979                radeon_add_legacy_encoder(dev,
1980                                          radeon_get_encoder_enum(dev,
1981                                                                ATOM_DEVICE_CRT1_SUPPORT,
1982                                                                1),
1983                                          ATOM_DEVICE_CRT1_SUPPORT);
1984                radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1985                                            DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1986                                            CONNECTOR_OBJECT_ID_VGA,
1987                                            &hpd);
1988                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1989                hpd.hpd = RADEON_HPD_NONE;
1990                radeon_add_legacy_encoder(dev,
1991                                          radeon_get_encoder_enum(dev,
1992                                                                ATOM_DEVICE_CRT2_SUPPORT,
1993                                                                2),
1994                                          ATOM_DEVICE_CRT2_SUPPORT);
1995                radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1996                                            DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1997                                            CONNECTOR_OBJECT_ID_VGA,
1998                                            &hpd);
1999                break;
2000        case CT_MAC_X800:
2001                DRM_INFO("Connector Table: %d (mac x800)\n",
2002                         rdev->mode_info.connector_table);
2003                /* DVI - primary dac, internal tmds */
2004                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2005                hpd.hpd = RADEON_HPD_1; /* ??? */
2006                radeon_add_legacy_encoder(dev,
2007                                          radeon_get_encoder_enum(dev,
2008                                                                  ATOM_DEVICE_DFP1_SUPPORT,
2009                                                                  0),
2010                                          ATOM_DEVICE_DFP1_SUPPORT);
2011                radeon_add_legacy_encoder(dev,
2012                                          radeon_get_encoder_enum(dev,
2013                                                                  ATOM_DEVICE_CRT1_SUPPORT,
2014                                                                  1),
2015                                          ATOM_DEVICE_CRT1_SUPPORT);
2016                radeon_add_legacy_connector(dev, 0,
2017                                            ATOM_DEVICE_DFP1_SUPPORT |
2018                                            ATOM_DEVICE_CRT1_SUPPORT,
2019                                            DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2020                                            CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2021                                            &hpd);
2022                /* DVI - tv dac, dvo */
2023                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2024                hpd.hpd = RADEON_HPD_2; /* ??? */
2025                radeon_add_legacy_encoder(dev,
2026                                          radeon_get_encoder_enum(dev,
2027                                                                  ATOM_DEVICE_DFP2_SUPPORT,
2028                                                                  0),
2029                                          ATOM_DEVICE_DFP2_SUPPORT);
2030                radeon_add_legacy_encoder(dev,
2031                                          radeon_get_encoder_enum(dev,
2032                                                                  ATOM_DEVICE_CRT2_SUPPORT,
2033                                                                  2),
2034                                          ATOM_DEVICE_CRT2_SUPPORT);
2035                radeon_add_legacy_connector(dev, 1,
2036                                            ATOM_DEVICE_DFP2_SUPPORT |
2037                                            ATOM_DEVICE_CRT2_SUPPORT,
2038                                            DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2039                                            CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2040                                            &hpd);
2041                break;
2042        case CT_MAC_G5_9600:
2043                DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2044                         rdev->mode_info.connector_table);
2045                /* DVI - tv dac, dvo */
2046                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2047                hpd.hpd = RADEON_HPD_1; /* ??? */
2048                radeon_add_legacy_encoder(dev,
2049                                          radeon_get_encoder_enum(dev,
2050                                                                  ATOM_DEVICE_DFP2_SUPPORT,
2051                                                                  0),
2052                                          ATOM_DEVICE_DFP2_SUPPORT);
2053                radeon_add_legacy_encoder(dev,
2054                                          radeon_get_encoder_enum(dev,
2055                                                                  ATOM_DEVICE_CRT2_SUPPORT,
2056                                                                  2),
2057                                          ATOM_DEVICE_CRT2_SUPPORT);
2058                radeon_add_legacy_connector(dev, 0,
2059                                            ATOM_DEVICE_DFP2_SUPPORT |
2060                                            ATOM_DEVICE_CRT2_SUPPORT,
2061                                            DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2062                                            CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2063                                            &hpd);
2064                /* ADC - primary dac, internal tmds */
2065                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2066                hpd.hpd = RADEON_HPD_2; /* ??? */
2067                radeon_add_legacy_encoder(dev,
2068                                          radeon_get_encoder_enum(dev,
2069                                                                  ATOM_DEVICE_DFP1_SUPPORT,
2070                                                                  0),
2071                                          ATOM_DEVICE_DFP1_SUPPORT);
2072                radeon_add_legacy_encoder(dev,
2073                                          radeon_get_encoder_enum(dev,
2074                                                                  ATOM_DEVICE_CRT1_SUPPORT,
2075                                                                  1),
2076                                          ATOM_DEVICE_CRT1_SUPPORT);
2077                radeon_add_legacy_connector(dev, 1,
2078                                            ATOM_DEVICE_DFP1_SUPPORT |
2079                                            ATOM_DEVICE_CRT1_SUPPORT,
2080                                            DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2081                                            CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2082                                            &hpd);
2083                /* TV - TV DAC */
2084                ddc_i2c.valid = false;
2085                hpd.hpd = RADEON_HPD_NONE;
2086                radeon_add_legacy_encoder(dev,
2087                                          radeon_get_encoder_enum(dev,
2088                                                                ATOM_DEVICE_TV1_SUPPORT,
2089                                                                2),
2090                                          ATOM_DEVICE_TV1_SUPPORT);
2091                radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2092                                            DRM_MODE_CONNECTOR_SVIDEO,
2093                                            &ddc_i2c,
2094                                            CONNECTOR_OBJECT_ID_SVIDEO,
2095                                            &hpd);
2096                break;
2097        case CT_SAM440EP:
2098                DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n",
2099                         rdev->mode_info.connector_table);
2100                /* LVDS */
2101                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
2102                hpd.hpd = RADEON_HPD_NONE;
2103                radeon_add_legacy_encoder(dev,
2104                                          radeon_get_encoder_enum(dev,
2105                                                                ATOM_DEVICE_LCD1_SUPPORT,
2106                                                                0),
2107                                          ATOM_DEVICE_LCD1_SUPPORT);
2108                radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
2109                                            DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
2110                                            CONNECTOR_OBJECT_ID_LVDS,
2111                                            &hpd);
2112                /* DVI-I - secondary dac, int tmds */
2113                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2114                hpd.hpd = RADEON_HPD_1; /* ??? */
2115                radeon_add_legacy_encoder(dev,
2116                                          radeon_get_encoder_enum(dev,
2117                                                                ATOM_DEVICE_DFP1_SUPPORT,
2118                                                                0),
2119                                          ATOM_DEVICE_DFP1_SUPPORT);
2120                radeon_add_legacy_encoder(dev,
2121                                          radeon_get_encoder_enum(dev,
2122                                                                ATOM_DEVICE_CRT2_SUPPORT,
2123                                                                2),
2124                                          ATOM_DEVICE_CRT2_SUPPORT);
2125                radeon_add_legacy_connector(dev, 1,
2126                                            ATOM_DEVICE_DFP1_SUPPORT |
2127                                            ATOM_DEVICE_CRT2_SUPPORT,
2128                                            DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2129                                            CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2130                                            &hpd);
2131                /* VGA - primary dac */
2132                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2133                hpd.hpd = RADEON_HPD_NONE;
2134                radeon_add_legacy_encoder(dev,
2135                                          radeon_get_encoder_enum(dev,
2136                                                                ATOM_DEVICE_CRT1_SUPPORT,
2137                                                                1),
2138                                          ATOM_DEVICE_CRT1_SUPPORT);
2139                radeon_add_legacy_connector(dev, 2,
2140                                            ATOM_DEVICE_CRT1_SUPPORT,
2141                                            DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2142                                            CONNECTOR_OBJECT_ID_VGA,
2143                                            &hpd);
2144                /* TV - TV DAC */
2145                ddc_i2c.valid = false;
2146                hpd.hpd = RADEON_HPD_NONE;
2147                radeon_add_legacy_encoder(dev,
2148                                          radeon_get_encoder_enum(dev,
2149                                                                ATOM_DEVICE_TV1_SUPPORT,
2150                                                                2),
2151                                          ATOM_DEVICE_TV1_SUPPORT);
2152                radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT,
2153                                            DRM_MODE_CONNECTOR_SVIDEO,
2154                                            &ddc_i2c,
2155                                            CONNECTOR_OBJECT_ID_SVIDEO,
2156                                            &hpd);
2157                break;
2158        case CT_MAC_G4_SILVER:
2159                DRM_INFO("Connector Table: %d (mac g4 silver)\n",
2160                         rdev->mode_info.connector_table);
2161                /* DVI-I - tv dac, int tmds */
2162                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2163                hpd.hpd = RADEON_HPD_1; /* ??? */
2164                radeon_add_legacy_encoder(dev,
2165                                          radeon_get_encoder_enum(dev,
2166                                                                ATOM_DEVICE_DFP1_SUPPORT,
2167                                                                0),
2168                                          ATOM_DEVICE_DFP1_SUPPORT);
2169                radeon_add_legacy_encoder(dev,
2170                                          radeon_get_encoder_enum(dev,
2171                                                                ATOM_DEVICE_CRT2_SUPPORT,
2172                                                                2),
2173                                          ATOM_DEVICE_CRT2_SUPPORT);
2174                radeon_add_legacy_connector(dev, 0,
2175                                            ATOM_DEVICE_DFP1_SUPPORT |
2176                                            ATOM_DEVICE_CRT2_SUPPORT,
2177                                            DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2178                                            CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2179                                            &hpd);
2180                /* VGA - primary dac */
2181                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2182                hpd.hpd = RADEON_HPD_NONE;
2183                radeon_add_legacy_encoder(dev,
2184                                          radeon_get_encoder_enum(dev,
2185                                                                ATOM_DEVICE_CRT1_SUPPORT,
2186                                                                1),
2187                                          ATOM_DEVICE_CRT1_SUPPORT);
2188                radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
2189                                            DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2190                                            CONNECTOR_OBJECT_ID_VGA,
2191                                            &hpd);
2192                /* TV - TV DAC */
2193                ddc_i2c.valid = false;
2194                hpd.hpd = RADEON_HPD_NONE;
2195                radeon_add_legacy_encoder(dev,
2196                                          radeon_get_encoder_enum(dev,
2197                                                                ATOM_DEVICE_TV1_SUPPORT,
2198                                                                2),
2199                                          ATOM_DEVICE_TV1_SUPPORT);
2200                radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2201                                            DRM_MODE_CONNECTOR_SVIDEO,
2202                                            &ddc_i2c,
2203                                            CONNECTOR_OBJECT_ID_SVIDEO,
2204                                            &hpd);
2205                break;
2206        default:
2207                DRM_INFO("Connector table: %d (invalid)\n",
2208                         rdev->mode_info.connector_table);
2209                return false;
2210        }
2211
2212        radeon_link_encoder_connector(dev);
2213
2214        return true;
2215}
2216
2217static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2218                                       int bios_index,
2219                                       enum radeon_combios_connector
2220                                       *legacy_connector,
2221                                       struct radeon_i2c_bus_rec *ddc_i2c,
2222                                       struct radeon_hpd *hpd)
2223{
2224        struct radeon_device *rdev = dev->dev_private;
2225
2226        /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2227           one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2228        if (rdev->pdev->device == 0x515e &&
2229            rdev->pdev->subsystem_vendor == 0x1014) {
2230                if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2231                    ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2232                        return false;
2233        }
2234
2235        /* X300 card with extra non-existent DVI port */
2236        if (rdev->pdev->device == 0x5B60 &&
2237            rdev->pdev->subsystem_vendor == 0x17af &&
2238            rdev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2239                if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2240                        return false;
2241        }
2242
2243        return true;
2244}
2245
2246static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2247{
2248        struct radeon_device *rdev = dev->dev_private;
2249
2250        /* Acer 5102 has non-existent TV port */
2251        if (rdev->pdev->device == 0x5975 &&
2252            rdev->pdev->subsystem_vendor == 0x1025 &&
2253            rdev->pdev->subsystem_device == 0x009f)
2254                return false;
2255
2256        /* HP dc5750 has non-existent TV port */
2257        if (rdev->pdev->device == 0x5974 &&
2258            rdev->pdev->subsystem_vendor == 0x103c &&
2259            rdev->pdev->subsystem_device == 0x280a)
2260                return false;
2261
2262        /* MSI S270 has non-existent TV port */
2263        if (rdev->pdev->device == 0x5955 &&
2264            rdev->pdev->subsystem_vendor == 0x1462 &&
2265            rdev->pdev->subsystem_device == 0x0131)
2266                return false;
2267
2268        return true;
2269}
2270
2271static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2272{
2273        struct radeon_device *rdev = dev->dev_private;
2274        uint32_t ext_tmds_info;
2275
2276        if (rdev->flags & RADEON_IS_IGP) {
2277                if (is_dvi_d)
2278                        return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2279                else
2280                        return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2281        }
2282        ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2283        if (ext_tmds_info) {
2284                uint8_t rev = RBIOS8(ext_tmds_info);
2285                uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2286                if (rev >= 3) {
2287                        if (is_dvi_d)
2288                                return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2289                        else
2290                                return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2291                } else {
2292                        if (flags & 1) {
2293                                if (is_dvi_d)
2294                                        return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2295                                else
2296                                        return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2297                        }
2298                }
2299        }
2300        if (is_dvi_d)
2301                return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2302        else
2303                return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2304}
2305
2306bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2307{
2308        struct radeon_device *rdev = dev->dev_private;
2309        uint32_t conn_info, entry, devices;
2310        uint16_t tmp, connector_object_id;
2311        enum radeon_combios_ddc ddc_type;
2312        enum radeon_combios_connector connector;
2313        int i = 0;
2314        struct radeon_i2c_bus_rec ddc_i2c;
2315        struct radeon_hpd hpd;
2316
2317        conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2318        if (conn_info) {
2319                for (i = 0; i < 4; i++) {
2320                        entry = conn_info + 2 + i * 2;
2321
2322                        if (!RBIOS16(entry))
2323                                break;
2324
2325                        tmp = RBIOS16(entry);
2326
2327                        connector = (tmp >> 12) & 0xf;
2328
2329                        ddc_type = (tmp >> 8) & 0xf;
2330                        if (ddc_type == 5)
2331                                ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev);
2332                        else
2333                                ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2334
2335                        switch (connector) {
2336                        case CONNECTOR_PROPRIETARY_LEGACY:
2337                        case CONNECTOR_DVI_I_LEGACY:
2338                        case CONNECTOR_DVI_D_LEGACY:
2339                                if ((tmp >> 4) & 0x1)
2340                                        hpd.hpd = RADEON_HPD_2;
2341                                else
2342                                        hpd.hpd = RADEON_HPD_1;
2343                                break;
2344                        default:
2345                                hpd.hpd = RADEON_HPD_NONE;
2346                                break;
2347                        }
2348
2349                        if (!radeon_apply_legacy_quirks(dev, i, &connector,
2350                                                        &ddc_i2c, &hpd))
2351                                continue;
2352
2353                        switch (connector) {
2354                        case CONNECTOR_PROPRIETARY_LEGACY:
2355                                if ((tmp >> 4) & 0x1)
2356                                        devices = ATOM_DEVICE_DFP2_SUPPORT;
2357                                else
2358                                        devices = ATOM_DEVICE_DFP1_SUPPORT;
2359                                radeon_add_legacy_encoder(dev,
2360                                                          radeon_get_encoder_enum
2361                                                          (dev, devices, 0),
2362                                                          devices);
2363                                radeon_add_legacy_connector(dev, i, devices,
2364                                                            legacy_connector_convert
2365                                                            [connector],
2366                                                            &ddc_i2c,
2367                                                            CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2368                                                            &hpd);
2369                                break;
2370                        case CONNECTOR_CRT_LEGACY:
2371                                if (tmp & 0x1) {
2372                                        devices = ATOM_DEVICE_CRT2_SUPPORT;
2373                                        radeon_add_legacy_encoder(dev,
2374                                                                  radeon_get_encoder_enum
2375                                                                  (dev,
2376                                                                   ATOM_DEVICE_CRT2_SUPPORT,
2377                                                                   2),
2378                                                                  ATOM_DEVICE_CRT2_SUPPORT);
2379                                } else {
2380                                        devices = ATOM_DEVICE_CRT1_SUPPORT;
2381                                        radeon_add_legacy_encoder(dev,
2382                                                                  radeon_get_encoder_enum
2383                                                                  (dev,
2384                                                                   ATOM_DEVICE_CRT1_SUPPORT,
2385                                                                   1),
2386                                                                  ATOM_DEVICE_CRT1_SUPPORT);
2387                                }
2388                                radeon_add_legacy_connector(dev,
2389                                                            i,
2390                                                            devices,
2391                                                            legacy_connector_convert
2392                                                            [connector],
2393                                                            &ddc_i2c,
2394                                                            CONNECTOR_OBJECT_ID_VGA,
2395                                                            &hpd);
2396                                break;
2397                        case CONNECTOR_DVI_I_LEGACY:
2398                                devices = 0;
2399                                if (tmp & 0x1) {
2400                                        devices |= ATOM_DEVICE_CRT2_SUPPORT;
2401                                        radeon_add_legacy_encoder(dev,
2402                                                                  radeon_get_encoder_enum
2403                                                                  (dev,
2404                                                                   ATOM_DEVICE_CRT2_SUPPORT,
2405                                                                   2),
2406                                                                  ATOM_DEVICE_CRT2_SUPPORT);
2407                                } else {
2408                                        devices |= ATOM_DEVICE_CRT1_SUPPORT;
2409                                        radeon_add_legacy_encoder(dev,
2410                                                                  radeon_get_encoder_enum
2411                                                                  (dev,
2412                                                                   ATOM_DEVICE_CRT1_SUPPORT,
2413                                                                   1),
2414                                                                  ATOM_DEVICE_CRT1_SUPPORT);
2415                                }
2416                                /* RV100 board with external TDMS bit mis-set.
2417                                 * Actually uses internal TMDS, clear the bit.
2418                                 */
2419                                if (rdev->pdev->device == 0x5159 &&
2420                                    rdev->pdev->subsystem_vendor == 0x1014 &&
2421                                    rdev->pdev->subsystem_device == 0x029A) {
2422                                        tmp &= ~(1 << 4);
2423                                }
2424                                if ((tmp >> 4) & 0x1) {
2425                                        devices |= ATOM_DEVICE_DFP2_SUPPORT;
2426                                        radeon_add_legacy_encoder(dev,
2427                                                                  radeon_get_encoder_enum
2428                                                                  (dev,
2429                                                                   ATOM_DEVICE_DFP2_SUPPORT,
2430                                                                   0),
2431                                                                  ATOM_DEVICE_DFP2_SUPPORT);
2432                                        connector_object_id = combios_check_dl_dvi(dev, 0);
2433                                } else {
2434                                        devices |= ATOM_DEVICE_DFP1_SUPPORT;
2435                                        radeon_add_legacy_encoder(dev,
2436                                                                  radeon_get_encoder_enum
2437                                                                  (dev,
2438                                                                   ATOM_DEVICE_DFP1_SUPPORT,
2439                                                                   0),
2440                                                                  ATOM_DEVICE_DFP1_SUPPORT);
2441                                        connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2442                                }
2443                                radeon_add_legacy_connector(dev,
2444                                                            i,
2445                                                            devices,
2446                                                            legacy_connector_convert
2447                                                            [connector],
2448                                                            &ddc_i2c,
2449                                                            connector_object_id,
2450                                                            &hpd);
2451                                break;
2452                        case CONNECTOR_DVI_D_LEGACY:
2453                                if ((tmp >> 4) & 0x1) {
2454                                        devices = ATOM_DEVICE_DFP2_SUPPORT;
2455                                        connector_object_id = combios_check_dl_dvi(dev, 1);
2456                                } else {
2457                                        devices = ATOM_DEVICE_DFP1_SUPPORT;
2458                                        connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2459                                }
2460                                radeon_add_legacy_encoder(dev,
2461                                                          radeon_get_encoder_enum
2462                                                          (dev, devices, 0),
2463                                                          devices);
2464                                radeon_add_legacy_connector(dev, i, devices,
2465                                                            legacy_connector_convert
2466                                                            [connector],
2467                                                            &ddc_i2c,
2468                                                            connector_object_id,
2469                                                            &hpd);
2470                                break;
2471                        case CONNECTOR_CTV_LEGACY:
2472                        case CONNECTOR_STV_LEGACY:
2473                                radeon_add_legacy_encoder(dev,
2474                                                          radeon_get_encoder_enum
2475                                                          (dev,
2476                                                           ATOM_DEVICE_TV1_SUPPORT,
2477                                                           2),
2478                                                          ATOM_DEVICE_TV1_SUPPORT);
2479                                radeon_add_legacy_connector(dev, i,
2480                                                            ATOM_DEVICE_TV1_SUPPORT,
2481                                                            legacy_connector_convert
2482                                                            [connector],
2483                                                            &ddc_i2c,
2484                                                            CONNECTOR_OBJECT_ID_SVIDEO,
2485                                                            &hpd);
2486                                break;
2487                        default:
2488                                DRM_ERROR("Unknown connector type: %d\n",
2489                                          connector);
2490                                continue;
2491                        }
2492
2493                }
2494        } else {
2495                uint16_t tmds_info =
2496                    combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2497                if (tmds_info) {
2498                        DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2499
2500                        radeon_add_legacy_encoder(dev,
2501                                                  radeon_get_encoder_enum(dev,
2502                                                                        ATOM_DEVICE_CRT1_SUPPORT,
2503                                                                        1),
2504                                                  ATOM_DEVICE_CRT1_SUPPORT);
2505                        radeon_add_legacy_encoder(dev,
2506                                                  radeon_get_encoder_enum(dev,
2507                                                                        ATOM_DEVICE_DFP1_SUPPORT,
2508                                                                        0),
2509                                                  ATOM_DEVICE_DFP1_SUPPORT);
2510
2511                        ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2512                        hpd.hpd = RADEON_HPD_1;
2513                        radeon_add_legacy_connector(dev,
2514                                                    0,
2515                                                    ATOM_DEVICE_CRT1_SUPPORT |
2516                                                    ATOM_DEVICE_DFP1_SUPPORT,
2517                                                    DRM_MODE_CONNECTOR_DVII,
2518                                                    &ddc_i2c,
2519                                                    CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2520                                                    &hpd);
2521                } else {
2522                        uint16_t crt_info =
2523                                combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2524                        DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2525                        if (crt_info) {
2526                                radeon_add_legacy_encoder(dev,
2527                                                          radeon_get_encoder_enum(dev,
2528                                                                                ATOM_DEVICE_CRT1_SUPPORT,
2529                                                                                1),
2530                                                          ATOM_DEVICE_CRT1_SUPPORT);
2531                                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2532                                hpd.hpd = RADEON_HPD_NONE;
2533                                radeon_add_legacy_connector(dev,
2534                                                            0,
2535                                                            ATOM_DEVICE_CRT1_SUPPORT,
2536                                                            DRM_MODE_CONNECTOR_VGA,
2537                                                            &ddc_i2c,
2538                                                            CONNECTOR_OBJECT_ID_VGA,
2539                                                            &hpd);
2540                        } else {
2541                                DRM_DEBUG_KMS("No connector info found\n");
2542                                return false;
2543                        }
2544                }
2545        }
2546
2547        if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2548                uint16_t lcd_info =
2549                    combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2550                if (lcd_info) {
2551                        uint16_t lcd_ddc_info =
2552                            combios_get_table_offset(dev,
2553                                                     COMBIOS_LCD_DDC_INFO_TABLE);
2554
2555                        radeon_add_legacy_encoder(dev,
2556                                                  radeon_get_encoder_enum(dev,
2557                                                                        ATOM_DEVICE_LCD1_SUPPORT,
2558                                                                        0),
2559                                                  ATOM_DEVICE_LCD1_SUPPORT);
2560
2561                        if (lcd_ddc_info) {
2562                                ddc_type = RBIOS8(lcd_ddc_info + 2);
2563                                switch (ddc_type) {
2564                                case DDC_LCD:
2565                                        ddc_i2c =
2566                                                combios_setup_i2c_bus(rdev,
2567                                                                      DDC_LCD,
2568                                                                      RBIOS32(lcd_ddc_info + 3),
2569                                                                      RBIOS32(lcd_ddc_info + 7));
2570                                        radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2571                                        break;
2572                                case DDC_GPIO:
2573                                        ddc_i2c =
2574                                                combios_setup_i2c_bus(rdev,
2575                                                                      DDC_GPIO,
2576                                                                      RBIOS32(lcd_ddc_info + 3),
2577                                                                      RBIOS32(lcd_ddc_info + 7));
2578                                        radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2579                                        break;
2580                                default:
2581                                        ddc_i2c =
2582                                                combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2583                                        break;
2584                                }
2585                                DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2586                        } else
2587                                ddc_i2c.valid = false;
2588
2589                        hpd.hpd = RADEON_HPD_NONE;
2590                        radeon_add_legacy_connector(dev,
2591                                                    5,
2592                                                    ATOM_DEVICE_LCD1_SUPPORT,
2593                                                    DRM_MODE_CONNECTOR_LVDS,
2594                                                    &ddc_i2c,
2595                                                    CONNECTOR_OBJECT_ID_LVDS,
2596                                                    &hpd);
2597                }
2598        }
2599
2600        /* check TV table */
2601        if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2602                uint32_t tv_info =
2603                    combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2604                if (tv_info) {
2605                        if (RBIOS8(tv_info + 6) == 'T') {
2606                                if (radeon_apply_legacy_tv_quirks(dev)) {
2607                                        hpd.hpd = RADEON_HPD_NONE;
2608                                        ddc_i2c.valid = false;
2609                                        radeon_add_legacy_encoder(dev,
2610                                                                  radeon_get_encoder_enum
2611                                                                  (dev,
2612                                                                   ATOM_DEVICE_TV1_SUPPORT,
2613                                                                   2),
2614                                                                  ATOM_DEVICE_TV1_SUPPORT);
2615                                        radeon_add_legacy_connector(dev, 6,
2616                                                                    ATOM_DEVICE_TV1_SUPPORT,
2617                                                                    DRM_MODE_CONNECTOR_SVIDEO,
2618                                                                    &ddc_i2c,
2619                                                                    CONNECTOR_OBJECT_ID_SVIDEO,
2620                                                                    &hpd);
2621                                }
2622                        }
2623                }
2624        }
2625
2626        radeon_link_encoder_connector(dev);
2627
2628        return true;
2629}
2630
2631static const char *thermal_controller_names[] = {
2632        "NONE",
2633        "lm63",
2634        "adm1032",
2635};
2636
2637void radeon_combios_get_power_modes(struct radeon_device *rdev)
2638{
2639        struct drm_device *dev = rdev->ddev;
2640        u16 offset, misc, misc2 = 0;
2641        u8 rev, tmp;
2642        int state_index = 0;
2643        struct radeon_i2c_bus_rec i2c_bus;
2644
2645        rdev->pm.default_power_state_index = -1;
2646
2647        /* allocate 2 power states */
2648        rdev->pm.power_state = kcalloc(2, sizeof(struct radeon_power_state),
2649                                       GFP_KERNEL);
2650        if (rdev->pm.power_state) {
2651                /* allocate 1 clock mode per state */
2652                rdev->pm.power_state[0].clock_info =
2653                        kcalloc(1, sizeof(struct radeon_pm_clock_info),
2654                                GFP_KERNEL);
2655                rdev->pm.power_state[1].clock_info =
2656                        kcalloc(1, sizeof(struct radeon_pm_clock_info),
2657                                GFP_KERNEL);
2658                if (!rdev->pm.power_state[0].clock_info ||
2659                    !rdev->pm.power_state[1].clock_info)
2660                        goto pm_failed;
2661        } else
2662                goto pm_failed;
2663
2664        /* check for a thermal chip */
2665        offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
2666        if (offset) {
2667                u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
2668
2669                rev = RBIOS8(offset);
2670
2671                if (rev == 0) {
2672                        thermal_controller = RBIOS8(offset + 3);
2673                        gpio = RBIOS8(offset + 4) & 0x3f;
2674                        i2c_addr = RBIOS8(offset + 5);
2675                } else if (rev == 1) {
2676                        thermal_controller = RBIOS8(offset + 4);
2677                        gpio = RBIOS8(offset + 5) & 0x3f;
2678                        i2c_addr = RBIOS8(offset + 6);
2679                } else if (rev == 2) {
2680                        thermal_controller = RBIOS8(offset + 4);
2681                        gpio = RBIOS8(offset + 5) & 0x3f;
2682                        i2c_addr = RBIOS8(offset + 6);
2683                        clk_bit = RBIOS8(offset + 0xa);
2684                        data_bit = RBIOS8(offset + 0xb);
2685                }
2686                if ((thermal_controller > 0) && (thermal_controller < 3)) {
2687                        DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2688                                 thermal_controller_names[thermal_controller],
2689                                 i2c_addr >> 1);
2690                        if (gpio == DDC_LCD) {
2691                                /* MM i2c */
2692                                i2c_bus.valid = true;
2693                                i2c_bus.hw_capable = true;
2694                                i2c_bus.mm_i2c = true;
2695                                i2c_bus.i2c_id = 0xa0;
2696                        } else if (gpio == DDC_GPIO)
2697                                i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
2698                        else
2699                                i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
2700                        rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2701                        if (rdev->pm.i2c_bus) {
2702                                struct i2c_board_info info = { };
2703                                const char *name = thermal_controller_names[thermal_controller];
2704                                info.addr = i2c_addr >> 1;
2705                                strlcpy(info.type, name, sizeof(info.type));
2706                                i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2707                        }
2708                }
2709        } else {
2710                /* boards with a thermal chip, but no overdrive table */
2711
2712                /* Asus 9600xt has an f75375 on the monid bus */
2713                if ((rdev->pdev->device == 0x4152) &&
2714                    (rdev->pdev->subsystem_vendor == 0x1043) &&
2715                    (rdev->pdev->subsystem_device == 0xc002)) {
2716                        i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2717                        rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2718                        if (rdev->pm.i2c_bus) {
2719                                struct i2c_board_info info = { };
2720                                const char *name = "f75375";
2721                                info.addr = 0x28;
2722                                strlcpy(info.type, name, sizeof(info.type));
2723                                i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2724                                DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2725                                         name, info.addr);
2726                        }
2727                }
2728        }
2729
2730        if (rdev->flags & RADEON_IS_MOBILITY) {
2731                offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2732                if (offset) {
2733                        rev = RBIOS8(offset);
2734                        /* power mode 0 tends to be the only valid one */
2735                        rdev->pm.power_state[state_index].num_clock_modes = 1;
2736                        rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2737                        rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2738                        if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2739                            (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2740                                goto default_mode;
2741                        rdev->pm.power_state[state_index].type =
2742                                POWER_STATE_TYPE_BATTERY;
2743                        misc = RBIOS16(offset + 0x5 + 0x0);
2744                        if (rev > 4)
2745                                misc2 = RBIOS16(offset + 0x5 + 0xe);
2746                        rdev->pm.power_state[state_index].misc = misc;
2747                        rdev->pm.power_state[state_index].misc2 = misc2;
2748                        if (misc & 0x4) {
2749                                rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2750                                if (misc & 0x8)
2751                                        rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2752                                                true;
2753                                else
2754                                        rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2755                                                false;
2756                                rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2757                                if (rev < 6) {
2758                                        rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2759                                                RBIOS16(offset + 0x5 + 0xb) * 4;
2760                                        tmp = RBIOS8(offset + 0x5 + 0xd);
2761                                        rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2762                                } else {
2763                                        u8 entries = RBIOS8(offset + 0x5 + 0xb);
2764                                        u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2765                                        if (entries && voltage_table_offset) {
2766                                                rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2767                                                        RBIOS16(voltage_table_offset) * 4;
2768                                                tmp = RBIOS8(voltage_table_offset + 0x2);
2769                                                rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2770                                        } else
2771                                                rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2772                                }
2773                                switch ((misc2 & 0x700) >> 8) {
2774                                case 0:
2775                                default:
2776                                        rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2777                                        break;
2778                                case 1:
2779                                        rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2780                                        break;
2781                                case 2:
2782                                        rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2783                                        break;
2784                                case 3:
2785                                        rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2786                                        break;
2787                                case 4:
2788                                        rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2789                                        break;
2790                                }
2791                        } else
2792                                rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2793                        if (rev > 6)
2794                                rdev->pm.power_state[state_index].pcie_lanes =
2795                                        RBIOS8(offset + 0x5 + 0x10);
2796                        rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2797                        state_index++;
2798                } else {
2799                        /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2800                }
2801        } else {
2802                /* XXX figure out some good default low power mode for desktop cards */
2803        }
2804
2805default_mode:
2806        /* add the default mode */
2807        rdev->pm.power_state[state_index].type =
2808                POWER_STATE_TYPE_DEFAULT;
2809        rdev->pm.power_state[state_index].num_clock_modes = 1;
2810        rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2811        rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2812        rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2813        if ((state_index > 0) &&
2814            (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2815                rdev->pm.power_state[state_index].clock_info[0].voltage =
2816                        rdev->pm.power_state[0].clock_info[0].voltage;
2817        else
2818                rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2819        rdev->pm.power_state[state_index].pcie_lanes = 16;
2820        rdev->pm.power_state[state_index].flags = 0;
2821        rdev->pm.default_power_state_index = state_index;
2822        rdev->pm.num_power_states = state_index + 1;
2823
2824        rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2825        rdev->pm.current_clock_mode_index = 0;
2826        return;
2827
2828pm_failed:
2829        rdev->pm.default_power_state_index = state_index;
2830        rdev->pm.num_power_states = 0;
2831
2832        rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2833        rdev->pm.current_clock_mode_index = 0;
2834}
2835
2836void radeon_external_tmds_setup(struct drm_encoder *encoder)
2837{
2838        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2839        struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2840
2841        if (!tmds)
2842                return;
2843
2844        switch (tmds->dvo_chip) {
2845        case DVO_SIL164:
2846                /* sil 164 */
2847                radeon_i2c_put_byte(tmds->i2c_bus,
2848                                    tmds->slave_addr,
2849                                    0x08, 0x30);
2850                radeon_i2c_put_byte(tmds->i2c_bus,
2851                                       tmds->slave_addr,
2852                                       0x09, 0x00);
2853                radeon_i2c_put_byte(tmds->i2c_bus,
2854                                    tmds->slave_addr,
2855                                    0x0a, 0x90);
2856                radeon_i2c_put_byte(tmds->i2c_bus,
2857                                    tmds->slave_addr,
2858                                    0x0c, 0x89);
2859                radeon_i2c_put_byte(tmds->i2c_bus,
2860                                       tmds->slave_addr,
2861                                       0x08, 0x3b);
2862                break;
2863        case DVO_SIL1178:
2864                /* sil 1178 - untested */
2865                /*
2866                 * 0x0f, 0x44
2867                 * 0x0f, 0x4c
2868                 * 0x0e, 0x01
2869                 * 0x0a, 0x80
2870                 * 0x09, 0x30
2871                 * 0x0c, 0xc9
2872                 * 0x0d, 0x70
2873                 * 0x08, 0x32
2874                 * 0x08, 0x33
2875                 */
2876                break;
2877        default:
2878                break;
2879        }
2880
2881}
2882
2883bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2884{
2885        struct drm_device *dev = encoder->dev;
2886        struct radeon_device *rdev = dev->dev_private;
2887        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2888        uint16_t offset;
2889        uint8_t blocks, slave_addr, rev;
2890        uint32_t index, id;
2891        uint32_t reg, val, and_mask, or_mask;
2892        struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2893
2894        if (!tmds)
2895                return false;
2896
2897        if (rdev->flags & RADEON_IS_IGP) {
2898                offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2899                rev = RBIOS8(offset);
2900                if (offset) {
2901                        rev = RBIOS8(offset);
2902                        if (rev > 1) {
2903                                blocks = RBIOS8(offset + 3);
2904                                index = offset + 4;
2905                                while (blocks > 0) {
2906                                        id = RBIOS16(index);
2907                                        index += 2;
2908                                        switch (id >> 13) {
2909                                        case 0:
2910                                                reg = (id & 0x1fff) * 4;
2911                                                val = RBIOS32(index);
2912                                                index += 4;
2913                                                WREG32(reg, val);
2914                                                break;
2915                                        case 2:
2916                                                reg = (id & 0x1fff) * 4;
2917                                                and_mask = RBIOS32(index);
2918                                                index += 4;
2919                                                or_mask = RBIOS32(index);
2920                                                index += 4;
2921                                                val = RREG32(reg);
2922                                                val = (val & and_mask) | or_mask;
2923                                                WREG32(reg, val);
2924                                                break;
2925                                        case 3:
2926                                                val = RBIOS16(index);
2927                                                index += 2;
2928                                                udelay(val);
2929                                                break;
2930                                        case 4:
2931                                                val = RBIOS16(index);
2932                                                index += 2;
2933                                                mdelay(val);
2934                                                break;
2935                                        case 6:
2936                                                slave_addr = id & 0xff;
2937                                                slave_addr >>= 1; /* 7 bit addressing */
2938                                                index++;
2939                                                reg = RBIOS8(index);
2940                                                index++;
2941                                                val = RBIOS8(index);
2942                                                index++;
2943                                                radeon_i2c_put_byte(tmds->i2c_bus,
2944                                                                    slave_addr,
2945                                                                    reg, val);
2946                                                break;
2947                                        default:
2948                                                DRM_ERROR("Unknown id %d\n", id >> 13);
2949                                                break;
2950                                        }
2951                                        blocks--;
2952                                }
2953                                return true;
2954                        }
2955                }
2956        } else {
2957                offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2958                if (offset) {
2959                        index = offset + 10;
2960                        id = RBIOS16(index);
2961                        while (id != 0xffff) {
2962                                index += 2;
2963                                switch (id >> 13) {
2964                                case 0:
2965                                        reg = (id & 0x1fff) * 4;
2966                                        val = RBIOS32(index);
2967                                        WREG32(reg, val);
2968                                        break;
2969                                case 2:
2970                                        reg = (id & 0x1fff) * 4;
2971                                        and_mask = RBIOS32(index);
2972                                        index += 4;
2973                                        or_mask = RBIOS32(index);
2974                                        index += 4;
2975                                        val = RREG32(reg);
2976                                        val = (val & and_mask) | or_mask;
2977                                        WREG32(reg, val);
2978                                        break;
2979                                case 4:
2980                                        val = RBIOS16(index);
2981                                        index += 2;
2982                                        udelay(val);
2983                                        break;
2984                                case 5:
2985                                        reg = id & 0x1fff;
2986                                        and_mask = RBIOS32(index);
2987                                        index += 4;
2988                                        or_mask = RBIOS32(index);
2989                                        index += 4;
2990                                        val = RREG32_PLL(reg);
2991                                        val = (val & and_mask) | or_mask;
2992                                        WREG32_PLL(reg, val);
2993                                        break;
2994                                case 6:
2995                                        reg = id & 0x1fff;
2996                                        val = RBIOS8(index);
2997                                        index += 1;
2998                                        radeon_i2c_put_byte(tmds->i2c_bus,
2999                                                            tmds->slave_addr,
3000                                                            reg, val);
3001                                        break;
3002                                default:
3003                                        DRM_ERROR("Unknown id %d\n", id >> 13);
3004                                        break;
3005                                }
3006                                id = RBIOS16(index);
3007                        }
3008                        return true;
3009                }
3010        }
3011        return false;
3012}
3013
3014static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
3015{
3016        struct radeon_device *rdev = dev->dev_private;
3017
3018        if (offset) {
3019                while (RBIOS16(offset)) {
3020                        uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
3021                        uint32_t addr = (RBIOS16(offset) & 0x1fff);
3022                        uint32_t val, and_mask, or_mask;
3023                        uint32_t tmp;
3024
3025                        offset += 2;
3026                        switch (cmd) {
3027                        case 0:
3028                                val = RBIOS32(offset);
3029                                offset += 4;
3030                                WREG32(addr, val);
3031                                break;
3032                        case 1:
3033                                val = RBIOS32(offset);
3034                                offset += 4;
3035                                WREG32(addr, val);
3036                                break;
3037                        case 2:
3038                                and_mask = RBIOS32(offset);
3039                                offset += 4;
3040                                or_mask = RBIOS32(offset);
3041                                offset += 4;
3042                                tmp = RREG32(addr);
3043                                tmp &= and_mask;
3044                                tmp |= or_mask;
3045                                WREG32(addr, tmp);
3046                                break;
3047                        case 3:
3048                                and_mask = RBIOS32(offset);
3049                                offset += 4;
3050                                or_mask = RBIOS32(offset);
3051                                offset += 4;
3052                                tmp = RREG32(addr);
3053                                tmp &= and_mask;
3054                                tmp |= or_mask;
3055                                WREG32(addr, tmp);
3056                                break;
3057                        case 4:
3058                                val = RBIOS16(offset);
3059                                offset += 2;
3060                                udelay(val);
3061                                break;
3062                        case 5:
3063                                val = RBIOS16(offset);
3064                                offset += 2;
3065                                switch (addr) {
3066                                case 8:
3067                                        while (val--) {
3068                                                if (!
3069                                                    (RREG32_PLL
3070                                                     (RADEON_CLK_PWRMGT_CNTL) &
3071                                                     RADEON_MC_BUSY))
3072                                                        break;
3073                                        }
3074                                        break;
3075                                case 9:
3076                                        while (val--) {
3077                                                if ((RREG32(RADEON_MC_STATUS) &
3078                                                     RADEON_MC_IDLE))
3079                                                        break;
3080                                        }
3081                                        break;
3082                                default:
3083                                        break;
3084                                }
3085                                break;
3086                        default:
3087                                break;
3088                        }
3089                }
3090        }
3091}
3092
3093static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
3094{
3095        struct radeon_device *rdev = dev->dev_private;
3096
3097        if (offset) {
3098                while (RBIOS8(offset)) {
3099                        uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
3100                        uint8_t addr = (RBIOS8(offset) & 0x3f);
3101                        uint32_t val, shift, tmp;
3102                        uint32_t and_mask, or_mask;
3103
3104                        offset++;
3105                        switch (cmd) {
3106                        case 0:
3107                                val = RBIOS32(offset);
3108                                offset += 4;
3109                                WREG32_PLL(addr, val);
3110                                break;
3111                        case 1:
3112                                shift = RBIOS8(offset) * 8;
3113                                offset++;
3114                                and_mask = RBIOS8(offset) << shift;
3115                                and_mask |= ~(0xff << shift);
3116                                offset++;
3117                                or_mask = RBIOS8(offset) << shift;
3118                                offset++;
3119                                tmp = RREG32_PLL(addr);
3120                                tmp &= and_mask;
3121                                tmp |= or_mask;
3122                                WREG32_PLL(addr, tmp);
3123                                break;
3124                        case 2:
3125                        case 3:
3126                                tmp = 1000;
3127                                switch (addr) {
3128                                case 1:
3129                                        udelay(150);
3130                                        break;
3131                                case 2:
3132                                        mdelay(1);
3133                                        break;
3134                                case 3:
3135                                        while (tmp--) {
3136                                                if (!
3137                                                    (RREG32_PLL
3138                                                     (RADEON_CLK_PWRMGT_CNTL) &
3139                                                     RADEON_MC_BUSY))
3140                                                        break;
3141                                        }
3142                                        break;
3143                                case 4:
3144                                        while (tmp--) {
3145                                                if (RREG32_PLL
3146                                                    (RADEON_CLK_PWRMGT_CNTL) &
3147                                                    RADEON_DLL_READY)
3148                                                        break;
3149                                        }
3150                                        break;
3151                                case 5:
3152                                        tmp =
3153                                            RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
3154                                        if (tmp & RADEON_CG_NO1_DEBUG_0) {
3155#if 0
3156                                                uint32_t mclk_cntl =
3157                                                    RREG32_PLL
3158                                                    (RADEON_MCLK_CNTL);
3159                                                mclk_cntl &= 0xffff0000;
3160                                                /*mclk_cntl |= 0x00001111;*//* ??? */
3161                                                WREG32_PLL(RADEON_MCLK_CNTL,
3162                                                           mclk_cntl);
3163                                                mdelay(10);
3164#endif
3165                                                WREG32_PLL
3166                                                    (RADEON_CLK_PWRMGT_CNTL,
3167                                                     tmp &
3168                                                     ~RADEON_CG_NO1_DEBUG_0);
3169                                                mdelay(10);
3170                                        }
3171                                        break;
3172                                default:
3173                                        break;
3174                                }
3175                                break;
3176                        default:
3177                                break;
3178                        }
3179                }
3180        }
3181}
3182
3183static void combios_parse_ram_reset_table(struct drm_device *dev,
3184                                          uint16_t offset)
3185{
3186        struct radeon_device *rdev = dev->dev_private;
3187        uint32_t tmp;
3188
3189        if (offset) {
3190                uint8_t val = RBIOS8(offset);
3191                while (val != 0xff) {
3192                        offset++;
3193
3194                        if (val == 0x0f) {
3195                                uint32_t channel_complete_mask;
3196
3197                                if (ASIC_IS_R300(rdev))
3198                                        channel_complete_mask =
3199                                            R300_MEM_PWRUP_COMPLETE;
3200                                else
3201                                        channel_complete_mask =
3202                                            RADEON_MEM_PWRUP_COMPLETE;
3203                                tmp = 20000;
3204                                while (tmp--) {
3205                                        if ((RREG32(RADEON_MEM_STR_CNTL) &
3206                                             channel_complete_mask) ==
3207                                            channel_complete_mask)
3208                                                break;
3209                                }
3210                        } else {
3211                                uint32_t or_mask = RBIOS16(offset);
3212                                offset += 2;
3213
3214                                tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3215                                tmp &= RADEON_SDRAM_MODE_MASK;
3216                                tmp |= or_mask;
3217                                WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3218
3219                                or_mask = val << 24;
3220                                tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3221                                tmp &= RADEON_B3MEM_RESET_MASK;
3222                                tmp |= or_mask;
3223                                WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3224                        }
3225                        val = RBIOS8(offset);
3226                }
3227        }
3228}
3229
3230static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3231                                   int mem_addr_mapping)
3232{
3233        struct radeon_device *rdev = dev->dev_private;
3234        uint32_t mem_cntl;
3235        uint32_t mem_size;
3236        uint32_t addr = 0;
3237
3238        mem_cntl = RREG32(RADEON_MEM_CNTL);
3239        if (mem_cntl & RV100_HALF_MODE)
3240                ram /= 2;
3241        mem_size = ram;
3242        mem_cntl &= ~(0xff << 8);
3243        mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3244        WREG32(RADEON_MEM_CNTL, mem_cntl);
3245        RREG32(RADEON_MEM_CNTL);
3246
3247        /* sdram reset ? */
3248
3249        /* something like this????  */
3250        while (ram--) {
3251                addr = ram * 1024 * 1024;
3252                /* write to each page */
3253                WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef);
3254                /* read back and verify */
3255                if (RREG32_IDX((addr) | RADEON_MM_APER) != 0xdeadbeef)
3256                        return 0;
3257        }
3258
3259        return mem_size;
3260}
3261
3262static void combios_write_ram_size(struct drm_device *dev)
3263{
3264        struct radeon_device *rdev = dev->dev_private;
3265        uint8_t rev;
3266        uint16_t offset;
3267        uint32_t mem_size = 0;
3268        uint32_t mem_cntl = 0;
3269
3270        /* should do something smarter here I guess... */
3271        if (rdev->flags & RADEON_IS_IGP)
3272                return;
3273
3274        /* first check detected mem table */
3275        offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3276        if (offset) {
3277                rev = RBIOS8(offset);
3278                if (rev < 3) {
3279                        mem_cntl = RBIOS32(offset + 1);
3280                        mem_size = RBIOS16(offset + 5);
3281                        if ((rdev->family < CHIP_R200) &&
3282                            !ASIC_IS_RN50(rdev))
3283                                WREG32(RADEON_MEM_CNTL, mem_cntl);
3284                }
3285        }
3286
3287        if (!mem_size) {
3288                offset =
3289                    combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3290                if (offset) {
3291                        rev = RBIOS8(offset - 1);
3292                        if (rev < 1) {
3293                                if ((rdev->family < CHIP_R200)
3294                                    && !ASIC_IS_RN50(rdev)) {
3295                                        int ram = 0;
3296                                        int mem_addr_mapping = 0;
3297
3298                                        while (RBIOS8(offset)) {
3299                                                ram = RBIOS8(offset);
3300                                                mem_addr_mapping =
3301                                                    RBIOS8(offset + 1);
3302                                                if (mem_addr_mapping != 0x25)
3303                                                        ram *= 2;
3304                                                mem_size =
3305                                                    combios_detect_ram(dev, ram,
3306                                                                       mem_addr_mapping);
3307                                                if (mem_size)
3308                                                        break;
3309                                                offset += 2;
3310                                        }
3311                                } else
3312                                        mem_size = RBIOS8(offset);
3313                        } else {
3314                                mem_size = RBIOS8(offset);
3315                                mem_size *= 2;  /* convert to MB */
3316                        }
3317                }
3318        }
3319
3320        mem_size *= (1024 * 1024);      /* convert to bytes */
3321        WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3322}
3323
3324void radeon_combios_asic_init(struct drm_device *dev)
3325{
3326        struct radeon_device *rdev = dev->dev_private;
3327        uint16_t table;
3328
3329        /* port hardcoded mac stuff from radeonfb */
3330        if (rdev->bios == NULL)
3331                return;
3332
3333        /* ASIC INIT 1 */
3334        table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3335        if (table)
3336                combios_parse_mmio_table(dev, table);
3337
3338        /* PLL INIT */
3339        table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3340        if (table)
3341                combios_parse_pll_table(dev, table);
3342
3343        /* ASIC INIT 2 */
3344        table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3345        if (table)
3346                combios_parse_mmio_table(dev, table);
3347
3348        if (!(rdev->flags & RADEON_IS_IGP)) {
3349                /* ASIC INIT 4 */
3350                table =
3351                    combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3352                if (table)
3353                        combios_parse_mmio_table(dev, table);
3354
3355                /* RAM RESET */
3356                table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3357                if (table)
3358                        combios_parse_ram_reset_table(dev, table);
3359
3360                /* ASIC INIT 3 */
3361                table =
3362                    combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3363                if (table)
3364                        combios_parse_mmio_table(dev, table);
3365
3366                /* write CONFIG_MEMSIZE */
3367                combios_write_ram_size(dev);
3368        }
3369
3370        /* quirk for rs4xx HP nx6125 laptop to make it resume
3371         * - it hangs on resume inside the dynclk 1 table.
3372         */
3373        if (rdev->family == CHIP_RS480 &&
3374            rdev->pdev->subsystem_vendor == 0x103c &&
3375            rdev->pdev->subsystem_device == 0x308b)
3376                return;
3377
3378        /* quirk for rs4xx HP dv5000 laptop to make it resume
3379         * - it hangs on resume inside the dynclk 1 table.
3380         */
3381        if (rdev->family == CHIP_RS480 &&
3382            rdev->pdev->subsystem_vendor == 0x103c &&
3383            rdev->pdev->subsystem_device == 0x30a4)
3384                return;
3385
3386        /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume
3387         * - it hangs on resume inside the dynclk 1 table.
3388         */
3389        if (rdev->family == CHIP_RS480 &&
3390            rdev->pdev->subsystem_vendor == 0x103c &&
3391            rdev->pdev->subsystem_device == 0x30ae)
3392                return;
3393
3394        /* quirk for rs4xx HP Compaq dc5750 Small Form Factor to make it resume
3395         * - it hangs on resume inside the dynclk 1 table.
3396         */
3397        if (rdev->family == CHIP_RS480 &&
3398            rdev->pdev->subsystem_vendor == 0x103c &&
3399            rdev->pdev->subsystem_device == 0x280a)
3400                return;
3401        /* quirk for rs4xx Toshiba Sattellite L20-183 latop to make it resume
3402         * - it hangs on resume inside the dynclk 1 table.
3403         */
3404        if (rdev->family == CHIP_RS400 &&
3405            rdev->pdev->subsystem_vendor == 0x1179 &&
3406            rdev->pdev->subsystem_device == 0xff31)
3407                return;
3408
3409        /* DYN CLK 1 */
3410        table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3411        if (table)
3412                combios_parse_pll_table(dev, table);
3413
3414}
3415
3416void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3417{
3418        struct radeon_device *rdev = dev->dev_private;
3419        uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3420
3421        bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3422        bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3423        bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3424
3425        /* let the bios control the backlight */
3426        bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3427
3428        /* tell the bios not to handle mode switching */
3429        bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3430                           RADEON_ACC_MODE_CHANGE);
3431
3432        /* tell the bios a driver is loaded */
3433        bios_7_scratch |= RADEON_DRV_LOADED;
3434
3435        WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3436        WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3437        WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3438}
3439
3440void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3441{
3442        struct drm_device *dev = encoder->dev;
3443        struct radeon_device *rdev = dev->dev_private;
3444        uint32_t bios_6_scratch;
3445
3446        bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3447
3448        if (lock)
3449                bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3450        else
3451                bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3452
3453        WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3454}
3455
3456void
3457radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3458                                      struct drm_encoder *encoder,
3459                                      bool connected)
3460{
3461        struct drm_device *dev = connector->dev;
3462        struct radeon_device *rdev = dev->dev_private;
3463        struct radeon_connector *radeon_connector =
3464            to_radeon_connector(connector);
3465        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3466        uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3467        uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3468
3469        if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3470            (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3471                if (connected) {
3472                        DRM_DEBUG_KMS("TV1 connected\n");
3473                        /* fix me */
3474                        bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3475                        /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3476                        bios_5_scratch |= RADEON_TV1_ON;
3477                        bios_5_scratch |= RADEON_ACC_REQ_TV1;
3478                } else {
3479                        DRM_DEBUG_KMS("TV1 disconnected\n");
3480                        bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3481                        bios_5_scratch &= ~RADEON_TV1_ON;
3482                        bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3483                }
3484        }
3485        if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3486            (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3487                if (connected) {
3488                        DRM_DEBUG_KMS("LCD1 connected\n");
3489                        bios_4_scratch |= RADEON_LCD1_ATTACHED;
3490                        bios_5_scratch |= RADEON_LCD1_ON;
3491                        bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3492                } else {
3493                        DRM_DEBUG_KMS("LCD1 disconnected\n");
3494                        bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3495                        bios_5_scratch &= ~RADEON_LCD1_ON;
3496                        bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3497                }
3498        }
3499        if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3500            (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3501                if (connected) {
3502                        DRM_DEBUG_KMS("CRT1 connected\n");
3503                        bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3504                        bios_5_scratch |= RADEON_CRT1_ON;
3505                        bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3506                } else {
3507                        DRM_DEBUG_KMS("CRT1 disconnected\n");
3508                        bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3509                        bios_5_scratch &= ~RADEON_CRT1_ON;
3510                        bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3511                }
3512        }
3513        if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3514            (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3515                if (connected) {
3516                        DRM_DEBUG_KMS("CRT2 connected\n");
3517                        bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3518                        bios_5_scratch |= RADEON_CRT2_ON;
3519                        bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3520                } else {
3521                        DRM_DEBUG_KMS("CRT2 disconnected\n");
3522                        bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3523                        bios_5_scratch &= ~RADEON_CRT2_ON;
3524                        bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3525                }
3526        }
3527        if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3528            (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3529                if (connected) {
3530                        DRM_DEBUG_KMS("DFP1 connected\n");
3531                        bios_4_scratch |= RADEON_DFP1_ATTACHED;
3532                        bios_5_scratch |= RADEON_DFP1_ON;
3533                        bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3534                } else {
3535                        DRM_DEBUG_KMS("DFP1 disconnected\n");
3536                        bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3537                        bios_5_scratch &= ~RADEON_DFP1_ON;
3538                        bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3539                }
3540        }
3541        if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3542            (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3543                if (connected) {
3544                        DRM_DEBUG_KMS("DFP2 connected\n");
3545                        bios_4_scratch |= RADEON_DFP2_ATTACHED;
3546                        bios_5_scratch |= RADEON_DFP2_ON;
3547                        bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3548                } else {
3549                        DRM_DEBUG_KMS("DFP2 disconnected\n");
3550                        bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3551                        bios_5_scratch &= ~RADEON_DFP2_ON;
3552                        bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3553                }
3554        }
3555        WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3556        WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3557}
3558
3559void
3560radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3561{
3562        struct drm_device *dev = encoder->dev;
3563        struct radeon_device *rdev = dev->dev_private;
3564        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3565        uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3566
3567        if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3568                bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3569                bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3570        }
3571        if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3572                bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3573                bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3574        }
3575        if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3576                bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3577                bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3578        }
3579        if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3580                bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3581                bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3582        }
3583        if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3584                bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3585                bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3586        }
3587        if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3588                bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3589                bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3590        }
3591        WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3592}
3593
3594void
3595radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3596{
3597        struct drm_device *dev = encoder->dev;
3598        struct radeon_device *rdev = dev->dev_private;
3599        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3600        uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3601
3602        if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3603                if (on)
3604                        bios_6_scratch |= RADEON_TV_DPMS_ON;
3605                else
3606                        bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3607        }
3608        if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3609                if (on)
3610                        bios_6_scratch |= RADEON_CRT_DPMS_ON;
3611                else
3612                        bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3613        }
3614        if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3615                if (on)
3616                        bios_6_scratch |= RADEON_LCD_DPMS_ON;
3617                else
3618                        bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3619        }
3620        if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3621                if (on)
3622                        bios_6_scratch |= RADEON_DFP_DPMS_ON;
3623                else
3624                        bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3625        }
3626        WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3627}
3628