LXR linux/drivers/gpu/host1x/hw/debug_hw

   1/*
   2 * Copyright (C) 2010 Google, Inc.
   3 * Author: Erik Gilling <konkers@android.com>
   4 *
   5 * Copyright (C) 2011-2017 NVIDIA Corporation
   6 *
   7 * This software is licensed under the terms of the GNU General Public
   8 * License version 2, as published by the Free Software Foundation, and
   9 * may be copied, distributed, and modified under those terms.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 */
  17
  18#include "../dev.h"
  19#include "../debug.h"
  20#include "../cdma.h"
  21#include "../channel.h"
  22
  23static void host1x_debug_show_channel_cdma(struct host1x *host,
  24                                           struct host1x_channel *ch,
  25                                           struct output *o)
  26{
  27        struct host1x_cdma *cdma = &ch->cdma;
  28        u32 dmaput, dmaget, dmactrl;
  29        u32 offset, class;
  30        u32 ch_stat;
  31
  32        dmaput = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAPUT);
  33        dmaget = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAGET);
  34        dmactrl = host1x_ch_readl(ch, HOST1X_CHANNEL_DMACTRL);
  35        offset = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDP_OFFSET);
  36        class = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDP_CLASS);
  37        ch_stat = host1x_ch_readl(ch, HOST1X_CHANNEL_CHANNELSTAT);
  38
  39        host1x_debug_output(o, "%u-%s: ", ch->id, dev_name(ch->dev));
  40
  41        if (dmactrl & HOST1X_CHANNEL_DMACTRL_DMASTOP ||
  42            !ch->cdma.push_buffer.mapped) {
  43                host1x_debug_output(o, "inactive\n\n");
  44                return;
  45        }
  46
  47        if (class == HOST1X_CLASS_HOST1X && offset == HOST1X_UCLASS_WAIT_SYNCPT)
  48                host1x_debug_output(o, "waiting on syncpt\n");
  49        else
  50                host1x_debug_output(o, "active class %02x, offset %04x\n",
  51                                    class, offset);
  52
  53        host1x_debug_output(o, "DMAPUT %08x, DMAGET %08x, DMACTL %08x\n",
  54                            dmaput, dmaget, dmactrl);
  55        host1x_debug_output(o, "CHANNELSTAT %02x\n", ch_stat);
  56
  57        show_channel_gathers(o, cdma);
  58        host1x_debug_output(o, "\n");
  59}
  60
  61static void host1x_debug_show_channel_fifo(struct host1x *host,
  62                                           struct host1x_channel *ch,
  63                                           struct output *o)
  64{
  65        u32 val, rd_ptr, wr_ptr, start, end;
  66        u32 payload = INVALID_PAYLOAD;
  67        unsigned int data_count = 0;
  68
  69        host1x_debug_output(o, "%u: fifo:\n", ch->id);
  70
  71        val = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDFIFO_STAT);
  72        host1x_debug_output(o, "CMDFIFO_STAT %08x\n", val);
  73        if (val & HOST1X_CHANNEL_CMDFIFO_STAT_EMPTY) {
  74                host1x_debug_output(o, "[empty]\n");
  75                return;
  76        }
  77
  78        val = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDFIFO_RDATA);
  79        host1x_debug_output(o, "CMDFIFO_RDATA %08x\n", val);
  80
  81        /* Peek pointer values are invalid during SLCG, so disable it */
  82        host1x_hypervisor_writel(host, 0x1, HOST1X_HV_ICG_EN_OVERRIDE);
  83
  84        val = 0;
  85        val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_ENABLE;
  86        val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_CHANNEL(ch->id);
  87        host1x_hypervisor_writel(host, val, HOST1X_HV_CMDFIFO_PEEK_CTRL);
  88
  89        val = host1x_hypervisor_readl(host, HOST1X_HV_CMDFIFO_PEEK_PTRS);
  90        rd_ptr = HOST1X_HV_CMDFIFO_PEEK_PTRS_RD_PTR_V(val);
  91        wr_ptr = HOST1X_HV_CMDFIFO_PEEK_PTRS_WR_PTR_V(val);
  92
  93        val = host1x_hypervisor_readl(host, HOST1X_HV_CMDFIFO_SETUP(ch->id));
  94        start = HOST1X_HV_CMDFIFO_SETUP_BASE_V(val);
  95        end = HOST1X_HV_CMDFIFO_SETUP_LIMIT_V(val);
  96
  97        do {
  98                val = 0;
  99                val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_ENABLE;
 100                val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_CHANNEL(ch->id);
 101                val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_ADDR(rd_ptr);
 102                host1x_hypervisor_writel(host, val,
 103                                         HOST1X_HV_CMDFIFO_PEEK_CTRL);
 104
 105                val = host1x_hypervisor_readl(host,
 106                                              HOST1X_HV_CMDFIFO_PEEK_READ);
 107
 108                if (!data_count) {
 109                        host1x_debug_output(o, "%03x 0x%08x: ",
 110                                            rd_ptr - start, val);
 111                        data_count = show_channel_command(o, val, &payload);
 112                } else {
 113                        host1x_debug_cont(o, "%08x%s", val,
 114                                          data_count > 1 ? ", " : "])\n");
 115                        data_count--;
 116                }
 117
 118                if (rd_ptr == end)
 119                        rd_ptr = start;
 120                else
 121                        rd_ptr++;
 122        } while (rd_ptr != wr_ptr);
 123
 124        if (data_count)
 125                host1x_debug_cont(o, ", ...])\n");
 126        host1x_debug_output(o, "\n");
 127
 128        host1x_hypervisor_writel(host, 0x0, HOST1X_HV_CMDFIFO_PEEK_CTRL);
 129        host1x_hypervisor_writel(host, 0x0, HOST1X_HV_ICG_EN_OVERRIDE);
 130}
 131
 132static void host1x_debug_show_mlocks(struct host1x *host, struct output *o)
 133{
 134        /* TODO */
 135}
 136