LXR linux/drivers/iio/dac/ad5686.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * This file is part of AD5686 DAC driver
   4 *
   5 * Copyright 2018 Analog Devices Inc.
   6 */
   7
   8#ifndef __DRIVERS_IIO_DAC_AD5686_H__
   9#define __DRIVERS_IIO_DAC_AD5686_H__
  10
  11#include <linux/types.h>
  12#include <linux/cache.h>
  13#include <linux/mutex.h>
  14#include <linux/kernel.h>
  15
  16#define AD5683_DATA(x)                          ((x) << 4)
  17#define AD5686_ADDR(x)                          ((x) << 16)
  18#define AD5686_CMD(x)                           ((x) << 20)
  19
  20#define AD5686_ADDR_DAC(chan)                   (0x1 << (chan))
  21#define AD5686_ADDR_ALL_DAC                     0xF
  22
  23#define AD5686_CMD_NOOP                         0x0
  24#define AD5686_CMD_WRITE_INPUT_N                0x1
  25#define AD5686_CMD_UPDATE_DAC_N                 0x2
  26#define AD5686_CMD_WRITE_INPUT_N_UPDATE_N       0x3
  27#define AD5686_CMD_POWERDOWN_DAC                0x4
  28#define AD5686_CMD_LDAC_MASK                    0x5
  29#define AD5686_CMD_RESET                        0x6
  30#define AD5686_CMD_INTERNAL_REFER_SETUP         0x7
  31#define AD5686_CMD_DAISY_CHAIN_ENABLE           0x8
  32#define AD5686_CMD_READBACK_ENABLE              0x9
  33
  34#define AD5686_LDAC_PWRDN_NONE                  0x0
  35#define AD5686_LDAC_PWRDN_1K                    0x1
  36#define AD5686_LDAC_PWRDN_100K                  0x2
  37#define AD5686_LDAC_PWRDN_3STATE                0x3
  38
  39#define AD5686_CMD_CONTROL_REG                  0x4
  40#define AD5686_CMD_READBACK_ENABLE_V2           0x5
  41#define AD5683_REF_BIT_MSK                      BIT(12)
  42#define AD5693_REF_BIT_MSK                      BIT(12)
  43
  44/**
  45 * ad5686_supported_device_ids:
  46 */
  47enum ad5686_supported_device_ids {
  48        ID_AD5671R,
  49        ID_AD5672R,
  50        ID_AD5675R,
  51        ID_AD5676,
  52        ID_AD5676R,
  53        ID_AD5681R,
  54        ID_AD5682R,
  55        ID_AD5683,
  56        ID_AD5683R,
  57        ID_AD5684,
  58        ID_AD5684R,
  59        ID_AD5685R,
  60        ID_AD5686,
  61        ID_AD5686R,
  62        ID_AD5691R,
  63        ID_AD5692R,
  64        ID_AD5693,
  65        ID_AD5693R,
  66        ID_AD5694,
  67        ID_AD5694R,
  68        ID_AD5695R,
  69        ID_AD5696,
  70        ID_AD5696R,
  71};
  72
  73enum ad5686_regmap_type {
  74        AD5683_REGMAP,
  75        AD5686_REGMAP,
  76        AD5693_REGMAP
  77};
  78
  79struct ad5686_state;
  80
  81typedef int (*ad5686_write_func)(struct ad5686_state *st,
  82                                 u8 cmd, u8 addr, u16 val);
  83
  84typedef int (*ad5686_read_func)(struct ad5686_state *st, u8 addr);
  85
  86/**
  87 * struct ad5686_chip_info - chip specific information
  88 * @int_vref_mv:        AD5620/40/60: the internal reference voltage
  89 * @num_channels:       number of channels
  90 * @channel:            channel specification
  91 * @regmap_type:        register map layout variant
  92 */
  93
  94struct ad5686_chip_info {
  95        u16                             int_vref_mv;
  96        unsigned int                    num_channels;
  97        struct iio_chan_spec            *channels;
  98        enum ad5686_regmap_type         regmap_type;
  99};
 100
 101/**
 102 * struct ad5446_state - driver instance specific data
 103 * @spi:                spi_device
 104 * @chip_info:          chip model specific constants, available modes etc
 105 * @reg:                supply regulator
 106 * @vref_mv:            actual reference voltage used
 107 * @pwr_down_mask:      power down mask
 108 * @pwr_down_mode:      current power down mode
 109 * @use_internal_vref:  set to true if the internal reference voltage is used
 110 * @data:               spi transfer buffers
 111 */
 112
 113struct ad5686_state {
 114        struct device                   *dev;
 115        const struct ad5686_chip_info   *chip_info;
 116        struct regulator                *reg;
 117        unsigned short                  vref_mv;
 118        unsigned int                    pwr_down_mask;
 119        unsigned int                    pwr_down_mode;
 120        ad5686_write_func               write;
 121        ad5686_read_func                read;
 122        bool                            use_internal_vref;
 123
 124        /*
 125         * DMA (thus cache coherency maintenance) requires the
 126         * transfer buffers to live in their own cache lines.
 127         */
 128
 129        union {
 130                __be32 d32;
 131                __be16 d16;
 132                u8 d8[4];
 133        } data[3] ____cacheline_aligned;
 134};
 135
 136
 137int ad5686_probe(struct device *dev,
 138                 enum ad5686_supported_device_ids chip_type,
 139                 const char *name, ad5686_write_func write,
 140                 ad5686_read_func read);
 141
 142int ad5686_remove(struct device *dev);
 143
 144
 145#endif /* __DRIVERS_IIO_DAC_AD5686_H__ */
 146