1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22#include <linux/interrupt.h>
23#include <linux/irqdomain.h>
24#include <linux/irq.h>
25#include <linux/irqchip.h>
26#include <linux/of_irq.h>
27#include <linux/of_address.h>
28#include <linux/of_platform.h>
29#include <linux/io.h>
30#include <linux/slab.h>
31#include <linux/bitops.h>
32
33#define AB_IRQCTL_INT_ENABLE 0x00
34#define AB_IRQCTL_INT_STATUS 0x04
35#define AB_IRQCTL_SRC_MODE 0x08
36#define AB_IRQCTL_SRC_POLARITY 0x0C
37#define AB_IRQCTL_INT_MODE 0x10
38#define AB_IRQCTL_INT_POLARITY 0x14
39#define AB_IRQCTL_INT_FORCE 0x18
40
41#define AB_IRQCTL_MAXIRQ 32
42
43static inline void ab_irqctl_writereg(struct irq_chip_generic *gc, u32 reg,
44 u32 val)
45{
46 irq_reg_writel(gc, val, reg);
47}
48
49static inline u32 ab_irqctl_readreg(struct irq_chip_generic *gc, u32 reg)
50{
51 return irq_reg_readl(gc, reg);
52}
53
54static int tb10x_irq_set_type(struct irq_data *data, unsigned int flow_type)
55{
56 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
57 uint32_t im, mod, pol;
58
59 im = data->mask;
60
61 irq_gc_lock(gc);
62
63 mod = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_MODE) | im;
64 pol = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_POLARITY) | im;
65
66 switch (flow_type & IRQF_TRIGGER_MASK) {
67 case IRQ_TYPE_EDGE_FALLING:
68 pol ^= im;
69 break;
70 case IRQ_TYPE_LEVEL_HIGH:
71 mod ^= im;
72 break;
73 case IRQ_TYPE_NONE:
74 flow_type = IRQ_TYPE_LEVEL_LOW;
75 case IRQ_TYPE_LEVEL_LOW:
76 mod ^= im;
77 pol ^= im;
78 break;
79 case IRQ_TYPE_EDGE_RISING:
80 break;
81 default:
82 irq_gc_unlock(gc);
83 pr_err("%s: Cannot assign multiple trigger modes to IRQ %d.\n",
84 __func__, data->irq);
85 return -EBADR;
86 }
87
88 irqd_set_trigger_type(data, flow_type);
89 irq_setup_alt_chip(data, flow_type);
90
91 ab_irqctl_writereg(gc, AB_IRQCTL_SRC_MODE, mod);
92 ab_irqctl_writereg(gc, AB_IRQCTL_SRC_POLARITY, pol);
93 ab_irqctl_writereg(gc, AB_IRQCTL_INT_STATUS, im);
94
95 irq_gc_unlock(gc);
96
97 return IRQ_SET_MASK_OK;
98}
99
100static void tb10x_irq_cascade(struct irq_desc *desc)
101{
102 struct irq_domain *domain = irq_desc_get_handler_data(desc);
103 unsigned int irq = irq_desc_get_irq(desc);
104
105 generic_handle_irq(irq_find_mapping(domain, irq));
106}
107
108static int __init of_tb10x_init_irq(struct device_node *ictl,
109 struct device_node *parent)
110{
111 int i, ret, nrirqs = of_irq_count(ictl);
112 struct resource mem;
113 struct irq_chip_generic *gc;
114 struct irq_domain *domain;
115 void __iomem *reg_base;
116
117 if (of_address_to_resource(ictl, 0, &mem)) {
118 pr_err("%pOFn: No registers declared in DeviceTree.\n",
119 ictl);
120 return -EINVAL;
121 }
122
123 if (!request_mem_region(mem.start, resource_size(&mem),
124 ictl->full_name)) {
125 pr_err("%pOFn: Request mem region failed.\n", ictl);
126 return -EBUSY;
127 }
128
129 reg_base = ioremap(mem.start, resource_size(&mem));
130 if (!reg_base) {
131 ret = -EBUSY;
132 pr_err("%pOFn: ioremap failed.\n", ictl);
133 goto ioremap_fail;
134 }
135
136 domain = irq_domain_add_linear(ictl, AB_IRQCTL_MAXIRQ,
137 &irq_generic_chip_ops, NULL);
138 if (!domain) {
139 ret = -ENOMEM;
140 pr_err("%pOFn: Could not register interrupt domain.\n",
141 ictl);
142 goto irq_domain_add_fail;
143 }
144
145 ret = irq_alloc_domain_generic_chips(domain, AB_IRQCTL_MAXIRQ,
146 2, ictl->name, handle_level_irq,
147 IRQ_NOREQUEST, IRQ_NOPROBE,
148 IRQ_GC_INIT_MASK_CACHE);
149 if (ret) {
150 pr_err("%pOFn: Could not allocate generic interrupt chip.\n",
151 ictl);
152 goto gc_alloc_fail;
153 }
154
155 gc = domain->gc->gc[0];
156 gc->reg_base = reg_base;
157
158 gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
159 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
160 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
161 gc->chip_types[0].chip.irq_set_type = tb10x_irq_set_type;
162 gc->chip_types[0].regs.mask = AB_IRQCTL_INT_ENABLE;
163
164 gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
165 gc->chip_types[1].chip.name = gc->chip_types[0].chip.name;
166 gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit;
167 gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit;
168 gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit;
169 gc->chip_types[1].chip.irq_set_type = tb10x_irq_set_type;
170 gc->chip_types[1].regs.ack = AB_IRQCTL_INT_STATUS;
171 gc->chip_types[1].regs.mask = AB_IRQCTL_INT_ENABLE;
172 gc->chip_types[1].handler = handle_edge_irq;
173
174 for (i = 0; i < nrirqs; i++) {
175 unsigned int irq = irq_of_parse_and_map(ictl, i);
176
177 irq_set_chained_handler_and_data(irq, tb10x_irq_cascade,
178 domain);
179 }
180
181 ab_irqctl_writereg(gc, AB_IRQCTL_INT_ENABLE, 0);
182 ab_irqctl_writereg(gc, AB_IRQCTL_INT_MODE, 0);
183 ab_irqctl_writereg(gc, AB_IRQCTL_INT_POLARITY, 0);
184 ab_irqctl_writereg(gc, AB_IRQCTL_INT_STATUS, ~0UL);
185
186 return 0;
187
188gc_alloc_fail:
189 irq_domain_remove(domain);
190irq_domain_add_fail:
191 iounmap(reg_base);
192ioremap_fail:
193 release_mem_region(mem.start, resource_size(&mem));
194 return ret;
195}
196IRQCHIP_DECLARE(tb10x_intc, "abilis,tb10x-ictl", of_tb10x_init_irq);
197
