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16#include <linux/slab.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/i2c.h>
20#include <linux/regmap.h>
21#include <linux/wait.h>
22#include <linux/delay.h>
23#include <linux/mutex.h>
24#include <linux/io.h>
25
26#include "cxd2099.h"
27
28static int buffermode;
29module_param(buffermode, int, 0444);
30MODULE_PARM_DESC(buffermode, "Enable CXD2099AR buffer mode (default: disabled)");
31
32static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount);
33
34struct cxd {
35 struct dvb_ca_en50221 en;
36
37 struct cxd2099_cfg cfg;
38 struct i2c_client *client;
39 struct regmap *regmap;
40
41 u8 regs[0x23];
42 u8 lastaddress;
43 u8 clk_reg_f;
44 u8 clk_reg_b;
45 int mode;
46 int ready;
47 int dr;
48 int write_busy;
49 int slot_stat;
50
51 u8 amem[1024];
52 int amem_read;
53
54 int cammode;
55 struct mutex lock;
56
57 u8 rbuf[1028];
58 u8 wbuf[1028];
59};
60
61static int read_block(struct cxd *ci, u8 adr, u8 *data, u16 n)
62{
63 int status = 0;
64
65 if (ci->lastaddress != adr)
66 status = regmap_write(ci->regmap, 0, adr);
67 if (!status) {
68 ci->lastaddress = adr;
69
70 while (n) {
71 int len = n;
72
73 if (ci->cfg.max_i2c && len > ci->cfg.max_i2c)
74 len = ci->cfg.max_i2c;
75 status = regmap_raw_read(ci->regmap, 1, data, len);
76 if (status)
77 return status;
78 data += len;
79 n -= len;
80 }
81 }
82 return status;
83}
84
85static int read_reg(struct cxd *ci, u8 reg, u8 *val)
86{
87 return read_block(ci, reg, val, 1);
88}
89
90static int read_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
91{
92 int status;
93 u8 addr[2] = {address & 0xff, address >> 8};
94
95 status = regmap_raw_write(ci->regmap, 2, addr, 2);
96 if (!status)
97 status = regmap_raw_read(ci->regmap, 3, data, n);
98 return status;
99}
100
101static int write_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
102{
103 int status;
104 u8 addr[2] = {address & 0xff, address >> 8};
105
106 status = regmap_raw_write(ci->regmap, 2, addr, 2);
107 if (!status) {
108 u8 buf[256];
109
110 memcpy(buf, data, n);
111 status = regmap_raw_write(ci->regmap, 3, buf, n);
112 }
113 return status;
114}
115
116static int read_io(struct cxd *ci, u16 address, unsigned int *val)
117{
118 int status;
119 u8 addr[2] = {address & 0xff, address >> 8};
120
121 status = regmap_raw_write(ci->regmap, 2, addr, 2);
122 if (!status)
123 status = regmap_read(ci->regmap, 3, val);
124 return status;
125}
126
127static int write_io(struct cxd *ci, u16 address, u8 val)
128{
129 int status;
130 u8 addr[2] = {address & 0xff, address >> 8};
131
132 status = regmap_raw_write(ci->regmap, 2, addr, 2);
133 if (!status)
134 status = regmap_write(ci->regmap, 3, val);
135 return status;
136}
137
138static int write_regm(struct cxd *ci, u8 reg, u8 val, u8 mask)
139{
140 int status = 0;
141 unsigned int regval;
142
143 if (ci->lastaddress != reg)
144 status = regmap_write(ci->regmap, 0, reg);
145 if (!status && reg >= 6 && reg <= 8 && mask != 0xff) {
146 status = regmap_read(ci->regmap, 1, ®val);
147 ci->regs[reg] = regval;
148 }
149 ci->lastaddress = reg;
150 ci->regs[reg] = (ci->regs[reg] & (~mask)) | val;
151 if (!status)
152 status = regmap_write(ci->regmap, 1, ci->regs[reg]);
153 if (reg == 0x20)
154 ci->regs[reg] &= 0x7f;
155 return status;
156}
157
158static int write_reg(struct cxd *ci, u8 reg, u8 val)
159{
160 return write_regm(ci, reg, val, 0xff);
161}
162
163static int write_block(struct cxd *ci, u8 adr, u8 *data, u16 n)
164{
165 int status = 0;
166 u8 *buf = ci->wbuf;
167
168 if (ci->lastaddress != adr)
169 status = regmap_write(ci->regmap, 0, adr);
170 if (status)
171 return status;
172
173 ci->lastaddress = adr;
174 while (n) {
175 int len = n;
176
177 if (ci->cfg.max_i2c && (len + 1 > ci->cfg.max_i2c))
178 len = ci->cfg.max_i2c - 1;
179 memcpy(buf, data, len);
180 status = regmap_raw_write(ci->regmap, 1, buf, len);
181 if (status)
182 return status;
183 n -= len;
184 data += len;
185 }
186 return status;
187}
188
189static void set_mode(struct cxd *ci, int mode)
190{
191 if (mode == ci->mode)
192 return;
193
194 switch (mode) {
195 case 0x00:
196 write_regm(ci, 0x06, 0x00, 0x07);
197 break;
198 case 0x01:
199 write_regm(ci, 0x06, 0x02, 0x07);
200 break;
201 default:
202 break;
203 }
204 ci->mode = mode;
205}
206
207static void cam_mode(struct cxd *ci, int mode)
208{
209 u8 dummy;
210
211 if (mode == ci->cammode)
212 return;
213
214 switch (mode) {
215 case 0x00:
216 write_regm(ci, 0x20, 0x80, 0x80);
217 break;
218 case 0x01:
219 if (!ci->en.read_data)
220 return;
221 ci->write_busy = 0;
222 dev_info(&ci->client->dev, "enable cam buffer mode\n");
223 write_reg(ci, 0x0d, 0x00);
224 write_reg(ci, 0x0e, 0x01);
225 write_regm(ci, 0x08, 0x40, 0x40);
226 read_reg(ci, 0x12, &dummy);
227 write_regm(ci, 0x08, 0x80, 0x80);
228 break;
229 default:
230 break;
231 }
232 ci->cammode = mode;
233}
234
235static int init(struct cxd *ci)
236{
237 int status;
238
239 mutex_lock(&ci->lock);
240 ci->mode = -1;
241 do {
242 status = write_reg(ci, 0x00, 0x00);
243 if (status < 0)
244 break;
245 status = write_reg(ci, 0x01, 0x00);
246 if (status < 0)
247 break;
248 status = write_reg(ci, 0x02, 0x10);
249 if (status < 0)
250 break;
251 status = write_reg(ci, 0x03, 0x00);
252 if (status < 0)
253 break;
254 status = write_reg(ci, 0x05, 0xFF);
255 if (status < 0)
256 break;
257 status = write_reg(ci, 0x06, 0x1F);
258 if (status < 0)
259 break;
260 status = write_reg(ci, 0x07, 0x1F);
261 if (status < 0)
262 break;
263 status = write_reg(ci, 0x08, 0x28);
264 if (status < 0)
265 break;
266 status = write_reg(ci, 0x14, 0x20);
267 if (status < 0)
268 break;
269
270
271
272
273 status = write_reg(ci, 0x0A, 0xA7);
274 if (status < 0)
275 break;
276
277 status = write_reg(ci, 0x0B, 0x33);
278 if (status < 0)
279 break;
280 status = write_reg(ci, 0x0C, 0x33);
281 if (status < 0)
282 break;
283
284 status = write_regm(ci, 0x14, 0x00, 0x0F);
285 if (status < 0)
286 break;
287 status = write_reg(ci, 0x15, ci->clk_reg_b);
288 if (status < 0)
289 break;
290 status = write_regm(ci, 0x16, 0x00, 0x0F);
291 if (status < 0)
292 break;
293 status = write_reg(ci, 0x17, ci->clk_reg_f);
294 if (status < 0)
295 break;
296
297 if (ci->cfg.clock_mode == 2) {
298
299 u32 reg = ((ci->cfg.bitrate << 13) + 71999) / 72000;
300
301 if (ci->cfg.polarity) {
302 status = write_reg(ci, 0x09, 0x6f);
303 if (status < 0)
304 break;
305 } else {
306 status = write_reg(ci, 0x09, 0x6d);
307 if (status < 0)
308 break;
309 }
310 status = write_reg(ci, 0x20, 0x08);
311 if (status < 0)
312 break;
313 status = write_reg(ci, 0x21, (reg >> 8) & 0xff);
314 if (status < 0)
315 break;
316 status = write_reg(ci, 0x22, reg & 0xff);
317 if (status < 0)
318 break;
319 } else if (ci->cfg.clock_mode == 1) {
320 if (ci->cfg.polarity) {
321 status = write_reg(ci, 0x09, 0x6f);
322 if (status < 0)
323 break;
324 } else {
325 status = write_reg(ci, 0x09, 0x6d);
326 if (status < 0)
327 break;
328 }
329 status = write_reg(ci, 0x20, 0x68);
330 if (status < 0)
331 break;
332 status = write_reg(ci, 0x21, 0x00);
333 if (status < 0)
334 break;
335 status = write_reg(ci, 0x22, 0x02);
336 if (status < 0)
337 break;
338 } else {
339 if (ci->cfg.polarity) {
340 status = write_reg(ci, 0x09, 0x4f);
341 if (status < 0)
342 break;
343 } else {
344 status = write_reg(ci, 0x09, 0x4d);
345 if (status < 0)
346 break;
347 }
348 status = write_reg(ci, 0x20, 0x28);
349 if (status < 0)
350 break;
351 status = write_reg(ci, 0x21, 0x00);
352 if (status < 0)
353 break;
354 status = write_reg(ci, 0x22, 0x07);
355 if (status < 0)
356 break;
357 }
358
359 status = write_regm(ci, 0x20, 0x80, 0x80);
360 if (status < 0)
361 break;
362 status = write_regm(ci, 0x03, 0x02, 0x02);
363 if (status < 0)
364 break;
365 status = write_reg(ci, 0x01, 0x04);
366 if (status < 0)
367 break;
368 status = write_reg(ci, 0x00, 0x31);
369 if (status < 0)
370 break;
371
372
373 status = write_regm(ci, 0x09, 0x08, 0x08);
374 if (status < 0)
375 break;
376 ci->cammode = -1;
377 cam_mode(ci, 0);
378 } while (0);
379 mutex_unlock(&ci->lock);
380
381 return 0;
382}
383
384static int read_attribute_mem(struct dvb_ca_en50221 *ca,
385 int slot, int address)
386{
387 struct cxd *ci = ca->data;
388 u8 val;
389
390 mutex_lock(&ci->lock);
391 set_mode(ci, 1);
392 read_pccard(ci, address, &val, 1);
393 mutex_unlock(&ci->lock);
394 return val;
395}
396
397static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot,
398 int address, u8 value)
399{
400 struct cxd *ci = ca->data;
401
402 mutex_lock(&ci->lock);
403 set_mode(ci, 1);
404 write_pccard(ci, address, &value, 1);
405 mutex_unlock(&ci->lock);
406 return 0;
407}
408
409static int read_cam_control(struct dvb_ca_en50221 *ca,
410 int slot, u8 address)
411{
412 struct cxd *ci = ca->data;
413 unsigned int val;
414
415 mutex_lock(&ci->lock);
416 set_mode(ci, 0);
417 read_io(ci, address, &val);
418 mutex_unlock(&ci->lock);
419 return val;
420}
421
422static int write_cam_control(struct dvb_ca_en50221 *ca, int slot,
423 u8 address, u8 value)
424{
425 struct cxd *ci = ca->data;
426
427 mutex_lock(&ci->lock);
428 set_mode(ci, 0);
429 write_io(ci, address, value);
430 mutex_unlock(&ci->lock);
431 return 0;
432}
433
434static int slot_reset(struct dvb_ca_en50221 *ca, int slot)
435{
436 struct cxd *ci = ca->data;
437
438 if (ci->cammode)
439 read_data(ca, slot, ci->rbuf, 0);
440
441 mutex_lock(&ci->lock);
442 cam_mode(ci, 0);
443 write_reg(ci, 0x00, 0x21);
444 write_reg(ci, 0x06, 0x1F);
445 write_reg(ci, 0x00, 0x31);
446 write_regm(ci, 0x20, 0x80, 0x80);
447 write_reg(ci, 0x03, 0x02);
448 ci->ready = 0;
449 ci->mode = -1;
450 {
451 int i;
452
453 for (i = 0; i < 100; i++) {
454 usleep_range(10000, 11000);
455 if (ci->ready)
456 break;
457 }
458 }
459 mutex_unlock(&ci->lock);
460 return 0;
461}
462
463static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot)
464{
465 struct cxd *ci = ca->data;
466
467 dev_dbg(&ci->client->dev, "%s\n", __func__);
468 if (ci->cammode)
469 read_data(ca, slot, ci->rbuf, 0);
470 mutex_lock(&ci->lock);
471 write_reg(ci, 0x00, 0x21);
472 write_reg(ci, 0x06, 0x1F);
473 msleep(300);
474
475 write_regm(ci, 0x09, 0x08, 0x08);
476 write_regm(ci, 0x20, 0x80, 0x80);
477 write_regm(ci, 0x06, 0x07, 0x07);
478
479 ci->mode = -1;
480 ci->write_busy = 0;
481 mutex_unlock(&ci->lock);
482 return 0;
483}
484
485static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot)
486{
487 struct cxd *ci = ca->data;
488
489 mutex_lock(&ci->lock);
490 write_regm(ci, 0x09, 0x00, 0x08);
491 set_mode(ci, 0);
492 cam_mode(ci, 1);
493 mutex_unlock(&ci->lock);
494 return 0;
495}
496
497static int campoll(struct cxd *ci)
498{
499 u8 istat;
500
501 read_reg(ci, 0x04, &istat);
502 if (!istat)
503 return 0;
504 write_reg(ci, 0x05, istat);
505
506 if (istat & 0x40)
507 ci->dr = 1;
508 if (istat & 0x20)
509 ci->write_busy = 0;
510
511 if (istat & 2) {
512 u8 slotstat;
513
514 read_reg(ci, 0x01, &slotstat);
515 if (!(2 & slotstat)) {
516 if (!ci->slot_stat) {
517 ci->slot_stat |=
518 DVB_CA_EN50221_POLL_CAM_PRESENT;
519 write_regm(ci, 0x03, 0x08, 0x08);
520 }
521
522 } else {
523 if (ci->slot_stat) {
524 ci->slot_stat = 0;
525 write_regm(ci, 0x03, 0x00, 0x08);
526 dev_info(&ci->client->dev, "NO CAM\n");
527 ci->ready = 0;
528 }
529 }
530 if ((istat & 8) &&
531 ci->slot_stat == DVB_CA_EN50221_POLL_CAM_PRESENT) {
532 ci->ready = 1;
533 ci->slot_stat |= DVB_CA_EN50221_POLL_CAM_READY;
534 }
535 }
536 return 0;
537}
538
539static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open)
540{
541 struct cxd *ci = ca->data;
542 u8 slotstat;
543
544 mutex_lock(&ci->lock);
545 campoll(ci);
546 read_reg(ci, 0x01, &slotstat);
547 mutex_unlock(&ci->lock);
548
549 return ci->slot_stat;
550}
551
552static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
553{
554 struct cxd *ci = ca->data;
555 u8 msb, lsb;
556 u16 len;
557
558 mutex_lock(&ci->lock);
559 campoll(ci);
560 mutex_unlock(&ci->lock);
561
562 if (!ci->dr)
563 return 0;
564
565 mutex_lock(&ci->lock);
566 read_reg(ci, 0x0f, &msb);
567 read_reg(ci, 0x10, &lsb);
568 len = ((u16)msb << 8) | lsb;
569 if (len > ecount || len < 2) {
570
571 read_block(ci, 0x12, ci->rbuf, len);
572 mutex_unlock(&ci->lock);
573 return -EIO;
574 }
575 read_block(ci, 0x12, ebuf, len);
576 ci->dr = 0;
577 mutex_unlock(&ci->lock);
578 return len;
579}
580
581static int write_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
582{
583 struct cxd *ci = ca->data;
584
585 if (ci->write_busy)
586 return -EAGAIN;
587 mutex_lock(&ci->lock);
588 write_reg(ci, 0x0d, ecount >> 8);
589 write_reg(ci, 0x0e, ecount & 0xff);
590 write_block(ci, 0x11, ebuf, ecount);
591 ci->write_busy = 1;
592 mutex_unlock(&ci->lock);
593 return ecount;
594}
595
596static struct dvb_ca_en50221 en_templ = {
597 .read_attribute_mem = read_attribute_mem,
598 .write_attribute_mem = write_attribute_mem,
599 .read_cam_control = read_cam_control,
600 .write_cam_control = write_cam_control,
601 .slot_reset = slot_reset,
602 .slot_shutdown = slot_shutdown,
603 .slot_ts_enable = slot_ts_enable,
604 .poll_slot_status = poll_slot_status,
605 .read_data = read_data,
606 .write_data = write_data,
607};
608
609static int cxd2099_probe(struct i2c_client *client,
610 const struct i2c_device_id *id)
611{
612 struct cxd *ci;
613 struct cxd2099_cfg *cfg = client->dev.platform_data;
614 static const struct regmap_config rm_cfg = {
615 .reg_bits = 8,
616 .val_bits = 8,
617 };
618 unsigned int val;
619 int ret;
620
621 ci = kzalloc(sizeof(*ci), GFP_KERNEL);
622 if (!ci) {
623 ret = -ENOMEM;
624 goto err;
625 }
626
627 ci->client = client;
628 memcpy(&ci->cfg, cfg, sizeof(ci->cfg));
629
630 ci->regmap = regmap_init_i2c(client, &rm_cfg);
631 if (IS_ERR(ci->regmap)) {
632 ret = PTR_ERR(ci->regmap);
633 goto err_kfree;
634 }
635
636 ret = regmap_read(ci->regmap, 0x00, &val);
637 if (ret < 0) {
638 dev_info(&client->dev, "No CXD2099AR detected at 0x%02x\n",
639 client->addr);
640 goto err_rmexit;
641 }
642
643 mutex_init(&ci->lock);
644 ci->lastaddress = 0xff;
645 ci->clk_reg_b = 0x4a;
646 ci->clk_reg_f = 0x1b;
647
648 ci->en = en_templ;
649 ci->en.data = ci;
650 init(ci);
651 dev_info(&client->dev, "Attached CXD2099AR at 0x%02x\n", client->addr);
652
653 *cfg->en = &ci->en;
654
655 if (!buffermode) {
656 ci->en.read_data = NULL;
657 ci->en.write_data = NULL;
658 } else {
659 dev_info(&client->dev, "Using CXD2099AR buffer mode");
660 }
661
662 i2c_set_clientdata(client, ci);
663
664 return 0;
665
666err_rmexit:
667 regmap_exit(ci->regmap);
668err_kfree:
669 kfree(ci);
670err:
671
672 return ret;
673}
674
675static int cxd2099_remove(struct i2c_client *client)
676{
677 struct cxd *ci = i2c_get_clientdata(client);
678
679 regmap_exit(ci->regmap);
680 kfree(ci);
681
682 return 0;
683}
684
685static const struct i2c_device_id cxd2099_id[] = {
686 {"cxd2099", 0},
687 {}
688};
689MODULE_DEVICE_TABLE(i2c, cxd2099_id);
690
691static struct i2c_driver cxd2099_driver = {
692 .driver = {
693 .name = "cxd2099",
694 },
695 .probe = cxd2099_probe,
696 .remove = cxd2099_remove,
697 .id_table = cxd2099_id,
698};
699
700module_i2c_driver(cxd2099_driver);
701
702MODULE_DESCRIPTION("Sony CXD2099AR Common Interface controller driver");
703MODULE_AUTHOR("Ralph Metzler");
704MODULE_LICENSE("GPL");
705
